LM2502SMX/NOPB

LM2502 www.ti.com SNLS176L – JANUARY 2004 – REVISED MAY 2013 Mobile Pixel Link (MPL) Display Interface Serializer and Deserializer Check for Samples: LM2502 FEATURES DESCRIPTION • • • • • • The LM2502 device is a dual link display interface SERDES that adapts existing CPU / video busses to a low power current-mode serial MPL link. The chipset may also be used for a RGB565 application with glue logic. The interconnect is reduced from 22 signals to only 3 active signals with the LM2502 chipset easing flex interconnect design, size and cost. 1 2 • • • • • • >300 Mbps Dual Link Raw Throughput MPL Physical Layer (MPL-0) Pin Selectable Master / Slave Mode Frequency Reference Transport Complete LVCMOS / MPL Translation Interface Modes: – 16-bit CPU, i80 or m68 Style – RGB565 with Glue Logic −30°C to 85°C Operating Range Link Power Down Mode Reduces IDDZ < 10 µA Dual Display Support (CS1* & CS2*) Via-less MPL Interconnect Feature 3.0V Supply Voltage (VDD and VDDA) Interfaces to 1.7V to 3.3V Logic (VDDIO) The Master Serializer (SER) resides beside an application processor or baseband processor and translates a parallel bus from LVCMOS levels to serial MPL levels for transmission over a flex cable and PCB traces to the Slave Deserializer (DES) located near the display module. Dual display support is provided for a primary and sub display through the use of two ChipSelect signals. A Mode pin selects either a i80 or m68 style interface. The Power_Down (PD*) input controls the power state of the MPL interface. When PD* is asserted, the MD1/0 and MC signals are powered down to save current. SYSTEM BENEFITS • • • • • Small Interface Low Power Low EMI Frequency Reference Transport Intrinsic Level Translation The LM2502 implements the physical layer of the MPL Standard (MPL-0). The LM2502 is offered in NOPB (Lead-free) NFBGA and WQFN packages. Typical Application Diagram BBP or APP Processor Memory Port (Display) LM2502 MPL Master INTR R/W*(WR*) E (RD*) A/D D[15:0] CS2* CS1* LM2502 MPL Slave MC MD0 CLK CLK (optional) R/W*(WR*) R/W* E (RD*) A/D D[15:0] CS2* CS1* PD* Mode PD* M/S* = H PLL_CON[2:0], Mode are application dependent M/S* PLL_Con[2:0] Mode GND MD1 GND CLKDIS* PLL_Con [2:0] Primary Display (A) Sub Display (B) M/S* M/S* = L PLL_CON[2:0], Mode, CLKDIS* are application dependent, PD* = GPIO 1 2 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. All trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2004–2013, Texas Instruments Incorporated LM2502 SNLS176L – JANUARY 2004 – REVISED MAY 2013 www.ti.com NFBGA Connection Diagram Ball A1 A B C D E F G 1 2 3 4 5 6 7 TOP VIEW (not to scale) Table 1. Ball Assignment (1) (1) 2 Ball # Master Slave Ball # Master Slave A1 D0 D0 D5 NC NC A2 D1 D1 D6 VSScore VSScore A3 D2 D2 D7 VDDcore VDDcore D8 A4 VDDA VDDA E1 D8 A5 INTR CLKDIS* E2 D9 D9 A6 MD1 MD0 E3 NC NC A7 MC MC E4 NC NC B1 D3 D3 E5 NC NC B2 D4 D4 E6 CS1* CS1* B3 D5 D5 E7 PLLCON2 PLLCON2 B4 VSSA VSSA F1 D10 D10 B5 M/S* M/S* F2 D11 D11 B6 Mode Mode F3 D12 D12 VSSIO B7 MD0 MD1 F4 VSSIO C1 D6 D6 F5 MF0 MF0 C2 D7 D7 F6 PLLCON1 PLLCON1 C3 NC NC F7 PD* PD* C4 NC NC G1 D13 D13 C5 NC NC G2 D14 D14 C6 CS2* CS2* G3 D15 D15 VDDIO C7 MF1 MF1 G4 VDDIO D1 VDDIO VDDIO G5 A/D A/D D2 VSSIO VSSIO G6 PLLCON0 PLLCON0 D3 NC NC G7 CLK CLK D4 NC NC NC = Not Connected Note: Three pins are different between Master and Slave configurations - see also Figure 17 Submit Documentation Feedback Copyright © 2004–2013, Texas Instruments Incorporated Product Folder Links: LM2502 LM2502 www.ti.com SNLS176L – JANUARY 2004 – REVISED MAY 2013 WQFN Connection Diagram D11 D10 D9 D8 VDDIO VSSIO D6 D7 D3 D0 10 9 8 7 6 5 4 3 2 1 D13 11 40 D4 D14 12 39 D1 D12 13 38 D5 D15 14 37 D2 VSSIO 15 36 VDDA VDDIO 16 35 VSSA A/D 17 34 LM2502SQ TOP VIEW 40 Lead WQFN 5mm x 5mm x 0.8mm 0.4mm pitch (not to scale) INTRM / CLKDIS*S MF0 18 PLLCON0 PLLCON1 (DAP connection, center pad = GND) 33 M/S* 19 32 MD1M / MD0S 20 31 MC 27 28 29 30 MF1 CS2* MD0M / MD1S MODE PLLCON2 VDDcore 24 CS1* 26 23 PD* VSScore 22 CLK 25 21 TOP VIEW (not to scale) Submit Documentation Feedback Copyright © 2004–2013, Texas Instruments Incorporated Product Folder Links: LM2502 3 LM2502 SNLS176L – JANUARY 2004 – REVISED MAY 2013 www.ti.com Table 2. Pad Assignment (1) (1) Pin # Master Slave Ball # Master Slave 1 D0 D0 21 CLK CLK 2 D3 D3 22 PD* PD* 3 D7 D7 23 CS1* CS1* 4 D6 D6 24 PLLCON2 PLLCON2 5 VSSIO VSSIO 25 VSScore VSScore 6 VDDIO VDDIO 26 VDDcore VDDcore 7 D8 D8 27 MF1 MF1 8 D9 D9 28 CS2* CS2* 9 D10 D10 29 MD0M MD1S 10 D11 D11 30 MODE MODE 11 D13 D13 31 MC MC 12 D14 D14 32 MD1M MD0S 13 D12 D12 33 M/S* M/S* 14 D15 D15 34 INTRM CLKDIS*S 15 VSSIO VSSIO 35 VSSA VSSA 16 VDDIO VDDIO 36 VDDA VDDA 17 A/D A/D 37 D2 D2 18 MF0 MF0 38 D5 D5 19 PLLCON0 PLLCON0 39 D1 D1 20 PLLCON1 PLLCON1 40 D4 D4 DAP GND GND DAP GND GND Note: Three pins are different between Master and Slave configurations. Pin Descriptions Pin Name No. of Pins I/O, Type (1) Description Master (SER) Slave (DES) MPL SERIAL BUS PINS MD[1:0] 2 IO, MPL MPL Data Line Driver/Receiver MPL Data Receiver/Line Driver MC 1 IO, MPL MPL Clock Line Driver MPL Clock Receiver Ground MPL Ground - see Power/Ground Pins MPL Ground - see Power/Ground Pins VSSA CONFIGURATION/PARALLEL BUS PINS M/S* 1 I, LVCMOS Master/Slave* Input, M/S* = H for Master Master/Slave* Input M/S* = L for Slave PD* 1 I, LVCMOS Power_Down* Input, H = Active L = Power Down Mode Power_Down* Input, H = Active L = Power Down Mode MF0 (E or RD*) 1 IO, LVCMOS Multi-function Input Zero (0): If MODE = L (m68 mode), E input pin, data is latched on E High-to-Low transition or E may be static High and Data is latched on CS* Low-to-High edge If MODE = H (i80 mode), Read Enable input pin, active low. Read data is driven when both RD* and CS* are Low. Multi-function Output Zero (0): If MODE = L (m68 mode), E output pin, static High. If MODE = H (i80 mode), Read Enable output pin, active Low. MF1 (R/W* or WR*) 1 IO, LVCMOS Multi-function Input One (1): If Mode = L (m68 mode), Read/Write* pin, Read High, Write* Low If Mode = H (i80 mode), Write* enable input pin, active Low. Write data is latched on the Low-to-High transition of either WR* or CS* (which ever occurs first). Multi-function Output One (1): If Mode = L (m68 mode) Read/Write* pin, Read High, Write* Low If Mode = H (i80 mode) Write* enable output pin, active Low. (1) 4 Note: I = Input, O = Output, IO = Input/Output, VDDIO ≤ VDD (VDDA = VDDcore). Do not float input pins. Submit Documentation Feedback Copyright © 2004–2013, Texas Instruments Incorporated Product Folder Links: LM2502 LM2502 www.ti.com SNLS176L – JANUARY 2004 – REVISED MAY 2013 Pin Descriptions (continued) Description Pin Name No. of Pins I/O, Type (1) CS1* 1 IO, LVCMOS ChipSelect1* – Input H = Ignored L = Active ChipSelect1* – Output H = Ignored L = Active CS2* 1 IO, LVCMOS ChipSelect2* – Input H = Ignored L = Active ChipSelect2* – Output H = Ignored L = Active A/D (RS or A0) 1 IO, LVCMOS Address/Data – Input H = Data L = Address (Command) Address/Data – Output H = Data L = Address (Command) D[15:0] 16 IO, LVCMOS Data Bus – Inputs/Outputs Data Bus – Outputs/Inputs INTR or CLKDIS* 1 O or I, LVCMOS INTR is asserted when the read data is ready and de-asserted upon a second CPU Read cycle. Clock Disable - CLKDIS*: H = CLK output ON L = CLK output LOW, allows for the Slave clock output to be held static if not used. CLK 1 IO, LVCMOS Clock Input Clock Output (Frequency Reference) – no phase relationship to data – frequency reference only. Mode 1 I, LVCMOS Mode Input Pin H = i80 Mode, L = m68 Mode Mode Input Pin H = i80 Mode, L = m68 Mode PLL_CON [2:0] 3 I, LVCMOS PLL Configuration Input Pins – see Table 12 Clock Divisor Configuration Input Pins – see Table 12 Master (SER) Slave (DES) POWER/GROUND PINS VDDA 1 Power Power Supply Pin for the MPL Interface. 2.9V to 3.3V VSSA 1 Ground Ground Pin for the MPL Interface, a low impedance ground path is required between the Master and the Slave device - see Applications Information section. VDDcore 1 Power Power Supply Pin for the digital core. 2.9V to 3.3V VSScore 1 Ground Ground Pin for the digital core. VDDIO 2 Power Power Supply Pin for the parallel interface. 1.7V to 3.3V VSSIO 2 Ground Ground Pin for the parallel interface. 9 NC 1 Ground Not Connected (C3-5, D3-5, E3-5). NFBGA Package only. DAP = Ground. WQFN Package only. Table 3. Master Pinout - NFBGA Package MST 1 2 3 4 5 6 7 A D0 D1 D2 VDDA INTR MD1 MC B D3 D4 D5 VSSA M/S* Mode MD0 C D6 D7 NC NC NC CS2* MF1 D VDDIO VSSIO NC NC NC VSScore VDDcore E D8 D9 NC NC NC CS1* PLLCON2 F D10 D11 D12 VSSIO MF0 PLLCON1 PD* G D13 D14 D15 VDDIO A/D PLLCON0 CLK 6 7 Table 4. Slave Pinout - NFBGA Package SLV 1 2 3 4 5 A D0 D1 D2 VDDA CLKDIS* MD0 MC B D3 D4 D5 VSSA M/S* Mode MD1 C D6 D7 NC NC NC CS2* MF1 D VDDIO VSSIO NC NC NC VSScore VDDcore E D8 D9 NC NC NC CS1* PLLCON2 Submit Documentation Feedback Copyright © 2004–2013, Texas Instruments Incorporated Product Folder Links: LM2502 5 LM2502 SNLS176L – JANUARY 2004 – REVISED MAY 2013 www.ti.com Table 4. Slave Pinout - NFBGA Package (continued) SLV 1 2 3 4 5 6 7 F D10 D11 D12 VSSIO MF0 PLLCON1 PD* G D13 D14 D15 VDDIO A/D PLLCON0 CLK These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. ABSOLUTE MAXIMUM RATINGS (1) (2) Supply Voltage (VDDA) −0.3V to +4.0 V Supply Voltage (VDD) −0.3V to +4.0 V −0.3V to +4.0 V Supply Voltage (VDDIO) LVCMOS Input/Output Voltage −0.3V to (VDDIO +0.3) V MPL Input/Output Voltage −0.3V to (VDDA +0.3) V Junction Temperature +150 °C Storage Temperature −65°C to +150 °C Lead Temperature Soldering, 40 Seconds +260 °C ESD Ratings: ≥±2 kV HBM, 1.5 kΩ, 100pF ≥±200 V EIAJ, 0Ω, 200 pF Maximum Package Power Dissipation Capacity at 25°C NFBGA Package (3) 2.5 W Derate NFBGA Package above 25°C 25 mW/°C Theta JA 45 °C/W WQFN Package (3) 1.39 W Derate WQFN Package above 25°C 11 mW/°C Theta JA (1) (2) (3) 90 °C/W “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be specified. They are not meant to imply that the device should be operated at these limits. The tables of “Electrical Characteristics” specify conditions for device operation. If Military/Aerospace specified devices are required, please contact the TI Sales Office/ Distributors for availability and specifications. NFBGA assumes 4 layer PCB, WQFN assumes 2 layer PCB for thermal calculations. RECOMMENDED OPERATING CONDITIONS Supply Voltage Min Typ Max Units VDDA to VSSA and VDDcore to VSScore 2.9 3.0 3.3 V VDDIO to VSSIO 1.7 3.3 V Clock Frequency 3.0 26 MHz Ambient Temperature −30 85 °C 6 Submit Documentation Feedback 25 Copyright © 2004–2013, Texas Instruments Incorporated Product Folder Links: LM2502 LM2502 www.ti.com SNLS176L – JANUARY 2004 – REVISED MAY 2013 ELECTRICAL CHARACTERISTICS Over recommended operating supply and temperature ranges unless otherwise specified. (1) (2) Symbol Parameter Conditions Min Typ Max Units 3.67 IB 5.0 IB 6.33 IB µA MPL IOLL Logic Low Current (5X IB) IOMS Mid Scale Current IOLH Logic High Current (1X IB) IB Current Bias IOFF MPL Leakage Current 3.0 IB 0.7 IB 1.0 IB µA 1.3 IB 150 PD* = L (PowerDown mode) −2 0 µA µA +2 µA VDDIO +0.3 V 0.3 VDDIO V LVCMOS (1.7V to 3.3V Operation) VIH Input Voltage High Level VDDIO = 2.0V to 3.3V 0.7 VDDIO VDDIO = 1.7V to