LM2512ASNX/NOPB

LM2512A www.ti.com SNLS269B – AUGUST 2007 – REVISED MAY 2013 LM2512A Mobile Pixel Link (MPL-1), 24-Bit RGB Display Interface Serializer with Optional Dithering and Look Up Table Check for Samples: LM2512A FEATURES DESCRIPTION • The LM2512A is a MPL Serializer (SER) that performs a 24-bit to 18-bit Dither operation and serialization of the video signals to Mobile Pixel link (MPL) levels on only 3 or 4 active signals. An optional Look Up Table (Three X 256 X 8 bit RAM) is also provided for independent color correction. 18-bit Bufferless or partial buffer displays from QVGA (320 x 240) up to VGA (640 x 480) pixels can utilize a 24bit video source. 1 2 • • • • • • • • • • 24-bit RGB Interface Support up to 640 x 480 VGA Format Optional 24 to 18-bit Dithering Optional Look Up Table for Independent Color Correction MPL-1 Physical Layer SPI Interface for Look Up Table Control and Loading Low Power Consumption & Powerdown State Level Translation Between Host and Display Optional Auto Power Down on STOP PCLK Frame Sequence Bits Auto Resync upon Data or Clock Error 1.6V to 2.0V Core / Analog Supply Voltage 1.6V to 3.0V I/O Supply Voltage Range SYSTEM BENEFITS • • • • • The interconnect is reduced from 28 signals to only 3 or 4 active signals with the LM2512A and companion deserializer easing flex interconnect design, size constraints and cost. The LM2512A SER resides by the application, graphics or baseband processor and translates the wide parallel video bus from LVCMOS levels to serial Mobile Pixel Link levels for transmission over a flex cable (or coax) and PCB traces to the DES located near or in the display module. When in Power_Down, the SER is put to sleep and draws less than 10μA. The link can also be powered down by stopping the PCLK (DES dependant) or by the PD* input pins. Dithered Data Reduction Independent RGB Color Correction 24-bit Color Input Small Interface, Low Power and Low EMI Intrinsic Level Translation The LM2512A provides enhanced AC performance over the LM2512. It implements the physical layer of the MPL-1 and uses a single-ended current-mode transmission. Typical 3 MD Lane Application Diagram - Bridge Chip MPL-1 Deserializer LM2512A Serializer Apps Processor --Graphics Processor --Baseband Processor MD0 D R[7:0] G[7:0] B[7:0] VS HS DE PCLK i t h e r P 2 S MD1 MC R[5:0] G[5:0] B[5:0] VS HS DE PCLK RGB Display VGA at 18-Bit Color Depth SPI_CSX SPI_SCL SPI_SDA S P I MD2 Three 256 X 8 LUT PD* PLL [Supply, Configuration pins, and bypass caps. and grounding not shown] PD* PDOUT* 1 2 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. All trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2007–2013, Texas Instruments Incorporated LM2512A SNLS269B – AUGUST 2007 – REVISED MAY 2013 www.ti.com Pin Descriptions No. of Pins I/O, Type (1) MD[2:0] 3 O, MPL MPL Data Line Driver MC 1 O, MPL MPL Clock Line Driver Pin Name Description RGB Serializer MPL SERIAL BUS PINS SPI INTERFACE and CONFIGURATION PINS SPI_CSX 1 I, LVCMOS SPI_Chip Select Input SPI port is enabled when: SPI_CSX is Low, PD* is High, and PCLK is static. SPI_SCL 1 I, LVCMOS SPI_Clock Input SPI_SDA/HS 1 IO, LVCMOS Multi-function Pin: If SPI_CSX is Low, this is the SPI_SDA IO signal. Default is Input. Pin will be an output for a SPI Read transaction. See HS description below also. PD* 1 I, LVCMOS Power Down Mode Input SER is in sleep mode when PD* = Low, SER is enabled when PD* = High In PD*=L - Sleep mode: SPI interface is OFF, Register settings are RESET, and LUT data is retained. RES1 1 I, LVCMOS Reserved 1 - Tie High (VDDIO) only available on NZK0049A package TM 1 I, LVCMOS Test Mode L = Normal Mode, tie to GND H = Test Mode (Reserved) NC 1 NA PCLK 1 I, LVCMOS Pixel Clock Input Video Signals are latched on the RISING edge. R[7:0] G[7:0] B[7:0] 24 I, LVCMOS RGB Data Bus Inputs – Bit 7 is the MSB. VS 1 I, LVCMOS Vertical Sync. Input This signal is used as a frame start for the Dither block and is required. The VS signal is serialized unmodified. SPI_SDA/HS 1 IO, LVCMOS Multi-function Pin: Horizontal Sync. Input (when SPI_CSX = High) See SPI_SDA description above also. DE 1 I, LVCMOS Data Enable Input VDDA 1 Power Power Supply Pin for the PLL (SER) and MPL Interface. 1.6V to 2.0V VDD 1 Power Power Supply Pin for the digital core. 1.6V to 2.0V VDDIO 3 Power Power Supply Pin for the parallel interface I/Os. 1.6V to 3.0V VSSA 1 Ground Ground Pin for PLL (SER) and MPL interface VSS 1 Ground Ground Pin for digital core. For SN40A package, this is the large center pad. VSSIO 4 Ground Ground Pin for the parallel interface I/Os. For NJM0040A package, this is the large center pad. Not Connected - Leave Open; only on NZK0049A package VIDEO INTERFACE PINS POWER/GROUND PINS (1) Note: I = Input, O = Output, IO = Input/Output. Do not float input pins. These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. 2 Submit Documentation Feedback Copyright © 2007–2013, Texas Instruments Incorporated Product Folder Links: LM2512A LM2512A www.ti.com SNLS269B – AUGUST 2007 – REVISED MAY 2013 ABSOLUTE MAXIMUM RATINGS (1) (2) Supply Voltage (VDDA) −0.3V to +2.2V Supply Voltage (VDD) −0.3V to +2.2V −0.3V to +3.3V Supply Voltage (VDDIO) −0.3V to (VDDIO +0.3V) LVCMOS Input/Output Voltage −0.3V to VDDA MPL Output Voltage Junction Temperature +150°C Storage Temperature −65°C to +150°C ESD Ratings: Maximum Package Power Dissipation Capacity at 25°C (1) (2) HBM - JESD22−A114C std. ≥±2 kV MM - JESD22−A115−A std. ≥±200V CDM - JESD22−C101−C std. ≥±500V NZK0049A Package 2.5 W NJM0040A Package 3.2 W Derate NZK0049A Package above 25°C 25 mW/°C Derate NJM0040A Package above 25°C 26 mW/°C “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be specified. They are not meant to imply that the device should be operated at these limits. The tables of “Electrical Characteristics” specify conditions for device operation. If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/ Distributors for availability and specifications. RECOMMENDED OPERATING CONDITIONS Min Typ Max Units VDDA to VSSA and VDD to VSS 1.6 1.8 2.0 V VDDIO to VSSIO 1.6 3.0 V 7.5 22.5 MHz PClock Frequency (6X) 5 15 MHz MC Frequency 30 90 MHz 85 °C Supply Voltage PClock Frequency (4X) −30 Ambient Temperature 25 ELECTRICAL CHARACTERISTICS Over recommended operating supply and temperature ranges unless otherwise specified. (1) (2) Symbol Parameter Conditions Min Typ Max Units 3.947IB 5.0 IB 6.842IB µA MPL IOLL Logic Low Current (5X IB) IOMS Mid Scale Current IOLH Logic High Current (1X IB) IB Current Bias IOFF MPL Leakage Current 3.0 IB 0.711 IB 1.0 IB µA 1.368 IB 190 VMPL = 0V µA µA −2 +2 µA VDDIO V LVCMOS (1.6V to 3.0V Operation) VIH Input Voltage High Level 0.7 VDDIO VIL Input Voltage Low Level GND VHY Input Hysteresis IIN Input Current VOH Output Voltage High Level VOL Output Voltage Low Level 0.3 VDDIO 100 −1 SPI_SDA IOH = −1 mA IOL = 1 mA 0 V mV +1 µA 0.7 VDDIO VDDIO V VSSIO 0.2 VDDIO V SUPPLY CURRENT (1) (2) Typical values are given for VDDIO = 1.8V and VDD = VDDA = 1.8V and TA = 25°C. Current into a device pin is defined as positive. Current out of device pins is defined as negative. Voltages are referenced to Ground unless otherwise specified. Submit Documentation Feedback Copyright © 2007–2013, Texas Instruments Incorporated Product Folder Links: LM2512A 3 LM2512A SNLS269B – AUGUST 2007 – REVISED MAY 2013 www.ti.com ELECTRICAL CHARACTERISTICS (continued) Over recommended operating supply and temperature ranges unless otherwise specified.(1)(2) Symbol IDD Parameter Total Supply Current Enabled (3) Supply Current -Enabled IDDZ Supply Current—Disable Power Down Modes Ta = 25°C Conditions Typ Max Units MC = 80 MHz, VDDIO Checkerboard Pattern VDD/VDDA (4) 3 MD Lane 0.02 0.07 mA 5.4 9.0 mA MC = 60 MHz, VDDIO Checkerboard Pattern VDD/VDDA 2 MD Lane 0.01 mA 4.1 mA MC = 60 MHz, Pseudo-Random Pattern 2 MD Lane VDDIO 0.02 mA 3.7 mA PD* = L VDDIO