LM2619
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SNVS212B – NOVEMBER 2002 – REVISED MAY 2013
500-mA Sub-Miniature Step-Down DC-DC Converter
Check for Samples: LM2619
FEATURES
DESCRIPTION
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The LM2619 step down DC-DC converter is
optimized for powering circuits from a single lithiumion cell. It steps down an input voltage of 2.8V to
5.5V to an output of 1.5V to 3.6V at up to 500mA.
Output voltage is set using resistor feedback dividers.
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2
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Sub-Miniature 10-Bump Thin DSBGA Package
Uses Small Ceramic Capacitors
5-mV (Typical) PWM Mode Output Voltage
Ripple (COUT = 22 µF)
Internal Soft Start
Current Overload Protection
Thermal Shutdown
External Compensation
KEY SPECIFICATIONS
•
•
•
•
•
•
•
•
•
•
Operates from a single Li-ion cell : 2.8V to 5.5V
Output voltage : 1.5V to 3.6V
DC feedback voltage precision: ±1%
Maximum Load Capability: 500mA
PWM Mode Quiescent Current: 600µA typ
Shutdown Current: 0.02 µA typ
PWM switching frequency: 600kHz
SYNC input for PWM mode frequency
synchronization from 0.5MHz to 1MHz
High efficiency (96% typical at 3.9 VIN, 3.6 VOUT
and 200 mA) in PWM mode from internal
synchronous rectification
100% Maximum Duty Cycle for Lowest
Dropout
The device offers three modes for mobile phones and
similar portable applications. Fixed-frequency PWM
mode minimizes RF interference. A SYNC input
allows synchronizing the switching frequency in a
range of 500 kHz to 1 MHz. Low-current hysteretic
PFM mode reduces quiescent current to 160 µA
(typical). Shutdown mode turns the device off and
reduces battery consumption to 0.02 µA (typical).
Current limit and thermal shutdown features protect
the device and system during fault conditions.
The LM2619 is available in a 10-bump DSBGA
package. This packaging uses chip-scale DSBGA
technology and offers the smallest possible size. A
high switching frequency (600 kHz) allows use of tiny
surface-mount components.
The device features external compensation to tailor
the response to a wide range of operating conditions.
APPLICATIONS
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•
•
•
Mobile Phones
Hand-Held Radios
RF PC Cards
Wireless LAN Cards
Typical Application Circuits
VIN
2.8V to
5. 5V
10PF
EN
ON/OFF
VDD
VOU T
1.8 V
PVIN
SW
1 0 PH
SYNC/
MODE
10PF
EN
ON/OFF
LM2619
FB
PWM/PFM
EAOUT
VIN
3.2V to
5. 5V
EANEG SGND
PGND
6.65k
22PF
33.2k
Figure 1. Typical Circuit for 1.8-V Output Voltage
VOU T
2.5V
PVIN
SW
10 PH
SYNC/
MODE
LM2619
FB
PWM/PFM
EAOUT
EANEG SGND
PGND
22.1k
22PF
33.2k
68.1k
39.2k
330pF
VDD
330pF
Figure 2. Typical Circuit for 2.5-V Output Voltage
1
2
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2002–2013, Texas Instruments Incorporated
LM2619
SNVS212B – NOVEMBER 2002 – REVISED MAY 2013
VIN
2.8V to
5.5V
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10PF
VDD
EN
SW
ON/OFF
SYNC/
MODE
PWM/PFM
V OU T
1.5V
10PH
PVIN
LM2619
FB
22PF
EANEG SGND PGND
EAOUT
22.1k
680pF
Figure 3. Typical Circuit for 1.5-V Output Voltage
Connection Diagrams
10-Bump DSBGA Package
SGND
SGND
A1
FB
B3
B1
EANEG
SW
C3
C1
EAOUT
PGND
D3
D1
SYNC/
MODE
A3
VDD
VDD
A3
B1
B3
PVIN
PVIN
EAOUT
C1
C3
SW
SYNC/
MODE
D1
D3
PGND
FB
A1
EANEG
A2
D2
EN
A2
D2
EN
Figure 4. YPA Package Top View
Figure 5. YPA Package Bottom View
Pin Functions
Table 1. Pin Description
2
Pin No.
Pin Name
A1
FB
Function
B1
EANEG
Inverting input of error amplifier.
C1
EAOUT
Output of error amplifier.
D1
SYNC/MODE
Synchronization Input. Use this digital input for frequency selection or modulation control. Set:
SYNC/MODE = high for low-noise 600kHz PWM mode
SYNC/MODE = low for low-current PFM mode
SYNC/MODE = a 500kHz–1MHz external clock for synchronization in PWM mode. (See OPERATING
MODE SELECTION and FREQUENCY SYNCHRONIZATION in Device Information.)
D2
EN
Enable Input. Set this Schmitt trigger digital input high for normal operation. For shutdown, set low. Set
EN low during system power-up and other low supply voltage conditions. (See SHUTDOWN MODE in
Device Information.)
D3
PGND
C3
SW
B3
PVIN
Power Supply Voltage Input to the internal PFET switch. Connect to the input filter capacitor.
A3
VDD
Analog Supply Input. If board layout is not optimum, an optional 0.1µF ceramic capacitor is suggested.
A2
SGND
Feedback Analog Input.
Power Ground.
Switching Node connection to the internal PFET switch and NFET synchronous rectifier. Connect to an
inductor with a saturation current rating that exceeds the max Switch Peak Current Limit of the LM2619.
Analog and Control Ground.
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These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
Absolute Maximum Ratings (1)
−0.2V to +6V
PVIN, VDD to SGND
−0.2V to +0.2V
PGND to SGND, PVIN to VDD
−0.2V to +6V
EN, EAOUT, EANEG, SYNC/MODE to SGND
(GND −0.2V) to (VDD +0.2V)
FB, SW
−45°C to +150°C
Storage temperature range
Lead temperature (soldering, 10 sec.)
Junction temperature
260°C
(2)
−25°C to +125°C
Minimum ESD rating (Human Body Model, C = 100 pF, R = 1.5 kΩ)
Thermal resistance (θJA)
(1)
±2 kV
(3)
140°C/W
Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for
which the device is functional. For specifications and associated test conditions, see the Min and Max limits and Conditions in the
Electrical Characteristics table. Typical (typ) specifications are mean or average values at 25°C.
Thermal shutdown will occur if the junction temperature exceeds 150°C.
Thermal resistance specified with 2 layer PCB (0.5/0.5 oz. cu).
(2)
(3)
Electrical Characteristics
Specifications with standard typeface are for TA = TJ = 25°C, and those in boldface type apply over the full Operating
Temperature Range of TA = TJ = −25°C to +85°C. Unless otherwise specified, PVIN = VDD = EN = SYNC/MODE = 3.6V.
Symbol
Parameter
VIN
Input voltage range
VFB
Feedback voltage
Conditions
PVIN = VDD = VIN (1)
Min
Typ
Max
Unit
2.8
3.6
5.5
V
1.485
1.50
1.515
V
(2)
VHYST
PFM comparator hysteresis voltage
PFM Mode (SYNC/MODE = 0V)
ISHDN
Shutdown supply current
VIN = 3.6V, EN = 0V
0.02
3
µA
IQ1_PWM
DC bias current into VDD
SYNC/MODE = VIN, FB = 2V
600
725
µA
SYNC/MODE = 0V, FB = 2V
IQ2_PFM
24
mV
160
195
µA
RDSON (P)
Pin-pin resistance for PFET
395
550
mΩ
RDSON (N)
Pin-pin resistance for NFET
330
500
mΩ
RDSON (TC)
FET resistance temperature coefficient
ILIM
Switch peak current limit
VIH
Logic high input, EN, SYNC/MODE
VIL
Logic low input, EN, SYNC/MODE
FSYNC
SYNC/MODE clock frequency range
FOSC
Internal oscillator frequency
Tmin
Minimum on-time of PFET switch in
PWM mode
(1)
(2)
(3)
(4)
0.5
(3)
620
0.4
(4)
PWM Mode
1100
mA
0.95
1.3
V
0.80
500
468
%/C
810
600
V
1000
kHz
732
kHz
200
ns
The LM2619 is designed for mobile phone applications where turn-on after system power-up is controlled by the system controller.
Thus, it should be kept in shutdown by holding the EN pin low until the input voltage exceeds 2.8V.
The hysteresis voltage is the minimum voltage swing on the FB pin that causes the internal feedback and control circuitry to turn the
internal PFET switch on and then off during PFM mode. When resistor dividers are used like in the operating circuit of Figure 20, the
hysteresis at the output will be the value of the hysteresis at the feedback pin times the resistor divider ratio. In this case, 24mV (typ) x
((46.4k + 33.2k)/33.2k).
Current limit is built-in, fixed, and not adjustable. If the current limit is reached while the voltage at the FB pin is pulled below 0.7V, the
internal PFET switch turns off for 2.5µs to allow the inductor current to diminish.
SYNC driven with an external clock switching between VIN and GND. When an external clock is present at SYNC; the IC is forced to be
in PWM mode at the external clock frequency. The LM2619 synchronizes to the rising edge of the external clock.
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Typical Performance Characteristics
LM2619ATL, Circuit of Figure 3, VIN = 3.6V, TA = 25°C, unless otherwise noted.
Shutdown Quiescent Current vs Temperature
(Circuit in Figure 3)
Quiescent Supply Current vs Supply Voltage
800
VFB = 2V
SUPPLY CURRENT (PA)
700
600
PWM
500
400
300
200
PFM
100
0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
SUPPLY VOLTAGE (V)
Figure 6.
Figure 7.
Output Voltage vs Supply Voltage
(VOUT = 1.5V, PWM MODE)
Output Voltage vs Supply Voltage
(VOUT = 1.5V, PFM MODE)
1.5030
1.0035
1.5015
1.5010
1.5005
1.5000
1.4995
300mA
1.4990
3.0
3.5
4.0
4.5
5.0
1.0020
VIN = 3.6V
1.0015
1.0010
VIN = 2.8V
1.0005
0.9995
5.5
6.0
0
100
200
300
Figure 8.
Figure 9.
Output Voltage vs Output Current
(VOUT = 1.5V, PWM MODE)
Output Voltage vs Output Current
(VOUT = 1.5V, PFM MODE)
1.5015
400
OUTPUT CURRENT (mA)
SUPPLY VOLTAGE (V)
SYNC = VIN
VOUT = 1.5V
1.5010
OUTPUT VOLTAGE (V)
VIN = 4.2V
1.0025
1.0000
SYNC = VIN
VOUT = 1.5V
1.4985
1.4980
2.5
SYNC = VIN
VOUT = 1.0V
1.0030
100mA
1.5020
OUTPUT VOLTAGE (V)
OUTPUT VOLTAGE (V)
1.5025
VIN = 4.2V
1.5005
1.5000 VIN = 3.6V
1.4995
VIN = 2.8V
1.4990
1.4985
1.4980
1.4975
0
100
200
300
400
OUTPUT CURRENT (mA)
Figure 10.
4
Figure 11.
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Typical Performance Characteristics (continued)
LM2619ATL, Circuit of Figure 3, VIN = 3.6V, TA = 25°C, unless otherwise noted.
Output Voltage vs Output Current
(VOUT = 3.6V, PWM MODE)
(Circuit in Figure 20)
Output Voltage vs Output Current
(VOUT = 3.6V, PWM MODE)
(Circuit in Figure 20)
3.7
VIN = 4.2V
OUTPUT VOLTAGE (V)
3.5
VIN = 3.6V
3.3
3.1
2.9
2.7
2.5
2.3
100
VIN = 2.8V
VCON = 0V
SYNC = VIN
200
300
400
500
OUTPUT CURRENT (mA)
Figure 12.
Figure 13.
Switching Frequency vs Temperature
(Circuit in Figure 3, PWM MODE)
Feedback Bias Current vs Temperature
(Circuit in Figure 3)
Figure 14.
Figure 15.
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Typical Performance Characteristics (continued)
LM2619ATL, Circuit of Figure 3, VIN = 3.6V, TA = 25°C, unless otherwise noted.
Efficiency vs Output Current
(VOUT = 1.5V, PWM MODE)
Efficiency vs Output Current
(VOUT = 1.5V, PWM MODE, with Diode)
100
100
VIN = 2.8V
VIN = 2.8V
90
80
EFFICIENCY (%)
EFFICIENCY (%)
90
VIN = 5.5V
VIN = 4.2V
70
VIN = 3.6V
60
50
0
VIN = 3.6V
70
60
50
SYNC = VIN
VOUT = 1.5V
40
VIN = 5.5V
VIN = 4.2V
80
50 100 150 200 250 300 350 400 450
SYNC = VIN
VOUT = 1.5V
D1 = MBRM120
40
0
OUTPUT CURRENT (mA)
OUTPUT CURRENT (mA)
Figure 16.
Figure 17.
Efficiency vs Output Current
(VOUT = 3.6V, PWM MODE)
(Circuit in Figure 20)
Efficiency vs Output Current
(VOUT = 3.6V, PWM MODE, with Diode)
(Circuit in Figure 20)
100
100
VIN = 3.9V
VIN = 3.9V
95
EFFICIENCY (%)
EFFICIENCY (%)
95
90
VIN = 5.5V
VIN = 4.2V
85
80
75
70
SYNC = VIN
VOUT = 3.6V
0
50 100 150 200 250 300 350 400 450
OUTPUT CURRENT (mA)
90
VIN = 5.5V
VIN = 4.2V
85
80
SYNC = VIN
VOUT = 3.6V
D1 = MBRM120
75
70
0
50 100 150 200 250 300 350 400 450
OUTPUT CURRENT (mA)
Figure 18.
6
50 100 150 200 250 300 350 400 450
Figure 19.
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DEVICE INFORMATION
The LM2619 is a simple, step-down DC-DC converter optimized for powering circuits in mobile phones, portable
communicators, and similar battery powered RF devices. It is based on a current-mode buck architecture, with
synchronous rectification in PWM mode for high efficiency. It is designed for a maximum load capability of
500mA in PWM mode. Maximum load range may vary from this depending on input voltage, output voltage and
the inductor chosen.
The device has all three of the pin-selectable operating modes required for powering circuits in mobile phones
and other sophisticated portable devices with complex power management needs. Fixed-frequency PWM
operation offers full output current capability at high efficiency while minimizing interference with sensitive IF and
data acquisition circuits. During standby operation, hysteretic PFM mode reduces quiescent current to 160µA typ.
to maximize battery life. Shutdown mode turns the device off and reduces battery consumption to 0.02µA (typ).
DC PWM mode feedback voltage precision is ±1%. Efficiency is typically 96% for a 200mA load with 3.6V output,
3.9V input. The efficiency can be further increased by using a schottky diode like MBRM120L as shown in
Figure 20. PWM mode quiescent current is 600µA typ. The output voltage can be set from 1.5V to 3.6V by using
external feedback resistors.
Additional features include soft-start, current overload protection, over voltage protection and thermal shutdown
protection.
The LM2619 is constructed using a chip-scale 10-pin thin DSBGA package. This package offers the smallest
possible size, for space-critical applications such as cell phones, where board area is an important design
consideration. Use of a high switching frequency (600kHz) reduces the size of external components. Board area
required for implementation is only 0.58in2(375mm2).
Use of a DSBGA package requires special design considerations for implementation. (See DSBGA PACKAGE
ASSEMBLY AND USE in Application Information.) Its fine bump-pitch requires careful board design and
precision assembly equipment.
VIN
3.9V to
5.5V
C3*
0.1PF
C1
10PF
V DD
L1
10PH
PVIN
SW
D1**
SYSTEM
CONTROLLER
PWM/PFM
ON/OFF
VOUT
3.6V
LM2619
SYNC/MODE
FB
R3 68.1k
C2
10PF
EANEG
C5
10pF
EN
SGND
R1
46.4k
PGND EAOUT
C4
220pF
*C3 IS OPTIONAL
R2
33.2k
**D1 IS OPTIONAL FOR
HIGHER EFFICIENCY
Figure 20. Typical Operating Circuit for 3.6V Output Voltage
CIRCUIT OPERATION
Referring to Figure 20, Figure 21, Figure 22, and Figure 23, the LM2619 operates as follows. During the first part
of each switching cycle, the control block in the LM2619 turns on the internal PFET switch. This allows current to
flow from the input through the inductor to the output filter capacitor and load. The inductor limits the current to a
ramp with a slope of (VIN–VOUT)/L, by storing energy in a magnetic field. During the second part of each cycle,
the controller turns the PFET switch off, blocking current flow from the input, and then turns the NFET
synchronous rectifier on. In response, the inductor's magnetic field collapses, generating a voltage that forces
current from ground through the synchronous rectifier to the output filter capacitor and load. As the stored energy
is transferred back into the circuit and depleted, the inductor current ramps down with a slope of VOUT/L. If the
inductor current reaches zero before the next cycle, the synchronous rectifier is turned off to prevent current
reversal. The output filter capacitor stores charge when the inductor current is high, and releases it when low,
smoothing the voltage across the load.
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The output voltage is regulated by modulating the PFET switch on time to control the average current sent to the
load. The effect is identical to sending a duty-cycle modulated rectangular wave formed by the switch and
synchronous rectifier at SW to a low-pass filter formed by the inductor and output filter capacitor. The output
voltage is equal to the average voltage at the SW pin.
VDD
SYNC/
MODE
OSCILLATOR
AND MODE
CONTROL
6
PVIN
CURRENT
SENSE
EAOUT
EANEG
PWM
COMP.
5k
MOSFET
CONTROL
LOGIC
OVP
COMP.
FB
PFM
COMP.
1.5V
REF
SW
ZERO
CROSSING
DETECTOR
SHUTDOWN
CONTROL
SOFT
START
EN
PGND
SGND
Figure 21. Simplified Functional Diagram
PWM OPERATION
While in PWM (Pulse Width Modulation) mode, the output voltage is regulated by switching at a constant
frequency and then modulating the energy per cycle to control power to the load. Energy per cycle is set by
modulating the PFET switch on-time pulse-width to control the peak inductor current. This is done by comparing
the signal from the current-sense amplifier with a slope compensated error signal from the voltage-feedback error
amplifier. At the beginning of each cycle, the clock turns on the PFET switch, causing the inductor current to
ramp up. When the current sense signal ramps past the error amplifier signal, the PWM comparator turns off the
PFET switch and turns on the NFET synchronous rectifier, ending the first part of the cycle. If an increase in load
pulls the output voltage down, the error amplifier output increases, which allows the inductor current to ramp
higher before the comparator turns off the PFET. This increases the average current sent to the output and
adjusts for the increase in the load.
Before going to the PWM comparator, the error signal is summed with a slope compensation ramp from the
oscillator for stability of the current feedback loop. During the second part of the cycle, a zero crossing detector
turns off the NFET synchronous rectifier if the inductor current ramps to zero. The minimum on time of the PFET
in PWM mode is about 200ns.
8
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PWM Mode Switching Waveform
A: Inductor Current, 500mA/div
B: SW Pin, 2V/div
C: VOUT, 10mV/div, AC Coupled
PFM Mode Switching Waveform
A: Inductor Current, 500mA/div
B: SW Pin, 2V/div
C: VOUT, 50mV/div, AC Coupled
Figure 22.
Figure 23.
PFM OPERATION
Connecting the SYNC/MODE to SGND sets the LM2619 to hysteretic PFM operation. While in PFM (Pulse
Frequency Modulation) mode, the output voltage is regulated by switching with a discrete energy per cycle and
then modulating the cycle rate, or frequency, to control power to the load. This is done by using an error
comparator to sense the output voltage. The device waits as the load discharges the output filter capacitor, until
the output voltage drops below the lower threshold of the PFM error-comparator. Then the device initiates a cycle
by turning on the PFET switch. This allows current to flow from the input, through the inductor to the output,
charging the output filter capacitor. The PFET is turned off when the output voltage rises above the regulation
threshold of the PFM error comparator. Thus, the output voltage ripple in PFM mode is proportional to the
hysteresis of the error comparator.
In PFM mode, the device only switches as needed to service the load. This lowers current consumption by
reducing power consumed during the switching action in the circuit, due to transition losses in the internal
MOSFETs, gate drive currents, eddy current losses in the inductor, etc. It also improves light-load voltage
regulation. During the second half of the cycle, the intrinsic body diode of the NFET synchronous rectifier
conducts until the inductor current ramps to zero.
OPERATING MODE SELECTION
The LM2619 is designed for digital control of the operating modes by the system controller. This prevents the
spurious switch over from low-noise PWM mode between transmission intervals in mobile phone applications
that can occur in other products.
The SYNC/MODE digital input pin is used to select the operating mode. Setting SYNC/MODE high (above 1.3V)
selects 600kHz current-mode PWM operation. PWM mode is optimized for low-noise, high-power operation for
use when the load is active. Setting SYNC/MODE low (below 0.4V) selects hysteretic voltage-mode PFM
operation. PFM mode is optimized for reducing power consumption and extending battery life when the load is in
a low-power standby mode. In PFM mode, quiescent current into the VDD pin is 160µA typ. In contrast, PWM
mode VDD-pin quiescent current is 600µA typ.
PWM operation is intended for use with loads of 50mA or more, when low noise operation is desired. Below
100mA, PFM operation can be used to allow precise regulation, and reduced current consumption. The LM2619
has an over-voltage feature that prevents the output voltage from rising too high, when the device is left in PWM
mode under low-load conditions. See Overvoltage Protection, for more information.
Switch modes with the SYNC/MODE pin, using a signal with a slew rate faster than 5V/100µs. Use a
comparator, Schmitt trigger or logic gate to drive the SYNC/MODE pin. Do not leave the pin floating or allow it to
linger between thresholds. These measures will prevent output voltage errors in response to an indeterminate
logic state. The LM2619 switches on each rising edge of SYNC. Ensure a minimum load to keep the output
voltage in regulation when switching modes frequently.
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FREQUENCY SYNCHRONIZATION
The SYNC/MODE input can also be used for frequency synchronization. During synchronization, the LM2619
initiates cycles on the rising edge of the clock. When synchronized to an external clock, it operates in PWM
mode. The device can synchronize to a 50% duty-cycle clock over frequencies from 500kHz to 1MHz. If a
different duty cycle is used other than 50% the range for acceptable duty cycles is 30% to 70%.
Use the following waveform and duty cycle guidelines when applying an external clock to the SYNC/MODE pin.
Clock under/overshoot should be less than 100mV below GND or above VDD. When applying noisy clock signals,
especially sharp edged signals from a long cable during evaluation, terminate the cable at its characteristic
impedance and add an RC filter to the SYNC pin, if necessary, to soften the slew rate and over/undershoot. Note
that sharp edged signals from a pulse or function generator can develop under/overshoot as high as 10V at the
end of an improperly terminated cable.
OVERVOLTAGE PROTECTION
The LM2619 has an over-voltage comparator that prevents the output voltage from rising too high when the
device is left in PWM mode under low-load conditions. When the output voltage rises by about 100mV (Figure 3)
over its regulation threshold, the OVP comparator inhibits PWM operation to skip pulses until the output voltage
returns to the regulation threshold. When resistor dividers are used the OVP threshold at the output will be the
value of the threshold at the feedback pin times the resistor divider ratio. In over voltage protection, output
voltage and ripple will increase.
SHUTDOWN MODE
Setting the EN digital input pin low (
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