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LM3424
SNVS603D – AUGUST 2009 – REVISED JULY 2019
LM3424 Constant Current N-channel Controller
with Thermal Foldback For Driving LEDs
1 Features
3 Description
•
•
•
•
The LM3424 is a versatile high voltage N-channel
MOSFET controller for LED drivers. It can be easily
configured in buck, boost, buck-boost and SEPIC
topologies. In addition, the LM3424 includes a
thermal
foldback
feature
for
temperature
management of the LEDs. This flexibility, along with
an input voltage rating of 75 V, makes the LM3424
ideal for illuminating LEDs in a large family of
applications.
1
•
•
•
•
•
•
•
VIN range from 4.5 V to 75 V
High-side adjustable current sense
2-Ω, 1-A peak MOSFET gate driver
Input undervoltage and output overvoltage
protection
PWM and analog dimming
Cycle-by-cycle current limit
Programmable soft-start and slope compensation
Programmable, synchronizable switching
frequency
Programmable thermal foldback
Precision voltage reference
Low-power shutdown and thermal shutdown
2 Applications
•
•
•
•
LED Drivers (buck, boost, buck-boost, and
SEPIC)
Indoor and outdoor area SSL
General illumination
Constant-current regulators
Adjustable high-side current sense allows for tight
regulation of the LED current with the highest
efficiency possible. The LM3424 uses standard peak
current-mode control providing inherent input voltage
feed-forward compensation for better noise immunity.
It is designed to provide accurate thermal foldback
with a programmable foldback breakpoint and slope.
In addition, a 2.45V reference is provided.
The LM3424 includes a high-voltage startup regulator
that operates over a wide input range of 4.5 V to 75
V. The internal PWM controller is designed for
adjustable switching frequencies of up to 2.0 MHz
and external synchronization is possible. The
controller is capable of high speed PWM dimming
and analog dimming.
Device Information(1)
Typical Boost Application Circuit
PART NUMBER
VIN
1
2
3
4
5
PWM
6
7
8
TEMP
9
VIN
LM3424
HSP
HSN
EN
COMP
SLOPE
CSH
IS
RT/SYNC
VCC
GATE
nDIM
GND
SS
TGAIN
DDRV
OVP
TSENSE
LM3424
20
PACKAGE
HTSSOP (20)
BODY SIZE (NOM)
6.50 mm × 4.40 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
19
18
17
16
ILED
15
14
13
12
DAP
10
TREF
VS
11
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
LM3424
SNVS603D – AUGUST 2009 – REVISED JULY 2019
www.ti.com
Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
4
6.1
6.2
6.3
6.4
6.5
6.6
4
4
4
5
5
8
Absolute Maximum Ratings ......................................
ESD Ratings..............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics...........................................
Typical Characteristics .............................................
Detailed Description ............................................ 11
7.1 Overview ................................................................. 11
7.2 Functional Block Diagram ....................................... 11
7.3 Feature Description................................................. 12
7.4 Device Functional Modes........................................ 25
8
Application and Implementation ........................ 26
8.1 Application Information............................................ 26
8.2 Typical Applications ................................................ 29
9
Power Supply Recommendations...................... 61
9.1 Input Supply Current Limit ...................................... 61
10 Layout................................................................... 61
10.1 Layout Guidelines ................................................. 61
10.2 Layout Example .................................................... 62
11 Device and Documentation Support ................. 63
11.1
11.2
11.3
11.4
11.5
Device Support......................................................
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
63
63
63
63
63
12 Mechanical, Packaging, and Orderable
Information ........................................................... 63
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision C (August 2015) to Revision D
Page
•
Deleted references to automotive grade (LM3424-Q1) device, now available in data sheet SNVSB96 ............................... 1
•
Changed EN pulldown resistance specification minimum value from: 0.45 MΩ to: 0.245 MΩ Electrical
Characteristics table. ............................................................................................................................................................. 5
•
Changed EN pulldown resistance specification maximum value from: 1.3 MΩ to: 2.85 MΩ in Electrical
Characteristics table. ............................................................................................................................................................. 5
Changes from Revision B (October 2009) to Revision C
Page
•
Adjusted temperature range in Features section. .................................................................................................................. 1
•
Added Pin Configuration and Functions section, ESD Ratings table, Feature Description section, Device Functional
Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device
and Documentation Support section, and Mechanical, Packaging, and Orderable Information section .............................. 1
•
Changed "Operating Temperature Range (TJ = −40°C to +125°C)" to "Operating Temperature Range (TA = TJ =
−40°C to +125°C)" in Electrical Characterization table Condition statement ........................................................................ 5
2
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SNVS603D – AUGUST 2009 – REVISED JULY 2019
5 Pin Configuration and Functions
PWP Package
20-Pin HTSSOP With PowerPAD™
Top View
VIN
1
20 HSP
EN
2
19 HSN
COMP
3
18 SLOPE
CSH 4
RT
5
nDIM 6
17 IS
21
16 VCC
DAP
15 GATE
SS 7
14 GND
TGAIN 8
13 DDRV
12 OVP
TSENSE 9
11 VS
TREF 10
Pin Functions
PIN
I/O
DESCRIPTION
NO.
NAME
1
VIN
I
Input Voltage
Bypass with 100 nF capacitor to GND as close to the device as
possible.
2
EN
I
Enable
Connect to > 2.4V to enable the device or to < 0.8V for low power
shutdown.
3
COMP
I
Compensation
Connect a capacitor to GND to compensate control loop.
4
CSH
I
Current Sense High
Connect a resistor to GND to set the signal current. Can also be used to
analog dim as explained in the Thermal Foldback and Analog Dimming
section.
5
RT
I
Resistor Timing
Connect a resistor to GND to set the switching frequency. Can also be
used to synchronize to an external clock as explained in the Switching
Frequency section.
6
nDIM
I
Dimming Input /
Under-Voltage Protection
Connect a PWM signal for dimming as detailed in the PWM Dimming
section and/or a resistor divider from VIN to program input under-voltage
lockout.
7
SS
I
Soft-start
Connect a capacitor to GND to extend start-up time.
8
TGAIN
I
Temp Foldback Gain
Connect a resistor to GND to set the foldback slope.
9
TSENSE
I
Temp Sense Input
Connect a resistor/ thermistor divider from VS to sense the temperature
as explained in the Thermal Foldback and Analog Dimming section.
10
TREF
I
Temp Foldback Reference
Connect a resistor divider from VS to set the foldback reference voltage.
11
VS
O
Voltage Reference
2.45V reference for temperature foldback circuit and other external
circuitry.
12
OVP
I
Over-Voltage Protection
Connect a resistor divider from VO to program output over-voltage
lockout.
13
DDRV
O
Dimming Gate Drive Output
Connect to gate of dimming MOSFET.
14
GND
15
GATE
O
Main Gate Drive Output
Connect to gate of main switching MOSFET.
16
VCC
O
Internal Regulator Output
Bypass with a 2.2 µF – 3.3 µF ceramic capacitor to GND.
17
IS
I
Main Switch Current Sense
Connect to the drain of the main N-channel MOSFET switch for RDS-ON
sensing or to a sense resistor installed in the source of the same device.
18
SLOPE
I
Slope Compensation
Connect a resistor to GND to set slope of additional ramp.
19
HSN
I
LED Current Sense Negative
Connect through a series resistor to LED current sense resistor
(negative).
20
HSP
I
LED Current Sense Positive
Connect through a series resistor to LED current sense resistor
(positive).
DAP
DAP
GND Ground
Connect to DAP to provide proper system GND
GND Thermal pad on bottom of IC
Connect to GND.
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SNVS603D – AUGUST 2009 – REVISED JULY 2019
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1) (2)
MIN
MAX
VIN, EN, nDIM
–0.3
76
OVP, HSP, HSN
–0.3
76
–0.3
IS
Voltage
76
–2 for 100 ns
VCC
–0.3
8
VS, TREF, TSENSE, TGAIN, COMP, CSH,
RT, SLOPE, SS
–0.3
6
GATE, DDRV
GND
–0.3
VCC
VCC + 2.5 for 100 ns
–0.3
0.3
–2.5 for 100 ns
2.5 for 100 ns
–1
OVP, HSP, HSN
IS
mA
–30
30
µA
–1
1
mA
Maximum Junction Temperature
Internally Limited
Maximum lead temperature (Reflow and Solder) (3)
Storage temperature
(3)
µA
–1
GATE, DDRV
Internally Limited
(2)
mA
–100
SS
Continuous power dissipation
(1)
V
–2.5 for 100 ns
VIN, EN, nDIM
Continuous current
UNIT
–65
°C
260
°C
150
°C
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/Distributors for availability and
specifications.
Refer toTI’s packaging website for more detailed information and mounting techniques. http://www.ti.com/analogpackaging
6.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic
discharge
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins (1)
±2500
Charged device model (CDM), per JEDEC specification JESD22-C101, all
pins (2)
±1000
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
MIN
MAX
UNIT
Operating Ambient Temperature Range
–40
125
°C
Input Voltage VIN
4.5
75
V
4
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SNVS603D – AUGUST 2009 – REVISED JULY 2019
6.4 Thermal Information
LM3424
THERMAL METRIC (1)
PWP (HTSSOP)
UNIT
20 PINS
RθJA
Junction-to-ambient thermal resistance
36.7
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
21.5
°C/W
RθJB
Junction-to-board thermal resistance
18
°C/W
ψJT
Junction-to-top characterization parameter
0.5
°C/W
ψJB
Junction-to-board characterization parameter
17.8
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
1.9
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report (SPRA953).
6.5 Electrical Characteristics
VIN = 14 V, TA = TJ = −40°C to 125°C unless otherwise specified. Minimum and Maximum limits are ensured through test,
design, or statistical correlation. Typical values represent the most likely parametric norm at TJ = 25°C, and are provided for
reference purposes only.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
START-UP REGULATOR (VCC)
VCC-REG
VCC Regulation
ICC-LIM
VCC Current Limit
IQ
Quiescent Current
ISD
Shutdown Current
ICC = 0 mA
6.3
ICC = 0 mA, TJ = 25°C
VCC = 0 V
7.35
6.9
20
VCC = 0 V, TJ = 25°C
3
EN = 3 V, Static, TJ = 25°C
2
EN = 0 V, TJ = 25°C
0.1
VCC Increasing
VCC-UVLO
VCC UVLO Threshold
4.17
3.7
VCC Decreasing, TJ = 25°C
VCC-HYS
VCC UVLO Hysteresis
1
4.5
VCC Increasing, TJ = 25°C
VCC Decreasing
mA
25
EN = 3 V, Static
mA
µA
V
V
4.08
TJ = 25°C
V
0.1
V
ENABLE (EN)
EN Increasing
VEN-ST
EN start-up Threshold
2.4
EN Increasing, TJ = 25°C
EN Decreasing
1.75
0.8
EN Decreasing, TJ = 25°C
VEN-HYS
EN start-up Hysteresis
REN
EN pulldown resistance
V
1.63
TJ = 25°C
0.1
0.245
TJ = 25°C
V
V
2.85
0.82
MΩ
OVERVOLTAGE PROTECTION (OVP)
VTH-OVP
OVP OVLO Threshold
IHYS-OVP
OVP Hysteresis Source Current
OVP Increasing
1.185
OVP Increasing, TJ = 25°C
OVP Active (high)
1.285
1.24
13
OVP Active (high), TJ = 25°C
27
20
V
µA
ERROR AMPLIFIER
VCSH
CSH Reference Voltage
Error Amplifier Input Bias Current
COMP Sink / Source Current
With Respect to GND
1.21
With Respect to GND, TJ = 25°C
TJ = 25°C
1.26
1.235
–0.6
0
17
TJ = 25°C
0.6
35
26
V
µA
µA
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Electrical Characteristics (continued)
VIN = 14 V, TA = TJ = −40°C to 125°C unless otherwise specified. Minimum and Maximum limits are ensured through test,
design, or statistical correlation. Typical values represent the most likely parametric norm at TJ = 25°C, and are provided for
reference purposes only.
PARAMETER
TEST CONDITIONS
Transconductance
TJ = 25°C
Linear Input Range
See (1), TJ = 25°C
MIN
TYP
MAX
UNIT
100
µA/V
±125
mV
1
MHz
(1)
–6-dB Unloaded Response ,
TJ = 25°C
Transconductance Bandwidth
OSCILLATOR (RT)
RT = 36 kΩ
fSW
Switching Frequency
VRT-SYNC
164
RT = 36 kΩ, TJ = 25°C
RT = 12 kΩ
Sync Threshold
250
207
525
669
RT = 12 kΩ, TJ = 25°C
597
TJ = 25°C
3.5
kHz
kHz
V
PWM COMPARATOR
VCP-BASE
750
COMP to PWM Offset - No Slope
Compensation
TJ = 25°C
1050
900
mV
SLOPE COMPENSATION (SLOPE)
Additional COMP to PWM Offset
- SLOPE sinking 100 µA,
TJ = 25°C
Slope Compensation Amplitude
ΔVCP
85
mV
CURRENT LIMIT (IS)
VLIM
215
Current Limit Threshold
245
TJ = 25°C
35
75
VLIM Delay to Output
tON-MIN
275
TJ = 25°C
140
Leading Edge Blanking Time
TJ = 25°C
340
240
mV
ns
ns
HIGH-SIDE TRANSCONDUCTANCE AMPLIFIER
Input Bias Current
TJ = 25°C
Transconductance
10
µA
20
mA/V
–1.5
Input Offset Current
TJ = 25°C
1.5
0
–5
Input Offset Voltage
TJ = 25°C
0
ICSH = 100 µA (1), TJ = 25°C
Transconductance Bandwidth
5
500
µA
mV
kHz
GATE DRIVER (GATE)
RSRC-GATE
GATE Sourcing Resistance
RSNK-GATE
GATE Sinking Resistance
GATE = High
6
GATE = High, TJ = 25°C
2
GATE = Low
4.5
GATE = Low, TJ = 25°C
1.3
Ω
Ω
UNDERVOLTAGE LOCKOUT AND DIM INPUT (nDIM)
VTH-nDIM
nDIM / UVLO Threshold
1.185
1.240
1.285
V
IHYS-nDIM
nDIM Hysteresis Current
13
20
27
µA
DIM DRIVER (DDRV)
RSRC-DDRV
(1)
6
DDRV Sourcing Resistance
DDRV = High
DDRV = High, TJ = 25°C
30
13.5
Ω
These electrical parameters are ensured by design, and are not verified by test.
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Electrical Characteristics (continued)
VIN = 14 V, TA = TJ = −40°C to 125°C unless otherwise specified. Minimum and Maximum limits are ensured through test,
design, or statistical correlation. Typical values represent the most likely parametric norm at TJ = 25°C, and are provided for
reference purposes only.
PARAMETER
RSNK-DDRV
TEST CONDITIONS
MIN
TYP
DDRV = Low
DDRV Sinking Resistance
MAX
10
DDRV = Low, TJ = 25°C
3.5
UNIT
Ω
nDIM rising to DDRV rising
700
ns
nDIM falling to DDRV falling
360
ns
10
µA
SOFT-START (SS)
ISS
Soft-start current
THERMAL CONTROL
IVS = 0 A,
IVS = 1 mA
VS
ITGAIN-MAX
ITF
VS Voltage
2.4
2.5
V
IVS = 0 A,
IVS = 1 mA,
TJ = 25°C
2.45
TREF input bias current
VTREF = 1.5 V
VTSENSE = 1.5 V, TJ = 25°C
0.1
µA
TSENSE Input Bias Current
VTREF = 1.5 V
VTSENSE = 1.5 V, TJ = 25°C
0.1
µA
TGAIN Maximum Sourcing Current
CSH Current with High-side
Amplifier Disabled
VTGAIN = 2 V
200
VTGAIN = 2 V, TJ = 25°C
RTGAIN = 10
kΩ, TJ =
25°C
600
µA
VTREF = 1.5 V
VTSENSE = 0.5 V
100
µA
VTREF = 1.5 V
VTSENSE = 1.4 V
10
µA
VTREF = 1.5 V
VTSENSE = 1.5 V
2
µA
THERMAL SHUTDOWN
TSD
Thermal Shutdown Threshold
See (1), TJ = 25°C
165
°C
THYS
Thermal Shutdown Hysteresis
See (1), TJ = 25°C
25
°C
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6.6 Typical Characteristics
TA = 25°C and VIN = 14 V unless otherwise specified. The measurements for Figure 1, Figure 3, andFigure 6 were made
using the standard boost evaluation board from AN-1967 LM3424 Buck-Boost Evaluation Board (SNVA397). The
measurements for Figure 2, Figure 4, and Figure 5 were made using the standard buck-boost evaluation board from AN-1969
LM3424 Boost Evaluation Board (SNVA398).
100
100
95
EFFICIENCY (%)
EFFICIENCY (%)
95
90
90
85
80
85
75
80
10
15
20
25
70
30
0
16
32
Figure 1. Boost Efficiency vs Input Voltage
80
Figure 2. Buck-Boost Efficiency vs. Input Voltage
1.010
1.02
1.005
1.01
ILED (A)
ILED (A)
64
VO = 21 V (6 LEDs)
VO = 32 V (9 LEDs)
1.000
0.995
1.00
0.99
0.990
0.98
5
10
15
20
VIN (V)
25
30
0
16
32
48
64
80
VIN (V)
VO = 32 V (9 LEDs)
VO = 21 V (6 LEDs)
Figure 3. Boost LED Current vs. Input Voltage
Figure 4. Buck-Boost LED Current vs. Input Voltage
1.0
1.0
0.8
0.8
0.6
0.6
ILED (A)
ILED (A)
48
VIN (V)
VIN (V)
0.4
1 kHz
0.4
25 kHz
0.2
0.2
0.0
0
20
40
60
80
0.8
100
ICSH (éA)
VO = 21 V (6 LEDs)
20
40
60
80
100
DUTY CYCLE (%)
VIN = 24 V
Figure 5. Analog Dimming
8
0
VO = 32V (9 LEDs)
VIN = 24 V
Figure 6. PWM Dimming
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Typical Characteristics (continued)
TA = 25°C and VIN = 14 V unless otherwise specified. The measurements for Figure 1, Figure 3, andFigure 6 were made
using the standard boost evaluation board from AN-1967 LM3424 Buck-Boost Evaluation Board (SNVA397). The
measurements for Figure 2, Figure 4, and Figure 5 were made using the standard buck-boost evaluation board from AN-1969
LM3424 Boost Evaluation Board (SNVA398).
7.20
1.250
1.245
7.10
VCC (V)
VCSH (V)
1.240
1.235
7.00
6.90
1.230
6.80
1.225
1.220
-50
-14
22
58
94
6.70
-50
130
-14
22
58
94
130
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 7. VCSH vs. Junction Temperature
Figure 8. VCC vs. Junction Temperature
248
2.500
VLIM (mV)
VS (V)
246
2.450
244
242
2.400
-50
-14
22
58
94
240
-50
130
-14
TEMPERATURE (°C)
Figure 9. VS vs. Junction Temperature
58
94
130
Figure 10. VLIM vs. Junction Temperature
1000
255
RT = 12 kÖ
250
245
fSW (kHz)
tON-MIN (ns)
22
TEMPERATURE (°C)
240
RT = 36 kÖ
235
230
100
225
-50
-14
22
58
94
-50
130
-14
22
58
94
130
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 11. Minimum On-Time vs. Junction Temperature
Figure 12. Switching Frequency vs. Junction Temperature
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Typical Characteristics (continued)
TA = 25°C and VIN = 14 V unless otherwise specified. The measurements for Figure 1, Figure 3, andFigure 6 were made
using the standard boost evaluation board from AN-1967 LM3424 Buck-Boost Evaluation Board (SNVA397). The
measurements for Figure 2, Figure 4, and Figure 5 were made using the standard buck-boost evaluation board from AN-1969
LM3424 Boost Evaluation Board (SNVA398).
100.3
1M
100.1
RT (Ö)
ITF (éA)
100k
99.9
10k
99.7
99.5
-50
-14
22
58
94
1k
10k
130
100k
TEMPERATURE (°C)
RGAIN = 10 kΩ
VTSENSE = 0.5 V
1.25
1.00
1.00
0.75
0.75
ILED (A)
ILED (A)
Figure 14. Switching Frequency vs. Timing Resistance
1.25
RGAIN = 15 k:
0.25
0.00
0
RBIAS = 84.5 k:
0.25
RGAIN = 10 k:
50
75
100
0.00
0
125
TEMPERATURE (°C)
RBIAS = 43.2 k:
25
50
75
100
125
TEMPERATURE (°C)
RREF1 = RREF2 = 49.9 kΩ
RNTC-BK = RBIAS = 43.2 kΩ
RREF1 = RREF2 = 49.9 kΩ
Figure 15. Ideal Thermal Foldback with Varied Slope
10
RBIAS = 24.3 k:
0.50
RGAIN = 5 k:
25
10M
VTREF = 1.5 V
Figure 13. ITF vs. Junction Temperature
0.50
1M
fSW (Hz)
RGAIN = 10 kΩ
Figure 16. Ideal Thermal Foldback with Varied Breakpoint
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7 Detailed Description
7.1 Overview
The LM3424 is an N-channel MOSFET (NFET) controller for buck, boost and buck-boost current regulators
which are ideal for driving LED loads. The controller has wide input voltage range allowing for regulation of a
variety of LED loads. The high-side differential current sense, with low adjustable threshold voltage, provides an
excellent method for regulating output current while maintaining high system efficiency. The LM3424 uses peak
current mode control providing good noise immunity and an inherent cycle-by-cycle current limit. The adjustable
current sense threshold provides the capability to amplitude (analog) dim the LED current and the thermal
foldback circuitry allows for precise temperature management of the LEDs. The output enable/disable function
coupled with an internal dimming drive circuit provides high speed PWM dimming through the use of an external
MOSFET placed at the LED load. When designing, the maximum attainable LED current is not internally limited
because the LM3424 is a controller. Instead it is a function of the system operating point, component choices,
and switching frequency allowing the LM3424 to easily provide constant currents up to 5 A. This simple controller
contains all the features necessary to implement a high efficiency versatile LED driver.
7.2 Functional Block Diagram
VIN
6.9V LDO
Regulator
EN
VCC
820k
UVLO
(4.1V)
VCC UVLO
UVLO
HYSTERESIS
1.24V
Standby
20 PA
nDIM
REFERENCE
TLIM Thermal
VCC
Limit
Dimming
1.24V
DDRV
OVLO
Reset
Dominant
Clock
RT
Oscillator
Artificial Ramp
VCC
Q
S
GATE
SLOPE
R
LEB
GND
W = 240 ns
COMP
20 PA
1.24V
PWM
OVP
HYSTERESIS
CSH
OVP
OVLO
HSP
90k
1.24V
10 PA
HSN
1.7k
1.24V
CURRENT
LIMIT
IS
0.245V
100k
100k
VS
LEB
100k
10 PA
100k
TREF
COMP
SS
TSENSE
100k
STANDBY
100k
TGAIN
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7.3 Feature Description
7.3.1 Current Regulators
iL (t)
IL-MAX
ÂiL-PP
IL
IL-MIN
tON = DTS
tOFF = (1-D)TS
t
0
TS
Figure 17. Ideal CCM Regulator Inductor Current iL(t)
Current regulators can be designed to accomplish three basic functions: buck, boost, and buck-boost. All three
topologies in their most basic form contain a main switching MOSFET, a recirculating diode, an inductor and
capacitors. The LM3424 is designed to drive a ground referenced NFET which is perfect for a standard boost
regulator. Buck and buck-boost regulators, on the other hand, usually have a high-side switch. When driving an
LED load, a ground referenced load is often not necessary, therefore a ground referenced switch can be used to
drive a floating load instead. The LM3424 can then be used to drive all three basic topologies as shown in the
Basic Topology Schematics section. Other topologies such as the SEPIC and flyback converter (both derivatives
of the buck-boost) can be implemented as well.
Looking at the buck-boost design, the basic operation of a current regulator can be analyzed. During the time
that the NFET (Q1) is turned on (tON), the input voltage source stores energy in the inductor (L1) while the output
capacitor (CO) provides energy to the LED load. When Q1 is turned off (tOFF), the re-circulating diode (D1)
becomes forward biased and L1 provides energy to both CO and the LED load. Figure 17 shows the inductor
current (iL(t)) waveform for a regulator operating in CCM.
The average output LED current (ILED) is proportional to the average inductor current (IL) , therefore if IL is tightly
controlled, ILED will be well regulated. As the system changes input voltage or output voltage, the ideal duty cycle
(D) is varied to regulate IL and ultimately ILED. For any current regulator, D is a function of the conversion ratio:
Buck
D=
VO
VIN
(1)
Boost
D=
VO - VIN
VO
(2)
Buck-Boost
D=
VO
VO + VIN
(3)
7.3.2 Peak Current Mode Control
Peak current mode control is used by the LM3424 to regulate the average LED current through an array of
HBLEDs. This method of control uses a series resistor in the LED path to sense LED current and can use either
a series resistor in the MOSFET path or the MOSFET RDS-ON for both cycle-by-cycle current limit and input
voltage feed forward. The controller has a fixed switching frequency set by an internal programmable oscillator
which means current mode instability can occur at duty cycles higher than 50%. To mitigate this standard
problem, an artificial ramp is added to the control signal internally. The slope of this ramp is programmable to
allow for a wider range of component choices for a given design. A detailed explanation of this control method is
presented in the following sections.
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Feature Description (continued)
7.3.3 Average LED Current
To first understand how the LM3424 regulates LED current, the thermal foldback functionality will be ignored.
Figure 18 shows the physical implementation of the LED current sense circuitry assuming the thermal foldback
circuitry is a simple current source which, for now, will be set to zero (ITF = 0A). The LM3424 uses an external
current sense resistor (RSNS) placed in series with the LED load to convert the LED current (ILED) into a voltage
(VSNS). The HSP and HSN pins are the inputs to the high-side sense amplifier which are forced to be equal
potential (VHSP=VHSN) through negative feedback. Because of this, the VSNS voltage is forced across RHSP which
generates a current that is summed with the thermal foldback current (ITF) to generate the signal current (ICSH)
which flows out of the CSH pin and through the RCSH resistor. The error amplifier will regulate the CSH pin to
1.24V and assuming ITF = 0A, ICSH can be calculated:
VSNS
ICSH =
RHSP
(4)
This means VSNS will be regulated as follows:
RHSP
VSNS = 1.24V x
RCSH
(5)
ILED can then be calculated:
VSNS
1.24V RHSP
x
ILED =
=
RSNS
RSNS
RCSH
(6)
The selection of the three resistors (RSNS, RCSH, and RHSP) is not arbitrary. For matching and noise performance,
the suggested signal current ICSH is approximately 100 µA. This current does not flow in the LEDs and will not
affect either the off-state LED current or the regulated LED current. ICSH can be above or below this value, but
the high-side amplifier offset characteristics may be affected slightly. In addition, to minimize the effect of the
high-side amplifier voltage offset on LED current accuracy, the minimum VSNS is suggested to be 50 mV. Finally,
a resistor (RHSN = RHSP) should be placed in series with the HSN pin to cancel out the effects of the input bias
current (~10 µA) of both inputs of the high-side sense amplifier.
Note that he CSH pin can also be used as a low-side current sense input regulated to 1.24V. The high-side
sense amplifier is disabled if HSP and HSN are tied to GND.
LM3424
ILED
VSNS
RSNS
RHSP
RHSN
HSP
High-Side
Sense Amplifier
Thermal Foldback Current
HSN
ITF
RCSH
CSH
ICSH
Error Amplifier
1.24V
CCMP
To PWM
Comparator
COMP
Figure 18. LED Current Sense Circuitry
7.3.4 Thermal Foldback and Analog Dimming
Thermal foldback is necessary in many applications due to the extreme temperatures created in LED
environments. In general, two functions are necessary: a temperature breakpoint (TBK) after which the nominal
operating current needs to be reduced, and a slope corresponding to the amount of LED current decrease per
temperature increase as shown in Figure 19. The LM3424 allows the user to program both the breakpoint and
slope of the thermal foldback profile.
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Feature Description (continued)
ILED
v
1
RGAIN
0
TBK
TEND
T
Figure 19. Ideal Thermal Foldback Profile
LM3424
VS
2.45V
ILED
VSNS
RSNS
RHSP
RHSN
HSP
High-Side
Sense Amplifier
RREF2
100k
100k
100k
TGAIN
ICSH
RNTC
Error Amplifier
1.24V
CCMP
RBIAS
TSENSE
100k
CSH
RREF1
VDIF
HSN
ITF
RCSH
NTC
TREF
To PWM
Comparator
RGAIN
COMP
LM94022
Precision Temp Sensor
Figure 20. Thermal Foldback Circuitry
Foldback is accomplished by adding current (ITF) to the CSH summing node. As more current is added, less
current is needed from the high side amplifier and correspondingly, the LED current is regulated to a lower value.
The final temperature (TEND) is reached when ITF = ICSH causing no current to be needed from the high-side
amplifier, yielding ILED = 0A.
Figure 20 shows how the thermal foldback circuitry is physically implemented in the system. ITF is set by placing
a differential voltage (VDIF = VTREF – VTSENSE) across TSENSE and TREF. VTREF can be set with a simple resistor
divider (RREF1 and RREF2) supplied from the VS voltage reference (typical 2.45V). VTSENSE is set with a
temperature dependant voltage (as temperature increases, voltage should decrease).
An NTC thermistor is the most cost effective device used to sense temperature. As the temperature of the
thermistor increases, its resistance decreases (albeit non-linearly). Usually, the NTC manufacturer's datasheet
will detail the resistance-temperature characteristic of the thermistor. The thermistor will have a different
resistance (RNTC) at each temperature. The nominal resistance of an NTC is the resistance when the
temperature is 25°C (R25) and in many datasheets this will be given a multiplier of 1. Then the resistance at a
higher temperature will have a multiplier less than 1 (that is, R85 multiplier is 0.161 therefore R85 = 0.161 x R25).
Given a desired TBK and TEND, the corresponding resistances at those temperatures (RNTC-BK and RNTC-END) can
be found.
Using the NTC method, a resistor divider from VS can be implemented with a resistor connected between VS and
TSENSE and the NTC thermistor placed at the desired location and connected from TSENSE to GND. This will
ensure that the desired temperature-voltage characteristic occurs at TSENSE.
If a linear decrease over the foldback range is necessary, a precision temperature sensor such as the LM94022
can be used instead as shown in Figure 20. Either method can be used to set VTSENSE according to the
temperature. However, for the rest of this datasheet, the NTC method will be used for thermal foldback
calculations.
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Feature Description (continued)
During operation, if VDIF < 0V, then the sensed temperature is less than TBK and the differential sense amplifier
will regulate its output to zero forcing ITF = 0. This maintains the nominal LED current and no foldback is
observed.
At TBK, VDIF = 0V exactly and ITF is still zero. Looking at the manufacturer's datasheet for the NTC thermistor,
RNTC-BK can be obtained for the desired TBK and the voltage relationship at the breakpoint (VTSENSE-BK = VTREF)
can be defined:
RREF1
RNTC-BK
=
RREF1 + RREF2 RNTC-BK + RBIAS
(7)
A general rule of thumb is to set RREF1 = RREF2 simplifying the breakpoint relationship to RBIAS = RNTC-BK.
If VDIF > 0V (temperature is above TBK), then the amplifier will regulate its output equal to the input forcing VDIF
across the resistor (RGAIN) connected from TGAIN to GND. RGAIN ultimately sets the slope of the LED current
decrease with respect to increasing temperature by changing ITF:
VTREF - VTSENSE
ITF =
RGAIN
(8)
If an analog temperature sensor such as the LM94022 is used, then RBIAS and the NTC are not necessary and
VTSENSE will be the direct voltage output of the sensor.
Since the NTC is not usually local to the controller, a bypass capacitor (CNTC) is suggested from TSENSE to
GND. If a capacitor is used at TSENSE, then a capacitor (CREF) of equal or greater value should be placed from
TREF to GND in order to ensure the controller does not start-up in foldback. Alternatively, a smaller CREF can be
used to create a fade-up function at start-up (see Application Information).
Thermal foldback is simply analog dimming according to a specific profile, therefore any method of controlling the
differential voltage between TREF and TSENSE can be use to analog dim the LED current. The corresponding
LED current for any VDIF > 0V is defined:
§ RHSP·
¸
© RSNS¹
ILED = (ICSH - ITF) x ¨
(9)
The CSH pin can also be used to analog dim the LED current by adjusting the current sense voltage (VSNS),
similar to thermal foldback. There are several different methods to adjust VSNS using the CSH pin:
1. External variable resistance: Adjust a potentiometer placed in series with RCSH to vary VSNS.
2. External variable current source: Source current (0 µA to ICSH) into the CSH pin to adjust VSNS.
Variable Current Source
LM3424
VS
VCC
Q8
Q7
RMAX
Q6
RADJ
RBIAS
CSH
RCSH
RADJ
Variable
Resistance
Figure 21. Analog Dimming Circuitry
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Feature Description (continued)
In general, analog dimming applications require a lower switching frequency to minimize the effect of the leading
edge blanking circuit. As the LED current is reduced, the output voltage and the duty cycle decreases.
Eventually, the minimum on-time is reached. The lower the switching frequency, the wider the linear dimming
range. Figure 21 shows how both CSH methods are physically implemented.
Method 1 uses an external potentiometer in the CSH path which is a simple addition to the existing circuitry.
However, the LEDs cannot dim completely because there is always some resistance causing signal current to
flow. This method is also susceptible to noise coupling at the CSH pin since the potentiometer increases the size
of the signal current loop.
Method 2 provides a complete dimming range and better noise performance, though it is more complex. Like
thermal foldback, it simply sources current into the CSH pin, decreasing the amount of signal current that is
necessary. This method consists of a PNP current mirror and a bias network consisting of an NPN, 2 resistors
and a potentiometer (RADJ), where RADJ controls the amount of current sourced into the CSH pin. A higher
resistance value will source more current into the CSH pin causing less regulated signal current through RHSP,
effectively dimming the LEDs. Q7 and Q8 should be a dual pair PNP for best matching and performance. The
additional current (IADD) sourced into the CSH pin can be calculated:
IADD =
§ RADJ x VREF ·
¨R + R ¸ - VBE-Q6
© ADJ MAX ¹
RBIAS
(10)
The corresponding ILED for a specific IADD is:
§ RHSP·
¸
© RSNS¹
ILED = (ICSH - IADD) x ¨
(11)
7.3.5 Current Sense and Current Limit
The LM3424 achieves peak current mode control using a comparator that monitors the main MOSFET (Q1)
transistor current, comparing it with the COMP pin voltage as shown in Figure 22. Further, it incorporates a
cycle-by-cycle over-current protection function. Current limit is accomplished by a redundant internal current
sense comparator. If the voltage at the current sense comparator input (IS) exceeds 245 mV (typical), the on
cycle is immediately terminated. The IS input pin has an internal N-channel MOSFET which pulls it down at the
conclusion of every cycle. The discharge device remains on an additional 240 ns (typical) after the beginning of a
new cycle to blank the leading edge spike on the current sense signal. The leading edge blanking (LEB)
determines the minimum achievable on-time (tON-MIN).
RDS-ON
Sensing
Q1
LM3424
COMP
GATE
0.9V
RLIM
Sensing
PWM
Ramp
IS
0.245V
IT
RLIM
LEB
Ramp
Ramp
Generator
GND
SLOPE
RSLP
Figure 22. Current Sense / Current Limit Circuitry
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Feature Description (continued)
There are two possible methods to sense the transistor current. The RDS-ON of the main power MOSFET can be
used as the current sense resistance because the IS pin was designed to withstand the high voltages present on
the drain when the MOSFET is in the off state. Alternatively, a sense resistor located in the source of the
MOSFET may be used for current sensing, however a low inductance (ESL) type is suggested. The cycle-bycycle current limit (ILIM) can be calculated using either method as the limiting resistance (RLIM):
245 mV
ILIM =
RLIM
(12)
In general, the external series resistor allows for more design flexibility, however it is important to ensure all of
the noise sensitive low power ground connections are connected together local to the controller and a single
connection is made to GND.
7.3.6 Slope Compensation
The LM3424 has programmable slope compensation in order to provide stability over a wide range of operating
conditions. Without slope compensation, a well-known condition called current mode instability (or sub-harmonic
oscillation) can result if there is a perturbation of the MOSFET current sense voltage at the IS pin, due to noise
or a some type of transient.
Through a mathematical / geometrical analysis of the inductor current (IL) and the corresponding control current
(IC, it can be shown that if D < 0.5, the effect of the perturbation will decrease each switching cycle and the
system will remain stable. However, if D > 0.5 then the perturbation will grow as shown in Figure 23, eventually
causing a "period doubling" effect where the effect of the perturbation remains, yielding current mode instability.
Looking at Figure 22, the positive PWM comparator input is the IS voltage, a mirror of IL during tON, plus a typical
900 mV offset. The negative input of the PWM comparator is the COMP pin which is proportional to IC, the
threshold at which the main MOSFET (Q1) is turned off.
The LM3424 mitigates current mode instability by implementing an aritifical ramp (commonly called slope
compensation) which is summed with the sensed MOSFET current at the IS pin as shown in Figure 22. This
combined signal is compared to the COMP pin to generate the PWM signal. An increase in the ramp that is
added to the sense voltage will increase the maximum achievable duty cycle. It should be noted that as the
artificial ramp is increased more and more, the control method approaches standard voltage mode control and
the benefits of current mode control are reduced.
To program the slope compensation, an external resistor, RSLP, is connected from SLOPE to GND. This sets the
slope of the artificial ramp that is added to the MOSFET current sense voltage. A smaller RSLP value will increase
the slope of the added ramp. A simple calculation is suggested to ensure any duty cycle is attainable while
preventing the addition of excessive ramp. This method requires the artifical ramp slope (MA) to be equal to half
the inductor slope during tOFF:
12
VO
7.5 x 10
MA =
=
R T x R SLP x RLIM 2 x L1
(13)
iL (t)
IC
Ideal
iL (t)
Actual
iL (t)
TS
2TS
t
0
Figure 23. "Period Doubling" due to Current Mode Instability
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Feature Description (continued)
7.3.7 Control Loop Compensation
The LM3424 control loop is modeled like any current mode controller. Using a first order approximation, the
uncompensated loop can be modeled as a single pole created by the output capacitor and, in the boost and
buck-boost topologies, a right half plane zero created by the inductor, where both have a dependence on the
LED string dynamic resistance. There is also a high frequency pole in the model, however it is near the switching
frequency and plays no part in the compensation design process therefore it will be neglected. Since ceramic
capacitance is recommended for use with LED drivers due to long lifetimes and high ripple current rating, the
ESR of the output capacitor can also be neglected in the loop analysis. Finally, there is a DC gain of the
uncompensated loop which is dependent on internal controller gains and the external sensing network.
A buck-boost regulator will be used as an example case. See the Application Information section for
compensation of all topologies.
The uncompensated loop gain for a buck-boost regulator is given by the following equation:
§
s ·
¨1 ¸
¨ ZZ1 ¸
©
¹
TU = TU0 x
§
s ·
¸
¨1+
¨ ZP1 ¸
¹
©
(14)
Where the uncompensated DC loop gain of the system is described as:
Dc x 500V x RCSH x RSNS
Dc x 620V
TU0 =
=
(1+ D) x RHSP x R LIM (1+ D) x ILED x R LIM
(15)
And the output pole (ωP1) is approximated:
3
1+ D
ZP1 =
rD x CO
(16)
And the right half plane zero (ωZ1) is:
rD x Dc2
ZZ1 =
D x L1
(17)
100
öZ1
80
135
öP1
90
GAIN
GAIN (dB)
0
40
PHASE
-45
20
0° Phase Margin
-90
0
-20
-135
-40
-180
-60
1e-1
PHASE (°)
45
60
1e1
1e3
1e5
-225
1e7
FREQUENCY (Hz)
Figure 24. Uncompensated Loop Gain Frequency Response
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Feature Description (continued)
Figure 24 shows the uncompensated loop gain in a worst-case scenario when the RHP zero is below the output
pole. This occurs at high duty cycles when the regulator is trying to boost the output voltage significantly. The
RHP zero adds 20dB/decade of gain while loosing 45°/decade of phase which places the crossover frequency
(when the gain is zero dB) extremely high because the gain only starts falling again due to the high frequency
pole (not modeled or shown in figure). The phase will be below -180° at the crossover frequency which means
there is no phase margin (180° + phase at crossover frequency) causing system instability. Even if the output
pole is below the RHP zero, the phase will still reach -180° before the crossover frequency in most cases yielding
instability.
LM3424
ILED
RHSP
HSP
High-Side
Sense Amplifier
CFS
VSNS
RSNS
RHSN
Thermal Foldback Current
HSN
RFS
sets öP3
RCSH
Error Amplifier
CSH
1.24V
sets öP2
CCMP
RO
To PWM
Comparator
COMP
Figure 25. Compensation Circuitry
To mitigate this problem, a compensator should be designed to give adequate phase margin (above 45°) at the
crossover frequency. A simple compensator using a single capacitor at the COMP pin (CCMP) will add a dominant
pole to the system, which will ensure adequate phase margin if placed low enough. At high duty cycles (as
shown in Figure 24), the RHP zero places extreme limits on the achievable bandwidth with this type of
compensation. However, because an LED driver is essentially free of output transients (except catastrophic
failures open or short), the dominant pole approach, even with reduced bandwidth, is usually the best approach.
The dominant compensation pole (ωP2) is determined by CCMP and the output resistance (RO) of the error
amplifier (typically 5 MΩ):
1
ωP2 =
5 x 106Ω x CCMP
(18)
It may also be necessary to add one final pole at least one decade above the crossover frequency to attenuate
switching noise and, in some cases, provide better gain margin. This pole can be placed across RSNS to filter the
ESL of the sense resistor at the same time. Figure 25 shows how the compensation is physically implemented in
the system.
The high frequency pole (ωP3) can be calculated:
1
ZP3 =
RFS x CFS
(19)
The total system transfer function becomes:
§ s ·
¸
¨1 ¨ ZZ1¸
¹
©
T = TU0 x
·
§
§
s
s · §
s ·
¸ ¨
¸ ¨
¸
¨1+
¨ ZP1¸ x ¨1+ ZP2¸ x ¨1+ ZP3¸
¹ ©
¹ ©
¹
©
(20)
The resulting compensated loop gain frequency response shown in Figure 26 indicates that the system has
adequate phase margin (above 45°) if the dominant compensation pole is placed low enough, ensuring stability:
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Feature Description (continued)
90
80
öP2
45
60
0
GAIN
20
0
öZ1
-45
öP1
-90
PHASE
öP3
-20
60° Phase Margin
-40
PHASE (°)
GAIN (dB)
40
-135
-180
-225
-60
-80
1e-1
1e1
1e3
1e5
-270
1e7
FREQUENCY (Hz)
Figure 26. Compensated Loop Gain Frequency Response
7.3.8 Start-Up Regulator and Soft-Start
The LM3424 includes a high voltage, low dropout bias regulator. When power is applied, the regulator is enabled
and sources current into an external capacitor (CBYP) connected to the VCC pin. The recommended bypass
capacitance for the VCC regulator is 2.2 µF to 3.3 µF. The output of the VCC regulator is monitored by an internal
UVLO circuit that protects the device from attempting to operate with insufficient supply voltage and the supply is
also internally current limited.
The LM3424 also has programmable soft-start, set by an external capacitor (CSS), connected from SS to GND.
For CSS to affect start-up, CREF > CNTC must be maintained so that the converter does not start in foldback mode.
Figure 27 shows the typical start-up waveforms for the LM3424 assuming CREF > CNTC.
VCMP
0.9V
0
tVCC
tCMP
tCO
0.9V
0.7V
0
tVCC
tCMP-SS
tSS
tCO
t
Figure 27. Start-up Waveforms
First, CBYP is charged to be above VCC UVLO threshold (~4.2V). The CVCC charging time (tVCC) can be estimated
as:
4.2V
t VCC =
x CBYP = 168: x CBYP
25 mA
(21)
Assuming there is no CSS or if CSS is less than 40% of CCMP , CCMP is then charged to 0.9V over the charging
time (tCMP) which can be estimated as:
t CMP =
20
0.9V
x CCMP = 36 k: x CCMP
25 PA
(22)
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Feature Description (continued)
Once CCMP = 0.9V, the part starts switching to charge CO until the LED current is in regulation. The CO charging
time (tCO) can be roughly estimated as:
V
t CO = CO x O
ILED
(23)
If CSS is greater than 40% of CCMP, the compensation capacitor will only charge to 0.7V over a smaller CCMP
charging time (tCMP-SS) which can be estimated as:
0.70V
t CMP - SS =
x CCMP = 28 k: x CCMP
25 PA
(24)
Then COMP will clamp to SS, forcing COMP to rise (the last 200 mV before switching begins) according to the
CSS charging time (tSS) which can be estimated as:
0. 2V
t SS =
x CSS = 20 k: x CSS
10 PA
(25)
The system start-up time (tSU or tSU-SS) is defined as:
CSS < 0.4 x CCMP
t SU = t VCC + t CMP + t CO
(26)
CSS > 0.4 x CCMP
t SU - SS = t VCC + t CMP- SS + t SS + t CO
(27)
As a general rule of thumb, standard smooth startup operation can be achieved with CSS = CCMP.
7.3.9 Overvoltage Lockout (OVLO)
The LM3424 can be configured to detect an output (or input) over-voltage condition via the OVP pin. The pin
features a precision 1.24V threshold with 20 µA (typical) of hysteresis current as shown in Figure 28. When the
OVLO threshold is exceeded, the GATE pin is immediately pulled low and a 20 µA current source provides
hysteresis to the lower threshold of the OVLO hysteretic band.
If the LEDs are referenced to a potential other than ground (floating), as in the buck-boost and buck
configuration, the output voltage (VO) should be sensed and translated to ground by using a single PNP as
shown in Figure 29.
The over-voltage turn-off threshold (VTURN-OFF) is defined:
Ground Referenced
§R + ROV 2·
¸
VTURN - OFF = 1.24V x ¨¨ OV1
¸
© R OV1 ¹
(28)
Floating
§0.5 x R OV1+ R OV2·
¸
VTURN - OFF = 1.24V x ¨¨
¸
R OV1
¹
©
(29)
In the ground referenced configuration, the voltage across ROV2 is VO - 1.24 V whereas in the floating
configuration it is VO - 620 mV where 620 mV approximates VBE of the PNP.
The over-voltage hysteresis (VHYSO) is defined:
VHYSO = 20 PA x ROV2
(30)
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Feature Description (continued)
LM3424
VO
20 PA
ROV2
OVP
OVLO
1.24V
ROV1
Figure 28. Overvoltage Protection Circuitry
LED+
ROV2
LM3424
LEDOVP
ROV1
Figure 29. Floating Output OVP Circuitry
7.3.10 Input Undervoltage Lockout (UVLO)
The nDIM pin is a dual-function input that features an accurate 1.24V threshold with programmable hysteresis as
shown in Figure 30. This pin functions as both the PWM dimming input for the LEDs and as a VIN UVLO. When
the pin voltage rises and exceeds the 1.24V threshold, 20 µA (typical) of current is driven out of the nDIM pin into
the resistor divider providing programmable hysteresis.
LM3424
VIN
20 PA
RUV2
RUV1
nDIM
1.24V
RUVH
UVLO
(optional)
Figure 30. UVLO Circuit
When using the nDIM pin for UVLO and PWM dimming concurrently, the UVLO circuit can have an extra series
resistor to set the hysteresis. This allows the standard resistor divider to have smaller resistor values minimizing
PWM delays due to a pull-down MOSFET at the nDIM pin (see PWM Dimming section). In general, at least 3V of
hysteresis is preferable when PWM dimming, if operating near the UVLO threshold.
The turn-on threshold (VTURN-ON) is defined as follows:
§R UV1 + RUV2·
¸
¨
VTURN ON
- = 1. 24V x ¨
¸
© RUV1 ¹
22
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Feature Description (continued)
The hysteresis (VHYS) is defined as follows:
7.3.10.1 UVLO Only
VHYS = 20 PA x RUV2
(32)
7.3.10.2 PWM Dimming and UVLO
§
R x (RUV1 + RUV2) ·
¸
VHYS = 20 PA x ¨¨RUV2 + UVH
¸
RUV1
¹
©
(33)
7.3.11 PWM Dimming
The active low nDIM pin can be driven with a PWM signal which controls the main NFET and the dimming FET
(dimFET). The brightness of the LEDs can be varied by modulating the duty cycle of this signal. LED brightness
is approximately proportional to the PWM signal duty cycle, (that is, 30% duty cycle at approximately 30% LED
brightness). This function can be ignored if PWM dimming is not required by using nDIM solely as a VIN UVLO
input as described in the Input Undervoltage Lockout (UVLO) section or by tying it directly to VCC or VIN.
Inverted
PWM
VIN
LM3424
DDIM
RUV2
nDIM
RUVH
RUV1
QDIM
Standard
PWM
Figure 31. PWM Dimming Circuit
Figure 31 shows how the PWM signal is applied to nDIM:
1. Connect the dimming MOSFET (QDIM) with the drain to the nDIM pin and the source to GND. Apply an
external logic-level PWM signal to the gate of QDIM.
2. Connect the anode of a Schottky diode (DDIM) to the nDIM pin. Apply an inverted external logic-level PWM
signal to the cathode of the same diode.
The DDRV pin is a PWM output that follows the nDIM PWM input signal. When the nDIM pin rises, the DDRV pin
rises and the PWM latch reset signal is removed allowing the main MOSFET Q1 to turn on at the beginning of
the next clock set pulse. In boost and buck-boost topologies, the DDRV pin is used to control a N-channel
MOSFET placed in series with the LED load, while it would control a P-channel MOSFET in parallel with the load
for a buck topology.
The series dimFET will open the LED load, when nDIM is low, effectively speeding up the rise and fall times of
the LED current. Without any dimFET, the rise and fall times are limited by the inductor slew rate and dimming
frequencies above 1 kHz are impractical. Using the series dimFET, dimming frequencies up to 30 kHz are
achievable. With a parallel dimFET (buck topology), even higher dimming frequencies are achievable.
When using the PWM functionality in a boost regulator, the PWM signal drives a ground referenced FET.
However, with buck-boost and buck topologies, level shifting circuitry is necessary to translate the PWM dim
signal to the floating dimFET as shown in Figure 32 and Figure 33.
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Feature Description (continued)
When using a series dimFET to PWM dim the LED current, more output capacitance is always better. A general
rule of thumb is to use a minimum of 40 µF when PWM dimming. For most applications, this will provide
adequate energy storage at the output when the dimFET turns off and opens the LED load. Then when the
dimFET is turned back on, the capacitance helps source current into the load, improving the LED current rise
time.
A minimum on-time must be maintained in order for PWM dimming to operate in the linear region of its transfer
function. Because the controller is disabled during dimming, the PWM pulse must be long enough such that the
energy intercepted from the input is greater than or equal to the energy being put into the LEDs. For boost and
buck-boost regulators, the minimum dimming pulse length in seconds (tPULSE) is:
2 x ILED x VO X L1
tPULSE =
VIN2
(34)
Even maintaining a dimming pulse greater than tPULSE, preserving linearity at low dimming duty cycles is difficult.
Several modifications are suggested for applications requiring low dimming duty cycles. Since nDIM rising
releases the latch but does not trigger the on-time specifically, there will be an effective jitter on the rising edge of
the LED current. This jitter can be easily removed by tying the PWM input signal through the synchronization
network at the RT pin (shown in Figure 35), forcing the on-time to synchronize with the nDIM pulse.
The second helpful modification is to remove the CFS capacitor and RFS resistor, eliminating the high frequency
compensation pole. This should not affect stability, but it will speed up the response of the CSH pin, specifically
at the rising edge of the LED current when PWM dimming, thus improving the achievable linearity at low dimming
duty cycles.
LED+
LM3424
10:
5 k:
Q7
100 nF
Q2
VCC
Q6
Q4
RSNS
100 pF
10V
VIN
500:
DDRV
Figure 32. Buck-Boost Level-Shifted PWM Circuit
LM3424
RSNS
100
k:
10V
Q2
100 nF
DDRV
Figure 33. Buck Level-Shifted PWM Circuit
24
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Feature Description (continued)
7.3.12 Thermal Shutdown
The LM3424 includes thermal shutdown. If the die temperature reaches approximately 165°C the device will shut
down (GATE pin low), until it reaches approximately 140°C where it turns on again.
7.4 Device Functional Modes
There are no additional device functional modes for this part.
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8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
8.1.1 Inductor
The inductor (L1) is the main energy storage device in a switching regulator. Depending on the topology, energy
is stored in the inductor and transfered to the load in different ways (as an example, buck-boost operation is
detailed in the Current Regulators section). The size of the inductor, the voltage across it, and the length of the
switching subinterval (tON or tOFF) determines the inductor current ripple (ΔiL-PP). In the design process, L1 is
chosen to provide a desired ΔiL-PP. For a buck regulator the inductor has a direct connection to the load, which is
good for a current regulator. This requires little to no output capacitance therefore ΔiL-PP is basically equal to the
LED ripple current ΔiLED-PP. However, for boost and buck-boost regulators, there is always an output capacitor
which reduces ΔiLED-PP, therefore the inductor ripple can be larger than in the buck regulator case where output
capacitance is minimal or completely absent.
In general, ΔiLED-PP is recommended by manufacturers to be less than 40% of the average LED current (ILED).
Therefore, for the buck regulator with no output capacitance, ΔiL-PP should also be less than 40% of ILED. For the
boost and buck-boost topologies, ΔiL-PP can be much higher depending on the output capacitance value.
However, ΔiL-PP is suggested to be less than 100% of the average inductor current (IL) to limit the RMS inductor
current.
L1 is also suggested to have an RMS current rating at least 25% higher than the calculated minimum allowable
RMS inductor current (IL-RMS).
8.1.2 LED Dynamic Resistance
When the load is a string of LEDs, the output load resistance is the LED string dynamic resistance plus RSNS.
LEDs are PN junction diodes, and their dynamic resistance shifts as their forward current changes. Dividing the
forward voltage of a single LED (VLED) by the forward current (ILED) leads to an incorrect calculation of the
dynamic resistance of a single LED (rLED). The result can be 5 to 10 times higher than the true rLED value.
Figure 34. Dynamic Resistance
Obtaining rLED is accomplished by referring to the manufacturer's LED I-V characteristic. It can be calculated as
the slope at the nominal operating point as shown in Figure 34. For any application with more than 2 series
LEDs, RSNS can be neglected allowing rD to be approximated as the number of LEDs multiplied by rLED.
26
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Application Information (continued)
8.1.3 Output Capacitor
For boost and buck-boost regulators, the output capacitor (CO) provides energy to the load when the recirculating
diode (D1) is reverse biased during the first switching subinterval. An output capacitor in a buck topology will
simply reduce the LED current ripple (ΔiLED-PP) below the inductor current ripple (ΔiL-PP). In all cases, CO is sized
to provide a desired ΔiLED-PP. As mentioned in the Inductor section, ΔiLED-PP is recommended by manufacturers to
be less than 40% of the average LED current (ILED).
CO should be carefully chosen to account for derating due to temperature and operating voltage. It must also
have the necessary RMS current rating. Ceramic capacitors are the best choice due to their high ripple current
rating, long lifetime, and good temperature performance. An X7R dieletric rating is suggested.
8.1.4 Input Capacitors
The input capacitance (CIN) provides energy during the discontinuous portions of the switching period. For buck
and buck-boost regulators, CIN provides energy during tON and during tOFF, the input voltage source charges up
CIN with the average input current (IIN). For boost regulators, CIN only needs to provide the ripple current due to
the direct connection to the inductor. CIN is selected given the maximum input voltage ripple (ΔvIN-PP) which can
be tolerated. ΔvIN-PP is suggested to be less than 10% of the input voltage (VIN).
An input capacitance at least 100% greater than the calculated CIN value is recommended to account for derating
due to temperature and operating voltage. When PWM dimming, even more capacitance can be helpful to
minimize the large current draw from the input voltage source during the rising transistion of the LED current
waveform.
The chosen input capacitors must also have the necessary RMS current rating. Ceramic capacitors are again the
best choice due to their high ripple current rating, long lifetime, and good temperature performance. An X7R
dieletric rating is suggested.
For most applications, it is recommended to bypass the VIN pin with an 0.1 µF ceramic capacitor placed as close
as possible to the pin. In situations where the bulk input capacitance may be far from the LM3424 device, a 10 Ω
series resistor can be placed between the bulk input capacitance and the bypass capacitor, creating a 150 kHz
filter to eliminate undesired high frequency noise.
8.1.5 Main MOSFET and Dimming MOSFET
The LM3424 requires an external NFET (Q1) as the main power MOSFET for the switching regulator. Q1 is
recommended to have a voltage rating at least 15% higher than the maximum transistor voltage to ensure safe
operation during the ringing of the switch node. In practice, all switching regulators have some ringing at the
switch node due to the diode parasitic capacitance and the lead inductance. The current rating is recommended
to be at least 10% higher than the average transistor current. The power rating is then verified by calculating the
power loss given the RMS transistor current and the NFET on-resistance (RDS-ON).
When PWM dimming, the LM3424 requires another MOSFET (Q2) placed in series (or parallel for a buck
regulator) with the LED load. This MOSFET should have a voltage rating greater than the output voltage (VO)
and a current rating at least 10% higher than the nominal LED current (ILED) . The power rating is simply VO
multiplied by RDS-ON, assuming 100% dimming duty cycle (continuous operation) will occur.
In general, the NFETs should be chosen to minimize total gate charge (Qg) when fSW is high and minimize RDS-ON
otherwise. This will minimize the dominant power losses in the system. Frequently, higher current NFETs in
larger packages are chosen for better thermal performance.
8.1.6 Re-Circulating Diode
A re-circulating diode (D1) is required to carry the inductor current during tOFF. The most efficient choice for D1 is
a Schottky diode due to low forward voltage drop and near-zero reverse recovery time. Similar to Q1, D1 is
recommended to have a voltage rating at least 15% higher than the maximum transistor voltage to ensure safe
operation during the ringing of the switch node and a current rating at least 10% higher than the average diode
current. The power rating is verified by calculating the power loss through the diode. This is accomplished by
checking the typical diode forward voltage from the I-V curve on the product datasheet and multiplying by the
average diode current. In general, higher current diodes have a lower forward voltage and come in better
performing packages minimizing both power losses and temperature rise.
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Application Information (continued)
8.1.7 Switching Frequency
The switching frequency of the LM3424 is programmed using an external resistor (RT) connected from the RT pin
to GND as shown in Figure 35.
Alternatively, an external PWM signal can be applied to the RT pin through a filter (RFLT and CFLT) and an ACcoupling capacitor (CAC) to synchronize the part to an external clock as shown in Figure 35. If the external PWM
signal is applied at a frequency higher than the base frequency set by the RT resistor, the internal oscillator is
bypassed and the switching frequency becomes the synchronized frequency. The external synchronization signal
should have a pulse width of 100 ns, an amplitude between 3 V and 6 V, and be AC coupled to the RT pin with a
ceramic capacitor (CAC = 100 pF). A 10-MHz RC filter (RFLT = 150 Ω and CFLT = 100 pF) should be placed
between the PWM signal and CAC to eliminate unwanted high frequency noise from coupling into the RT pin.
The switching frequency is defined:
1
fSW =
1.4 x 10-10 x R T - 1.95 x 10 - 8
(35)
See the Typical Characteristics section for a plot of RT vs. fSW.
LM3424
External Synchronization
RFLT
Start tON
CAC
RT
PWM
CFLT
Oscillator
RT
Figure 35. Timing Circuitry
28
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8.2 Typical Applications
8.2.1 Basic Topology Schematics
L1
D1
VIN
CIN
1
RUV2
2
VIN
LM3424
HSP
HSN
EN
20
RHSP
19
RHSN
18
RSLP
CFS
RSNS
RFS
CCMP
RCSH
RT
3
4
5
COMP
SLOPE
CSH
IS
RT/SYNC
VCC
17
COUT
ROV2
COV
ROV1
ILED
16
CBYP
RUVH
6
RUV1
CSS
RGAIN
7
8
9
GATE
nDIM
GND
SS
DDRV
TGAIN
TSENSE
OVP
15
Q1
14
RLIM
13
Q2
12
DAP
RREF1
10
TREF
VS
11
RREF2
RBIAS
CREF
Q3
CNTC
PWM
NTC
Figure 36. Boost Regulator (VIN < VO)
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Typical Applications (continued)
VIN
CIN
1
RUV2
2
VIN
LM3424
HSP
HSN
EN
20
19
RHSP
CFS
RHSN
RSNS
RFS
CCMP
3
COMP
SLOPE
18
COUT
RSLP
RPU
D2
RCSH
4
CSH
IS
17
Q2
DIM
RT
5
RT/SYNC
VCC
D1
16
L1
CBYP
RUVH
6
GATE
nDIM
ROV2
ILED
Q5
15
Q1
CSS
RUV1
7
GND
SS
14
RLIM
RGAIN
8
TGAIN
DDRV
13
DIM
CDIM
9
OVP
TSENSE
12
DAP
RREF1
10
TREF
VS
COV
11
RREF2
CREF
Q3
PWM
ROV1
RBIAS
NTC
CNTC
Figure 37. Buck Regulator (VIN > VO)
30
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Typical Applications (continued)
D1
VIN
LED+
L1
CIN
1
RUV2
2
LM3424
VIN
ILED
HSP
HSN
EN
RHSP
DIM
RHSN
CFS
20
19
COUT
Q2
RSNS
VIN
RFS
CCMP
3
SLOPE
COMP
18
RSLP
LED+
RCSH
RT
4
IS
CSH
RPU
17
Q7
DIM
5
VCC
RT/SYNC
16
Q6
Q4
CBYP
RUVH
6
RUV1
CSS
RGAIN
GATE
nDIM
ROV2
D2
15
Q5
Q1
VIN
7
8
9
GND
SS
TGAIN
DDRV
OVP
TSENSE
14
RLIM
RSER
13
12
DAP
RREF1
10
TREF
VS
COV
11
RREF2
CREF
Q3
PWM
CNTC
ROV1
RBIAS
NTC
Figure 38. Buck-Boost Regulator
8.2.1.1 Design Requirements
Number of series LEDs: N
Single LED forward voltage: VLED
Single LED dynamic resistance: rLED
Nominal input voltage: VIN
Input voltage range: VIN-MAX, VIN-MIN
Switching frequency: fSW
Current sense voltage: VSNS
Average LED current: ILED
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Typical Applications (continued)
Inductor current ripple: ΔiL-PP
LED current ripple: ΔiLED-PP
Peak current limit: ILIM
Input voltage ripple: ΔvIN-PP
Output OVLO characteristics: VTURN-OFF, VHYSO
Input UVLO characteristics: VTURN-ON, VHYS
Thermal foldback characteristics: TBK, TEND
Total start-up time: tTSU
8.2.1.2 Detailed Design Procedure
8.2.1.2.1 Operating Point
Given the number of series LEDs (N), the forward voltage (VLED) and dynamic resistance (rLED) for a single LED,
solve for the nominal output voltage (VO) and the nominal LED string dynamic resistance (rD):
VO = N ´ VLED
rD = N ´ rLED
(36)
(37)
Solve for the ideal nominal duty cycle (D):
Buck
D=
VO
VIN
(38)
Boost
D=
VO - VIN
VO
(39)
Buck-Boost
D=
VO
VO + VIN
(40)
Using the same equations, find the minimum duty cycle (DMIN) using maximum input voltage (VIN-MAX) and the
maximum duty cycle (DMAX) using the minimum input voltage (VIN-MIN). Also, remember that D' = 1 - D.
8.2.1.2.2 Switching Frequency
Set the switching frequency (fSW) by solving for RT:
RT
1 1.95x10 8 x fSW
1.40x10
10
x fSW
(41)
8.2.1.2.3 Average LED Current
For all topologies, set the average LED current (ILED) knowing the desired current sense voltage (VSNS) and
solving for RSNS:
VSNS
RSNS =
ILED
(42)
If the calculated RSNS is too far from a desired standard value, then VSNS will have to be adjusted to obtain a
standard value.
Setup the suggested signal current of 100 µA by assuming RCSH = 12.4 kΩ and solving for RHSP:
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Typical Applications (continued)
RHSP =
ILED x RCSH x RSNS
1.24V
(43)
If the calculated RHSP is too far from a desired standard value, then RCSH can be adjusted to obtain a standard
value.
8.2.1.2.4 Thermal Foldback
For all topologies, set the thermal foldback breakpoint (TBK) by finding corresponding RNTC-BK from manufacturer's
datasheet and solving for RBIAS:
RREF2
RBIAS = RNTC-BK x
RREF1
(44)
The easiest approach is to set RREF1 = RREF2, therefore setting RBIAS = RNTC-BK will properly set TBK. Remember,
capacitance is recommended at the TSENSE and TREF pins, so ensure CREF > CNTC to prevent start-up in
foldback.
Then set the thermal foldback endpoint (TEND) by finding the corresponding RNTC-END from manufacturer's
datasheet and solving for RGAIN:
·
§
R NTC - END
R REF1
¸
¨
¨RREF1 + RREF2 - RNTC - END + RBIAS ¸ x 2.45V
¹
©
R GAIN =
ICSH
(45)
8.2.1.2.5 Inductor Ripple Current
Set the nominal inductor ripple current (ΔiL-PP) by solving for the appropriate inductor (L1):
Buck
L1 =
(VIN - VO) x D
üiL - PP x fSW
(46)
Boost and Buck-boost
VIN x D
L1=
üiL- PP x fSW
(47)
To set the worst case inductor ripple current, use VIN-MAX and DMIN when solving for L1.
The minimum allowable inductor RMS current rating (IL-RMS) can be calculated as:
Buck
IL-RMS = ILED x
1 § 'IL-PP·
x
1+
¸
12 ¨ ILED
©
2
¹
(48)
Boost and Buck-Boost
1 §'IL-PP x D' ·
x
x 1+
IL-RMS =
¸
12 ¨ ILED
D'
ILED
©
2
¹
(49)
8.2.1.2.6 LED Ripple Current
Set the nominal LED ripple current (ΔiLED-PP), by solving for the output capacitance (CO):
Buck
CO =
'iL - PP
8 x fSW x rD x 'iLED - PP
(50)
Boost and Buck-Boost
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Typical Applications (continued)
CO =
ILED x D
rD xüiLED- PP x fSW
(51)
To set the worst case LED ripple current, use DMAX when solving for CO. Remember, when PWM dimming it is
recommended to use a minimum of 40 µF of output capacitance to improve performance.
The minimum allowable RMS output capacitor current rating (ICO-RMS) can be approximated:
Buck
ICO - RMS =
üiLED - PP
12
(52)
Boost and Buck-Boost
ICO-RMS = ILED x
DMAX
1-DMAX
(53)
8.2.1.2.7 Peak Current Limit
Set the peak current limit (ILIM) by solving for the transistor path sense resistor (RLIM):
245 mV
R LIM =
ILIM
(54)
8.2.1.2.8 Slope Compensation
For all topologies, the preferred method to set slope compensation is to ensure any duty cycle is attainable for
the nominal VO and chosen L by solving for RSLP:
RSLP =
1.5x1013 x L1
VOxR TxR LIM
(55)
8.2.1.2.9 Loop Compensation
Using a simple first order peak current mode control model, neglecting any output capacitor ESR dynamics, the
necessary loop compensation can be determined.
First, the uncompensated loop gain (TU) of the regulator can be approximated:
Buck
TU = TU0 x
1
§
s ·
¨1+
¸
¨ ZP1 ¸
©
¹
(56)
Boost and Buck-Boost
§
s ·
¨1 ¸
¨ ZZ1 ¸
©
¹
TU = TU0 x
§
s ·
¸
¨1+
¨ ZP1 ¸
¹
©
(57)
Where the pole (ωP1) is approximated:
Buck
3
ZP1 =
Boost
(58)
3
ZP1 =
34
1
rD x CO
2
rD x CO
(59)
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Typical Applications (continued)
Buck-Boost
3
1+ D
ZP1 =
rD x CO
(60)
And the RHP zero (ωZ1) is approximated:
Boost
rD x Dc2
L1
(61)
Buck-Boost
rD x Dc2
ZZ1 =
D x L1
(62)
ZZ1 =
And the uncompensated DC loop gain (TU0) is approximated:
Buck
TU0 =
500V x RCSH x RSNS
620V
=
RHSP x R LIM
ILED x RLIM
(63)
Dc x 500V x RCSH x RSNS
Dc x 310V
=
2 x RHSP x R LIM
ILED x R LIM
(64)
Boost
TU0 =
Buck-Boost
Dc x 500V x RCSH x RSNS
Dc x 620V
TU0 =
=
(1+ D) x RHSP x R LIM (1+ D) x ILED x R LIM
(65)
For all topologies, the primary method of compensation is to place a low frequency dominant pole (ωP2) which will
ensure that there is ample phase margin at the crossover frequency. This is accomplished by placing a capacitor
(CCMP) from the COMP pin to GND, which is calculated according to the lower value of the pole and the RHP
zero of the system (shown as a minimizing function):
min(Z P1, ZZ1)
ZP2 =
5 x TU0
(66)
CCMP
1
ZP2 x 5x106
(67)
If analog dimming is used, CCMP should be approximately 4x larger to maintain stability as the LEDs are dimmed
to zero.
A high frequency compensation pole (ωP3) can be used to attenuate switching noise and provide better gain
margin. Assuming RFS = 10Ω, CFS is calculated according to the higher value of the pole and the RHP zero of
the system (shown as a maximizing function):
ZP3 = max (ZP1, ZZ1) x 10
1
CFS =
10 x ZP3
(68)
(69)
The total system loop gain (T) can then be written as:
Buck
T = TU0 x
1
§
s ·
¨1+
¸
¨ ZP1¸ x
©
¹
§
s · §
s ·
¸
¨1+
¸ ¨
¨ ZP2¸ x ¨1+ ZP3¸
¹
©
¹ ©
(70)
Boost and Buck-Boost
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Typical Applications (continued)
§ s ·
¸
¨1 ¨ ZZ1¸
¹
©
T = TU0 x
§
s · §
s · §
s ·
¸ ¨
¸ ¨
¸
¨1+
¨ ZP1¸ x ¨1+ ZP2¸ x ¨1+ ZP3¸
¹ ©
¹ ©
¹
©
(71)
8.2.1.2.10 Input Capacitance
Set the nominal input voltage ripple (ΔvIN-PP) by solving for the required capacitance (CIN):
Buck
CIN =
ILED x (1 - D) x D
'VIN-PP x fSW
(72)
Boost
CIN =
'iL-PP
8 x 'VIN-PP x fSW
(73)
Buck-Boost
CIN =
ILED x D
'VIN-PP x fSW
(74)
Use DMAX to set the worst case input voltage ripple, when solving for CIN in a buck-boost regulator and DMID = 0.5
when solving for CIN in a buck regulator.
The minimum allowable RMS input current rating (ICIN-RMS) can be approximated:
Buck
ICIN - RMS = ILED x DMID x (1-DMID)
(75)
Boost
ICIN-RMS =
'iL-PP
12
(76)
Buck-Boost
ICIN-RMS = ILED x
DMAX
1-DMAX
(77)
8.2.1.2.11 NFET
The NFET voltage rating should be at least 15% higher than the maximum NFET drain-to-source voltage (VTMAX):
Buck
VT - MAX = VIN - MAX
(78)
Boost
VT - MAX = VO
(79)
Buck-Boost
VT - MAX = VIN - MAX + VO
(80)
The current rating should be at least 10% higher than the maximum average NFET current (IT-MAX):
Buck
IT-MAX = DMAX x ILED
(81)
Boost and Buck-Boost
36
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Typical Applications (continued)
IT-MAX =
DMAX
1 - DMAX
x ILED
(82)
Approximate the nominal RMS transistor current (IT-RMS) :
Buck
IT- RMS = ILED x D
(83)
Boost and Buck-Boost
ILED
x D
IT - RMS =
Dc
(84)
Given an NFET with on-resistance (RDS-ON), solve for the nominal power dissipation (PT):
2
PT = IT - RMS x R DSON
(85)
8.2.1.2.12 Diode
The Schottky diode voltage rating should be at least 15% higher than the maximum blocking voltage (VRD-MAX):
Buck
VRD-MAX = VIN-MAX
(86)
Boost
VRD-MAX = VO
(87)
Buck-Boost
VRD-MAX = VIN-MAX + VO
(88)
The current rating should be at least 10% higher than the maximum average diode current (ID-MAX):
Buck
ID-MAX = (1 - DMIN) x ILED
(89)
Boost and Buck-Boost
ID-MAX = ILED
(90)
Replace DMAX with D in the ID-MAX equation to solve for the average diode current (ID). Given a diode with forward
voltage (VFD), solve for the nominal power dissipation (PD):
PD = ID x VFD
(91)
8.2.1.2.13 Output OVLO
For boost and buck-boost regulators, output OVLO is programmed with the turn-off threshold voltage (VTURN-OFF)
and the desired hysteresis (VHYSO). To set VHYSO, solve for ROV2:
VHYSO
ROV2 =
20 PA
(92)
To set VTURN-OFF, solve for ROV1:
Boost
ROV1 =
1.24V x ROV2
VTURN - OFF - 1.24V
(93)
Buck-Boost
R OV1 =
1.24V x R OV2
VTURN - OFF - 620 mV
(94)
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Typical Applications (continued)
A small filter capacitor (COVP = 47 pF) should be added from the OVP pin to ground to reduce coupled switching
noise.
8.2.1.2.14 Input UVLO
For all topologies, input UVLO is programmed with the turn-on threshold voltage (VTURN-ON) and the desired
hysteresis (VHYS).
Method 1: If no PWM dimming is required, a two resistor network can be used. To set VHYS, solve for RUV2:
VHYS
RUV2 =
20 PA
(95)
To set VTURN-ON, solve for RUV1:
1.24V x RUV2
RUV1 =
VTURN - ON - 1.24V
(96)
Method 2: If PWM dimming is required, a three resistor network is suggested. To set VTURN-ON, assume RUV2 =
10 kΩ and solve for RUV1 as in Method 1. To set VHYS, solve for RUVH:
RUVH =
R UV1 x (VHYS - 20 PA x RUV2)
20 PA x (RUV1 + R UV2)
(97)
8.2.1.2.15 Soft-Start
For all topologies, if soft-start is desired, find the start-up time without CSS (tSU):
t SU = t VCC + t CMP + t CO
(98)
Then, if the desired total start-up time (tTSU) is larger than tSU, solve for the base start-up time (tSU-SS-BASE),
assuming that a CSS greater than 40% of CCMP will be used:
V
t SU - SS - BASE = 168: x CBYP + 28 k: x CCMP + O x CO
ILED
(99)
Then solve for CSS:
CSS =
10 PA
x (t TSU - t SU - SS - BASE)
0.2V
(100)
8.2.1.2.16 PWM Dimming Method
PWM dimming can be performed several ways:
Method 1: Connect the dimming MOSFET (Q3) with the drain to the nDIM pin and the source to GND. Apply an
external PWM signal to the gate of QDIM. A pull down resistor may be necessary to properly turn off Q3.
Method 2: Connect the anode of a Schottky diode to the nDIM pin. Apply an external inverted PWM signal to the
cathode of the same diode.
The DDRV pin should be connected to the gate of the dimFET with or without level-shifting circuitry as described
in the PWM Dimming section. The dimFET should be rated to handle the average LED current and the nominal
output voltage.
8.2.1.2.17 Analog Dimming Method
Analog dimming can be performed several ways:
Method 1: Place a potentiometer in place of the thermistor in the thermal foldback circuit shown in the Thermal
Foldback and Analog Dimming section.
Method 2: Place a potentiometer in series with the RCSH resistor to dim the LED current from the nominal ILED to
near zero.
Method 3: Connect a controlled current source as detailed in the Thermal Foldback and Analog Dimming section
to the CSH pin. Increasing the current sourced into the CSH node will decrease the LEDs from the nominal ILED
to zero current in the same manner as the thermal foldback circuit.
38
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Typical Applications (continued)
8.2.2 Buck-Boost Application
10V ± 70V
VIN
D1
L1
CIN
RHSP
1
RUV2
2
CCMP
RCSH
RT
3
4
5
LM3424
VIN
HSP
HSN
EN
COMP
SLOPE
CSH
IS
RT/SYNC
VCC
20
19
1A
ILED
RHSN
COUT
18
RSLP
17
CFS
RSNS
VIN
16
RFS
CBYP
6
RUV1
CSS
RGAIN
7
8
9
GATE
nDIM
GND
SS
DDRV
TGAIN
TSENSE
OVP
15
Q1
14
ROV2
RLIM
13
VIN
Q2
12
DAP
RREF1
10
TREF
VS
COV
11
RREF2
CREF
CNTC
ROV1
RBIAS
NTC
Figure 39. Buck-Boost Application
8.2.2.1 Design Requirements
N=6
VLED = 3.5V
rLED = 325 mΩ
VIN = 24V
VIN-MIN = 10V
VIN-MAX = 70V
fSW = 500 kHz
VSNS = 100 mV
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Typical Applications (continued)
ILED = 1A
ΔiL-PP = 700 mA
ΔiLED-PP = 12 mA
ΔvIN-PP = 100 mV
ILIM = 6A
VTURN-ON = 10V
VHYS = 3V
VTURN-OFF = 40V
VHYSO = 10V
TBK = 70°C
TEND= 120°C
tTSU = 30 ms
8.2.2.2 Detailed Design Procedure
8.2.2.2.1 Operating Point
Solve for VO and rD:
VO = N x VLED = 6 x 3.5V = 21V
(101)
rD = N x rLED = 6 x 325 m: = 1. 95:
(102)
Solve for D, D', DMAX, and DMIN:
VO
21V
D=
=
= 0.467
VO + VIN 21V + 24V
D' = 1 - D = 1 - 0. 467 = 0. 533
VO
21V
=
= 0.231
DMIN =
VO + VIN-MAX 21V + 70V
DMAX =
VO
21V
=
= 0.677
VO + VIN-MIN 21V + 10V
(103)
(104)
(105)
(106)
8.2.2.2.2 Switching Frequency
Solve for RT:
-8
RT =
1+1.95 x 10 x fSW
1.4 x 10
- 10
x fSW
-8
=
1+1.95 x 10 x 500 kHz
= 14.4 kΩ
1.4 x 10-10 x 500 kHz
The closest standard resistor is 14.3 kΩ therefore fSW is:
1
fSW =
- 10
1.4 x 10 x R T - 1.95 x 10 - 8
1
fSW =
- 8 = 504 kHz
- 10
1.4 x 10 x14.3 kΩ - 1.95 x 10
(107)
(108)
The chosen component from step 2 is:
RT = 14.3 k:
(109)
8.2.2.2.3 Average LED Current
Solve for RSNS:
40
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Typical Applications (continued)
RSNS =
VSNS 100 mV
=
= 0.1:
ILED
1A
(110)
Assume RCSH = 12.4 kΩ and solve for RHSP:
ILED x RCSH x RSNS 1A x 12.4 k : x 0.1:
RHSP =
=
= 1.0 k:
1.24V
1.24V
(111)
The closest standard resistor for RSNS is actually 0.1Ω and for RHSP is actually 1 kΩ therefore ILED is:
1.24V x RHSP 1.24V x 1.0 k:
ILED =
=
= 1.0A
R SNS x R CSH 0.1: x 12.4 k:
(112)
The chosen components from step 3 are:
RS NS = 0.1:
R CSH = 12.4 k :
RHSP = RHSN = 1 k:
(113)
8.2.2.2.4 Thermal Foldback
Find the resistances corresponding to TBK and TEND (RNTC-BK = 24.3 kΩ and RNTC-END = 7.15 kΩ) from the
manufacturer's datasheet. Assuming RREF1 = RREF2 = 49.9 kΩ, then RBIAS = RNTC-BK= 24.3 kΩ.
Solve for RGAIN:
R GAIN =
§
·
R NTC - END
RREF1
¨
¸
¨RREF1 + R REF2 - R NTC - END + RBIAS ¸ x 2.45V
©
¹
ICSH
§1
·
7.15 k:
¨¨ ¸¸ x 2.45V
© 2 7.15 k: + 24.3 k: ¹
R GAIN =
= 6.68 k:
100 PA
(114)
The chosen components from step 4 are:
R GAIN = 6.81 k Ω
R BIAS = 24.3 k Ω
R REF1 = R REF2 = 49.9 k Ω
(115)
8.2.2.2.5 Inductor Ripple Current
Solve for L1:
VIN x D
24V x 0. 467
L1 =
=
= 32 PH
'iL- PP x fSW 700 mA x 504 kHz
(116)
The closest standard inductor is 33 µH therefore ΔiL-PP is:
V xD
24V x 0. 467
'iL- PP = IN
= 674 mA
=
L1 x fSW 33 PH x 504 kHz
(117)
Determine minimum allowable RMS current rating:
2
I
1 §¨ 'iL - PP x Dc·¸
x
IL - RMS = LED x 1+
12 ¨© ILED ¸¹
Dc
2
IL - RMS =
1 §674 mA x 0.533· 1.89A
1A
x¨
¸¸ =
x 1+
1A
12 ¨©
0. 533
¹
(118)
The chosen component from step 5 is:
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Typical Applications (continued)
L1 = 33 PH
(119)
8.2.2.2.6 Output Capacitance
Solve for CO:
CO =
CO =
ILED x D
rD x 'iLED- PP x fSW
1A x 0. 467
= 39.6 PF
1.95: x 12 mA x 5 04 kHz
(120)
The closest capacitance totals 40 µF therefore ΔiLED-PP is:
I xD
'iLED- PP = LED
rD x CO x fSW
'iLED- PP =
1A x 0. 467
= 12 mA
1.95 : x 40 PF x 5 04 kHz
(121)
Determine minimum allowable RMS current rating:
ICO- RMS = ILED x
DMAX
0.677
= 1.45A
= 1A x
1- DMAX
1- 0.677
(122)
The chosen components from step 6 are:
CO = 4 x 10 PF
(123)
8.2.2.2.7 Peak Current Limit
Solve for RLIM:
245 mV 245 mV
RLIM =
=
= 0.041:
ILIM
6A
(124)
The closest standard resistor is 0.04 Ω therefore ILIM is:
245 mV 245 mV
ILIM =
=
= 6.13A
RLIM
0.04 :
(125)
The chosen component from step 7 is:
RLIM = 0.04:
(126)
8.2.2.2.8 Slope Compensation
Solve for RSLP:
R SLP =
R SLP =
1.5 x 1013 x L1
VO x R T x RLIM
1. 5 e13 x 33 μH
= 41.2 kΩ
21 V x 14.3 kΩ x 0.04 Ω
(127)
The chosen component from step 8 is:
R SLP = 41.2 kΩ
(128)
8.2.2.2.9 Loop Compensation
ωP1 is approximated:
rad
1.467
1+ D
ZP1 =
=
= 19 k
sec
rD x CO 1.95: x 40 PF
42
(129)
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Typical Applications (continued)
ωZ1 is approximated:
rD x Dc2 1.95: x 0.5332
rad
ZZ1 =
=
= 36k
D x L1 0.467 x 33 PH
sec
(130)
TU0 is approximated:
0.533 x 620V
Dc x 620V
TU0 =
=
= 5630
1
.
467
x 1A x 0.04:
(1+ D) x ILED x R LIM
(131)
To ensure stability, calculate ωP2:
rad
19k
min(ZP1, ZZ1)
ZP1
sec
rad
ZP2 =
=
=
= 0. 675
5 x 5630 5 x 5630
5 x TU0
sec
(132)
Solve for CCMP:
CCMP =
1
1
=
= 0.30 μF
ωP2 x 5 x 106Ω 0.675 rad x 5 x 10 6Ω
sec
(133)
To attenuate switching noise, calculate ωP3:
ZP3 = (max ZP1, ZZ1) x 10 = ZZ1 x 10
ZP3 = 36 k
rad
rad
x 10 = 360k
sec
sec
(134)
Assume RFS = 10Ω and solve for CFS:
1
1
CFS =
=
= 0.28 PF
rad
10: x ZP3
10: x 360k
sec
(135)
The chosen components from step 9 are:
CCMP = 0.33 PF
RFS = 10:
CFS = 0.27PF
(136)
8.2.2.2.10 Input Capacitance
Solve for the minimum CIN:
ILED x D
1A x 0. 467
= 9.27 PF
CIN =
=
'vIN- PP x fSW 100 mV x 504 kHz
(137)
To minimize power supply interaction a 200% larger capacitance of approximately 20 µF is used, therefore the
actual ΔvIN-PP is much lower. Since high voltage ceramic capacitor selection is limited, four 4.7 µF X7R capacitors
are chosen.
Determine minimum allowable RMS current rating:
IIN- RMS = ILED x
DMAX
0.677
= 1.45A
= 1A x
1- DMAX
1- 0.677
(138)
The chosen components from step 10 are:
CIN = 4 x 4.7 PF
(139)
8.2.2.2.11 NFET
Determine minimum Q1 voltage rating and current rating:
VT - MAX = VIN - MAX + VO = 70V + 21V = 91V
(140)
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Typical Applications (continued)
IT- MAX =
0. 677
x 1A = 2.1A
1- 0.677
(141)
A 100V NFET is chosen with a current rating of 32A due to the low RDS-ON = 50 mΩ. Determine IT-RMS and PT:
ILED
1A
IT - RMS =
x 0.467 = 1. 28A
x D=
0. 533
(142)
Dc
2
PT = IT- RMS x RDSON = 1. 28A2 x 50 m: = 82 mW
(143)
The chosen component from step 11 is:
Q1 o 32A, 100V, DPAK
(144)
8.2.2.2.12 Diode
Determine minimum D1 voltage rating and current rating:
VRD - MAX = VIN - MAX + VO = 70V + 21V = 91V
(145)
ID - MAX = ILED = 1A
(146)
A 100V diode is chosen with a current rating of 12A and VDF = 600 mV. Determine PD:
PD = ID x VFD = 1A x 600 mV = 600 mW
(147)
The chosen component from step 12 is:
D1 o 12A, 100V, DPAK
(148)
8.2.2.2.13 Input UVLO
Solve for RUV2:
VHYS
3V
R UV2 =
=
= 150 k:
20 P A 20 PA
(149)
The closest standard resistor is 150 kΩ therefore VHYS is:
VHYS = RUV2 x 20 P A = 150 k: x 20 P A = 3V
(150)
Solve for RUV1:
1.24V x R UV2
1.24V x 150 k:
R UV1 =
=
= 21.2 k:
VTURN - ON - 1.24V
10V -1.24V
(151)
The closest standard resistor is 21 kΩ making VTURN-ON:
VTURN - ON =
1.24V x (R UV1 + R UV2)
R UV1
VTURN- ON =
1.24V x (21 k: + 150 k:)
= 10.1V
21 k:
(152)
The chosen components from step 13 are:
RUV1 = 21 k:
RUV2 = 150 k:
(153)
8.2.2.2.14 Output OVLO
Solve for ROV2:
VHYSO
10V
ROV2 =
=
= 500 k:
20 P A 20 P A
(154)
The closest standard resistor is 499 kΩ therefore VHYSO is:
44
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Typical Applications (continued)
VHYSO = ROV2 x 20 PA = 499 k: x 20 PA = 9.98V
(155)
Solve for ROV1:
1.24V x ROV2
1.24V x 499 k:
R OV1 =
=
= 15.7 k:
VTURN - OFF - 0.62V
40V - 0.62V
(156)
The closest standard resistor is 15.8 kΩ making VTURN-OFF:
VTURN - OFF =
1.24V x (0.5 x R OV1 + R OV2)
R OV1
VTURN- OFF =
1.24V x (0.5 x15.8 k: + 499 k:)
= 39.8V
15.8 k:
(157)
The chosen components from step 14 are:
ROV1 = 15.8 k:
ROV2 = 499 k:
(158)
8.2.2.2.15 Soft-Start
Solve for tSU:
t SU = 168: x CBYP + 36 k: x CCMP +
VO
x CO
ILED
t SU = 168: x 2.2 PF + 36 k: x 0. 33 PF +
21V
x 40 PF
1A
t SU = 13.1 ms
(159)
If tSU is less than tTSU, solve for tSU-SS-BASE:
t SU - SS - BASE = 168: x CBYP + 28 k: x CCMP +
VO
x CO
ILED
t SU
SS BASE
= 168: x 2.2 PF + 28 k: x 0. 33 PF +
t SU
SS BASE
= 10.5 ms
21V
x 40 PF
1A
(160)
Solve for CSS:
(t TSU - t SU - SS - BASE) (30 ms - 10.5 ms)
CSS =
= 975 nF
=
20 k :
20 k :
(161)
The chosen component from step 15 is:
CSS = 1 PF
(162)
Table 1. Bill of Materials
QTY
PART ID
PART VALUE
MANUFACTURER
PART NUMBER
1
LM3424
Boost controller
TI
LM3424MH
1
CBYP
2.2 µF X7R 10% 16V
MURATA
GRM21BR71C225KA12L
2
CCMP, CNTC
0.33 µF X7R 10% 25V
MURATA
GRM21BR71E334KA01L
1
CFS
0.27 µF X7R 10% 25V
MURATA
GRM21BR71E274KA01L
4
CIN
4.7 µF X7R 10% 100V
TDK
C5750X7R2A475K
4
CO
10 µF X7R 10% 50V
TDK
C4532X7R1H106K
1
COV
47 pF COG/NPO 5% 50V
AVX
08055A470JAT2A
1
CREF, CSS
1 µF X7R 10% 25V
MURATA
GRM21BR71E105KA01L
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Typical Applications (continued)
Table 1. Bill of Materials (continued)
QTY
PART ID
PART VALUE
MANUFACTURER
PART NUMBER
1
D1
Schottky 100V 12A
VISHAY
12CWQ10FNPBF
1
L1
33 µH 20% 6.3A
COILCRAFT
MSS1278-333MLB
1
Q1
NMOS 100V 32A
FAIRCHILD
FDD3682
1
Q2
PNP 150V 600 mA
FAIRCHILD
MMBT5401
1
RBIAS
24.3 kΩ 1%
VISHAY
CRCW080524K3FKEA
1
RCSH
12.4 kΩ 1%
VISHAY
CRCW080512K4FKEA
1
RFS
10Ω 1%
VISHAY
CRCW080510R0FKEA
1
RGAIN
6.81 kΩ 1%
VISHAY
CRCW08056K81FKEA
2
RHSP, RHSN
1.0 kΩ 1%
VISHAY
CRCW08051K00FKEA
1
RLIM
0.04Ω 1% 1W
VISHAY
WSL2512R0400FEA
1
ROV1
15.8 kΩ 1%
VISHAY
CRCW080515K8FKEA
1
ROV2
499 kΩ 1%
VISHAY
CRCW0805499KFKEA
2
RREF1, RREF2
49.9 kΩ 1%
VISHAY
CRCW080549K9FKEA
1
RSLP
16.5 kΩ 1%
VISHAY
CRCW080516K5FKEA
1
RSNS
0.1Ω 1% 1W
VISHAY
WSL2512R1000FEA
1
RT
14.3 kΩ 1%
VISHAY
CRCW080514K3FKEA
1
RUV1
21 kΩ 1%
VISHAY
CRCW080521K0FKEA
1
RUV2
150 kΩ 1%
VISHAY
CRCW0805150KFKEA
1
NTC
Thermistor 100 kΩ 5%
TDK
NTCG204H154J
8.2.2.3 Application Curve
100
EFFICIENCY (%)
95
90
85
80
75
70
0
16
32
48
64
80
VIN (V)
Figure 40. Efficiency vs. Input Voltage
46
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8.2.3 Boost Application
8V ± 28V
VIN
D1
L1
CIN
RHSP
1
RUV2
2
VIN
LM3424
HSP
HSN
EN
20
19
CFS
RHSN
RSNS
RFS
CCMP
RCSH
RT
3
4
5
COMP
SLOPE
CSH
IS
RT/SYNC
VCC
18
RSLP
17
1A
ILED
16
COUT
CBYP
RUVH
RUV1
CSS
RGAIN
6
7
8
9
GATE
nDIM
GND
SS
DDRV
TGAIN
TSENSE
OVP
15
Q1
14
RLIM
13
Q2
ROV2
12
DAP
RREF1
10
TREF
VS
COV
11
RREF2
CREF
Q3
PWM
CNTC
ROV1
RBIAS
NTC
Figure 41. Boost Application
8.2.3.1 Design Requirements
• Input: 8 V to 28 V
• Output: 9 LEDs at 1A
• 65°C - 100°C Thermal Foldback
• PWM Dimming up to 30 kHz
• 700 kHz Switching Frequency
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8.2.3.2 Detailed Design Procedure
Table 2. Bill of Materials
QTY
PART ID
PART VALUE
MANUFACTURER
PART NUMBER
1
LM3424
Boost controller
TI
LM3424MH
1
CBYP
2.2 µF X7R 10% 16V
MURATA
GRM21BR71C225KA12L
1
CCMP
0.1 µF X7R 10% 25V
MURATA
GRM21BR71E104KA01L
0
CFS
DNP
4
CIN
4.7 µF X7R 10% 100V
TDK
C5750X7R2A475K
4
COUT
10 µF X7R 10% 50V
TDK
C4532X7R1H106K
1
COV
47 pF COG/NPO 5% 50V
AVX
08055A470JAT2A
2
CNTC, CSS
0.27 µF X7R 10% 25V
MURATA
GRM21BR71E274KA01L
1
CREF
1 µF X7R 10% 25V
MURATA
GRM21BR71E105KA01L
1
D1
Schottky 60V 5A
COMCHIP
CDBC560-G
1
L1
33 µH 20% 6.3A
COILCRAFT
MSS1278-333MLB
2
Q1, Q2
NMOS 60V 8A
VISHAY
SI4436DY
1
Q3
NMOS 60V 115mA
ON-SEMI
2N7002ET1G
1
RBIAS
19.6 kΩ 1%
VISHAY
CRCW080519K6FKEA
2
RCSH, ROV1
12.4 kΩ 1%
VISHAY
CRCW080512K4FKEA
1
RFS
0Ω 1%
VISHAY
CRCW08050000Z0EA
1
RGAIN
6.49 kΩ 1%
VISHAY
CRCW08056K49FKEA
2
RHSP, RHSN
1.0 kΩ 1%
VISHAY
CRCW08051K00FKEA
1
RLIM
0.06Ω 1% 1W
VISHAY
WSL2512R0600FEA
1
ROV2
499 kΩ 1%
VISHAY
CRCW0805499KFKEA
2
RREF1, RREF2
49.9 kΩ 1%
VISHAY
CRCW080549K9FKEA
1
RSNS
0.1Ω 1% 1W
VISHAY
WSL2512R1000FEA
2
RSLP, RUV2
10.0 kΩ 1%
VISHAY
CRCW080510K0FKEA
1
RT
14.3 kΩ 1%
VISHAY
CRCW080514K3FKEA
1
RUV1
1.82 kΩ 1%
VISHAY
CRCW08051K82FKEA
1
RUVH
17.8 kΩ 1%
VISHAY
CRCW080517K8FKEA
1
NTC
Thermistor 100 kΩ 5%
TDK
NTCG204H154J
48
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8.2.4 Buck-Boost Application
10V ± 30V
VIN
D1
L1
CIN
2A
ILED
RHSP
1
RUV2
2
CCMP
RCSH
RT
3
LM3424
VIN
HSP
COUT
HSN
EN
COMP
20
SLOPE
19
18
RHSN
Q2
DIM
RSLP
CFS
RSNS
VIN
4
5
CSH
IS
RT/SYNC
VCC
RFS
17
RPU
16
Q7
RUV1
CSS
6
GATE
nDIM
15
Q6
Q1
GND
SS
14
RLIM
ROV2
Q4
CB
7
CF
DIM
CBYP
RUVH
RF
D2
Q5
RSER
VIN
RGAIN
8
9
DDRV
TGAIN
TSENSE
OVP
13
12
DAP
RREF1
10
TREF
VS
COV
11
RREF2
CREF
Q3
CNTC
PWM
ROV1
RBIAS
RPOT
Figure 42. Buck-Boost Application
8.2.4.1 Design Requirements
• Input: 10V to 30V
• Output: 4 LEDs at 2A
• PWM Dimming up to 10 kHz
• Analog Dimming
• 600-kHz Switching Frequency
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8.2.4.2 Detailed Design Procedures
Table 3. Bill of Materials
QTY
PART ID
PART VALUE
MANUFACTURER
PART NUMBER
1
LM3424
Boost controller
TI
LM3424MH
1
CB
100 pF COG/NPO 5%
50V
MURATA
GRM2165C1H101JA01D
1
CBYP
2.2 µF X7R 10% 16V
MURATA
GRM21BR71C225KA12L
3
CCMP, CREF, CSS
1 µF X7R 10% 25V
MURATA
GRM21BR71E105KA01L
1
CF
0.1 µF X7R 10% 25V
MURATA
GRM21BR71E104KA01L
0
CFS
DNP
4
CIN
6.8 µF X7R 10% 50V
TDK
C5750X7R1H685K
1
CNTC
0.47 µF X7R 10% 25V
MURATA
GRM21BR71E474KA01L
4
COUT
10 µF X7R 10% 50V
TDK
C4532X7R1H106K
1
COV
47 pF COG/NPO 5% 50V
AVX
08055A470JAT2A
1
D1
Schottky 100V 12A
VISHAY
12CWQ10FNPBF
1
D2
Zener 10V 500mA
ON-SEMI
BZX84C10LT1G
1
L1
22 µH 20% 7.2A
COILCRAFT
MSS1278-223MLB
2
Q1, Q2
NMOS 60V 8A
VISHAY
SI4436DY
1
Q3
NMOS 60V 260mA
ON-SEMI
2N7002ET1G
1
Q4
PNP 40V 200 mA
FAIRCHILD
MMBT5087
1
Q5
PNP 150V 600 mA
FAIRCHILD
MMBT5401
1
Q6
NPN 300V 600 mA
FAIRCHILD
MMBTA42
1
Q7
NPN 40V 200 mA
FAIRCHILD
MMBT6428
3
RBIAS, RREF1, RREF2
49.9 kΩ 1%
VISHAY
CRCW080549K9FKEA
2
RCSH, RT
12.4 kΩ 1%
VISHAY
CRCW080512K4FKEA
1
RF
10Ω 1%
VISHAY
CRCW080510R0FKEA
1
RFS
0Ω 1%
VISHAY
CRCW08050000Z0EA
2
RGAIN, RUV2
10.0 kΩ 1%
VISHAY
CRCW080510K0FKEA
2
RHSP, RHSN
1.0 kΩ 1%
VISHAY
CRCW08051K00FKEA
1
RLIM
0.04Ω 1% 1W
VISHAY
WSL2512R0400FEA
1
ROV1
18.2 kΩ 1%
VISHAY
CRCW080518K2FKEA
1
ROV2
499 kΩ 1%
VISHAY
CRCW0805499KFKEA
1
RPOT
50 kΩ potentiometer
BOURNS
3352P-1-503
1
RPU
4.99 kΩ 1%
VISHAY
CRCW08054K99FKEA
1
RSER
499Ω 1%
VISHAY
CRCW0805499RFKEA
1
RSLP
34.0 kΩ 1%
VISHAY
CRCW080534K0FKEA
1
RSNS
0.05Ω 1% 1W
VISHAY
WSL2512R0500FEA
1
RUV1
1.43 kΩ 1%
VISHAY
CRCW08051K43FKEA
1
RUVH
17.4 kΩ 1%
VISHAY
CRCW080517K4FKEA
50
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8.2.5 Boost Application
18V ± 38V
VIN
D1
L1
CIN
RHSP
1
VCC
2
LM3424
VIN
HSP
HSN
EN
20
CFS
RHSN
19
VS
RSNS
RFS
Q4
Q3
CCMP
3
RMAX
4
Q2
RADJ
RBIAS2
RCSH
RT
COMP
SLOPE
CSH
IS
17
5
RT/SYNC
VCC
COUT
700 mA
ILED
VCC
RUV2
16
CBYP
6
RUV1
RSLP
18
CSS
RGAIN
7
8
9
GATE
nDIM
GND
SS
DDRV
TGAIN
TSENSE
OVP
15
Q1
14
RLIM
13
ROV2
12
DAP
RREF1
10
TREF
VS
VS
COV
11
RREF2
CREF
CNTC
ROV1
RBIAS
NTC
Figure 43. Boost Application
8.2.5.1 Design Requirements
• Input: 18V to 38V
• Output: 12 LEDs at 700mA
• 85°C - 125°C Thermal Foldback
• Analog Dimming
• 700 kHz Switching Frequency
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8.2.5.2 Detailed Design Procedure
Table 4. Bill of Materials
QTY
PART ID
PART VALUE
MANUFACTURER
PART NUMBER
1
LM3424
Boost controller
TI
LM3424MH
1
CBYP
2.2 µF X7R 10% 16V
MURATA
GRM21BR71C225KA12L
3
CCMP, CREF, CSS
1 µF X7R 10% 25V
MURATA
GRM21BR71E105KA01L
1
CNTC
0.33 µF X7R 10% 25V
MURATA
GRM21BR71E334KA01L
1
CFS
0.1 µF X7R 10% 25V
MURATA
GRM21BR71E104KA01L
4
CIN
4.7 µF X7R 10% 100V
TDK
C5750X7R2A475K
4
COUT
10 µF X7R 10% 50V
TDK
C4532X7R1H106K
1
COV
47 pF COG/NPO 5% 50V
AVX
08055A470JAT2A
1
D1
Schottky 60V 5A
COMCHIP
CDBC560-G
1
L1
47 µH 20% 5.3A
COILCRAFT
MSS1278-473MLB
1
Q1
NMOS 60V 8A
VISHAY
SI4436DY
1
Q2
NPN 40V 200 mA
FAIRCHILD
MMBT3904
1
Q3, Q4 (dual pack)
Dual PNP 40V 200mA
FAIRCHILD
FFB3906
1
RADJ
100 kΩ potentiometer
BOURNS
3352P-1-104
1
RBIAS
9.76 kΩ 1%
VISHAY
CRCW08059K76FKEA
1
RBIAS2
17.4 kΩ 1%
VISHAY
CRCW080517K4FKEA
3
RCSH, ROV1, RUV1
12.4 kΩ 1%
VISHAY
CRCW080512K4FKEA
1
RFS
10Ω 1%
VISHAY
CRCW080510R0FKEA
1
RGAIN
6.55 kΩ 1%
VISHAY
CRCW08056K55FKEA
3
RHSP, RHSN, RMAX
1.0 kΩ 1%
VISHAY
CRCW08051K00FKEA
1
RLIM
0.06Ω 1% 1W
VISHAY
WSL2512R0600FEA
1
ROV2
499 kΩ 1%
VISHAY
CRCW0805499KFKEA
2
RREF1, RREF2
49.9 kΩ 1%
VISHAY
CRCW080549K9FKEA
2
RSLP, RT
10.0 kΩ 1%
VISHAY
CRCW080510K0FKEA
1
RSNS
0.15Ω 1% 1W
VISHAY
WSL2512R1500FEA
1
RUV2
100 kΩ 1%
VISHAY
CRCW0805100KFKEA
1
NTC
Thermistor 100 kΩ 5%
TDK
NTCG204H154J
52
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8.2.6 Buck-Boost Application
10V ± 70V
VIN
D1
L1
CIN
RHSP
1
RUV2
2
CCMP
RCSH
3
4
LM3424
VIN
HSP
HSN
EN
COMP
SLOPE
CSH
IS
20
19
18
500 mA
ILED
COUT
RHSN
RSLP
DIM
17
Q2
CFS
RSNS
VIN
RT
5
RT/SYNC
VCC
RFS
16
RF
CBYP
RUVH
6
GATE
nDIM
Q7
RPU
15
CF
Q1
DIM
CSS
RUV1
RGAIN
7
GND
SS
Q6
14
8
9
DDRV
TGAIN
TSENSE
OVP
Q4
CB
RSER
ROV2
D2
Q5
13
VIN
12
DAP
RREF1
10
TREF
VS
RREF2
CREF
Q3
COV
11
ROV1
RBIAS
CNTC
PWM
Figure 44. Buck-Boost Application
8.2.6.1 Design Requirements
• Input: 10 V to 70 V
• Output: 6 LEDs at 500 mA
• PWM Dimming up to 10 kHz
• 5-s Fade-up
• MOSFET RDS-ON Sensing
• 700-kHz Switching Frequency
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8.2.6.2 Detailed Design Procedure
Table 5. Bill of Materials
QTY
PART ID
PART VALUE
MANUFACTURER
PART NUMBER
1
LM3424
Boost controller
TI
LM3424MH
1
CB
100 pF COG/NPO 5%
50V
MURATA
GRM2165C1H101JA01D
1
CBYP
2.2 µF X7R 10% 16V
MURATA
GRM21BR71C225KA12L
2
CCMP, CSS
1 µF X7R 10% 25V
MURATA
GRM21BR71E105KA01L
1
CREF
0.01 µF X7R 10% 25V
MURATA
GRM21BR71E103KA01L
1
CF
0.1 µF X7R 10% 25V
MURATA
GRM21BR71E104KA01L
0
CFS
DNP
4
CIN
4.7 µF X7R 10% 100V
TDK
C5750X7R2A475K
1
CNTC
10 µF X7R 10% 10V
MURATA
GRM21BR71A106KE51L
4
COUT
10 µF X7R 10% 50V
TDK
C4532X7R1H106K
1
COV
47 pF COG/NPO 5% 50V
AVX
08055A470JAT2A
1
D1
Schottky 100V 12A
VISHAY
12CWQ10FNPBF
1
D2
Zener 10V 500mA
ON-SEMI
BZX84C10LT1G
1
L1
68 µH 20% 4.3A
COILCRAFT
MSS1278-683MLB
2
Q1, Q2
NMOS 100V 32A
FAIRCHILD
FDD3682
1
Q3
NMOS 60V 260mA
ON-SEMI
2N7002ET1G
1
Q4
PNP 40V 200mA
FAIRCHILD
MMBT5087
1
Q5
PNP 150V 600 mA
FAIRCHILD
MMBT5401
1
Q6
NPN 300V 600mA
FAIRCHILD
MMBTA42
1
Q7
NPN 40V 200mA
FAIRCHILD
MMBT6428
3
RBIAS, RREF1, RREF2
49.9 kΩ 1%
VISHAY
CRCW080549K9FKEA
1
RCSH
12.4 kΩ 1%
VISHAY
CRCW080512K4FKEA
1
RFS
0Ω 1%
VISHAY
CRCW08050000Z0EA
3
RGAIN, RT, RUV2
10.0 kΩ 1%
VISHAY
CRCW080510K0FKEA
2
RHSP, RHSN
1.0 kΩ 1%
VISHAY
CRCW08051K00FKEA
1
ROV1
15.8 kΩ 1%
VISHAY
CRCW080515K8FKEA
1
ROV2
499 kΩ 1%
VISHAY
CRCW0805499KFKEA
1
RPU
4.99 kΩ 1%
VISHAY
CRCW08054K99FKEA
1
RSER
499Ω 1%
VISHAY
CRCW0805499RFKEA
1
RSNS
0.2Ω 1% 1W
VISHAY
WSL2512R2000FEA
1
RSLP
24.3 kΩ 1%
VISHAY
CRCW080524K3FKEA
1
RUV1
1.43 kΩ 1%
VISHAY
CRCW08051K43FKEA
1
RUVH
17.4 kΩ 1%
VISHAY
CRCW080517K4FKEA
54
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8.2.7 Buck Application
15V ± 50V
VIN
L1
CIN
RHSP
1
RUV2
2
VIN
LM3424
HSP
HSN
EN
20
19
CFS
RHSN
RSNS
RFS
CCMP
3
COMP
SLOPE
18
CO
RSLP
RPU
RCSH
RT
4
5
CSH
IS
RT/SYNC
VCC
D2
17
ROV2
Q2
1.25A
ILED
D1
16
L1
CBYP
RUVH
RUV1
CSS
RGAIN
6
7
8
9
GATE
nDIM
GND
SS
DDRV
TGAIN
TSENSE
OVP
Q4
15
Q1
14
CDIM
RLIM
13
12
DAP
RREF1
10
TREF
VS
COV
11
RREF2
CREF
Q3
PWM
CNTC
ROV1
RBIAS
RPOT
Figure 45. Buck Application
8.2.7.1 Design Requirements
• Input: 15 V to 50 V
• Output: 3 LEDS AT 1.25 A
• PWM Dimming up to 50 kHz
• Analog Dimming
• 700-kHz Switching Frequency
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8.2.7.2 Detailed Design Procedure
Table 6. Bill of Materials
QTY
PART ID
PART VALUE
MANUFACTURER
PART NUMBER
1
LM3424
Boost controller
TI
LM3424MH
1
CBYP
2.2 µF X7R 10% 16V
MURATA
GRM21BR71C225KA12L
2
CCMP, CDIM
0.1 µF X7R 10% 25V
MURATA
GRM21BR71E104KA01L
0
CFS
DNP
1
CNTC
0.33 µF X7R 10% 25V
MURATA
GRM21BR71E334KA01L
4
CIN
4.7 µF X7R 10% 100V
TDK
C5750X7R2A475K
0
COUT
DNP
1
COV
47 pF COG/NPO 5% 50V
AVX
08055A470JAT2A
1
CREF, CSS
1 µF X7R 10% 25V
MURATA
GRM21BR71E105KA01L
1
D1
Schottky 100V 12A
VISHAY
12CWQ10FNPBF
1
D2
Zener 10V 500mA
ON-SEMI
BZX84C10LT1G
1
L1
22 µH 20% 7.3A
COILCRAFT
MSS1278-223MLB
1
Q1
NMOS 60V 8A
VISHAY
SI4436DY
1
Q2
PMOS 30V 6.2A
VISHAY
SI3483DV
1
Q3
NMOS 60V 115mA
ON-SEMI
2N7002ET1G
1
Q4
PNP 150V 600 mA
FAIRCHILD
MMBT5401
3
RBIAS, RREF1, RREF2
49.9 kΩ 1%
VISHAY
CRCW080549K9FKEA
1
RCSH
12.4 kΩ 1%
VISHAY
CRCW080512K4FKEA
1
RFS
0Ω 1%
VISHAY
CRCW08050000OZEA
1
RGAIN, RT
10.0 kΩ 1%
VISHAY
CRCW080510K0FKEA
2
RHSP, RHSN
1.0 kΩ 1%
VISHAY
CRCW08051K00FKEA
1
RLIM
0.04Ω 1% 1W
VISHAY
WSL2512R0400FEA
1
ROV1
21.5 kΩ 1%
VISHAY
CRCW080521K5FKEA
1
ROV2
499 kΩ 1%
VISHAY
CRCW0805499KFKEA
1
RPOT
50 kΩ potentiometer
BOURNS
3352P-1-503
2
RPU, RUV2
100 kΩ 1%
VISHAY
CRCW0805100KFKEA
1
RSLP
36.5 kΩ 1%
VISHAY
CRCW080536K5FKEA
1
RSNS
0.08Ω 1% 1W
VISHAY
WSL2512R0800FEA
1
RUV1
11.5 kΩ 1%
VISHAY
CRCW080511K5FKEA
56
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8.2.8 Buck-Boost Application
15V ± 60V
VIN
D1
L1
CIN
RHSP
1
RUV2
2
CCMP
RCSH
3
4
LM3424
VIN
HSP
COUT
HSN
EN
SLOPE
COMP
CSH
20
IS
19
18
RHSN
2.5A
ILED
RSLP
17
RT
CFLT
CAC
5
RT/SYNC
VCC
SYNC
6
CSS
RGAIN
7
8
9
GATE
nDIM
GND
SS
TGAIN
DDRV
OVP
TSENSE
RFS
15
14
RSNS
VIN
CBYP
RFLT
RUV1
CFS
16
Q1
ROV2
RLIM
VIN
13
Q2
12
DAP
RREF1
10
VS
TREF
COV
11
ROV1
RREF2
CREF
RBIAS
CNTC
NTC
Figure 46. Buck-Boost Application
8.2.8.1 Design Requirements
• Input: 15 V to 60 V
• Output: 8 LEDs at 2.5 A
• 80°C to 110°C Thermal Foldback
• 500-kHz Switching Frequency
• External Synchronization > 500 kHz
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8.2.8.2 Detailed Design Procedure
Table 7. Bill of Materials
QTY
PART ID
PART VALUE
MANUFACTURER
PART NUMBER
1
LM3424
Boost controller
TI
LM3424MH
2
CAC, CFLT
100 pF COG/NPO 5%
50V
MURATA
GRM2165C1H101JA01D
1
CBYP
2.2 µF X7R 10% 16V
MURATA
GRM21BR71C225KA12L
3
CCMP, CNTC, CSS
0.33 µF X7R 10% 25V
MURATA
GRM21BR71E334KA01L
1
CFS
0.1 µF X7R 10% 25V
MURATA
GRM21BR71E104KA01L
4
CIN
4.7 µF X7R 10% 100V
TDK
C5750X7R2A475K
4
COUT
10 µF X7R 10% 50V
TDK
C4532X7R1H106K
1
COV
47 pF COG/NPO 5% 50V
AVX
08055A470JAT2A
1
CREF
1 µF X7R 10% 25V
MURATA
GRM21BR71E105KA01L
1
D1
Schottky 100V 12A
VISHAY
12CWQ10FNPBF
1
L1
22 µH 20% 7.2A
COILCRAFT
MSS1278-223MLB
1
Q1
NMOS 100V 32A
FAIRCHILD
FDD3682
1
Q2
PNP 150V 600 mA
FAIRCHILD
MMBT5401
1
RBIAS
11.5 kΩ 1%
VISHAY
CRCW080511K5FKEA
2
RCSH, ROV1
12.4 kΩ 1%
VISHAY
CRCW080512K4FKEA
1
RFS
10Ω 1%
VISHAY
CRCW080510R0FKEA
1
RFLT
150Ω 1%
VISHAY
CRCW0805150RFKEA
1
RGAIN
5.49 kΩ 1%
VISHAY
CRCW08055K49FKEA
2
RHSP, RHSN
1.0 kΩ 1%
VISHAY
CRCW08051K00FKEA
2
RLIM, RSNS
0.04Ω 1% 1W
VISHAY
WSL2512R0400FEA
1
ROV1
15.8 kΩ 1%
VISHAY
CRCW080515K8FKEA
1
ROV2
499 kΩ 1%
VISHAY
CRCW0805499KFKEA
2
RREF1, RREF2
49.9 kΩ 1%
VISHAY
CRCW080549K9FKEA
1
RSLP
20.5 kΩ 1%
VISHAY
CRCW080520K5FKEA
1
RT
14.3 kΩ 1%
VISHAY
CRCW080514K3FKEA
1
RUV1
13.7 kΩ 1%
VISHAY
CRCW080513K7FKEA
1
RUV2
150 kΩ 1%
VISHAY
CRCW0805150KFKEA
1
NTC
Thermistor 100 kΩ 5%
TDK
NTCG204H154J
58
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8.2.9 SEPIC Application
9V ± 36V
VIN
D1
L1
CIN
CSEP
L2
RHSP
1
RUV2
2
VIN
LM3424
HSP
HSN
EN
20
19
CFS
RHSN
RSNS
RFS
CCMP
RCSH
RT
3
4
5
COMP
SLOPE
CSH
IS
RT/SYNC
VCC
18
RSLP
17
750 mA
ILED
16
COUT
CBYP
RUVH
RUV1
CSS
RGAIN
6
7
8
9
GATE
nDIM
GND
SS
DDRV
TGAIN
TSENSE
OVP
15
Q1
14
RLIM
13
Q2
ROV2
12
DAP
RREF1
10
TREF
VS
COV
11
RREF2
CREF
Q3
PWM
CNTC
ROV1
RBIAS
NTC
Figure 47. SEPIC Application
8.2.9.1 Design Requirements
• Input: 9 V to 36 V
• Output: 5 LEDs at 750 mA
• 60°C to 120°C Thermal Foldback
• PWM Dimming up to 30 kHz
• 500-kHz Switching Frequency
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8.2.9.2 Detailed Design Procedure
Table 8. Bill of Materials
QTY
PART ID
PART VALUE
MANUFACTURER
PART NUMBER
1
LM3424
Boost controller
TI
LM3424MH
1
CBYP
2.2 µF X7R 10% 16V
MURATA
GRM21BR71C225KA12L
3
CCMP, CNTC, CSS
0.47 µF X7R 10% 25V
MURATA
GRM21BR71E474KA01L
0
CFS
DNP
4
CIN
4.7 µF X7R 10% 100V
TDK
C5750X7R2A475K
4
COUT
10 µF X7R 10% 50V
TDK
C4532X7R1H106K
1
CSEP
1.0 µF X7R 10% 100V
TDK
C4532X7R2A105K
1
COV
47 pF COG/NPO 5% 50V
AVX
08055A470JAT2A
1
CREF
1 µF X7R 10% 25V
MURATA
GRM21BR71E105KA01L
1
D1
Schottky 60V 5A
COMCHIP
CDBC560-G
2
L1, L2
68 µH 20% 4.3A
COILCRAFT
DO3340P-683
2
Q1, Q2
NMOS 60V 8A
VISHAY
SI4436DY
1
Q3
NMOS 60V 115 mA
ON-SEMI
2N7002ET1G
1
RBIAS
23.7 kΩ 1%
VISHAY
CRCW080523K7FKEA
1
RCSH
12.4 kΩ 1%
VISHAY
CRCW080512K4FKEA
1
RFS
0Ω 1%
VISHAY
CRCW08050000OZEA
1
RGAIN
9.31 kΩ 1%
VISHAY
CRCW08059K31FKEA
2
RHSP, RHSN
750Ω 1%
VISHAY
CRCW0805750RFKEA
1
RLIM
0.04Ω 1% 1W
VISHAY
WSL2512R0400FEA
1
ROV1
15.8 kΩ 1%
VISHAY
CRCW080515K8FKEA
1
ROV2
499 kΩ 1%
VISHAY
CRCW0805499KFKEA
2
RREF1, RREF2
49.9 kΩ 1%
VISHAY
CRCW080549K9FKEA
1
RSLP
20.0 kΩ 1%
VISHAY
CRCW080520K0FKEA
1
RSNS
0.1Ω 1% 1W
VISHAY
WSL2512R1000FEA
1
RT
14.3 kΩ 1%
VISHAY
CRCW080514K3FKEA
1
RUV1
1.62 kΩ 1%
VISHAY
CRCW08051K62FKEA
1
RUV2
10.0 kΩ 1%
VISHAY
CRCW080510K0FKEA
1
RUVH
16.9 kΩ 1%
VISHAY
CRCW080516K9FKEA
1
NTC
Thermistor 100 kΩ 5%
TDK
NTCG204H154J
60
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9 Power Supply Recommendations
9.1 Input Supply Current Limit
It is important to set the output current limit of your input supply to an appropriate value to avoid delays in your
converter analysis and optimization. If not set high enough, current limit can be tripped during start up or when
your converter output power is increased, causing a foldback or shut-down condition. It is a common oversight
when powering up a converter for the first time.
10 Layout
10.1 Layout Guidelines
The performance of any switching regulator depends as much upon the layout of the PCB as the component
selection. Following a few simple guidelines will maximimize noise rejection and minimize the generation of EMI
within the circuit.
Discontinuous currents are the most likely to generate EMI, therefore care should be taken when routing these
paths. The main path for discontinuous current in the LM3424 buck regulator contains the input capacitor (CIN),
the recirculating diode (D1), the N-channel MOSFET (Q1), and the sense resistor (RLIM). In the LM3424 boost
regulator, the discontinuous current flows through the output capacitor (CO), D1, Q1, and RLIM. In the buck-boost
regulator both loops are discontinuous and should be carefully laid out. These loops should be kept as small as
possible and the connections between all the components should be short and thick to minimize parasitic
inductance. In particular, the switch node (where L1, D1, and Q1 connect) should be just large enough to
connect the components. To minimize excessive heating, large copper pours can be placed adjacent to the short
current path of the switch node.
The RT, COMP, CSH, IS, TSENSE, TREF, HSP, and HSN pins are all high-impedance inputs which couple
external noise easily, therefore the loops containing these nodes should be minimized whenever possible.
In some applications the LED or LED array can be far away (several inches or more) from the LM3424, or on a
separate PCB connected by a wiring harness. When an output capacitor is used and the LED array is large or
separated from the rest of the regulator, the output capacitor should be placed close to the LEDs to reduce the
effects of parasitic inductance on the AC impedance of the capacitor.
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10.2 Layout Example
Note critical paths and component placement:
Minimize power loop containing discontinuous currents
Minimize signal current loops (components close to IC)
x
Ground plane under IC for signal routing helps minimize noise coupling
discontinuous switching frequency currents
VIN
1
Input
Power
GND
2
3
4
5
6
PWM
7
8
9
TEMP
VIN
LM3424
EN
HSP
HSN
COMP
SLOPE
CSH
IS
RT/SYNC
VCC
GATE
nDIM
GND
SS
DDRV
TGAIN
TSENSE
OVP
20
19
18
17
16
15
14
13
12
DAP
10
TREF
ILED
STAR GROUND
VS
11
Power Ground
Figure 48. Layout Recommendation
62
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11 Device and Documentation Support
11.1 Device Support
11.1.1 Third-Party Products Disclaimer
TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT
CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES
OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER
ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE.
11.2 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
11.3 Trademarks
PowerPAD, E2E are trademarks of Texas Instruments.
All other trademarks are the property of their respective owners.
11.4 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
11.5 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
LM3424MH/NOPB
ACTIVE
HTSSOP
PWP
20
73
RoHS & Green
SN
Level-1-260C-UNLIM
-40 to 125
LM3424
MH
LM3424MHX/NOPB
ACTIVE
HTSSOP
PWP
20
2500
RoHS & Green
SN
Level-1-260C-UNLIM
-40 to 125
LM3424
MH
LM3424QMH/NOPB
ACTIVE
HTSSOP
PWP
20
73
RoHS & Green
SN
Level-1-260C-UNLIM
-40 to 125
LM3424
QMH
LM3424QMHX/NOPB
ACTIVE
HTSSOP
PWP
20
2500
RoHS & Green
SN
Level-1-260C-UNLIM
-40 to 125
LM3424
QMH
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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