LM3430SDX/NOPB

LM3430 www.ti.com SNVS472B – JANUARY 2007 – REVISED MAY 2013 Boost Controller for LED Backlighting Check for Samples: LM3430 FEATURES DESCRIPTION • • • • • • • • • • • The LM3430 is a high voltage low-side N-channel MOSFET controller. Ideal for use in a boost regulator, the LM3430 can power the LED backlight in LCD panels, such as in notebook PCs. It contains all of the features needed to implement single ended primary topologies. Output voltage regulation is based on current-mode control, which eases the design of loop compensation while providing inherent input voltage feed-forward. The LM3430 includes a start-up regulator that operates over a wide input range of 6V to 40V. The PWM controller is designed for high speed capability including an oscillator frequency range up to 2 MHz and total propagation delays less than 100 ns. Additional features include an error amplifier, precision reference, line under-voltage lockout, cycle-by-cycle current limit, slope compensation, soft-start, external synchronization capability and thermal shutdown. The LM3430 is available in the WSON-12 package. 1 2 Internal 40V Startup Regulator 1A Peak MOSFET Gate Driver VIN Range 6V to 40V Duty Cycle Limit in Excess of 90% Programmable UVLO with Hysteresis Cycle-by-Cycle Current Limit External Synchronizable (AC-coupled) Single Resistor Oscillator Frequency Set Slope Compensation Adjustable Soft-start WSON-12 (3mm x 3mm) APPLICATIONS • • • LED Backlight Driver (companion to LM3432) Boost Converter SEPIC Converter Typical Application VIN VO VDHC NC VIN OUT RT CS LM3430 UVLO GND SS VCC COMP FB 1 2 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. All trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2007–2013, Texas Instruments Incorporated LM3430 SNVS472B – JANUARY 2007 – REVISED MAY 2013 www.ti.com Connection Diagram 1 VDHC NC 12 2 VIN SS 11 3 FB RT 10 CS 9 DAP 4 COMP 5 VCC UVLO 8 6 OUT GND 7 Figure 1. 12-Lead WSON Package PIN DESCRIPTIONS 2 Pin(s) Name Description Application Information 1 VDHC Proprietary control input from LM3432 This pin accepts a control signal from LM3432 to adjust the output voltage in real time. 2 VIN Source input voltage Input to the start-up regulator. Operates from 6V to 40V. 3 FB Feedback pin Inverting input to the internal voltage error amplifier. The non-inverting input of the error amplifier connects to a 1.25V reference. 4 COMP Error amplifier output and PWM comparator input The control loop compensation components connect between this pin and the FB pin. 5 VCC Output of the internal, high voltage linear regulator. This pin should be bypassed to the GND pin with a ceramic capacitor. 6 OUT Output of gate driver Connect this pin to the gate of the external MOSFET. The gate driver has a 1A peak current capability. 7 GND System ground 8 UVLO Input Under-Voltage Lock-out 9 CS 10 RT/SYNC 11 Set the start-up and shutdown levels by connecting this pin to the input voltage through a resistor divider. A 20 µA current source provides hysteresis. Current Sense input Input for the switch current sensing used for current mode control and for current limiting. Oscillator frequency adjust pin and synchronization input An external resistor connected from this pin to GND sets the oscillator frequency. This pin can also accept an ac-coupled input for synchronization from an external clock. SS Soft-start pin An external capacitor placed from this pin to ground will be charged by a 10 µA current source, creating a ramp voltage to control the regulator startup. 12 NC No-connect Leave this pin open-circuit. DAP EP Exposed Pad Thermal connection pad, connect to GND. Submit Documentation Feedback Copyright © 2007–2013, Texas Instruments Incorporated Product Folder Links: LM3430 LM3430 www.ti.com SNVS472B – JANUARY 2007 – REVISED MAY 2013 These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. ABSOLUTE MAXIMUM RATINGS (1) If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/ Distributors for availability and specifications. VALUE / UNIT VIN to GND -0.3 V to 45 V VCC to GND -0.3 V to 16 V RT/SYNC to GND -0.3 V to 5.5 V OUT to GND -1.5 V for < 100 ns All other pins to GND -0.3 V to 7 V Power Dissipation Internally Limited Junction Temperature 150°C Storage Temperature -65°C to +150°C Soldering Information ESD Rating (1) (2) Vapor Phase (60 sec.) 215°C Infrared (15 sec.) 220°C Human Body Model (2) 2 kV Absolute Maximum Ratings are limits beyond which damage to the device may occur. The Recommended Operating Limits define the conditions within which the device is intended to be functional. For specifications and test conditions, see the Electrical Characteristics. The human body model is a 100 pF capacitor discharged through a 1.5kΩ resistor into each pin. RECOMMENDED OPERATING CONDITIONS (1) VALUE / UNIT Supply Voltage 6V to 40V External Volatge at VCC 7.5V to 14V Junction Temperature Range (1) -40°C to +125°C Device thermal limitations may limit usable range. Submit Documentation Feedback Copyright © 2007–2013, Texas Instruments Incorporated Product Folder Links: LM3430 3 LM3430 SNVS472B – JANUARY 2007 – REVISED MAY 2013 www.ti.com ELECTRICAL CHARACTERISTICS Limits in standard type are for TJ = 25°C only; limits in boldface type apply over the junction temperature (TJ) range of -40°C to +125°C. Minimum and Maximum limits are specified through test, design, or statistical correlation. Typical values represent the most likely parametric norm at TJ = 25°C, and are provided for reference purposes only. VIN = 18V and RT = 27.4 kΩ unless otherwise indicated. (Note 3) Symbol Parameter Conditions Min Typ Max Units 1.225 1.250 1.275 V 6.6 7 7.4 3.5 4 SYSTEM PARAMETERS VFB FB Pin Voltage -40°C ≤ TJ ≤ 125°C START-UP REGULATOR VCC Regulation 9V ≤ VIN ≤ 40V, ICC = 1 mA VCC Regulation 6V ≤ VIN < 9V, VCC Pin Open Circuit ICC Supply Current OUT Pin Capacitance = 0, VCC = 10V ICC-LIM VCC Current Limit VCC = 0V, (Note 4, 6) VIN - VCC Dropout Voltage Across Bypass Switch ICC = 0 mA, fSW < 200 kHz, 6V ≤ VIN ≤ 8.5V 200 VBYP-HI Bypass Switch Turn-off Threshold VIN increasing 8.7 V VBYP-HYS Bypass Switch Threshold Hysteresis VIN Decreasing 260 mV VIN = 6.0V 58 VIN = 8.0V 53 VIN = 18.0V 1.1 VCC 5 15 35 V mA mA mV ZVCC VCC Pin Output Impedance 0 mA ≤ ICC ≤ 5 mA VCC-HI VCC Pin UVLO Rising Threshold 5 V VCC-HYS VCC Pin UVLO Falling Hysteresis 300 mV IVIN Start-up Regulator Leakage VIN = 40V 150 500 µA IIN-SD Shutdown Current VUVLO = 0V, VCC = Open Circuit 350 450 µA Ω ERROR AMPLIFIER GBW Gain Bandwidth ADC DC Gain ICOMP COMP Pin Current Sink Capability 4 VFB = 1.5V, VCOMP = 1V MHz 75 dB 5 17 mA 1.22 1.25 1.28 V 16 20 24 µA UVLO VSD Shutdown Threshold ISD-HYS Shutdown Hysteresis Current Source CURRENT LIMIT tLIM-DLY Delay from ILIM to Output VCS Current Limit Threshold Voltage tBLK Leading Edge Blanking Time RCS CS Pin Sink Impedance CS steps from 0V to 0.6V OUT transitions to 90% of VCC 30 0.45 0.5 ns 0.55 65 Blanking active V ns 40 75 Ω SOFT-START ISS Soft-start Current Source 7 10 13 µA VSS-OFF Soft-start to COMP Offset 0.35 0.55 0.75 V OSCILLATOR fSW VSYNC-HI 4 RT to GND = 84.5 kΩ (Note 5) 170 200 230 kHz RT to GND = 27.4 kΩ (Note 5) 525 600 675 kHz RT to GND = 16.2 kΩ (Note 5) 865 990 1115 kHz Synchronization Rising Threshold 3.8 Submit Documentation Feedback V Copyright © 2007–2013, Texas Instruments Incorporated Product Folder Links: LM3430 LM3430 www.ti.com SNVS472B – JANUARY 2007 – REVISED MAY 2013 ELECTRICAL CHARACTERISTICS (continued) Limits in standard type are for TJ = 25°C only; limits in boldface type apply over the junction temperature (TJ) range of -40°C to +125°C. Minimum and Maximum limits are specified through test, design, or statistical correlation. Typical values represent the most likely parametric norm at TJ = 25°C, and are provided for reference purposes only. VIN = 18V and RT = 27.4 kΩ unless otherwise indicated. (Note 3) Symbol Parameter Conditions Min Typ Max Units PWM COMPARATOR tCOMP-DLY Delay from COMP to OUT Transition VCOMP = 2V, CS stepped from 0V to 0.4V DMIN Minimum Duty Cycle VCOMP = 0V 25 ns DMAX Maximum Duty Cycle APWM COMP to PWM Comparator Gain VCOMP-OC COMP Pin Open Circuit Voltage VFB = 0V 4.3 5.2 6.1 V ICOMP-SC COMP Pin Short Circuit Current VCOMP = 0V, VFB = 1.5V 0.6 1.1 1.5 mA 80 105 130 mV 0 90 % 95 % 0.33 V/V SLOPE COMPENSATION VSLOPE Slope Compensation Amplitude MOSFET DRIVER VSAT-HI Output High Saturation Voltage (VCC – VOUT) IOUT = 50 mA 0.25 0.75 V VSAT-LO Output Low Saturation Voltage (VOUT) IOUT = 100 mA 0.25 0.75 V tRISE OUT Pin Rise Time OUT Pin load = 1 nF 18 ns tFALL OUT Pin Fall Time OUT Pin load = 1 nF 15 ns °C THERMAL CHARACTERISTICS TSD Thermal Shutdown Threshold 165 TSD-HYS Thermal Shutdown Hysteresis 25 °C θJA Junction to Ambient Thermal Resistance 122 °C/W DQB-12A Package Submit Documentation Feedback Copyright © 2007–2013, Texas Instruments Incorporated Product Folder Links: LM3430 5 LM3430 SNVS472B – JANUARY 2007 – REVISED MAY 2013 www.ti.com TYPICAL PERFORMANCE CHARACTERISTICS SPACER 6 Efficiency, VO = 40V VFB vs. Temp (VIN = 18V) Figure 2. Figure 3. VFB vs. VIN (TA = 25°C) VCC vs. VIN (TA = 25°C) Figure 4. Figure 5. Max Duty Cycle vs. fSW (TA = 25°C) fSW vs. Temperature (RT = 16.2 kΩ) Figure 6. Figure 7. Submit Documentation Feedback Copyright © 2007–2013, Texas Instruments Incorporated Product Folder Links: LM3430 LM3430 www.ti.com SNVS472B – JANUARY 2007 – REVISED MAY 2013 TYPICAL PERFORMANCE CHARACTERISTICS (continued) SPACER RT vs. fSW (TA = 25°C) SS vs. Temperature Figure 8. Figure 9. OUT Pin tR vs. Gate Capacitance OUT Pin tF vs. Gate Capacitance Figure 10. Figure 11. Submit Documentation Feedback Copyright © 2007–2013, Texas Instruments Incorporated Product Folder Links: LM3430 7 LM3430 SNVS472B – JANUARY 2007 – REVISED MAY 2013 www.ti.com BLOCK DIAGRAM BYPASS SWITCH (6V to 8.7V) V I N VCC 7V SERIES REGULATOR REFERENCE ENABLE + - UVLO 5V 1.25V LOGIC 1.25V UVLO HYSTERESIS CLK (20 PA) RT/SYNC OSC DRIVER VDHC 45 PA VDHC CONTROL Max Duty Limit 0 S Q OUT R Q G N D 5V COMP 5k 1.25V PWM 100 k: F B -+ LOGIC 1.4V 50 k: SS CS 2 k: 0.5V SS 10 PA SS -+ CLK + LEB 8 Submit Documentation Feedback Copyright © 2007–2013, Texas Instruments Incorporated Product Folder Links: LM3430 LM3430 www.ti.com SNVS472B – JANUARY 2007 – REVISED MAY 2013 Example Circuit: LM3430 and LM3432 OTMb To MCU IOUT1 FAULTb DIMMING CONTROL PWM IOUT2 IREF MODE LM3432 VIN IOUT3 IOUT4 CDHC IOUT5 VDHC VCC GND IOUT6 RDHC VIN L1 CIN VDHC CINX RUV2 NC VIN Q1 CO COX OUT UVLO RUV1 LM3430 RT RT VO D1 SS RS1 RS2 CS GND CF VCC CSNS RSNS RFB2 CSS COMP FB R1 C2 RFB1 C1 Figure 12. LM3430 with LM3432 Submit Documentation Feedback Copyright © 2007–2013, Texas Instruments Incorporated Product Folder Links: LM3430 9 LM3430 SNVS472B – JANUARY 2007 – REVISED MAY 2013 www.ti.com APPLICATION PARAMETERS FOR VARIOUS LED CONFIGURATIONS Input Voltage 8V to 21V 8V to 21V 8V to 18V Maximum Output Voltage 33V 50V 33V LED Configuration 8 LEDs x 6 Strings, 20 mA per string 12 LEDs x 6 Strings, 20 mA per string 8 LEDs x 6 Strings, 20 mA per string Switching Frequency 1 MHz 1 MHz 2 MHz L1 22 µH 22 µH 4.7 µH Co 10 µF, 50V 20 µF, 100V 10 µF, 50V Cin 10 µF, 50V 10 µF, 50V 10 µF, 50V Cinx 100 nF 100 nF 100 nF Css 1 nF 1 nF 1 nF Rt 16.5 kΩ 16.5 kΩ 8.25 kΩ Rfb1 4.64 kΩ 3.01 kΩ 16.5 kΩ Rfb2 118 kΩ 118 kΩ 422 kΩ Ruv1 10 kΩ 10 kΩ 10 kΩ Ruv2 49.9 kΩ 49.9 kΩ 49.9 kΩ 12 pF 12 pF 39 pF R1 75 kΩ 118 kΩ 150 kΩ C2 220 nF 47 nF 4.7 nF Rdhc 30 kΩ 9.09 kΩ 60.4 kΩ Rs1 4.02 kΩ 4.02 kΩ 4.02 kΩ Rs2 301Ω 301Ω 301Ω Rsns 0.2Ω (1W) 0.2Ω (1W) Two 1Ω (1W) in parallel Csns 1 nF 1 nF 1 nF Control Loop Compensation C1 VDHC Slope Compensation Current Sensing 10 Submit Documentation Feedback Copyright © 2007–2013, Texas Instruments Incorporated Product Folder Links: LM3430 LM3430 www.ti.com SNVS472B – JANUARY 2007 – REVISED MAY 2013 APPLICATIONS INFORMATION OVERVIEW The LM3430 is a low-side N-channel MOSFET controller that contains all of the features needed to implement single ended power converter topologies. The LM3430 includes a high-voltage startup regulator that operates over a wide input range of 6V to 40V. The PWM controller is designed for high speed capability including an oscillator frequency range up to 2 MHz and total propagation delays less than 100 ns. Additional features include an error amplifier, precision reference, input under-voltage lockout, cycle-by-cycle current limit, slope compensation, soft-start, oscillator sync capability and thermal shutdown. The LM3430 is designed for current-mode control power converters that require a single drive output, such as boost and SEPIC topologies. The LM3430 provides all of the advantages of current-mode control including input voltage feed-forward, cycle-by-cycle current limiting and simplified loop compensation. HIGH VOLTAGE START-UP REGULATOR The LM3430 contains an internal high-voltage startup regulator that allows the VIN pin to be connected directly to line voltages as high as 40V. The regulator output is internally current limited to 35 mA (typical). When power is applied, the regulator is enabled and sources current into an external capacitor, CF, connected to the VCC pin. The recommended capacitance range for CF is 0.1 µF to 100 µF. When the voltage on the VCC pin reaches the rising threshold of 5V, the controller output is enabled. The controller will remain enabled until VCC falls below 4.7V. In applications using a transformer, an auxiliary winding can be connected through a diode to the VCC pin. This winding should raise the VCC pin voltage to above 7.5V to shut off the internal startup regulator. Powering VCC from an auxiliary winding improves conversion efficiency while reducing the power dissipated in the controller. The capacitance of CF must be high enough that the it maintains the VCC voltage greater than the VCC UVLO falling threshold (4.7V) during the initial start-up. During a fault condition when the converter auxiliary winding is inactive, external current draw on the VCC line should be limited such that the power dissipated in the start-up regulator does not exceed the maximum power dissipation capability of the controller. An external start-up or other bias rail can be used instead of the internal start-up regulator by connecting the VCC and the VIN pins together and feeding the external bias voltage (7.5V to 14V) to the two pins. INPUT UNDER-VOLTAGE DETECTOR The LM3430 contains an input Under Voltage Lock Out (UVLO) circuit. UVLO is programmed by connecting the UVLO pin to the center point of an external voltage divider from VIN to GND. The resistor divider must be designed such that the voltage at the UVLO pin is greater than 1.25V when VIN is in the desired operating range. If the under voltage threshold is not met, all functions of the controller are disabled and the controller remains in a low power standby state. UVLO hysteresis is accomplished with an internal 20 µA current source that is switched on or off into the impedance of the set-point divider. When the UVLO threshold is exceeded, the current source is activated to instantly raise the voltage at the UVLO pin. When the UVLO pin voltage falls below the 1.25V threshold the current source is turned off, causing the voltage at the UVLO pin to fall. The UVLO pin can also be used to implement a remote enable / disable function. If an external transistor pulls the UVLO pin below the 1.25V threshold, the converter will be disabled. This external shutdown method is shown in Figure 13. Submit Documentation Feedback Copyright © 2007–2013, Texas Instruments Incorporated Product Folder Links: LM3430 11 LM3430 SNVS472B – JANUARY 2007 – REVISED MAY 2013 www.ti.com VIN VIN RUV2 LM3430 UVLO ON/OFF RUV1 2N7000 or Equivalent GND Figure 13. Enable/Disable Using UVLO ERROR AMPLIFIER An internal high gain error amplifier is provided within the LM3430. The amplifier’s non-inverting input is internally set to a fixed reference voltage of 1.25V. The inverting input is connected to the FB pin. In non-isolated applications such as the boost converter the output voltage, VO, is connected to the FB pin through a resistor divider. The control loop compensation components are connected between the COMP and FB pins. For most isolated applications the error amplifier function is implemented on the secondary side of the converter and the internal error amplifier is not used. The internal error amplifier is configured as an open drain output and can be disabled by connecting the FB pin to ground. An internal 5 kΩ pull-up resistor between a 5V reference and COMP can be used as the pull-up for an opto-coupler in isolated applications. CURRENT SENSING AND CURRENT LIMITING The LM3430 provides a cycle-by-cycle over current protection function. Current limit is accomplished by an internal current sense comparator. If the voltage at the current sense comparator input exceeds 0.5V, the MOSFET gate drive will be immediately terminated. A small RC filter, located near the controller, is recommended to filter noise from the current sense signal. The CS input has an internal MOSFET which discharges the CS pin capacitance at the conclusion of every cycle. The discharge device remains on an additional 65 ns after the beginning of the new cycle to attenuate leading edge ringing on the current sense signal. The LM3430 current sense and PWM comparators are very fast, and may respond to short duration noise pulses. Layout considerations are critical for the current sense filter and sense resistor. The capacitor associated with the CS filter must be located very close to the device and connected directly to the pins of the controller (CS and GND). If a current sense transformer is used, both leads of the transformer secondary should be routed to the sense resistor and the current sense filter network. The current sense resistor can be located between the source of the primary power MOSFET and power ground, but it must be a low inductance type. When designing with a current sense resistor all of the noise sensitive low-power ground connections should be connected together locally to the controller and a single connection should be made to the high current power ground (sense resistor ground point). 12 Submit Documentation Feedback Copyright © 2007–2013, Texas Instruments Incorporated Product Folder Links: LM3430 LM3430 www.ti.com SNVS472B – JANUARY 2007 – REVISED MAY 2013 OSCILLATOR, SHUTDOWN AND SYNC A single external resistor, RT, connected between the RT/SYNC and GND pins sets the LM3430 oscillator frequency. To set the switching frequency, fSW, RT can be calculated from: -8 RT = 1 - 8 x 10 x fSW fSW x 5.77 x 10 -11 (fSW in Hz, RT in :) (1) The LM3430 can also be synchronized to an external clock. The external clock must have a higher frequency than the free running oscillator frequency set by the RT resistor. The clock signal should be capacitively coupled into the RT/SYNC pin with a 100 pF capacitor, shown in Figure 14. A peak voltage level greater than 3.8V at the RT/SYNC pin is required for detection of the sync pulse. The sync pulse width should be set between 15 ns to 150 ns by the external components. The RT resistor is always required, whether the oscillator is free running or externally synchronized. The voltage at the RT/SYNC pin is internally regulated to 2V, and the typical delay from a logic high at the RT/SYNC pin to the rise of the OUT pin voltage is 120 ns. RT should be located very close to the device and connected directly to the pins of the controller (RT/SYNC and GND). LM3430 EXTERNAL CLOCK CSS RT/SYNC 100 pF RT 15 ns to 150 ns EXTERNAL CLOCK 120 ns (Typical) OUT PIN Figure 14. Sync Operation PWM COMPARATOR AND SLOPE COMPENSATION The PWM comparator compares the current ramp signal with the error voltage derived from the error amplifier output. The error amplifier output voltage at the COMP pin is offset by 1.4V and then further attenuated by a 3:1 resistor divider. The PWM comparator polarity is such that 0V on the COMP pin will result in a zero duty cycle at the controller output. For duty cycles greater than 50%, current mode control circuits can experience subharmonic oscillation. By adding an additional fixed-slope voltage ramp signal (slope compensation) this oscillation can be avoided. The LM3430 generates the slope compensation with a 45 µAP-P sawtooth-waveform current source generated by the clock. (See Figure 15) This current flows through an internal 2 kΩ resistor to create a minimum compensation ramp voltage of 100 mV (typical). The amplitude of the compensation ramp increases when external resistance is added for filtering the current sense (RS1) or in the position RS2. As shown in Figure 15 and the block diagram, the sensed current slope and the compensation slope add together to create the signal used for current limiting and for the control loop itself. Submit Documentation Feedback Copyright © 2007–2013, Texas Instruments Incorporated Product Folder Links: LM3430 13 LM3430 SNVS472B – JANUARY 2007 – REVISED MAY 2013 www.ti.com LM3430 ISW 45 uA 0 RS1 RS2 CS 2 k: 0.5V RSNS CSNS + Current Limit VCL Figure 15. Slope Compensation In addition to preventing sub-harmonic oscillation, increasing the amplitude of the compensation ramp voltage decreases the voltage across RSNS required to trip the current limit comparator. This technique can be used to lower the value of RSNS and reduce power dissipation. Care must be taken not to add too much slope compensation, however. Reducing RSNS causes the control loop gain to increase, and too large of a compensation ramp can overwhelm the sensed current signal. This imbalance causes the system to act more like a voltage-mode regulator with a low frequency double pole that is more difficult to compensate. SOFT-START The soft-start feature allows the power converter output to gradually reach the initial steady state output voltage, thereby reducing start-up stresses and current surges. At power on, after the VCC and input under-voltage lockout thresholds are satisfied, an internal 10 µA current source charges an external capacitor connected to the SS pin. The capacitor voltage will ramp up slowly and will limit the COMP pin voltage and the switch current. MOSFET GATE DRIVER The LM3430 provides an internal gate driver through the OUT pin that can source and sink a peak current of 1A to control external, ground-referenced MOSFETs. DYNAMIC HEADROOM CONTROL The VDHC pin of the LM3430 can be used in conjunction with the LM3432 to provide on-the-fly adjustments to the output voltage for maximum efficiency when driving an array of LEDs. When this feature is not being used the VDHC pin should be left open circuit. THERMAL SHUTDOWN Internal thermal shutdown circuitry is provided to protect the LM3430 in the event that the maximum junction temperature is exceeded. When activated, typically at 165°C, the controller is forced into a low power standby state, disabling the output driver and the VCC regulator. After the temperature is reduced (typical hysteresis is 25°C) the VCC regulator will be re-enabled and the LM3430 will perform a soft-start. 14 Submit Documentation Feedback Copyright © 2007–2013, Texas Instruments Incorporated Product Folder Links: LM3430 LM3430 www.ti.com SNVS472B – JANUARY 2007 – REVISED MAY 2013 DESIGN CONSIDERATIONS The most common circuit controlled by the LM3430 is a non-isolated boost regulator. The boost regulator steps up the input voltage and has a duty ratio D of: D= VO - VIN -VD VO - VD (VD is the forward voltage drop of the output diode) (2) The following is a design procedure for selecting all the components for the boost converter portion of the Example Circuit of Figure 12. This circuit operates in continuous conduction mode (CCM), where inductor current stays above 0A at all times, and delivers an output voltage of 33.0V ±2% at an output current of 180 mA. The load is a white LED-based LCD monitor backlight, formed by six parallel strings of seven white LEDs each with a multi-channel linear current regulator to sink 30 mA through each string. The forward voltage of each LED varies from 3.0V to 4.2V over process and temperature and the current regulator requires approximately 4V of headroom. The required output voltage is therefore 7 x 4.2V + 4V ≊ 33V. The input voltage will come from a three-to-four-cell stack of lithium ion batteries (VIN = 9.0V to 16.8V) or a poorly regulated AC-DC adapter that supplies 14.0V to 20.9V. The diode drop VD will be 0.5V, typical of a Schottky diode. SWITCHING FREQUENCY The selection of switching frequency is based on the tradeoffs between size, cost, and efficiency. In general, a lower frequency means larger, more expensive inductors and capacitors will be needed. A higher switching frequency generally results in a smaller but less efficient solution, as the power MOSFET gate capacitances must be charged and discharged more often in a given amount of time. For this application, a frequency of 600 kHz was selected as a good compromise between the size of the inductor and efficiency. PCB area and component height are restricted in this application. Following the equation given for RT in the Applications Information section, a 27.4 kΩ 1% resistor should be used to switch at 600 kHz. MOSFET Selection of the power MOSFET is governed by tradeoffs between cost, size, and efficiency. Breaking down the losses in the MOSFET is one way to determine relative efficiencies between different devices. For this example, the SOIC-8 package provides a balance of a small footprint with good efficiency. Losses in the MOSFET can be broken down into conduction loss, gate charging loss, and switching loss. Conduction, or I2R loss, PC, is approximately: PC = D x IO 1-D 2 x RDSON x 1.3 (3) The factor 1.3 accounts for the increase in MOSFET on resistance due to heating. Alternatively, the factor of 1.3 can be ignored and the on resistance of the MOSFET can be estimated using the RDSON Vs. Temperature curves in the MOSFET datasheets. Gate charging loss, PG, results from the current required to charge and discharge the gate capacitance of the power MOSFET and is approximated as: PG = VCC x QG x fSW (4) QG is the total gate charge of the MOSFET. Gate charge loss differs from conduction and switching losses because the actual dissipation occurs in the LM3430 and not in the MOSFET itself. If no external bias is applied to the VCC pin, additional loss in the LM3430 IC occurs as the MOSFET driving current flows through the VCC regulator. This loss, PVCC, is estimated as: PVCC = (VIN – VCC) x QG x fSW (5) Submit Documentation Feedback Copyright © 2007–2013, Texas Instruments Incorporated Product Folder Links: LM3430 15 LM3430 SNVS472B – JANUARY 2007 – REVISED MAY 2013 www.ti.com Switching loss, PSW, occurs during the brief transition period as the MOSFET turns on and off. During the transition period both current and voltage are present in the channel of the MOSFET. The loss can be approximated as: PSW = 0.5 x VIN x [IO / (1 – D)] x (tR + tF) x fSW Where • tR and tF are the rise and fall times of the MOSFET (6) For this example, the maximum drain-to-source voltage applied across the MOSFET is VO plus the ringing due to parasitic inductance and capacitance. The maximum drive voltage at the gate of the high side MOSFET is VCC, or 7V typical. The MOSFET selected must be able to withstand 33V plus any ringing from drain to source, and be able to handle at least 7V plus ringing from gate to source. A minimum voltage rating of 40VD-S and 10VG-S MOSFET will be used. Comparing the losses in a spreadsheet leads to a 60VD-S rated MOSFET in SO-8 with a typical RDSON of 22 mΩ, a gate charge of 18 nC, and rise and falls times of 10 ns and 12 ns, respectively. BOOST DIODE The boost regulator requires a boost diode D1 (see the Typical Application circuit) to carrying the inductor current during the MOSFET off-time. The most efficient choice for D1 is a Schottky diode due to low forward drop and zero reverse recovery time. D1 must be rated to handle the maximum output voltage plus any switching node ringing when the MOSFET is on. In practice, all switching converters have some ringing at the switching node due to the diode parasitic capacitance and the lead inductance. D1 must also be rated to handle the average output current, IO. The overall converter efficiency becomes more dependent on the selection of D1 at low duty cycles, where the boost diode carries the load current for an increasing percentage of the time. This power dissipation can be calculating by checking the typical diode forward voltage, VD, from the I-V curve on the diode's datasheet and then multiplying it by ID. Diode datasheets will also provide a typical junction-to-ambient thermal resistance, θJA, which can be used to estimate the operating die temperature of the Schottky. Multiplying the power dissipation (PD = IO x VD) by θJA gives the temperature rise. The diode case size can then be selected to maintain the Schottky diode temperature below the operational maximum. In this example a Schottky diode rated to 40V and 0.5A will be suitable, as the maximum diode current will be 180 mA. A small case such as SOD-123 or SOT-23 can be used if a small footprint is critical. Larger case sizes generally have lower θJA and lower forward voltage drop, so for better efficiency, a larger case size such as SMA can be used. In applications with a high boost ratio, such as 1:4, the reverse recovery time, tRR, has a large impact on losses and efficiency. The Schottky diode selected should therefore have a tRR value below 15 ns. BOOST INDUCTOR The first criterion for selecting an inductor is the inductance itself. In fixed-frequency boost converters this value is based on the desired peak-to-peak ripple current, ΔiL, which flows in the inductor along with the average inductor current, IL. For a boost converter in CCM IL is greater than the average output current, IO. The two currents are related by the following expression: IL = IO / (1 – D) (7) As with switching frequency, the inductance used is a tradeoff between size and cost. Larger inductance means lower input ripple current, however because the inductor is connected to the output during the off-time only there is a limit to the reduction in output ripple voltage. Lower inductance results in smaller, less expensive magnetics. An inductance that gives a ripple current of 30% to 50% of IL is a good starting point for a CCM boost converter. Minimum inductance should be calculated at the extremes of input voltage to find the operating condition with the highest requirement: VIN x D L1 = fSW x 'iL (8) By calculating in terms of amperes, volts, and megahertz, the inductance value will come out in microhenrys. 16 Submit Documentation Feedback Copyright © 2007–2013, Texas Instruments Incorporated Product Folder Links: LM3430 LM3430 www.ti.com SNVS472B – JANUARY 2007 – REVISED MAY 2013 In order to ensure that the boost regulator operates in CCM a second equation is needed, and must also be evaluated at the corners of input voltage to find the minimum inductance required: D(1-D) x VIN L2 = IO x fSW (9) By calculating in terms of volts, amps and megahertz the inductance value will come out in microhenrys. For this design ΔiL will be set to 40% of the maximum IL. Duty cycle is evaluated first at VIN(MIN) and at VIN(MAX). Second, the average inductor current is evaluated at the two input voltages. Third, the inductor ripple current is determined. Finally, the inductance can be calculated, and a standard inductor value selected that meets all the criteria. Inductance for Minimum Input Voltage DVIN(MIN) = (33 – 9.0 – 0.5) / (33 – 0.5) = 72% IL-VIN(MIN) = 0.18 / (1 – 0.72) = 0.64A ΔiL = 0.4 x 0.64A = 0.26A L1-VIN(MIN) = L2-VIN(MIN) = 9 x 0.72 = 42 PH 0.6 x 0.26 (10) (11) 0.72 x 0.28 x 9 = 17 PH 0.18 x 0.6 (12) Inductance for Maximum Input Voltage DVIN(MAX) = (33 – 20.9) / 33 = 37% IL-VIN(MIAX) = 0.18 / (1 – 0.37) = 0.29A ΔiL = 0.4 x 0.29A = 0.12A L1-VIN(MAX) = L2-VIN(MAX) = 20.9 x 0.36 = 105 PH 0.6 x 0.12 (13) (14) 0.36 x 0.64 x 20.9 = 45 PH 0.18 x 0.6 (15) Maximum average inductor current occurs at VIN(MIN), and the corresponding inductor ripple current is 0.26AP-P. Selecting an inductance that exceeds the ripple current requirement at VIN(MIN) and the requirement to stay in CCM for VIN(MAX) provides a tradeoff that allows smaller magnetics at the cost of higher ripple current at maximum input voltage. For this example, a 47 µH inductor will satisfy these requirements. The second criterion for selecting an inductor is the peak current carrying capability. This is the level above which the inductor will saturate. In saturation the inductance can drop off severely, resulting in higher peak current that may overheat the inductor or push the converter into current limit. In a boost converter, peak current, IPK, is equal to the maximum average inductor current plus one half of the ripple current. First, the current ripple must be determined under the conditions that give maximum average inductor current: VIN x D 'iL = fSW x L (16) Maximum average inductor current occurs at VIN(MIN). Using the selected inductance of 47 µH yields the following: ΔiL = (9 x 0.72) / (0.6 x 47) = 230 mAP-P (17) The highest peak inductor current over all operating conditions is therefore: IPK = IL + 0.5 x ΔiL = 0.64 + 0.115 = 0.76A (18) Hence an inductor must be selected that has a peak current rating greater than 0.76A and an average current rating greater than 0.64A. One possibility is an off-the-shelf 47 µH ±20% inductor that can handle a peak current of 0.9A and an average current of 0.93A. Finally, the inductor current ripple is recalculated at the maximum input voltage: ΔiL-VIN(MAX) = (20.9 x 0.36) / (0.6 x 47) = 267 mAP-P (19) Submit Documentation Feedback Copyright © 2007–2013, Texas Instruments Incorporated Product Folder Links: LM3430 17 LM3430 SNVS472B – JANUARY 2007 – REVISED MAY 2013 www.ti.com OUTPUT CAPACITOR The output capacitor in a boost regulator supplies current to the load during the MOSFET on-time and also filters the AC portion of the load current during the off-time. This capacitor determines the steady state output voltage ripple, ΔVO, a critical parameter for all voltage regulators. Output capacitors are selected based on their capacitance, CO, their equivalent series resistance (ESR) and their RMS or AC current rating. The magnitude of ΔVO is comprised of three parts, and in steady state the ripple voltage during the on-time is equal to the ripple voltage during the off-time. For simplicity the analysis will be performed for the MOSFET turning off (off-time) only. The first part of the ripple voltage is the surge created as the output diode D1 turns on. At this point inductor/diode current is at the peak value, and the ripple voltage increase can be calculated as: ΔVO1 = IPK x ESR (20) The second portion of the ripple voltage is the increase due to the charging of CO through the output diode. This portion can be approximated as: ΔVO2 = (IO / CO) x (D / fSW) (21) The final portion of the ripple voltage is a decrease due to the flow of the diode/inductor current through the output capacitor’s ESR. This decrease can be calculated as: ΔVO3 = ΔiL x ESR (22) The total change in output voltage is then: ΔVO = ΔVO1 + ΔVO2 - ΔVO3 (23) The combination of two positive terms and one negative term may yield an output voltage ripple with a net rise or a net fall during the converter off-time. The ESR of the output capacitor(s) has a strong influence on the slope and direction of ΔVO. Capacitors with high ESR such as tantalum and aluminum electrolytic create an output voltage ripple that is dominated by ΔVO1 and ΔVO3, with a shape shown in Figure 16. Ceramic capacitors, in contrast, have very low ESR and lower capacitance. The shape of the output ripple voltage is dominated by ΔVO2, with a shape shown in Figure 17. ÂvO VO ID Figure 16. ΔVO Using High ESR Capacitors 18 Submit Documentation Feedback Copyright © 2007–2013, Texas Instruments Incorporated Product Folder Links: LM3430 LM3430 www.ti.com SNVS472B – JANUARY 2007 – REVISED MAY 2013 ÂvO VO ID Figure 17. ΔVO Using Low ESR Capacitors For this example, the load is fairly constant, and the height restriction favors the low profile of ceramic capacitors. The output ripple voltage waveform of Figure 17 is assumed, and the capacitance will be selected first. The desired ΔVO is ±2% of 33V, or 1.32VP-P. Beginning with the calculation for ΔVO2, the required minimum capacitance is: CO-MIN = (IO / ΔVO) x (DMAX / fSW) CO-MIN = (0.18 / 1.32) x (0.72 / 600000) = 164 nF (24) Ceramic capacitors rated 1.0 µF ±20% are available from many manufacturers. The minimum quality dielectric that is suitable for switching power supply output capacitors is X5R, while X7R (or better) is preferred. Careful attention must be paid to the DC voltage rating and case size, as ceramic capacitors can lose 60%+ of their rated capacitance at the maximum DC voltage. For example, the typical loss in capacitance for a 1.0 µF, 50V, 1206-size capacitor is 50% at 30V. This is the reason that ceramic capacitors are often de-rated to 50% of their capacitance at their working voltage. The ESR of the selected capacitor has a typical value of 3 mΩ. The worst-case value for ΔVO1 occurs during the peak current at minimum input voltage: ΔVO1 = 1.26 x 0.003 = 3.8 mV (25) The worst-case capacitor charging ripple occurs at maximum duty cycle, taking into account an output capacitance of 50% x 1 µF = 500 nF: ΔVO2 = (0.18 / 5 x 10-7) x (0.72 / 600000) = 432 mV (26) Finally, the worst-case value for ΔVO3 occurs when inductor ripple current is highest, at maximum input voltage: ΔVO3 = 0.398 x 0.003 = 1.2 mV (negligible) (27) The output voltage ripple can be estimated by summing the three terms: ΔVO = 3.8 mV + 432 mV - 1.2 mV = 435 mV (28) The RMS current through the output capacitor(s) can be estimated using the following, worst-case equation: IO-RMS = 1.13 x IL x D x (1 - D) (29) The highest RMS current occurs at minimum input voltage. For this example the maximum output capacitor RMS current is: IO-RMS(MAX) = 1.13 x 0.64 x (0.72 x 0.28)0.5 = 0.32ARMS (30) Ceramic capacitors in 1206 case sizes are generally capable of sustaining RMS currents in excess of 2A, making them more than adequate for this application. Submit Documentation Feedback Copyright © 2007–2013, Texas Instruments Incorporated Product Folder Links: LM3430 19 LM3430 SNVS472B – JANUARY 2007 – REVISED MAY 2013 www.ti.com VCC DECOUPLING CAPACITOR The VCC pin should be decoupled with a ceramic capacitor placed as close as possible to the VCC and GND pins of the LM3430. The decoupling capacitor should have a minimum X5R or X7R type dielectric to ensure that the capacitance remains stable over voltage and temperature, and be rated to a minimum of 470 nF. One good choice is a 1.0 µF device with X7R dielectric and 1206 case size rated to 25V. INPUT CAPACITOR The input capacitors to a boost regulator control the input voltage ripple, ΔVIN, hold up the input voltage during load transients, and prevent impedance mismatch (also called power supply interaction) between the LM3430 and the inductance of the input leads. Selection of input capacitors is based on their capacitance, ESR, and RMS current rating. The minimum value of ESR can be selected based on the maximum output current transient, ISTEP, using the following expression: (1-D) x 'vIN ESRMIN = 2 x ISTEP (31) For this example, no specific load transient is given, hence ISTEP is set equal to the maximum load current of 180 mA. The desired ΔVIN is 4%P-P. ΔVIN and duty cycle are taken at minimum input voltage to give the worst-case value: ESRMIN = [(1 – 0.72) x 0.36] / 0.36 = 0.28Ω (32) The minimum input capacitance can be selected based on ΔVIN, based on the drop in VIN during a load transient, or based on prevention of power supply interaction. In general, the requirement for greatest capacitance comes from the power supply interaction. The inductance and resistance of the input source must be estimated, and if this information is not available, they can be assumed to be 1 µH and 0.1Ω, respectively. Minimum capacitance is then estimated as: 2 x LS x VO x IO CMIN = 2 V IN x RS (33) As with ESR, the worst-case, highest minimum capacitance calculation comes at the minimum input voltage. Using the default estimates for LS and RS, minimum capacitance is: CMIN = 2 x 1 x 33 x 0.18 = 1.5 PF 2 9 x 0.1 (34) The closest standard 20% capacitor value is 1.5 µF, but because the actual input source impedance and resistance are not known, a 3.3 µF capacitor will be used. In general, doubling the calculated value of input capacitance provides a good safety margin. The final calculation is for the RMS current. For boost converters operating in CCM this can be estimated as: IRMS = 0.29 x ΔiL(MAX) (35) From the inductor section, maximum inductor ripple current is 267 mA, hence the input capacitor(s) must be rated to handle 0.29 x 0.267 = 77 mARMS. The input capacitors can be ceramic, tantalum, aluminum, or almost any type, however the low capacitance requirement makes ceramic capacitors particularly attractive. As with the output capacitors, the minimum quality dielectric used should X5R, with X7R or better preferred. The voltage rating for input capacitors need not be as conservative as the output capacitors, as the need for capacitance decreases as input voltage increases. For this example, the capacitor selected will be 3.3 µF ±20%, rated to 25V, in a 1206 case size. The RMS current rating is over 1A, more than enough for this application. CURRENT SENSE FILTER Parasitic circuit capacitance, inductance and gate drive current create a spike in the current sense voltage at the point where Q1 turns on. In order to prevent this spike from terminating the on-time prematurely, every circuit should have a low-pass filter that consists of CCS and RS1, shown in Figure 12. The time constant of this filter should be long enough to reduce the parasitic spike without significantly affecting the shape of the actual current sense voltage. The recommended range for RS1 is between 10Ω and 500Ω, and the recommended range for CCS is between 100 pF and 2.2 nF. For this example, the values of RS1 and CCS will be 100Ω and 1 nF, respectively. 20 Submit Documentation Feedback Copyright © 2007–2013, Texas Instruments Incorporated Product Folder Links: LM3430 LM3430 www.ti.com SNVS472B – JANUARY 2007 – REVISED MAY 2013 RSNS AND CURRENT LIMIT The current sensing resistor RSNS is used for steady state regulation of the inductor current and to sense overcurrent conditions. The resistance value selected must be low enough to keep the power dissipation to a minimum, yet high enough to provide good signal-to-noise ratio for the current sensing circuitry. The resistance should be set so that the current limit comparator, with a threshold of 0.5V, trips before the sensed current exceeds the peak current rating of the inductor. For this example the inductor peak current rating is 0.9A. The threshold for current limit, ILIM, is set slightly below to account for tolerance of the circuit components, at a level of 0.8A. The required resistor calculation must take into account both the switch current through RSNS and the compensation ramp current flowing through the internal 2 kΩ and external 100Ω resistors: RSNS = VCS ± 45 PA x (2 k: + RS1 + RS2) ILIM (36) (37) RSNS = [0.5 - 45µ x (2000 + 100)] / 0.8 = 0.51Ω Power dissipation in RSNS can be estimated by calculating the average current. The worst-case average current through RSNS occurs at minimum input voltage/maximum duty cycle and can be calculated as: PCS = IO 2 1-D x RSNS x D (38) (39) 2 PCS = [(0.18 / 0.27) x 0.51] x 0.73 = 0.16W For this example a 0.51Ω ±1%, thick-film chip resistor in a 1206 case size rated to 0.33W will be used. CONTROL LOOP COMPENSATION The LM3430 uses peak current-mode PWM control to correct changes in output voltage due to line and load transients. Peak current-mode provides inherent cycle-by-cycle current limiting, improved line transient response, and easier control loop compensation. The control loop is comprised of two parts. The first is the power stage, which consists of the pulse width modulator, output filter, and the load. The second part is the error amplifier, which is an op-amp configured as an inverting amplifier. Figure 18 shows the regulator control loop components. L + C O D VIN + - RO RSNS RC + RFB2 R1 C2 C1 + VREF RFB1 + - Figure 18. Power Stage and Error Amp Submit Documentation Feedback Copyright © 2007–2013, Texas Instruments Incorporated Product Folder Links: LM3430 21 LM3430 SNVS472B – JANUARY 2007 – REVISED MAY 2013 www.ti.com One popular method for selecting the compensation components is to create Bode plots of gain and phase for the power stage and error amplifier. Combined, they make the overall bandwidth and phase margin of the regulator easy to determine. Software tools such as Excel, MathCAD, and Matlab are useful for observing how changes in compensation or the power stage affect system gain and phase. The power stage in a CCM peak current mode boost converter consists of the DC gain, APS, a single low frequency pole, fLFP, the ESR zero, fZESR, a right-half plane zero, fRHP, and a double pole resulting from the sampling of the peak current. The power stage transfer function (also called the Control-to-Output transfer function) can be written: 1+ GPS = APS x s s ZZESR 1 - ZRHP s s s2 1+ Z 1 + Q x + n LEP Z2n Zn Where the DC gain is defined as: (1 - D) x RO APS = 2 x RSNS (40) (41) Where: RO = VO / IO (42) The system ESR zero is: ZZESR = 1 RC x C O (43) The low frequency pole is: ZLEP = 1 0.5 x (RO + ESR) x CO (44) The right-half plane zero is: VIN 2 RO x VO ZRHP = L (45) The sampling double pole quality factor is: 1 Qn = S -D + 0.5 + (1 - D) Se Sn (46) The sampling double corner frequency is: ωn = π x fSW (47) The natural inductor current slope is: Sn = RSNS x VIN / L (48) The external ramp slope is: Se = 45 µA x (2000 + RS1 + RS2)] x fSW (49) In the equation for APS, DC gain is highest when input voltage is at the maximum and output current is at the lower threshold of CCM operation. (IL = 0.5 x ΔiL) In this the example those conditions are VIN = 20.9V and IO = 180 mA. 22 Submit Documentation Feedback Copyright © 2007–2013, Texas Instruments Incorporated Product Folder Links: LM3430 LM3430 www.ti.com SNVS472B – JANUARY 2007 – REVISED MAY 2013 Maximum DC gain is 44 dB. The low frequency pole fP = 2πωP is at 1.9 kHz, the ESR zero fZ = 2πωZ is at 80 MHz, and the right-half plane zero fRHP = 2πωRHP is at 230 kHz. The sampling double-pole occurs at one-half of the switching frequency. Gain and phase plots for the power stage are shown in Figure 19. POWER STAGE GAIN (dB) 60 45 30 15 0 -15 -30 100 1k 10k 100k 1M FREQUENCY (Hz) POWER STAGE PHASE (°) 180 120 60 0 -60 -120 -180 100 1k 10k 100k 1M FREQUENCY (Hz) Figure 19. Power Stage Gain and Phase The single pole causes a roll-off in the gain of -20 dB/decade at lower frequency, which then flattens out due to the RHP zero. The sharp drop in gain beginning around 200 kHz is a result of the sampling double pole. The phase tends towards -90° at lower frequency but then increases to -180° from the RHP zero and the sampling double pole. The effect of the ESR zero is not seen because its frequency is several decades above the switching frequency. The combination of increasing gain and decreasing phase makes converters with RHP zeroes difficult to compensate. Setting the overall control loop bandwidth to 1/3 to 1/10 of the RHP zero frequency minimizes these negative effects. If this loop were left uncompensated, the bandwidth would be 312 kHz and the phase margin -100°. The converter would oscillate, and therefore is compensated using the error amplifier and a few passive components. Submit Documentation Feedback Copyright © 2007–2013, Texas Instruments Incorporated Product Folder Links: LM3430 23 LM3430 SNVS472B – JANUARY 2007 – REVISED MAY 2013 www.ti.com The transfer function of the compensation block, GEA, can be derived by treating the error amplifier as an inverting op-amp with input impedance ZI and feedback impedance ZF. The majority of applications will require a Type II, or two-pole one-zero amplifier, shown in Figure 18. The LaPlace domain transfer function for this Type II network is given by the following: GEA = ZF ZI = 1 X RFB2 (C1 + C2) s x R1 x C1 +1 s x R1 x C1 x C2 s +1 C1 + C2 (50) Many techniques exist for selecting the compensation component values. The following method is based upon setting the mid-band gain of the error amplifier transfer function first and then positioning the compensation zero and pole: 1. Determine the desired control loop bandwidth:The control loop bandwidth, f0dB, is the point at which the total control loop gain (H = GPS x GEA) is equal to 0 dB. For this example, a low bandwidth of 30 kHz, or approximately 1/8th of the RHP zero frequency, is chosen because of the wide variation in input voltage. 2. Determine the gain of the power stage at f0dB:This value, A, can be read graphically from the gain plot of GPS or calculated by replacing the ‘s’ terms in GPS with ‘2πf0dB’. For this example the gain at 30 kHz is approximately 20 dB. 3. Calculate the negative of A and convert it to a linear gain:By setting the mid-band gain of the error amplifier to the negative of the power stage gain at f0dB, the control loop gain will equal 0 dB at that frequency. For this example, -20 dB = 0.1V/V. 4. Select the resistance of the top feedback divider resistor RFB2:This value is arbitrary, however selecting a resistance between 10 kΩ and 100 kΩ will lead to practical values of R1, C1 and C2. For this example, RFB2 = 20 kΩ 1%. 5. Set R1 = A x RFB2:For this example: R1 = 0.1 x 20000 = 2 kΩ 6. Select a frequency for the compensation zero, fZ1:The suggested placement for this zero is at the low frequency pole of the power stage, fLFP = ωLFP / 2π. For this example, fZ1 = fLFP = 1.9 kHz 7. Set C2 = 1 : 2S x R1 x fZ1 (51) For this example, C2 = 41.2 nF 8. Select a frequency for the compensation pole, fP1:The suggested placement for this pole is at one-half of the switching frequency. For this example, fP1 = 200 kHz 9. Set C1 = C2 : 2S x C2 x R1 x fP1 -1 (52) For this example, C1 = 401 pF 10. Plug the closest 1% tolerance values for RFB2 and R1, then the closest 10% values for C1 and C2 into GEA and model the error amp:The open-loop gain and bandwidth of the LM3430’s internal error amplifier are 75 dB and 4 MHz, respectively. Their effect on GEA can be modeled using the following expression: 2S x GBW OPG = 2S x GBW s+ ADC (53) ADC is a linear gain, the linear equivalent of 75 dB is approximately 5600V/V. C1 = 390 pF 10%, C2 = 39 nF 10%, R1 = 2 kΩ 1% 11. Plot or evaluate the actual error amplifier transfer function: GEA-ACTUAL = 24 GEA x OPG 1 + GEA x OPG (54) Submit Documentation Feedback Copyright © 2007–2013, Texas Instruments Incorporated Product Folder Links: LM3430 LM3430 www.ti.com SNVS472B – JANUARY 2007 – REVISED MAY 2013 20 60 10 40 OVERALL LOOP GAIN (dB) ERROR AMP GAIN (dB) 12. Plot or evaluate the complete control loop transfer function: The complete control loop transfer function is obtained by multiplying the power stage and error amplifier functions together. The bandwidth and phase margin can then be read graphically or evaluated numerically. The bandwidth of this example circuit is 34 kHz, with a phase margin of 60°. 0 -10 -20 -30 -40 100 1k 10k 100k 20 0 -20 -40 -60 100 1M 1k 180 180 120 120 60 0 -60 -120 -180 100 1k 10k 100k 1M FREQUENCY (Hz) OVERALL LOOP PHASE (°) ERROR AMP PHASE (°) FREQUENCY (Hz) 10k 100k 1M 60 0 -60 -120 -180 100 FREQUENCY (Hz) 1k 10k 100k 1M FREQUENCY (Hz) Figure 20. Error Amplifier Gain and Phase Figure 21. Overall Loop Gain and Phase Efficiency Calculations A reasonable estimation for the efficiency of a boost regulator controlled by the LM3430 can be obtained by adding together the loss is each current carrying element and using the equation: K= PO PO + Ptotal-loss (55) The following shows an efficiency calculation to complement the circuit design from the Design Considerations section. Output power for this circuit is 33V x 0.18A = 5.9W. Input voltage is assumed to be 12V, and the calculations used assume that the converter runs in CCM. Duty cycle for VIN = 12V is 63%, and the average inductor current is 0.49A. Submit Documentation Feedback Copyright © 2007–2013, Texas Instruments Incorporated Product Folder Links: LM3430 25 LM3430 SNVS472B – JANUARY 2007 – REVISED MAY 2013 www.ti.com CHIP OPERATING LOSS This term accounts for the current drawn at the VIN pin. This current, IIN, drives the logic circuitry and the power MOSFETs. The gate driving loss term from the power MOSFET section of Design Considerations is included in the chip operating loss. For the LM3430, IIN is equal to the steady state operating current, ICC, plus the MOSFET driving current, IGC. Power is lost as this current passes through the internal linear regulator of the LM3430. IGC = QG X fSW IGC = 18 nC x 600 kHz = 11 mA (56) ICC is typically 3.5 mA, taken from the ELECTRICAL CHARACTERISTICS table. Chip Operating Loss is then: PQ = VIN X (IQ + IGC) PQ = 12 X (3.5m + 11m) = 0.17W (57) MOSFET SWITCHING LOSS PSW = 0.5 x VIN x IL x (tR + tF) x fSW PSW = 0.5 x 12 x 0.49 x (10 ns + 12 ns) x 6 x105 = 39 mW (58) MOSFET AND RSNS CONDUCTION LOSS PC = D x (I2L x (RDSON x 1.3 + RSNS)) PC = 0.63 x (0.492 x (0.029 + 0.51) = 82 mW (59) INPUT CAPACITOR LOSS This term represents the loss as input ripple current passes through the ESR of the input capacitor bank. In this equation ‘n’ is the number of capacitors in parallel. The 3.3 µF input capacitor selected has an ESR of approximately 3 mΩ, and ΔiL for a 12V input is 268 mA: I2IN-RMS x ESR PCIN = n 2 IIN-RMS = 0.29 x ΔiL = 0.29 x 0.268 = 0.08A PCIN = 0.08 x 0.003 = 0.3 mW (negligible) (60) (61) OUTPUT CAPACITOR LOSS This term is calculated using the same method as the input capacitor loss, substituting the output capacitor RMS current for VIN = 12V: IO-RMS = 1.13 x 0.49 x (0.37 x 0.63)0.5 = 0.267A PCO = 0.267 x 0.003 = 1 mW (62) BOOST INDUCTOR LOSS PDCR = IL2 x DCR PDCR = 0.492 x 0.18 = 43 mW (63) Core loss in the inductor is assumed to be equal to the DCR loss, adding an additional 43 mW to the total inductor loss. TOTAL LOSS PLOSS = Sum of All Loss Terms = 0.38W (64) EFFICIENCY η = 5.9/(5.9 + 0.38) = 94% (65) Layout Considerations To produce an optimal power solution with the LM3430, good layout and design of the PCB are as important as the component selection. The following are several guidelines to aid in creating a good layout. FILTER CAPACITORS The low-value ceramic filter capacitors are most effective when the inductance of the current loops that they filter is minimized. Place CINX as close as possible to the VIN and GND pins of the LM3430. Place COX close to the load. CCS should be placed right next to RSNS, and CF next to the VCC and GND pins of the LM3430. 26 Submit Documentation Feedback Copyright © 2007–2013, Texas Instruments Incorporated Product Folder Links: LM3430 LM3430 www.ti.com SNVS472B – JANUARY 2007 – REVISED MAY 2013 SENSE LINES The top of RSNS should be connected to the CS pin with a separate trace made as short as possible. Route this trace away from the inductor and the switch node (where D1, Q1, and L1 connect). For the voltage loop, keep RFB1/2 close to the LM3430 and run a trace from as close as possible to the positive side of COX to RFB2. As with the CS line, the FB line should be routed away from the inductor and the switch node. These measures minimize the length of high impedance lines and reduce noise pickup. COMPACT LAYOUT Parasitic inductance can be reduced by keeping the power path components close together and keeping the area of the loops that high currents travel small. Short, thick traces or copper pours (shapes) are best. In particular, the switch node should be just large enough to connect all the components together without excessive heating from the current it carries. The LM3430 (boost converter) operates in two distinct cycles whose high current paths are shown in Figure 22: + - Figure 22. Boost Converter Current Loops The dark grey, inner loops represents the high current paths during the MOSFET on-time. The light grey, outer loop represents the high current path during the off-time. GROUND PLANE AND SHAPE ROUTING The diagram of Figure 22 is also useful for analyzing the flow of continuous current vs. the flow of pulsating currents. The circuit paths with current flow during both the on-time and off-time are considered to be continuous current, while those that carry current during the on-time or off-time only are pulsating currents. Preference in routing should be given to the pulsating current paths, as these are the portions of the circuit most likely to emit EMI. The ground plane of a PCB is a conductor and return path, and it is susceptible to noise injection just as any other circuit path. The continuous current paths on the ground net can be routed on the system ground plane with less risk of injecting noise into other circuits. The path between the input source, input capacitor and the power switch and the path between the output capacitor and the load are examples of continuous current paths. In contrast, the path between the grounded side of the power switch and the negative output capacitor terminal carries a large pulsating current. This path should be routed with a short, thick shape, preferably on the component side of the PCB. Multiple vias in parallel should be used right at the negative pads of the input and output capacitors to connect the component side shapes to the ground plane. Vias should not be placed directly at the grounded side of the power switch (or RSNS) as they tend to inject noise into the ground plane. A second pulsating current loop that is often ignored but must be kept small is the gate drive loop formed by the OUT and VCC pins, Q1, RSNS and capacitor CF. Submit Documentation Feedback Copyright © 2007–2013, Texas Instruments Incorporated Product Folder Links: LM3430 27 LM3430 SNVS472B – JANUARY 2007 – REVISED MAY 2013 www.ti.com BOM for Example Circuit 28 ID Part Number Type Size U1 LM3430 Low-Side Controller WSON-12 Q1 Si4850EY MOSFET SO-8 D1 CMHSH5-4 Schottky Diode L1 SLF7045T-470M90-1PF Inductor Cin C3216X7R1E335M Capacitor Co C3216X7R1H105M Parameters Qty Vendor 1 TI 60V, 31mΩ, 18nC 1 Vishay SOD-123 40V, 0.5A 1 Central Semi 7.0 x7.0 x 4.5mm 47µH, 0.9A, 180mΩ 1 TDK 1206 3.3µF, 25V, 3mΩ 1 TDK Capacitor 1206 1µF, 50V, 3mΩ 1 TDK Cf C2012X7R1E105K Capacitor 0805 1µF, 25V 1 TDK Cinx Cox VJ0805Y104KXXAT Capacitor 0805 100nF 10% 1 Vishay C1 VJ0805A391KXXAT Capacitor 0805 390pF 10% 1 Vishay C2 VJ0805Y393KXXAT Capacitor 0805 39nF 10% 1 Vishay Css VJ0805Y103KXXAT Capacitor 0805 10nF 10% 1 Vishay Ccs VJ0805Y102KXXAT Capacitor 0805 1nF 10% 1 Vishay R1 CRCW08052001F Resistor 0805 2kΩ 1% 1 Vishay Rfb1 CRCW08057870F Resistor 0805 787Ω 1% 1 Vishay Rfb2 CRCW08052002F Resistor 0805 20kΩ 1% 1 Vishay Rs1 CRCW0805101J Resistor 0805 100Ω 5% 1 Vishay Rsns ERJ8BQFR51V Resistor 1206 0.51Ω 1%, 0.33W 1 Panasonic Rt CRCW08052742F Resistor 0805 27.4kΩ 1% 1 Vishay Ruv1 Ruv2 CRCW08051002F Resistor 0805 10kΩ 1% 2 Vishay Submit Documentation Feedback Copyright © 2007–2013, Texas Instruments Incorporated Product Folder Links: LM3430 LM3430 www.ti.com SNVS472B – JANUARY 2007 – REVISED MAY 2013 REVISION HISTORY Changes from Revision B (May 2013) to Revision C Page Submit Documentation Feedback Copyright © 2007–2013, Texas Instruments Incorporated Product Folder Links: LM3430 29 PACKAGE OPTION ADDENDUM www.ti.com 19-Oct-2016 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) Op Temp (°C) Device Marking (4/5) LM3430SD/NOPB OBSOLETE WSON DQB 12 TBD Call TI Call TI -40 to 125 L3430 LM3430SDX/NOPB OBSOLETE WSON DQB 12 TBD Call TI Call TI -40 to 125 L3430 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. 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