LM3450AEV120V30/NOPB

User's Guide SNVA485B – June 2011 – Revised May 2013 AN-2150 LM3450A Evaluation Board 1 Introduction The LM3450A evaluation board is designed to provide an AC to LED solution for a 30W LED load. Specifically, it takes an AC mains input and converts it to a constant current output of 700mA for a series string of 1 to 13 LEDs (maximum LED stack voltage of 45V). There are two assembly versions designed to operate from two different nominal AC input voltages, 120VAC or 230VAC. . The board employs a two stage design with an LM3450A flyback primary stage and an LM3409HV secondary stage. The LM3450A provides an isolated 50V regulated output voltage and a power factor corrected input current. The LM3409HV uses the 50V flyback output as its input and provides a constant current of 700mA to the LED load. This two stage design provides excellent line and load regulation as well as isolation. The board is comprised of two copper layers with components on both sides and an FR4 dielelctric. The two-stage design has several key advantages over a single stage design including: • No 120Hz LED current ripple • Better dimming performance at low dimming levels. • Better line disturbance rejection • Better efficiency using small LED stack voltages 2 Specifications • • • • • • • • 120VAC 30W Version Input Voltage Range: VIN = 90VAC – 135VAC Regulated Flyback Output Voltage: VOUT = 50V Maximum LED Stack Voltage: VLED < 45V Regulated LED Current: ILED = 700mA 230VAC 30W Version Input Voltage Range: VIN = 180VAC – 265VAC Regulated Flyback Output Voltage: VOUT = 50V Maximum LED Stack Voltage: VLED < 45V Regulated LED Current: ILED = 700mA All trademarks are the property of their respective owners. SNVA485B – June 2011 – Revised May 2013 Submit Documentation Feedback AN-2150 LM3450A Evaluation Board Copyright © 2011–2013, Texas Instruments Incorporated 1 Specifications www.ti.com VREF BIAS VADJ HOLD RETURN EMI FILTER FLT2 ZCD FLT1 VCC LM3409HV LED Driver LM3450A PWM AC INPUT DIM VAC COMP FB GATE LED LOAD CS OPTICAL ISOLATION GND ISEN PWM HOLD RETURN Figure 1. Schematic 2 AN-2150 LM3450A Evaluation Board SNVA485B – June 2011 – Revised May 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated Typical Performance www.ti.com 3 Typical Performance 84 84 82 120 VAC EFFICIENCY (%) EFFICIENCY (%) 82 80 100 VAC 78 76 16 200 VAC 230 VAC 80 78 20 24 28 76 16 32 20 24 28 32 POUT (W) POUT (W) Figure 2. 120V, 30W Version Efficiency vs. Output Power Figure 3. 230V, 30W Version Efficiency vs. Output Power 1.00 1.00 100 VAC 0.98 200 VAC 0.98 PF PF 120 VAC 0.96 0.94 0.92 16 0.96 230 VAC 0.94 20 24 28 32 0.92 16 20 POUT (W) Figure 4. 120V, 30W Version Power Factor vs. Output Power 24 28 32 POUT (W) Figure 5. 230V, 30W Version Power Factor vs. Output Power SNVA485B – June 2011 – Revised May 2013 Submit Documentation Feedback AN-2150 LM3450A Evaluation Board Copyright © 2011–2013, Texas Instruments Incorporated 3 Conducted EMI Performance Conducted EMI Performance AMPLITUDE in dbuV AMPLITUDE in dbuV 4 www.ti.com FREQUENCY FREQUENCY Figure 6. 120V, 30W Conducted EMI Peak Scan Figure 7. 230V, 30W Conducted EMI Peak Scan Line and Neutral - CISPR/FCC Class B Quasi Peak and Line and Neutral - CISPR/FCC Class B Quasi Peak and Average Limits Average Limits THD / Harmonic Performance 100 50 80 40 60 Limits 40 Measured 20 0 AMPLITUDE (mA) AMPLITUDE (mA) 5 30 Limits 20 Measured 10 0 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 1 3 5 7 9 11 HARMONIC NUMBER Figure 8. 120V, 30W THD Measurements EN 61000-3 Class C Limits THD = 6.27% ; Fundamental = 316mA 4 13 15 17 19 21 23 25 27 29 31 33 35 37 39 HARMONIC NUMBER Figure 9. 230V, 30W THD Measurements EN 61000-3 Class C Limits THD = 8.96% ; Fundamental = 167mA AN-2150 LM3450A Evaluation Board SNVA485B – June 2011 – Revised May 2013 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated LM3450A Pin Descriptions www.ti.com 6 LM3450A Pin Descriptions 1 2 3 4 5 6 7 8 Pin 1 Name VREF VREF BIAS VADJ HOLD FLT2 ZCD FLT1 VCC DIM GATE VAC CS COMP FB GND ISEN 16 15 14 13 12 11 10 9 Description Application Information 3V Reference Reference Output: Connect directly to VADJ or to resistor divider feeding VADJ and to necessary external circuits. 2 VADJ Analog Adjust Analog Dim and Phase Dimming Range Input: Connect directly to VREF to force standard 70% phase dimming range. Connect to resistor divider from VREF to extend usable range of some phase dimmers or for analog dimming. Connect to GND for low power mode. 3 FLT2 Filter 2 Ramp Comparator Input: Connect a series resistor from FLT1 capacitor and a capacitor to GND to establish second filter pole. 4 FLT1 Filter 1 Angle Decoder Output: Connect a series resistor to a capacitor to ground to establish first filter pole. 5 DIM 500 Hz PWM Output 6 VAC Sampled Rectified Line Multiplier and Angle Decoder Input: Connect to resistor divider from rectified AC line. 7 COMP Compensation Error Amplifier Output and PWM Comparator Input: Connect a capacitor to GND to set the compensation. 8 FB Open Drain PWM Dim Output: Connect to dimming input of output stage LED driver (directly or with isolation) to provide decoded dimming command. Feedback Error Amplifier Inverting Input: Connect to output voltage via resistor divider to control PFC voltage loop for nonisolated designs. Connect to a 5.11kΩ resistor to GND for isolated designs (bypasses error amplifier). Also includes over-voltage protection and shutdown modes. Input Current Sense Non-Inverting Input: Connect to diode bridge return and resistor to GND to sense input current for dynamic hold. Connect a 0.1µF capacitor and Schottky diode to GND, and a 0.22µF capacitor to HOLD. 9 ISEN Input Current Sense 10 GND Power Ground System Ground 11 CS Current Sense MosFET Current Sense Input: Connect to positive terminal of sense resistor in PFC MosFET source. 12 GATE Gate Drive 13 VCC Input Supply 14 ZCD Zero Crossing Detector 15 HOLD Dynamic Hold Gate Drive Output: Connect to gate of main power MosFET for PFC.Gate Drive Output: Connect to gate of main power MosFET for PFC. Power Supply Input: Connect to primary bias supply. Connect a 0.1µF bypass capacitor to ground. Demagnetization Sense Input: Connect a resistor to transformer/inductor winding to detect when all energy has been transferred. Open Drain Dynamic Hold Input: Connect to holding resistor which is connected to source of passFET. SNVA485B – June 2011 – Revised May 2013 Submit Documentation Feedback AN-2150 LM3450A Evaluation Board Copyright © 2011–2013, Texas Instruments Incorporated 5 LM3409HV Pin Descriptions 7 www.ti.com Pin Name Description 16 BIAS Pre-regulator Gate Bias Pre-regulator Gate Bias Output: Connect to gate of passFET and to resistor to rectified AC (drain of passFET) to aid with startup. LM3409HV Pin Descriptions 1 2 3 4 5 Pin 6 Application Information Name UVLO VIN IADJ VCC EN DAP CSP COFF GND CSN PGATE 10 9 8 7 6 Description Application Information 1 UVLO Input Under Voltage Lock-out Connect to a resistor divider from VIN. UVLO threshold is 1.24V and hysteresis is provided by a 22µA current source. 2 IADJ Analog LED Current Adjust Apply a voltage between 0 - 1.24V, or connect a resistor from this pin to GND, to set the current sense threshold voltage. 3 EN Logic Level Enable Apply a voltage >1.6V to enable device, a PWM signal to dim, or a voltage