LM34930TLEVAL

User's Guide SNVA347A – April 2008 – Revised May 2013 AN-1848 LM34930 Evaluation Board 1 Introduction The LM34930EVAL evaluation board provides the design engineer with a fully functional buck regulator, employing the constant on-time (COT) operating principle. This evaluation board provides a 5V output over an input range of 8V to 33V. The circuit delivers load currents to 1A, with current limit set at a nominal 1.16A. The board is populated with all components except R5, C9 and C10. These components provide options for managing the output ripple as described later in this document. The board’s specification are: • Input Voltage: 8V to 33V • Output Voltage: 5V • Maximum load current: 1A • Minimum load current: 0A • Current Limit: 1.14A to 1.19A • Measured Efficiency: 92.2% (VIN = 8V, IOUT = 400 mA) • Nominal Switching Frequency: 1500 kHz • Size: 2.6 in. x 1.6 in. x 0.5 in Figure 1. Evaluation Board - Top Side All trademarks are the property of their respective owners. SNVA347A – April 2008 – Revised May 2013 Submit Documentation Feedback AN-1848 LM34930 Evaluation Board Copyright © 2008–2013, Texas Instruments Incorporated 1 Theory of Operation 2 www.ti.com Theory of Operation Refer to the evaluation board schematic in Figure 5. When the circuit is in regulation, the buck switch is on each cycle for a time determined by R1 and VIN according to the equation: tON = 4.15 x 10 -11 x (R1 + 0.5 k:) VIN - 0.8V + 65 ns (1) The on-time of this evaluation board ranges from ≊416 ns at VIN = 8V, to ≊144 ns at VIN = 33V. The ontime varies inversely with VIN to maintain a nearly constant switching frequency. At the end of each ontime the Minimum Off-Timer ensures the buck switch is off for at least 90 ns. In normal operation, the offtime is much longer. During the off-time, the load current is supplied by the output capacitor (C7, C8). When the output voltage falls sufficiently that the voltage at FB is below 2.52V, the regulation comparator initiates a new on-time period. For stable, fixed frequency operation, a minimum of 25 mV of ripple is required at FB to switch the regulation comparator. The current limit threshold, is ≊1.19A at Vin = 8V, and ≊1.14A at Vin = 33V. Refer to the Ultra Small 33V, 1A Constant On-Time Buck Switching Regulator with Intelligent Current Limit (SNVS571) data sheet for a more detailed block diagram, and a complete description of the various functional blocks. 3 Board Layout and Probing The pictorial in Figure 1 shows the placement of the circuit components. The following should be kept in mind when the board is powered: • When operating at high input voltage and high load current, forced air flow may be necessary. • The LM34930, and diode D1 may be hot to the touch when operating at high input voltage and high load current. • Use CAUTION when probing the circuit at high input voltages to prevent injury, as well as possible damage to the circuit. • At maximum load current (1A), the wire size and length used to connect the load becomes important. • Ensure there is not a significant drop in the wires between this evaluation board and the load. 4 Board Connection/Start-up • • • • • • 5 The input connections are made to the J1 connector. The load is connected to the J2 (OUT) and J3 (GND) terminals. Ensure the wires are adequately sized for the intended load current. Before start-up a voltmeter should be connected to the input terminals, and to the output terminals. The load current should be monitored with an ammeter or a current probe. It is recommended that the input voltage be increased gradually to 8V, at which time the output voltage should be 5V. If the output voltage is correct with 8V at VIN, then increase the input voltage as desired and proceed with evaluating the circuit. DO NOT EXCEED 40V AT VIN. Output Ripple Control The LM34930 requires a minimum of 25 mVp-p ripple at the FB pin, in phase with the switching waveform at the SW pin, for proper operation. The required ripple can be supplied from ripple at VOUT, through the feedback resistors as described in Options A and B below, or the ripple can be generated separately (using R5, C9, and C10) in order to keep the ripple at VOUT at a minimum (Option C). Option A) Lowest Cost Configuration: In this configuration R4 is installed in series with the output capacitance (C7, C8). Since ≥25 mVp-p are required at the FB pin, R4 must be chosen to generate ≥50 mVp-p at VOUT, knowing that the minimum ripple current in this circuit is ≊125 mAp-p at minimum VIN. Using 0.43Ω for R4, the ripple at VOUT ranges from ≊54 mVp-p to ≊160 mVp-p over the input voltage range. If the application can accept this ripple level, this is the most economical solution. The circuit is shown in Figure 2 and Figure 8. 2 AN-1848 LM34930 Evaluation Board SNVA347A – April 2008 – Revised May 2013 Submit Documentation Feedback Copyright © 2008–2013, Texas Instruments Incorporated Output Ripple Control www.ti.com 8V - 33V Input VIN C2 1 PF C1 1 PF R1 60.4k C3 VCC C4 0.1 PF LM34930 0.1 PF BST J1 C5 0.022 PF RT VOV TP1 R7 100k L1 10 PH VOUT R6 0: 5V SW SS J2 D1 C6 0.022 PF R2 2.32k ISEN nOV OV TP2 FB GND R3 2.37k R4 0.43: C7 10 PF C8 10 PF J3 Gnd Figure 2. Lowest Cost Configuration Option B) Intermediate Ripple Configuration: This evaluation board is supplied with this configuration installed. This configuration generates less ripple at VOUT than option A above by the addition of one capacitor (C11) across R2, as shown in Figure 3. 8V - 33V Input VIN C2 1 PF C1 1 PF R1 60.4k C3 VCC C4 0.1 PF LM34930 0.1 PF BST J1 C5 0.022 PF RT VOV TP1 R7 100k L1 10 PH VOUT R6 0: 5V SW SS D1 C6 0.022 PF ISEN nOV OV TP2 J2 C11 1000 pF R2 2.32k R4 0.22: FB GND R3 2.37k C7 10 PF C8 10 PF Gnd J3 Figure 3. Intermediate Ripple Configuration Since the output ripple is passed by Cff to the FB pin with little or no attenuation, R4 can be reduced so the minimum ripple at VOUT is ≊25 mVp-p. The minimum value for Cff is calculated from: Cff t 3 x tON (max) (R2//R3) (2) where tON(max) is the maximum on-time (at minimum VIN), and R2//R3 is the parallel equivalent of the feedback resistors. The ripple at VOUT ranges from 32 mVp-p to 93 mVp-p over the input voltagr range. See Figure 8. Option C) Minimum Ripple Configuration: To obtain minimum ripple at VOUT, R4 is set to 0Ω, and R5, C9, and C10 are added to generate the required ripple for the FB pin. In this configuration, the output ripple is determined primarily by the characteristics of the output capacitance and the inductor’s ripple current. See Figure 4. SNVA347A – April 2008 – Revised May 2013 Submit Documentation Feedback AN-1848 LM34930 Evaluation Board Copyright © 2008–2013, Texas Instruments Incorporated 3 Over-Voltage Indicator www.ti.com The ripple voltage required by the FB pin is generated by R5, C10, and C9 since the SW pin switches from -1V to VIN, and the right end of C10 is a virtual ground. The values for R5 and C10 are chosen to generate a 50-100 mVp-p triangle waveform at their junction. That triangle wave is then coupled to the FB pin through C9. The following procedure is used to calculate values for R5, C10 and C9: 1) Calculate the voltage VA: VA = VOUT – (VSW x (1 – (VOUT/VIN))) (3) where VSW is the absolute value of the voltage at the SW pin during the off-time (typically 1V), and VIN is the minimum input voltage. For this circuit, VA calculates to 4.63V. This is the approximate DC voltage at the R5/C10 junction, and is used in the next equation. 2) Calculate the R5 x C10 product: R5 x C10 = (VIN ± VA) x tON 'V (4) where tON is the maximum on-time (≊416 ns), VIN is the minimum input voltage, and ΔV is the desired ripple amplitude at the R5/C10 junction, 100 mVp-p for this example. R5 x C10 = (8V - 4.63V) x 416 ns 0.1V = 14 x 10-6 (5) R5 and C10 are then chosen from standard value components to satisfy the above product. Typically C10 is 3000 to 10000 pF, and R5 is 10 kΩ to 300 kΩ. C9 is chosen large compared to C10, typically 0.1 µF. The ripple at VOUT is typically less than 10 mVp-p. See Figure 4 and Figure 8. 8V - 33V Input VIN C2 1 PF C1 1 PF R1 60.4k C3 VCC C4 0.1 PF LM34930 0.1 PF BST J1 C5 0.022 PF RT VOV TP1 R7 100k L1 10 PH VOUT R6 0: 5V SW SS D1 C6 0.022 PF ISEN nOV OV TP2 J2 R5 4.3k C9 0.1 PF C10 3300 pF FB GND R3 2.37k R2 2.32k C7 10 PF R4 0: C8 10 PF J3 Gnd Figure 4. Minimum Output Ripple Configuration 6 Over-Voltage Indicator The nOV pin, an open drain logic output, switches low when the voltage at VIN exceeds 19V. The overvoltage indicator comparator provides 1.95V hysteresis to reject noise and ripple on the VIN pin. A pull-up voltage not exceeding 7V must be connected to TP1. A 100 kΩ pull-up resistor (R7) is provided on this board. The state of the nOV pin can be monitored at TP2. The pull-up voltage can exceed the voltage at VIN. When nOV is low, the current into the pin must not exceed 10 mA. 7 Input Over-Voltage Shutdown If the input voltage at VIN increases above 36V an internal comparator disables the buck switch, and grounds the soft-start pin. The over-voltage shutdown comparator provides 400 mV hysteresis to reject noise and ripple on the VIN pin. Normal operation resumes when the voltage at VIN is reduced below the lower threshold. 4 AN-1848 LM34930 Evaluation Board SNVA347A – April 2008 – Revised May 2013 Submit Documentation Feedback Copyright © 2008–2013, Texas Instruments Incorporated Monitor The Inductor Current www.ti.com 8 Monitor The Inductor Current The inductor’s current can be monitored or viewed on a scope with a current probe. Remove R6, and install an appropriate current loop across the two large pads where R6 was located. In this way the inductor’s ripple current and peak current can be accurately determined. 9 Scope Probe Adapters Scope probe adapters are provided on this evaluation board for monitoring the waveform at the SW pin, and at the circuit’s output (VOUT), without using the probe’s ground lead which can pick up noise from the switching waveforms. The probe adapters are suitable for Tektronix P6137 or similar probes, with a 0.135” diameter. 10 Minimum Load Current The LM34930 requires a minimum load current of ≊1 mA to ensure the boost capacitor (C5) is recharged sufficiently during each off-time. In this evaluation board, the minimum load current is provided by the feedback resistors allowing the board’s minimum load current at VOUT to be specified at zero. 8V - 33V Input VIN R1 60.4k LM34930 C3 0.1 PF BST J1 C4 0.1 PF 0.022 PF C5 SW RT L1 10 PH VOV TP1 R7 100k VOUT R6 0: SW SS C6 0.022 PF ISEN R5 C9 nOV OV 5V J2 D1 R2 2.32k R4 0.22: FB GND TP2 C10 C11 1000 pF OUTPUT C2 1 PF C1 1 PF VCC R3 2.37k C7 10 PF C8 10 PF J3 Gnd Figure 5. Complete Evaluation Board Schematic (As Supplied) SNVA347A – April 2008 – Revised May 2013 Submit Documentation Feedback AN-1848 LM34930 Evaluation Board Copyright © 2008–2013, Texas Instruments Incorporated 5 Minimum Load Current www.ti.com Table 1. Bill of Materials 6 Item Description Mfg., Part Number Package Value C1 Ceramic Capacitor TDK C3216X7R1H105M 1206 1.0 µF, 50V C2 Ceramic Capacitor TDK C3216X7R1H105M 1206 1.0 µF, 50V C3 Ceramic Capacitor TDK C1608X7R1H104K 0603 0.1 µF, 50V C4 Ceramic Capacitor TDK C1608X7R1H104K 0603 0.1 µF, 50V C5 Ceramic Capacitor TDK C1608X7R1H223K 0603 0.022 µF, 50V C6 Ceramic Capacitor TDK C1608X7R1H223K 0603 0.022 µF, 50V C7, C8 Ceramic Capacitor TDK C3216X7R1C106K 1206 10 µF, 16V C9 Ceramic Capacitor Unpopulated 0603 C10 Ceramic Capacitor Unpopulated 0603 C11 Ceramic Capacitor TDK C1608X7R2A102M 0603 D1 Schottky Diode Zetex ZLLS2000 SOT23-6 40V, 2.2A L1 Power Inductor Bussman DR73-100 7.6 mm x 7.6 mm 10 µH, 2A R1 Resistor Vishay CRCW06036042F 0603 60.4 kΩ R2 Resistor Vishay CRCW06032321F 0603 2.32 kΩ R3 Resistor Vishay CRCW06032371F 0603 2.37 kΩ R4 Resistor Panasonic ERJ3RQFR22 0603 0.22Ω R5 Resistor Unpopulated 0603 R6 Resistor Vishay CRCW08050000Z 0805 0Ω Jumper R7 Resistor Vishay CRCW06031003F 0603 100 kΩ U1 Switching Regulator Texas Instruments LM34930 12 Bump DSBGA AN-1848 LM34930 Evaluation Board 1000 pF SNVA347A – April 2008 – Revised May 2013 Submit Documentation Feedback Copyright © 2008–2013, Texas Instruments Incorporated Circuit Performance www.ti.com 11 Circuit Performance Figure 6. Efficiency vs Load Current Figure 7. Efficiency vs Input Voltage Figure 8. Output Voltage Ripple SNVA347A – April 2008 – Revised May 2013 Submit Documentation Feedback AN-1848 LM34930 Evaluation Board Copyright © 2008–2013, Texas Instruments Incorporated 7 Typical Waveforms www.ti.com Figure 9. Switching Frequency vs. Input Voltage Figure 10. Load Current Limit vs Input Voltage 12 Typical Waveforms 3 0.5 Ps 50 mV 3 4 0.5 Ps 200 mA 4 1 0.5 Ps 10.0V 1 Trace 1 = SW Pin Trace 3 = VOUT Trace 4 = Inductor Current Vin = 16V, Iout = 400 mA Figure 11. Continuous Conduction Mode 8 AN-1848 LM34930 Evaluation Board SNVA347A – April 2008 – Revised May 2013 Submit Documentation Feedback Copyright © 2008–2013, Texas Instruments Incorporated PC Board Layout www.ti.com 3 2 ms 50 mV 3 4 2 ms 200 mA 4 1 2 ms 10.0V 1 Trace 1 = SW Pin Trace 3 = VOUT Trace 4 = Inductor Current Vin = 16V, Iout = 0 mA Figure 12. Discontinuous Conduction Mode 13 PC Board Layout Figure 13. Board Silkscreen SNVA347A – April 2008 – Revised May 2013 Submit Documentation Feedback AN-1848 LM34930 Evaluation Board Copyright © 2008–2013, Texas Instruments Incorporated 9 PC Board Layout www.ti.com Figure 14. Board Top Layer Figure 15. Board Bottom Layer (Viewed from Top) 10 AN-1848 LM34930 Evaluation Board SNVA347A – April 2008 – Revised May 2013 Submit Documentation Feedback Copyright © 2008–2013, Texas Instruments Incorporated IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. 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