LM4953SD/NOPB

LM4953, LM4953SDBD www.ti.com SNAS299F – SEPTEMBER 2005 – REVISED APRIL 2013 LM4953 Boomer™ Audio Power Amplifier Series Ground-Referenced, Ultra Low Noise, Ceramic Speaker Driver Check for Samples: LM4953, LM4953SDBD FEATURES DESCRIPTION • The LM4953 is an audio power amplifier designed for driving Ceramic Speaker in portable applications. When powered by a 3.6V supply, it is capable of forcing 12.6Vpp across a 2μF + 30Ω bridge-tied-load (BTL) with less than 1% THD+N. 1 23 • • • • • • Pop & Click Circuitry Eliminates Noise During Turn-On and Turn-Off Transitions Low, 1μA (Max) Shutdown Current Low, 7mA (Typ) Quiescent Current 12.6Vpp Mono BTL Output, Load = 2μF+ 30Ω Thermal Shutdown Unity-Gain Stable External Gain Configuration Capability APPLICATIONS • • Cellphone PDA KEY SPECIFICATIONS • • • Quiescent Power Supply Current (Vdd = 3V), 7mA(Typ) BTL Voltage Swing (2μF+30Ω load, 1% THD+N, Vdd = 3.6V), 12.6Vpp (Typ) Shutdown Current, 1µA (Max) Boomer audio power amplifiers were designed specifically to provide high quality output power with a minimal amount of external components. The LM4953 does not require bootstrap capacitors, or snubber circuits. Therefore it is ideally suited for display applications requiring high power and minimal size. The LM4953 features a low-power consumption shutdown mode. Additionally, the LM4953 features an internal thermal shutdown protection mechanism. The LM4953 contains advanced pop & click circuitry that eliminates noises which would otherwise occur during turn-on and turn-off transitions. The LM4953 is unity-gain stable and can be configured by external gain-setting resistors. 1 2 3 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Boomer is a trademark of Texas Instruments. All other trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2005–2013, Texas Instruments Incorporated LM4953, LM4953SDBD SNAS299F – SEPTEMBER 2005 – REVISED APRIL 2013 www.ti.com Typical Application 20 k: CPVDD Rf + C3 10 0.39 PF + Ci 20 k: SHUTDOWN *C4 13 Ri Vin1 4.7 PF 1 4.7 PF 2 Undervoltage Lockout, Click/Pop Suppression and Shutdown Control 11 15: + Ceramic Speaker 2 PF 3 Charge Pump C1 2.2 PF + 5 9 - 15: 100 k: 6 4 8 14 C2 2.2 PF 20 k: Figure 1. Typical Application Circuit Connection Diagram SD 1 14 SGND CPVDD 2 13 VIN CCP+ 3 12 NC PGND 4 11 OUT A CCP- 5 10 AVDD VCP_OUT 6 9 OUT B NC 7 8 AVSS Figure 2. WSON Package Top View See Package Number NHK0014A 2 Submit Documentation Feedback Copyright © 2005–2013, Texas Instruments Incorporated Product Folder Links: LM4953 LM4953SDBD LM4953, LM4953SDBD www.ti.com SNAS299F – SEPTEMBER 2005 – REVISED APRIL 2013 PIN DESCRIPTIONS Pin Name Function 1 SD Active Low Shutdown 2 CPVDD Charge Pump Power Supply 3 CCP+ Positive Terminal - Charge Pump Flying Capacitor 4 PGND Power Ground 5 CCP- Negative Terminal - Charge Pump Flying Capacitor 6 VCP_OUT Charge Pump Output 7 NC No Connect 8 AVSS Negative Power Supply - Amplifier 9 OUT B Output B 10 AVDD Positive Power Supply - Amplifier 11 OUT A Output A 12 NC No Connect 13 VIN Signal Input 14 SGND Signal Ground These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. Absolute Maximum Ratings (1) (2) (3) Supply Voltage (VDD) 4.5V Storage Temperature −65°C to +150°C Input Voltage Power Dissipation -0.3V to VDD + 0.3V (4) Internally Limited ESD Susceptibility (5) (6) 2000V ESD Susceptibility (7) (6) 200V Junction Temperature 150°C Thermal Resistance See AN-1187(SNOA401) 'Leadless Leadframe Packaging (LLP).' (1) (2) (3) (4) (5) (6) (7) All voltages are measured with respect to the GND pin unless otherwise specified. Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is functional but do not ensure specific performance limits. Electrical Characteristics state DC and AC electrical specifications under particular test conditions that ensure specific performance limits. This assumes that the device is within the Operating Ratings. Specifications are not ensured for parameters where no limit is given; however, the typical value is a good indication of device performance. If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/Distributors for availability and specifications. The maximum power dissipation must be derated at elevated temperatures and is dictated by TJMAX, θJA, and the ambient temperature, TA. The maximum allowable power dissipation is PDMAX = (TJMAX – TA)/θJA or the number given in Absolute Maximum Ratings, whichever is lower. For the LM4xxx typical application (shown in Figure 1) with VDD = yyV, RL = 2μF+30Ω mono BTL operation the total power dissipation is xxxW. θJA = 40°C/W. Human body model, 100pF discharged through a 1.5kΩ resistor. If the product is in shutdown mode and VDD exceeds 3.6V (to a max of 4V VDD), then most of the excess current will flow through the ESD protection circuits. If the source impedance limits the current to a max of 10mA, then the part will be protected. If the part is enabled when VDD is above 4V, circuit performance will be curtailed or the part may be permanently damaged. Machine Model, 220pF-240pF discharged through all pins. Operating Ratings TMIN ≤ TA ≤ TMAX Temperature Range −40°C ≤ TA ≤ 85°C 1.6V ≤ VDD ≤ 4.2V Supply Voltage (VDD) Copyright © 2005–2013, Texas Instruments Incorporated Product Folder Links: LM4953 LM4953SDBD Submit Documentation Feedback 3 LM4953, LM4953SDBD SNAS299F – SEPTEMBER 2005 – REVISED APRIL 2013 www.ti.com Electrical Characteristics VDD = 3.6V The following specifications apply for VDD = 3.6V, AV-BTL = 6dB, ZL = 2μF+30Ω unless otherwise specified. Limits apply to TA = 25°C. See Figure 1. Symbol Parameter Conditions LM4953 Typ (1) Units (Limits) Limit (2) (3) IDD Quiescent Power Supply Current VIN = 0, RLOAD = 2μF+30Ω 8 mA (max) Istandby Quiescent Power Supply Current Auto Standby Mode VIN = 0, ZLOAD = 2μF+30Ω 2.7 mA ISD Shutdown Current VSD = GND 0.1 VSDIH Shutdown Voltage Input High SD1 SD2 0.7*CPVdd VSDIL Shutdown Voltage Input Low SD1 SD2 0.3*CPVdd TWU Wake-up Time VOS Output Offset Voltage VOUT Output Voltage Swing THD = 1% (max); f = 1kHz RL = 2μF+30Ω, Mono BTL 12.6 Vpp THD+N Total Harmonic Distortion + Noise VOUT = 6Vp-p, fIN = 1kHz 0.02 % ∈OS Output Noise A-Weighted Filter, VIN = 0V 15 μV VRIPPLE = 200mVp-p, f = 217Hz, Input Referred 67 dB VRIPPLE = 200mVp-p, f = 1kHz, Input Referred 65 dB ZL = 2μF+30Ω, VOUT = 6Vp-p 105 dB PSRR SNR (1) (2) (3) 4 Power Supply Rejection Ratio Signal-to-Noise Ratio 1 V (min) V (max) μsec 125 1 µA (max) 10 mV (max) Typicals are measured at 25°C and represent the parametric norm. Limits are specified to Texas Instruments' AOQL (Average Outgoing Quality Level). Datasheet min/max specification limits are specified by design, test, or statistical analysis. Submit Documentation Feedback Copyright © 2005–2013, Texas Instruments Incorporated Product Folder Links: LM4953 LM4953SDBD LM4953, LM4953SDBD www.ti.com SNAS299F – SEPTEMBER 2005 – REVISED APRIL 2013 Electrical Characteristics VDD = 3.0V The following specifications apply for VDD = 3.0V, AV-BTL = 6dB, ZL = 2μF+30Ω unless otherwise specified. Limits apply to TA = 25°C. See Figure 1. Symbol Parameter Conditions LM4953 Units (Limits) Typ (1) Limit (2) (3) 10 IDD Quiescent Power Supply Current VIN = 0, ZLOAD = 2μF+30Ω 7 Istandby Quiescent Power Supply Current Auto Standby Mode VIN = 0, ZLOAD = 2μF+30Ω 2.3 ISD Shutdown Current VSD-LC = VSD-RC = GND 0.1 VSDIH Shutdown Voltage Input High SD1 SD2 0.7*CPVdd VSDIL Shutdown Voltage Input Low SD1 SD2 0.3*CPVdd TWU Wake-up Time VOS Output Offset Voltage VOUT Output Voltage Swing THD = 1% (max); f = 1kHz ZL = 2μF+30Ω, Mono BTL 10.2 Vpp THD+N Total Harmonic Distortion + Noise VOUT = 8.5Vp-p, fIN = 1kHz 0.02 % ∈OS Output Noise A-Weighted Filter, VIN = 0V 15 μV VRIPPLE = 200mVp-p, f = 217Hz, Input Referred 73 dB VRIPPLE = 200mVp-p, f = 1kHz, Input Referred 68 dB ZL = 2μF+30Ω, VOUT = 8.5Vp-p 105 dB PSRR SNR (1) (2) (3) mA 1 Power Supply Rejection Ratio Signal-to-Noise Ratio µA (max) V (min) V (max) μsec 125 1 mA (max) 10 mV (max) Typicals are measured at 25°C and represent the parametric norm. Limits are specified to Texas Instruments' AOQL (Average Outgoing Quality Level). Datasheet min/max specification limits are specified by design, test, or statistical analysis. Copyright © 2005–2013, Texas Instruments Incorporated Product Folder Links: LM4953 LM4953SDBD Submit Documentation Feedback 5 LM4953, LM4953SDBD SNAS299F – SEPTEMBER 2005 – REVISED APRIL 2013 www.ti.com Typical Performance Characteristics THD+N vs Frequency VDD = 3V, VO = 6Vpp, ZL = 2μF+30Ω 10 10 1 1 THD+N (%) THD+N (%) THD+N vs Frequency VDD = 2V, VO = 2Vpp, ZL = 2μF+30Ω 0.1 0.01 0.01 0.001 20 100 1000 20000 0.001 20 20000 1000 100 FREQUENCY (Hz) FREQUENCY (Hz) Figure 3. Figure 4. THD+N vs Frequency VDD = 3.6V, VO = 8.5Vpp, ZL = 2μF+30Ω THD+N vs Frequency VDD = 4.2V, VO = 10Vpp, ZL = 2μF+30Ω 10 10 1 1 THD+N (%) THD+N (%) 0.1 0.1 0.01 0.01 0.001 20 0.1 1000 100 20000 0.001 20 100 20000 1000 FREQUENCY (Hz) FREQUENCY(Hz) Figure 5. Figure 6. THD+N vs Output Voltage VDD = 2V, f = 1kHz, ZL = 2μF+30Ω THD+N vs Output Voltage VDD = 3V, f = 1kHz, ZL = 2μF+30Ω 10 1 THD+N (%) THD+N (%) 1 0.1 0.01 0.01 0.001 0.1 0.6 0.8 1 1.2 1.4 1.6 1.8 2.0 2.2 2.4 OUTPUT VOLTAGE SWING (Vrms) 0.001 0.5 1.0 Figure 7. 6 Submit Documentation Feedback 1.5 2.0 2.5 3.0 3.5 4.0 OUTPUT VOLTAGE SWING (Vrms) Figure 8. Copyright © 2005–2013, Texas Instruments Incorporated Product Folder Links: LM4953 LM4953SDBD LM4953, LM4953SDBD www.ti.com SNAS299F – SEPTEMBER 2005 – REVISED APRIL 2013 Typical Performance Characteristics (continued) THD+N vs Output Voltage VDD = 4.2V, f = 1kHz, ZL = 2μF+30Ω 10 10 1 1 THD+N (%) THD+N (%) THD+N vs Output Voltage VDD = 3.6V, f = 1kHz, ZL = 2μF+30Ω 0.1 0.01 0.1 0.01 0.001 0.5 1 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 0.001 2 5 PSRR vs Frequency VDD = 2V, ZL = 2μF+30Ω PSRR vs Frequency VDD = 3V, ZL = 2μF+30Ω -10 -10 -20 -20 -30 -30 -40 -50 -60 -70 -70 1k 10k -80 10 100k 100 1k 10k Figure 12. PSRR vs Frequency VDD = 3.6V, ZL = 2μF+30Ω PSRR vs Frequency VDD = 4.2V, ZL = 2μF+30Ω 0 -10 -10 -20 -20 -30 -30 PSRR (dB) 0 -40 -50 -40 -50 -60 -60 -70 -70 1k 100k FREQUENCY (Hz) Figure 11. 100 7 -50 -60 100 6 -40 FREQUENCY (Hz) PSRR (dB) 4 Figure 10. 0 -80 10 3 Figure 9. 0 -80 10 1 OUTPUT VOLTAGE SWING (Vrms) PSRR (dB) PSRR (dB) OUTPUT VOLTAGE SWING (Vrms) 10k 100k -80 10 FREQUENCY (Hz) 100 1k 10k 100k FREQUENCY (Hz) Figure 13. Figure 14. Copyright © 2005–2013, Texas Instruments Incorporated Product Folder Links: LM4953 LM4953SDBD Submit Documentation Feedback 7 LM4953, LM4953SDBD SNAS299F – SEPTEMBER 2005 – REVISED APRIL 2013 www.ti.com Typical Performance Characteristics (continued) 12 Supply Current vs Supply Voltage ZL = 2μF+30Ω SUPPLY CURRENT (mA) 10 Full Power Mode 8 6 Auto-Standby Mode 4 2 0 1.5 2 2.5 3 3.5 4 SUPPLY VOLTAGE (V) Figure 15. 8 Submit Documentation Feedback Copyright © 2005–2013, Texas Instruments Incorporated Product Folder Links: LM4953 LM4953SDBD LM4953, LM4953SDBD www.ti.com SNAS299F – SEPTEMBER 2005 – REVISED APRIL 2013 APPLICATION INFORMATION ELIMINATING THE OUTPUT COUPLING CAPACITOR The LM4953 features a low noise inverting charge pump that generates an internal negative supply voltage. This allows the outputs of the LM4953 to be biased about GND instead of a nominal DC voltage, like traditional headphone amplifiers. Because there is no DC component, the large DC blocking capacitors (typically 220µF) are not necessary. The coupling capacitors are replaced by two, small ceramic charge pump capacitors, saving board space and cost. Eliminating the output coupling capacitors also improves low frequency response. In traditional headphone amplifiers, the headphone impedance and the output capacitor form a high pass filter that not only blocks the DC component of the output, but also attenuates low frequencies, impacting the bass response. Because the LM4953 does not require the output coupling capacitors, the low frequency response of the device is not degraded by external components. In addition to eliminating the output coupling capacitors, the ground referenced output nearly doubles the available dynamic range of the LM4953 when compared to a traditional headphone amplifier operating from the same supply voltage. BRIDGE CONFIGURATION EXPLANATION The Audio Amplifier portion of the LM4953has two internal amplifiers allowing different amplifier configurations. The first amplifier’s gain is externally configurable, whereas the second amplifier is internally fixed in a unity-gain, inverting configuration. The closed-loop gain of the first amplifier is set by selecting the ratio of Rf to Ri while the second amplifier’s gain is fixed by the two internal 20kΩ resistors. Figure 1 shows that the output of amplifier one serves as the input to amplifier two. This results in both amplifiers producing signals identical in magnitude, but out of phase by 180°. Consequently, the differential gain for the Audio Amplifier is AVD = 2 *(Rf/Ri) (1) By driving the load differentially through outputs OUT A and OUT B, an amplifier configuration commonly referred to as “bridged mode” is established. Bridged mode operation is different from the classic single-ended amplifier configuration where one side of the load is connected to ground. A bridge amplifier design has a few distinct advantages over the single-ended configuration. It provides differential drive to the load, thus doubling the output swing for a specified supply voltage. Four times the output power is possible as compared to a single-ended amplifier under the same conditions. This increase in attainable output power assumes that the amplifier is not current limited or clipped. In order to choose an amplifier’s closedloop gain without causing excessive clipping, please refer to the Audio Power Amplifier Design section. The bridge configuration also creates a second advantage over single-ended amplifiers. Since the differential outputs, OUT A and OUT B, are biased at half-supply, no net DC voltage exists across the load. This eliminates the need for an output coupling capacitor which is required in a single supply, single-ended amplifier configuration. Without an output coupling capacitor, the half-supply bias across the load would result in both increased internal IC power dissipation and also possible loudspeaker damage. OUTPUT TRANSIENT ('CLICK AND POPS') ELIMINATED The LM4953 contains advanced circuitry that virtually eliminates output transients ('clicks and pops'). This circuitry prevents all traces of transients when the supply voltage is first applied or when the part resumes operation after coming out of shutdown mode. POWER DISSIPATION Power dissipation is a major concern when using any power amplifier and must be thoroughly understood to ensure a successful design. Equation 2 states the maximum power dissipation point for a single-ended amplifier operating at a given supply voltage and driving a specified output load. PDMAX = (VDD) 2 / (2π2ZL) (2) Since the LM4953 has two operational amplifiers in one package, the maximum internal power dissipation point is twice that of the number which results from Equation 2. Even with large internal power dissipation, the LM4953 does not require heat sinking over a large range of ambient temperatures. The maximum power dissipation point obtained must not be greater than the power dissipation that results from Equation 3: Copyright © 2005–2013, Texas Instruments Incorporated Product Folder Links: LM4953 LM4953SDBD Submit Documentation Feedback 9 LM4953, LM4953SDBD SNAS299F – SEPTEMBER 2005 – REVISED APRIL 2013 www.ti.com PDMAX = (TJMAX - TA) / (θJA) (3) Depending on the ambient temperature, TA, of the system surroundings, Equation 3 can be used to find the maximum internal power dissipation supported by the IC packaging. If the result of Equation 2 is greater than that of Equation 3, then either the supply voltage must be decreased, the load impedance increased or TA reduced. Power dissipation is a function of output power and thus, if typical operation is not around the maximum power dissipation point, the ambient temperature may be increased accordingly. POWER SUPPLY BYPASSING As with any power amplifier, proper supply bypassing is critical for low noise performance and high power supply rejection. Applications that employ a 3V power supply typically use a 4.7µF capacitor in parallel with a 0.1µF ceramic filter capacitor to stabilize the power supply's output, reduce noise on the supply line, and improve the supply's transient response. Keep the length of leads and traces that connect capacitors between the LM4953's power supply pin and ground as short as possible. AUTOMATIC STANDBY MODE The LM4953 features Automatic Standby Mode circuitry (patent pending). In the absence of an input signal, after approximately 3 seconds, the LM4953 goes into low current standby mode. The LM4953 recovers into full power operating mode immediately after a signal, which is greater than the input threshold voltage, is applied to either the left or right input pins. The input threshold voltage is not a static value, as the supply voltage increases, the input threshold voltage decreases. This feature reduces power supply current consumption in battery operated applications. To ensure correct operation of Automatic Standby Mode, proper layout techniques should be implemented. Separating PGND and SGND can help reduce noise entering the LM4953 in noisy environments. It is also important to use correct power off sequencing. The device should be in shutdown and then powered off in order to ensure proper functionality of the Auto-Standby feature. While Automatic Standby Mode reduces power consumption very effectively during silent periods, maximum power saving is achieved by putting the device into shutdown when it is not in use. MICRO POWER SHUTDOWN The voltage applied to the SD controls the LM4953’s shutdown function. When active, the LM4953’s micropower shutdown feature turns off the amplifiers’ bias circuitry, reducing the supply current. The trigger point is 0.3*CPVDD for a logic-low level, and 0.7*CPVDD for logic-high level. The low 0.01µA (typ) shutdown current is achieved by applying a voltage that is as near as ground a possible to the SD pins. A voltage that is higher than ground may increase the shutdown current. There are a few ways to control the micro-power shutdown. These include using a single-pole, single-throw switch, a microprocessor, or a microcontroller. When using a switch, connect an external 100kΩ pull-up resistor between the SD pins and VDD. Connect the switch between the SD pins and ground. Select normal amplifier operation by opening the switch. Closing the switch connects the SD pins to ground, activating micro-power shutdown. The switch and resistor ensure that the SD pins will not float. This prevents unwanted state changes. In a system with a microprocessor or microcontroller, use a digital output to apply the control voltage to the SD pins. Driving the SD pins with active circuitry eliminates the pull-up resistor. EXPOSED-DAP CONSIDERATIONS It is essential that the exposed Die Attach Paddle (DAP), for the LM4953, is NOT connected to GND. For optimal operation it should be connected to AVss and VCP-OUT (Pins 6 and 8). SELECTING PROPER EXTERNAL COMPONENTS Optimizing the LM4953's performance requires properly selecting external components. Though the LM4953 operates well when using external components with wide tolerances, best performance is achieved by optimizing component values. 10 Submit Documentation Feedback Copyright © 2005–2013, Texas Instruments Incorporated Product Folder Links: LM4953 LM4953SDBD LM4953, LM4953SDBD www.ti.com SNAS299F – SEPTEMBER 2005 – REVISED APRIL 2013 Charge Pump Capacitor Selection Use low ESR (equivalent series resistance) (