LM5019
SNVS788H – JANUARY 2012 – REVISED AUGUST 2021
LM5019 100-V, 100-mA Constant On-Time Synchronous Buck / Fly-Buck™ Regulator
1 Features
3 Description
•
•
The LM5019 is a 100-V, 100-mA synchronous stepdown regulator with integrated high-side and lowside MOSFETs. The constant-on-time (COT) control
scheme employed in the LM5019 requires no loop
compensation, provides excellent transient response,
and enables very low step-down ratios. The on-time
varies inversely with the input voltage resulting in
nearly constant frequency over the input voltage
range. A high-voltage start-up regulator provides
bias power for internal operation of the IC and for
integrated gate drivers.
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Wide 7.5-V to 100-V input range
Integrated 100-mA high-side and low-side
switches
No schottky required
Constant on-time control
No loop compensation required
Ultra-fast transient response
Nearly constant operating frequency
Intelligent peak current limit
Adjustable output voltage from 1.225 V
Precision 2% feedback reference
Frequency adjustable to 1 MHz
Adjustable undervoltage lockout
Remote shutdown
Thermal shutdown
Packages:
– 8-Pin WSON
– 8-Pin SO PowerPAD
Create a custom design using the LM5019 with the
WEBENCH® Power Designer
A peak current limit circuit protects against overload
conditions. The undervoltage lockout (UVLO) circuit
allows the input undervoltage threshold and
hysteresis to be independently programmed. Other
protection features include thermal shutdown and bias
supply undervoltage lockout.
The LM5019 device is available in WSON-8 and SO
PowerPAD-8 plastic packages.
Device Information
2 Applications
Smart power meters
Telecommunication systems
Automotive electronics
Isolated bias supply (Fly-Buck™)
LM5019
(1)
2
+
4
RUV2
BST
VIN
SW
RON
SO PowerPAD (8)
4.89 mm × 3.90 mm
WSON (8)
4.00 mm × 4.00 mm
3
VCC
UVLO
FB
RUV1
7
+
8
CBST
L1
VOUT
CVCC
RON
SD
BODY SIZE (NOM)
LM5019
7.5 V ± 100 V
VIN
CIN
PACKAGE(1)
For all available packages, see the orderable addendum at
the end of the data sheet.
+
•
•
•
•
PART NUMBER
6
RFB2
5
RTN
1
RC
+
RFB1
COUT
Typical Application
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
LM5019
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SNVS788H – JANUARY 2012 – REVISED AUGUST 2021
Table of Contents
1 Features............................................................................1
2 Applications..................................................................... 1
3 Description.......................................................................1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................3
6 Specifications.................................................................. 4
6.1 Absolute Maximum Ratings........................................ 4
6.2 ESD Ratings............................................................... 4
6.3 Recommended Operating Conditions.........................4
6.4 Thermal Information....................................................4
6.5 Electrical Characteristics.............................................5
6.6 Switching Characteristics............................................6
6.7 Typical Characteristics................................................ 7
7 Detailed Description........................................................9
7.1 Overview..................................................................... 9
7.2 Functional Block Diagram........................................... 9
7.3 Feature Description.....................................................9
7.4 Device Functional Modes..........................................14
8 Application and Implementation.................................. 15
8.1 Application Information............................................. 15
8.2 Typical Applications.................................................. 15
9 Power Supply Recommendations................................25
10 Layout...........................................................................26
10.1 Layout Guidelines................................................... 26
10.2 Layout Example...................................................... 26
11 Device and Documentation Support..........................27
11.1 Device Support........................................................27
11.2 Documentation Support.......................................... 27
11.3 Receiving Notification of Documentation Updates.. 27
11.4 Support Resources................................................. 27
11.5 Trademarks............................................................. 27
11.6 Electrostatic Discharge Caution.............................. 28
11.7 Glossary.................................................................. 28
12 Mechanical, Packaging, and Orderable
Information.................................................................... 28
4 Revision History
Changes from Revision G (November 2017) to Revision H (August 2021)
Page
• Added "Synchronous Fly-Buck" to the title ........................................................................................................ 1
• Updated the numbering format for tables, figures, and cross-references throughout the document. ................1
Changes from Revision F (December 2014) to Revision G (November 2017)
Page
• Added WEBENCH links to the data sheet.......................................................................................................... 1
• Deleted lead temperature from the Absolute Maximum Ratings table .............................................................. 4
• Changed 14 V to 13 V in VCC Regulator section.............................................................................................. 10
• Changed 8 to 4 on equation in Input Capacitor section ...................................................................................18
• Changed 0.06 μF to 0.12 μF in Input Capacitor section................................................................................... 18
2
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5 Pin Configuration and Functions
RTN
1
VIN
2
UVLO
3
RON
4
8
SW
Power
PAD-8
7
BST
Exp Pad
6
VCC
5
FB
RTN
1
VIN
2
UVLO
3
RON
4
8 SW
WSON-8
Exp Pad
7 BST
6 VCC
5 FB
Connect Exposed Pad to RTN
Connect Exposed Pad to RTN
Figure 5-1. DDA Package 8-Pin SO PowerPAD Top
View
Figure 5-2. NGU Package 8-Pin WSON Top View
Table 5-1. Pin Functions
PIN
I/O
NO.
NAME
1
RTN
—
2
VIN
I
DESCRIPTION
APPLICATION INFORMATION
Ground
Ground connection of the integrated circuit
Input Voltage
Operating input range is 7.5 V to 100 V.
3
UVLO
I
Input Pin of Undervoltage
Comparator
Resistor divider from VIN to UVLO to GND programs the
undervoltage detection threshold. An internal current source is
enabled when UVLO is above 1.225 V to provide hysteresis. When
UVLO pin is pulled below 0.66 V externally, the parts goes in
shutdown mode.
4
RON
I
On-Time Control
A resistor between this pin and VIN sets the switch on-time as a
function of VIN. Minimum recommended on-time is 100 ns at max
input voltage.
5
FB
I
Feedback
This pin is connected to the inverting input of the internal regulation
comparator. The regulation level is 1.225 V.
6
VCC
O
Output From the Internal High
Voltage Series Pass Regulator.
Regulated at 7.6 V
The internal VCC regulator provides bias supply for the gate
drivers and other internal circuitry. A 1.0-μF decoupling capacitor
is recommended.
7
BST
I
Bootstrap Capacitor
An external capacitor is required between the BST and SW pins
(0.01-μF ceramic). The BST pin capacitor is charged by the VCC
regulator through an internal diode when the SW pin is low.
8
SW
O
Switching Node
Power switching node. Connect to the output inductor and bootstrap
capacitor.
—
EP
—
Exposed Pad
Exposed pad must be connected to RTN pin. Connect to system
ground plane on application board for reduced thermal resistance.
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6 Specifications
6.1 Absolute Maximum Ratings
MIN(1)
MAX
UNIT
VIN, UVLO to RTN
–0.3
100
V
SW to RTN
–1.5
VIN + 0.3
V
–5
VIN + 0.3
V
BST to VCC
100
V
BST to SW
13
V
SW to RTN (100-ns transient)
RON to RTN
–0.3
100
V
VCC to RTN
–0.3
13
V
FB to RTN
–0.3
Maximum junction temperature(2)
Storage temperature, Tstg
(1)
(2)
–55
5
V
150
°C
150
°C
Absolute Maximum Ratings are limits beyond which damage to the device may occur. Section 6.3 are conditions under which
operation of the device is intended to be functional. For verified specifications and test conditions, see Section 6.5. The RTN pin is the
GND reference electrically connected to the substrate.
High junction temperatures degrade operating lifetimes. Operating lifetime is derated for junction temperatures greater than 125°C.
6.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC
JS-001(1)
UNIT
±2000
Charged-device model (CDM), per JEDEC specification JESD22-C101(2)
V
±750
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)(1)
VIN voltage
Operating junction
(1)
(2)
temperature(2)
MIN
MAX
UNIT
7.5
100
V
–40
125
°C
Recommended Operating Conditions are conditions under the device is intended to be functional. For specifications and test
conditions, see Section 6.5.
High junction temperatures degrade operating lifetimes. Operating lifetime is de-rated for junction temperatures greater than 125°C.
6.4 Thermal Information
LM5019
THERMAL
NGU (WSON)
DDA (SO PowerPAD)
8 PINS
8 PINS
UNIT
RθJA
Junction-to-ambient thermal resistance
41.3
41.1
°C/W
RθJCbot
Junction-to-case (bottom) thermal resistance
3.2
2.4
°C/W
ΨJB
Junction-to-board thermal characteristic parameter
19.2
24.4
°C/W
RθJB
Junction-to-board thermal resistance
19.1
30.6
°C/W
RθJCtop
Junction-to-case (top) thermal resistance
34.7
37.3
°C/W
ΨJT
Junction-to-top thermal characteristic parameter
0.3
6.7
°C/W
(1)
4
METRIC(1)
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report (SPRA953).
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6.5 Electrical Characteristics
Typical values correspond to TJ = 25°C. Minimum and maximum limits apply over –40°C to 125°C junction temperature range
unless otherwise stated. VIN = 48 V unless stated otherwise. See(2).
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
6.25
7.6
8.55
UNIT
VCC SUPPLY
VCC Reg VCC Regulator Output
VCC Current Limit
VIN = 48 V, ICC = 20 mA
VIN = 48 V(1)
VCC Undervoltage Lockout Voltage
(VCC Increasing)
26
4.15
VCC Undervoltage Hysteresis
V
mA
4.5
4.9
V
300
mV
2.3
V
VCC Drop Out Voltage
VIN = 9 V, ICC = 20 mA
IIN Operating Current
Non-Switching, FB = 3 V
IIN Shutdown Current
UVLO = 0 V
50
225
µA
Buck Switch RDS(ON)
ITEST = 200 mA, BST-SW = 7 V
0.8
1.8
Ω
Synchronous RDS(ON)
ITEST = 200 mA
0.45
1
Ω
Gate Drive UVLO
VBST − VSW Rising
3
3.6
V
1.75
mA
SWITCH CHARACTERISTICS
2.4
Gate Drive UVLO Hysteresis
260
mV
CURRENT LIMIT
Current Limit Threshold
–40°C ≤ TJ ≤ 125°C
Current Limit Response Time
Time to Switch Off
Off-Time Generator (Test 1)
Off-Time Generator (Test 2)
150
240
300
mA
150
ns
FB = 0.1 V, VIN = 48 V
12
µs
FB = 1 V, VIN = 48 V
2.5
µs
REGULATION AND OVERVOLTAGE COMPARATORS
FB Regulation Level
Internal Reference Trip Point for
Switch ON
FB Overvoltage Threshold
Trip Point for Switch OFF
1.2
FB Bias Current
1.225
1.25
V
1.62
V
60
nA
UNDERVOLTAGE SENSING FUNCTION
UV Threshold
UV Rising
UV Hysteresis Input Current
UV = 2.5 V
Remote Shutdown Threshold
Voltage at UVLO Falling
Remote Shutdown Hysteresis
1.19
1.225
1.26
V
–10
–20
–29
µA
0.32
0.66
V
110
mV
165
°C
20
°C
THERMAL SHUTDOWN
Tsd
Thermal Shutdown Temperature
Thermal Shutdown Hysteresis
(1)
(2)
VCC provides self bias for the internal gate drive and control circuits. Device thermal limitations limit external loading.
All hot and cold limits are specified by correlating the electrical characteristics to process and temperature variations and applying
statistical process control.
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6.6 Switching Characteristics
Typical values correspond to TJ = 25°C. Minimum and maximum limits apply over –40°C to 125°C junction temperature range
unless otherwise stated. VIN = 48 V unless stated otherwise. See(1).
MIN
TYP
MAX
UNIT
ON-TIME GENERATOR
TON Test 1
VIN = 32 V, RON = 100 kΩ
270
350
460
ns
TON Test 2
VIN = 48 V, RON = 100 kΩ
188
250
336
ns
TON Test 3
VIN = 75 V, RON = 100 kΩ
250
370
500
ns
TON Test 4
VIN = 10 V, RON = 250 kΩ
1880
3200
4425
ns
MINIMUM OFF-TIME
Minimum Off-Timer
(1)
6
FB = 0 V
144
ns
All hot and cold limits are specified by correlating the electrical characteristics to process and temperature variations and applying
statistical process control.
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6.7 Typical Characteristics
Figure 6-1. Efficiency at 240 kHz, 10 V
Figure 6-2. VCC versus VIN
Figure 6-3. VCC versus ICC
Figure 6-4. ICC versus External VCC
Figure 6-5. TON versus VIN and RON
Figure 6-6. TOFF (ILIM) versus VFB and VIN
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Figure 6-7. IIN versus VIN (Operating, NonSwitching)
Figure 6-8. IIN versus VIN (Shutdown)
Figure 6-9. Switching Frequency versus VIN
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7 Detailed Description
7.1 Overview
The LM5019 step-down switching regulator features all the functions needed to implement a low-cost, efficient,
buck converter capable of supplying up to 100 mA to the load. This high-voltage regulator contains 100 V,
N-channel buck and synchronous switches, is easy to implement, and is provided in thermally enhanced SO
PowerPAD-8 and WSON-8 packages. The regulator operation is based on a constant on-time control scheme
using an on-time inversely proportional to VIN. This control scheme does not require loop compensation. The
current limit is implemented with a forced off-time inversely proportional to VOUT. This scheme ensures short
circuit protection while providing minimum foldback.
The LM5019 can be applied in numerous applications to efficiently regulate down higher voltages. This regulator
is well suited for 48-V telecom and automotive power bus ranges. Protection features include: thermal shutdown,
undervoltage lockout, minimum forced off-time, and an intelligent current limit.
7.2 Functional Block Diagram
LM5019
START-UP
REGULATOR
VIN
VCC
V UVLO
20 µA
4.5V
UVLO
THERMAL
SHUTDOWN
UVLO
1.225V
SD
VDD REG
BST
0.66V
SHUTDOWN
BG REF
VIN
DISABLE
ON/OFF
TIMERS
RON
SW
COT CONTROL
LOGIC
1.225V
FEEDBACK
FB
ILIM
COMPARATOR
OVER-VOLTAGE
1.62V
CURRENT
LIMIT
ONE-SHOT
+
VILIM
RTN
7.3 Feature Description
7.3.1 Control Overview
The LM5019 buck regulator employs a control principle based on a comparator and a one-shot on-timer, with
the output voltage feedback (FB) compared to an internal reference (1.225 V). If the FB voltage is below the
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reference the internal buck switch is turned on for the one-shot timer period, which is a function of the input
voltage and the programming resistor (RON). Following the on-time, the switch remains off until the FB voltage
falls below the reference, but never before the minimum off-time forced by the minimum off-time one-shot timer.
When the FB pin voltage falls below the reference and the minimum off-time one-shot period expires, the buck
switch is turned on for another on-time one-shot period. This will continue until regulation is achieved and the FB
voltage is approximately equal to 1.225 V (typ).
In a synchronous buck converter, the low-side (sync) FET is ‘on’ when the high-side (buck) FET is ‘off’. The
inductor current ramps up when the high side switch is ‘on’ and ramps down when the high side switch is ‘off’.
There is no diode emulation feature in this IC, therefore, the inductor current can ramp in the negative direction
at light load. This causes the converter to operate in continuous conduction mode (CCM) regardless of the
output loading. The operating frequency remains relatively constant with load and line variations. The operating
frequency can be calculated as shown in Equation 1.
¦SW
VOUT1
K u RON
(1)
where
•
K = 9 × 10–11
The output voltage (VOUT) is set by two external resistors (RFB1 and RFB2). The regulated output voltage is
calculated as shown in Equation 2.
RFB2 VOUT - 1.225V
=
1.225V
RFB1
(2)
This regulator regulates the output voltage based on ripple voltage at the feedback input, requiring a minimum
amount of ESR for the output capacitor (COUT). A minimum of 25 mV of ripple voltage at the feedback pin (FB)
is required for the LM5019. In cases where the capacitor ESR is too small, additional series resistance can be
required (RC in Figure 7-1).
For applications where lower output voltage ripple is required, the output can be taken directly from a low ESR
output capacitor, as shown in Figure 7-1. However, RC slightly degrades the load regulation.
L1
VOUT
SW
LM5019
RFB2
FB
RC
+
RFB1
VOUT
(low ripple)
COUT
Figure 7-1. Low Ripple Output Configuration
7.3.2 VCC Regulator
The LM5019 contains an internal high-voltage linear regulator with a nominal output of 7.6 V. The input pin (VIN)
can be connected directly to the line voltages up to 100 V. The VCC regulator is internally current limited to
30 mA. The regulator sources current into the external capacitor at VCC. This regulator supplies current to
internal circuit blocks including the synchronous MOSFET driver and the logic circuits. When the voltage on the
VCC pin reaches the undervoltage lockout threshold of 4.5 V, the IC is enabled.
The VCC regulator contains an internal diode connection to the BST pin to replenish the charge in the gate drive
boot capacitor when SW pin is low.
At high input voltages, the power dissipated in the high voltage regulator is significant and can limit the overall
achievable output power. As an example, with the input at 48 V and switching at high frequency, the VCC
regulator can supply up to 7 mA of current resulting in 48 V × 7 mA = 336 mW of power dissipation. If the VCC
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voltage is driven externally by an alternate voltage source, between 8.55 V and 13 V, the internal regulator is
disabled. This reduces the power dissipation in the IC.
7.3.3 Regulation Comparator
The feedback voltage at FB is compared to an internal 1.225-V reference. In normal operation, when the output
voltage is in regulation, an on-time period is initiated when the voltage at FB falls below 1.225 V. The high-side
switch stays on for the on-time, causing the FB voltage to rise above 1.225 V. After the on-time period, the
high-side switch stays off until the FB voltage again falls below 1.225 V. During start-up, the FB voltage is below
1.225 V at the end of each on-time, causing the high-side switch to turn on immediately after the minimum forced
off-time of 144 ns. The high-side switch can be turned off before the on-time is over if the peak current in the
inductor reaches the current limit threshold.
7.3.4 Overvoltage Comparator
The feedback voltage at FB is compared to an internal 1.62-V reference. If the voltage at FB rises above 1.62
V, the on-time pulse is immediately terminated. This condition can occur if the input voltage, the output load, of
both, changes suddenly. The high-side switch does not turn on again until the voltage at FB falls below 1.225 V.
7.3.5 On-Time Generator
The on-time for the LM5019 is determined by the RON resistor, and is inversely proportional to the input voltage
(VIN), resulting in a nearly constant frequency as VIN is varied over its range. The on-time equation for the
LM5019 is shown in Equation 3.
TON =
10-10 x RON
VIN
(3)
See Figure 6-5. RON must be selected for a minimum on-time (at maximum VIN) greater than 100 ns, for proper
operation. This requirement limits the maximum switching frequency for high VIN.
7.3.6 Current Limit
The LM5019 contains an intelligent current limit off-timer. If the current in the buck switch exceeds 240 mA,
the present cycle is immediately terminated, and a non-resetable off-timer is initiated. The length of off-time is
controlled by the FB voltage and the input voltage VIN. As an example, when FB = 0 V and VIN = 48 V, the
maximum off-time is set to 16 μs. This condition occurs when the output is shorted, and during the initial part of
start-up. This amount of time ensures safe short circuit operation up to the maximum input voltage of 100 V.
In cases of overload where the FB voltage is above zero volts (not a short circuit), the current limit off-time is
reduced. Reducing the off-time during less severe overloads reduces the amount of foldback, recovery time, and
start-up time. The off-time is calculated from Equation 4:
TOFF(ILIM)
0.07 u VIN
Ps
VFB 0.2 V
(4)
The current limit protection feature is peak limited. The maximum average output will be less than the peak.
7.3.7 N-Channel Buck Switch and Driver
The LM5019 integrates an N-Channel Buck switch and associated floating high voltage gate driver. The gate
driver circuit works in conjunction with an external bootstrap capacitor and an internal high voltage diode. A
0.01-uF ceramic capacitor connected between the BST pin and the SW pin provides the voltage to the driver
during the on-time. During each off-time, the SW pin is at approximately 0 V, and the bootstrap capacitor charges
from VCC through the internal diode. The minimum off-timer, set to 144 ns, ensures a minimum time each cycle
to recharge the bootstrap capacitor.
7.3.8 Synchronous Rectifier
The LM5019 provides an internal synchronous N-Channel MOSFET rectifier. This MOSFET provides a path for
the inductor current to flow when the high-side MOSFET is turned off.
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The synchronous rectifier has no diode emulation mode, and is designed to keep the regulator in continuous
conduction mode even during light loads, which would otherwise result in discontinuous operation.
7.3.9 Undervoltage Detector
The LM5019 contains a dual-level Undervoltage Lockout (UVLO) circuit. When the UVLO pin voltage is below
0.66 V, the controller is in a low current shutdown mode. When the UVLO pin voltage is greater than 0.66 V
but less than 1.225 V, the controller is in standby mode. In standby mode, the VCC bias regulator is active while
the regulator output is disabled. When the VCC pin exceeds the VCC undervoltage threshold and the UVLO pin
voltage is greater than 1.225 V, normal operation begins. An external set-point voltage divider from VIN to GND
can be used to set the minimum operating voltage of the regulator.
UVLO hysteresis is accomplished with an internal 20-μA current source that is switched on or off into the
impedance of the set-point divider. When the UVLO threshold is exceeded, the current source is activated to
quickly raise the voltage at the UVLO pin. The hysteresis is equal to the value of this current times the resistance
RUV2.
If the UVLO pin is wired directly to the VIN pin, the regulator begins operation once the VCC undervoltage is
satisfied.
VIN
2
VIN
+
CIN
RUV2
LM5019
3
UVLO
RUV1
Figure 7-2. UVLO Resistor Setting
7.3.10 Thermal Protection
The LM5019 must be operated so the junction temperature does not exceed 150°C during normal operation.
An internal Thermal Shutdown circuit is provided to protect the LM5019 in the event of a higher than normal
junction temperature. When activated, typically at 165°C, the controller is forced into a low power reset state,
disabling the buck switch and the VCC regulator. This feature prevents catastrophic failures from accidental
device overheating. When the junction temperature reduces below 145°C (typical hysteresis = 20°C), the VCC
regulator is enabled, and normal operation is resumed.
7.3.11 Ripple Configuration
The LM5019 uses Constant-On-Time (COT) control scheme, in which the on-time is terminated by an ontimer, and the off-time is terminated by the feedback voltage (VFB) falling below the reference voltage (VREF).
Therefore, for stable operation, the feedback voltage must decrease monotonically, in phase with the inductor
current during the off-time. Furthermore, this change in feedback voltage (VFB) during off-time must be large
enough to suppress any noise component present at the feedback node.
Ripple Configuration shows three different methods for generating appropriate voltage ripple at the feedback
node. Type 1 and Type 2 ripple circuits couple the ripple at the output of the converter to the feedback node
(FB). The output voltage ripple has two components:
1. Capacitive ripple caused by the inductor current ripple charging/discharging the output capacitor.
2. Resistive ripple caused by the inductor current ripple flowing through the ESR of the output capacitor.
The capacitive ripple is not in phase with the inductor current. As a result, the capacitive ripple does not
decrease monotonically during the off-time. The resistive ripple is in phase with the inductor current and
decreases monotonically during the off-time. The resistive ripple must exceed the capacitive ripple at the output
node (VOUT) for stable operation. If this condition is not satisfied unstable switching behavior is observed in COT
converters, with multiple on-time bursts in close succession followed by a long off-time.
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Type 3 ripple method uses Rr and Cr and the switch node (SW) voltage to generate a triangular ramp. This
triangular ramp is ac coupled using Cac to the feedback node (FB). Since this circuit does not use the output
voltage ripple, it is ideally suited for applications where low output voltage ripple is required. See the AN-1481
Controlling Output Ripple and Achieving ESR Independence in Constant On-Time (COT) Regulator Designs
Application Report (SNVA166) for more details for each ripple generation method.
Ripple Configuration
TYPE 1
LOWEST COST CONFIGURATION
TYPE 2
REDUCED RIPPLE CONFIGURATION
TYPE 3
MINIMUM RIPPLE CONFIGURATION
VOUT
VOUT
L1
VOUT
L1
L1
Cac
R FB2
R FB2
RC
To FB
Cac
GND
C OUT
R FB1
R FB1
GND
25 mV VOUT
x
ûIL(MIN) VREF
COUT
Cr
R FB2
To FB
C OUT
RC >
Rr
RC
To FB
R FB1
GND
C>
5
gsw (RFB2||RFB1)
25 mV
RC >
ûIL(MIN)
Cr = 3300 pF
Cac = 100 nF
(VIN(MIN) - VOUT) x TON
RrCr <
25 mV
7.3.12 Soft Start
A soft-start feature can be implemented with the LM5019 using an external circuit. As shown in Figure 7-3,
the soft-start circuit consists of one capacitor, C1, two resistors, R1 and R2, and a diode, D. During the initial
start-up, the VCC voltage is established prior to the VOUT voltage. Capacitor C1 is discharged and D is thereby
forward biased. The FB voltage exceeds the reference voltage (1.225 V) and switching is therefore disabled.
As capacitor C1 charges, the voltage at node B gradually decreases and switching commences. VOUT gradually
rises to maintain the FB voltage at the reference voltage. Once the voltage at node B is less than a diode drop
above the FB voltage, the soft-start sequence is finished and D is reverse biased.
During the initial part of the start-up, the FB voltage can be approximated as follows. Note that the effect of R1
has been ignored to simplify the calculation shown in Equation 5.
VFB = (VCC - VD) x
RFB1 x RFB2
R2 x (RFB1 + RFB2) + RFB1 x RFB2
(8)
C1 is charged after the first start-up. Diode D1 is optional and can be added to discharge C1 and initialize the
soft-start sequence when the input voltage experiences a momentary drop.
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To achieve the desired soft start, the following design guidance is recommended:
1. R2 is selected so that VFB is higher than 1.225 V for a VCC of 4.5 V, but is lower than 5 V when VCC is 8.55 V.
If an external VCC is used, VFB must not exceed 5 V at maximum VCC.
2. C1 is selected to achieve the desired start-up time that can be determined as shown in Equation 6.
tS = C1 x (R2 +
RFB1 x RFB2
)
RFB1 + RFB2
(9)
3. R1 is used to maintain the node B voltage at zero after the soft start is finished. A value larger than the
feedback resistor divider is preferred.
With component values from the applications from the schematic shown in Figure 8-1, selecting C1 = 1 µF, R2 =
1 kΩ, and R1 = 30 kΩ results in a soft-start time of about 2 ms.
VOUT
VCC
C1
RFB2
R2
To FB
D
D1
B
RFB1
R1
Figure 7-3. Soft-Start Circuit
7.4 Device Functional Modes
The UVLO pin controls the operating mode of the LM5019 device (see Table 7-1 for the detailed functional
states).
Table 7-1. UVLO Mode
UVLO
VCC
MODE
< 0.66 V
Disabled
Shutdown
0.66 V to 1.225 V
Enabled
Standby
VCC regulator enabled
Switching disabled.
VCC < 4.5 V
Standby
VCC regulator enabled.
Switching disabled.
VCC > 4.5 V
Operating
> 1.225 V
14
DESCRIPTION
VCC regulator disabled.
Switching disabled.
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VCC enabled.
Switching enabled.
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8 Application and Implementation
Note
Information in the following applications sections is not part of the TI component specification,
and TI does not warrant its accuracy or completeness. TI’s customers are responsible for
determining suitability of components for their purposes, as well as validating and testing their design
implementation to confirm system functionality.
8.1 Application Information
The LM5019 device is step-down DC-DC converter. The device is typically used to convert a higher DC voltage
to a lower DC voltage with a maximum available output current of 100 mA. Use the following design procedure
to select component values for the LM5019 device. Alternately, use the WEBENCH® software to generate a
complete design. The WEBENCH software uses an iterative design procedure and accesses a comprehensive
database of components when generating a design. This section presents a simplified discussion of the design
process.
8.2 Typical Applications
8.2.1 Application Circuit: 12.5 V to 95 V Input and 10 V, 100-mA Output Buck Converter
The application schematic of a buck supply is shown in Figure 8-1. For output voltage (VOUT) more than one
diode drop higher than the maximum regulation threshold of VCC (8.55 V, see Section 6.5), the VCC pin can be
connected to VOUT through a diode (D2), to improve efficiency and reduce power dissipation in the IC.
The design example uses equations from the Section 7.3 with component names provided in the Figure 3-1
schematic. Corresponding component designators from Figure 8-1 are also provided for each selected value.
SW
12 V ± 95 V
VIN
(TP1)
LM5019
2
C4 + C5 +
R5
1 F 0.1 F 127 NŸ
GND
(TP2)
UVLO/SD
R3
4
237 NŸ
3
7 0.01 F
+ C1
8
SW
BST
VIN
RON
VOUT
220 H
UVLO
VCC
R7
14 NŸ
FB
EXP
L1
RTN
1
5
U1
C8
0.1 F
R1
6.98 NŸ
6
+
D2
+ C7
1 F
(TP3)
R2
1.5 Ÿ
R6
1 NŸ
C9
4.7 F
GND
(TP5)
Figure 8-1. 12.5-V to 95-V Input and 10-V, 100-mA Output Buck Converter
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8.2.1.1 Design Requirements
Table 8-1 lists the design parameters for this example.
Table 8-1. Buck Converter Design Specifications
DESIGN PARAMETERS
VALUE
Input Range
12.5 V to 95 V, transients up to 100 V
Output Voltage
10 V
Maximum Output Current
100 mA
Nominal Switching Frequency
≈ 440 kHz
8.2.1.2 Detailed Design Procedure
8.2.1.2.1 Custom Design With WEBENCH® Tools
Click here to create a custom design using the LM5019 device with the WEBENCH® Power Designer.
1. Start by entering the input voltage (VIN), output voltage (VOUT), and output current (IOUT) requirements.
2. Optimize the design for key parameters such as efficiency, footprint, and cost using the optimizer dial.
3. Compare the generated design with other possible solutions from Texas Instruments.
The WEBENCH Power Designer provides a customized schematic along with a list of materials with real-time
pricing and component availability.
In most cases, these actions are available:
• Run electrical simulations to see important waveforms and circuit performance
• Run thermal simulations to understand board thermal performance
• Export customized schematic and layout into popular CAD formats
• Print PDF reports for the design, and share the design with colleagues
Get more information about WEBENCH tools at www.ti.com/WEBENCH.
8.2.1.2.2 RFB1, RFB2
VOUT = VFB × (RFB2 / RFB1 + 1), and since VFB = 1.225 V, the ratio of RFB2 to RFB1 calculates to be 7:1. Standard
values are chosen with RFB2 = R1 = 6.98 kΩ and R FB1 = R6 = 1.00 kΩ are chosen. Other values can be used as
long as the 7:1 ratio is maintained.
8.2.1.2.3 Frequency Selection
At the minimum input voltage, the maximum switching frequency of the LM5019 is restricted by the forced
minimum off-time (TOFF(MIN)) as given by Equation 7.
¦SW(MAX)
1 DMIN
TOFF(MIN)
1 10 / 12.5
200 ns
0+]
(10)
Similarly, at maximum input voltage, the maximum switching frequency of the LM5019 is restricted by the
minimum TON as given by Equation 8.
¦SW(MAX)
DMIN
TON(MIN)
10 / 48
100 ns
0+]
(11)
Resistor RON sets the nominal switching frequency based on Equation 9.
¦SW
VOUT
K u RON
(12)
where
•
16
K = 9 × 10–11
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Operation at high switching frequency results in lower efficiency while providing the smallest solution. For this
example, 440 kHz was selected, resulting in RON = 253 kΩ. A standard value for RON = R3 = 237 kΩ is selected.
8.2.1.2.4 Inductor Selection
The inductance selection is a compromise between solution size, output ripple, and efficiency. The peak inductor
current at maximum load current must be smaller than the minimum current limit threshold of 150 mA. The
maximum permissible peak-to-peak inductor ripple is determined by Equation 10.
'IL
2 u ILIM(min) IOUT(max)
2 u 50
100 mA
(13)
The minimum inductance is determined by Equation 11.
VIN VOUT VOUT
u
L1u ¦SW
VIN
'IL
(14)
Using maximum VIN of 95 V, the calculation from Equation 11 results in L = 203 μH. A standard value of 220 μH
is selected. With this value of inductance, peak-to-peak minimum and maximum inductor current ripple of 27 mA
and 92 mA occur at the minimum and maximum input voltages, respectively. For robust short circuit protection,
the inductor saturation current should be higher than the maximum current limit threshold of 300 mA.
8.2.1.2.5 Output Capacitor
The output capacitor is selected to minimize the capacitive ripple across it. The maximum ripple is observed at
maximum input voltage and is given by Equation 12.
COUT
'IL
8 u ¦SW u '9ripple
(15)
where
•
•
ΔVripple is the voltage ripple across the capacitor
and ΔIL is the inductor ripple current.
Assuming VIN = 95 V and substituting ΔVripple = 10 mV gives COUT = 2.6 μF. A 4.7-μF standard value is selected
for COUT = C9. An X5R or X7R type capacitor with a voltage rating 16 V or higher must be selected.
8.2.1.2.6 Type II Ripple Circuit
Type II ripple circuit as described in Section 7.3.11 is chosen for this example. For a constant on-time converter
to be stable, the injected in-phase ripple must be larger than the capacitive ripple on COUT.
Using type II ripple circuit equations with minimum FB pin ripple of 25 mV, the values of the series resistor RC
and ac coupling capacitor Cac can calculated.
Ct
5
¦SW 5FB2 5FB1
RC t
25 m V
'IL(MIN)
(16)
Assuming RFB2 = 6.98 kΩ and RFB1 = 1 kΩ, the calculated minimum value of Cac is 0.013 µF. A standard value
of 0.1 µF is selected for Cac = C8. The value of the series output resistor RC is calculated for the minimum input
voltage condition when the inductor ripple current as at a minimum. Using Equation 11 and assuming VIN = 12.5
V, the minimum inductor ripple current is 27 mA. The calculated minimum value of RC is 0.93 Ω. A standard
value of 1.5 Ω is selected for RC = R2 to provide additional ripple for stable switching at low VIN.
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8.2.1.2.7 VCC and Bootstrap Capacitor
The VCC capacitor provides charge to bootstrap capacitor as well as internal circuitry and low-side gate driver.
The bootstrap capacitor provides charge to the high-side gate driver. The recommended value for CVCC = C7 is 1
μF. A good value for CBST = C1 is 0.01 μF.
8.2.1.2.8 Input Capacitor
The input capacitor must be large enough to limit the input voltage ripple shown in Equation 14.
CIN t
IOUT(MAX )
4 u ¦SW u 'VIN
(17)
Choosing a ΔVIN = 0.5 V gives a minimum CIN = 0.12 μF. A standard value of 1.0 μF is selected for CIN = C4.
The input capacitor must be rated for the maximum input voltage under all conditions. A 50-V, X7R dielectric
must be selected for this design.
The input capacitor must be placed directly across VIN and RTN (pin 2 and 1) of the IC. If it is not possible to
place all of the input capacitor close to the IC, a 0.1-μF capacitor must be placed near the IC to provide a bypass
path for the high frequency component of the switching current. This helps limit the switching noise.
8.2.1.2.9 UVLO
The UVLO resistors RUV1 and RUV2 set the UVLO threshold and hysteresis according to Equation 15 and
Equation 16.
VIN (HYS) = IHYS x RUV2
(18)
where
•
IHYS = 20 µA
§R
VIN (UVLO, rising) 1.225 V u ¨ UV2
© RUV1
·
1¸
¹
(19)
For UVLO hysteresis of 2.5 V and UVLO rising threshold of 12 V, the calculated values of the UVLO resistors are
RUV2 = 127 kΩ and RUV1 = 14.5 kΩ. Selecting standard values for RUV1 = R7 = 14 kΩ and RUV2 = R5 = 127 kΩ
results in UVLO rising threshold of 12.5 V and hysteresis of 2.5 V.
8.2.1.3 Application Curves
Figure 8-2. Efficiency versus Load Current
18
Figure 8-3. Frequency versus Input Voltage
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Figure 8-4. Typical Switching Waveform (VIN = 48 V, IOUT = 100 mA)
8.2.2 Application Circuit: 20 V to 95 V Input and 10 V, 100 mA Output Isolated Fly-Buck® Converter
VOUT2
D1
+
N2
COUT2
1 µF
X1
LM5019
BST
VIN
20V-95V
0.01 µF
+
CBST
+
150 µH
VOUT1
SW
46.4 kΩ 1 nF
Rr
Cr
VIN
CBYP
0.1 µF
CIN
1 µF
N1
+
RON
RUV2
127 kΩ
RON
130 kΩ
RUV1
8.25 kΩ
0.1 µF
+
Cac
RFB2
VCC
UVLO
RTN
COUT1
1 µF
FB
+
D2
7.32 kΩ
CVCC
1 µF
RFB1
1 kΩ
Figure 8-5. Isolated Fly-Buck™ Converter Using LM5019
8.2.2.1 Design Requirements
Selection of external components is illustrated through a design example. The design example specifications are
shown in Table 8-2.
Table 8-2. Buck Converter Design Specifications
DESIGN PARAMETERS
VALUE
Input Voltage Range
20 V to 95 V
Primary Output Voltage
10 V
Secondary (Isolated) Output Voltage
9.5 V
Maximum Output Current (Primary + Secondary)
100 mA
Maximum Power Output
1W
Nominal Switching Frequency
750 kHz
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8.2.2.2 Detailed Design Procedure
8.2.2.2.1 Transformer Turns Ratio
The transformer turns ratio is selected based on the ratio of the primary output voltage to the secondary
(isolated) output voltage. In this design example, the two outputs are nearly equal and a 1:1 turns ratio
transformer is selected. Therefore, N2 / N1 = 1.
If the secondary (isolated) output voltage is significantly higher or lower than the primary output voltage, a turns
ratio less than or greater than 1 is recommended. The primary output voltage is normally selected based on the
input voltage range such that the duty cycle of the converter does not exceed 50% at the minimum input voltage.
This condition is satisfied if VOUT1 < VIN_MIN / 2.
8.2.2.2.2 Total IOUT
The total primary referred load current is calculated by multiplying the isolated output load or loads by the turns
ratio of the transformer as shown in Equation 17.
IOUT(MAX)
IOUT1 IOUT2 u
N2
N1
0.1 A
(20)
8.2.2.2.3 RFB1, RFB2
The feedback resistors are selected to set the primary output voltage. The selected value for RFB1 is 1 kΩ. RFB2
can be calculated using the following equations to set VOUT1 to the specified value of 10 V. A standard resistor
value of 7.32 kΩ is selected for RFB2.
VOUT1 = 1.225V x (1 +
: RFB2 =
V
OUT1
( 1.225
RFB2
)
RFB1
(21)
- 1) x RFB1 = 7.16 k:
(22)
8.2.2.2.4 Frequency Selection
Equation 20 is used to calculate the value of RON required to achieve the desired switching frequency.
f SW =
VOUT1
. x RON
(23)
where
•
K = 9 × 10–11
For VOUT1 of 10 V and fSW of 750 kHz, the calculated value of RON is 148 kΩ. A lower value of 130 kΩ is
selected for this design to allow for second order effects at high switching frequency that are not included in
Equation 1.
8.2.2.2.5 Transformer Selection
A coupled inductor or a flyback-type transformer is required for this topology. Energy is transferred from primary
to secondary when the low-side synchronous switch of the buck converter is conducting.
The maximum inductor primary ripple current that can be tolerated without exceeding the buck switch peak
current limit threshold (0.15 A minimum) is given by Equation 21.
'IL1
N2 ·
§
¨ 0.15 IOUT1 IOUT2 u N1 ¸ u 2
©
¹
0.1 A
(24)
Using the maximum peak-to-peak inductor ripple current ΔIL1 from Equation 21, the minimum inductor value is
given by Equation 22.
20
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VIN(MAX)
VOUT
'IL1 u ¦SW
u
VOUT
VIN(MAX)
119.3 PH
(25)
A higher value of 150 µH is selected to ensure the high-side switch current does not exceed the minimum peak
current limit threshold.
8.2.2.2.6 Primary Output Capacitor
In a conventional buck converter, the output ripple voltage is calculated as shown in Equation 23.
f
'VOUT =
'IL1
x f x COUT1
(26)
To limit the primary output ripple voltage ΔVOUT1 to approximately 50 mV, an output capacitor COUT1 of 0.33 µF is
required.
Figure 8-6 shows the primary winding current waveform (IL1) of a Fly-Buck converter. The reflected secondary
winding current adds to the primary winding current during the buck switch off-time. Because of this increased
current, the output voltage ripple is not the same as in conventional buck converter. The output capacitor value
calculated in Equation 23 must be used as the starting point. Optimization of output capacitance over the entire
line and load range must be done experimentally. If the majority of the load current is drawn from the secondary
isolated output, a better approximation of the primary output voltage ripple is given by Equation 24.
'VOUT1
N2 ·
§
¨ IOUT2 u N1 ¸ u TON(MAX)
©
¹
| 67 mV
COUT1
(27)
TON(MAX) x IOUT2 x N2/N1
IL1
IOUT2
IL2
TON(MAX) x IOUT2
Figure 8-6. Current Waveforms for COUT1 Ripple Calculation
A standard 1-µF, 25-V capacitor is selected for this design. If lower output voltage ripple is required, a higher
value must be selected for COUT1, COUT2, or both.
8.2.2.2.7 Secondary Output Capacitor
A simplified waveform for secondary output current (IOUT2) is shown in Figure 8-7.
IOUT2
IL2
TON(MAX) x IOUT2
Figure 8-7. Secondary Current Waveforms for COUT2 Ripple Calculation
The secondary output current (IOUT2) is sourced by COUT2 during on-time of the buck switch, TON. Ignoring
the current transition times in the secondary winding, the secondary output capacitor ripple voltage can be
calculated using Equation 25.
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'VOUT2 =
IOUT2 x TON (MAX)
COUT2
(28)
For a 1:1 transformer turns ratio, the primary and secondary voltage ripple equations are identical. Therefore,
COUT2 is chosen to be equal to COUT1 (1 µF) to achieve comparable ripple voltages on primary and secondary
outputs.
If lower output voltage ripple is required, a higher value must be selected for COUT1, COUT2, or both.
8.2.2.2.8 Type III Feedback Ripple Circuit
A Type III ripple circuit as described in the Section 7.3.11 section is required for the Fly-Buck topology. Type
I and Type II ripple circuits use series resistance and the triangular inductor ripple current to generate ripple
at VOUT and the FB pin. The primary ripple current of a Fly-Buck is the combination or primary and reflected
secondary currents as illustrated in Figure 8-6. In the Fly-Buck topology, Type I and Type II ripple circuits suffer
from large jitter as the reflected load current affects the feedback ripple.
VOUT
L1
Rr
Cac
C OUT
Cr
R FB2
GND
To FB
R FB1
Figure 8-8. Type III Ripple Circuit
Selecting the Type III ripple components using the equations from the Section 7.3.11 section ensures that the FB
pin ripple is be greater than the capacitive ripple from the primary output capacitor COUT1. The feedback ripple
component values are chosen as shown in Equation 26.
Cr = 1000 pF
Cac = 0.1 PF
RrCr d
(VIN (MIN) - VOUT) x TON
50 mV
(29)
The calculated value for Rr is 66 kΩ. This value provides the minimum ripple for stable operation. A smaller
resistance must be selected to allow for variations in TON, COUT1, and other components. For this design, Rr
value of 46.4 kΩ is selected.
8.2.2.2.9 Secondary Diode
The reverse voltage across secondary-rectifier diode D1 when the high-side buck switch is off can be calculated
using Equation 27.
VD1 =
N2
VIN
N1
(30)
For a VIN_MAX of 95 V and the 1:1 turns ratio of this design, a 100-V Schottky is selected.
8.2.2.2.10 VCC and Bootstrap Capacitor
A 1-µF capacitor of 16 V or higher rating is recommended for the VCC regulator bypass capacitor.
A good value for the BST pin bootstrap capacitor is 0.01 µF with a 16 V or higher rating.
22
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8.2.2.2.11 Input Capacitor
The input capacitor is typically a combination of a smaller bypass capacitor located near the regulator IC and
a larger bulk capacitor. The total input capacitance must be large enough to limit the input voltage ripple to a
desired amplitude. For input ripple voltage ΔVIN, CIN can be calculated using Equation 28.
CIN t
IOUT(MAX)
4 u ¦ u '9IN
(31)
Choosing a ΔVIN of 0.5 V gives a minimum CIN of 0.067 μF. A standard value of 0.1 μF is selected for CBYP
in this design. A bulk capacitor of higher value reduces voltage spikes due to parasitic inductance between the
power source to the converter. A standard value of 1 μF is selected for CIN in this design. The voltage ratings of
the two input capacitors should be greater than the maximum input voltage under all conditions.
8.2.2.2.12 UVLO Resistors
UVLO resistors RUV1 and RUV2 set the undervoltage lockout threshold and hysteresis according to Equation 29
and Equation 30.
VIN (HYS) = IHYS x RUV2
(32)
where
•
IHYS = 20 μA, typical
VIN (UVLO, rising) = 1.225V x
R
( RUV2
UV1
+ 1)
(33)
For a UVLO hysteresis of 2.5 V and UVLO rising threshold of 20 V, Equation 29 and Equation 30 require RUV1 of
8.25 kΩ and RUV2 of 127 kΩ and these values are selected for this design example.
8.2.2.2.13 VCC Diode
Diode D2 is an optional diode connected between VOUT1 and the VCC regulator output pin. When VOUT1 is more
than one diode drop greater than the VCC voltage, the VCC bias current is supplied from VOUT1. This results in
reduced power losses in the internal VCC regulator which improves converter efficiency. VOUT1 must be set to
a voltage at least one diode drop higher than 8.55 V (the maximum VCC voltage) if D2 is used to supply bias
current.
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8.2.2.3 Application Curves
VIN = 48 V
IOUT1 = 0 mA
IOUT2 = 100 mA
Figure 8-10. Steady-State Waveform
Figure 8-9. Efficiency at 750 kHz, VOUT1 = 10 V
24
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9 Power Supply Recommendations
The LM5019 is a power management device. The power supply for the device is any DC voltage source within
the specified input range.
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10 Layout
10.1 Layout Guidelines
A proper layout is essential for optimum performance of the circuit. In particular, the following guidelines should
be observed:
1. CIN: The loop consisting of input capacitor (CIN), VIN pin, and RTN pin carries switching currents. Therefore,
the input capacitor should be placed close to the IC, directly across VIN and RTN pins and the connections to
these two pins must be direct to minimize the loop area. In general it is not possible to accommodate all of
input capacitance near the IC. A good practice is to use a 0.1-μF or 0.47-μF capacitor directly across the VIN
and RTN pins close to the IC, and the remaining bulk capacitor as close as possible (see Figure 10-1).
2. CVCC and CBST: The VCC and bootstrap (BST) bypass capacitors supply switching currents to the high and
low side gate drivers. These two capacitors should also be placed as close to the IC as possible, and the
connecting trace length and loop area must be minimized (see Figure 10-1).
3. The Feedback trace carries the output voltage information and a small ripple component that is necessary
for proper operation of the LM5019. Therefore, care must be taken while routing the feedback trace to avoid
coupling any noise to this pin. In particular, feedback trace must not run close to magnetic components, or
parallel to any other switching trace.
4. SW trace: The SW node switches rapidly between VIN and GND every cycle and is therefore a possible
source of noise. The SW node area must be minimized. In particular, the SW node must not be inadvertently
connected to a copper plane or pour.
10.2 Layout Example
RTN
1
VIN
2
8
SW
7
BST
CIN
Power
PAD-8
UVLO
3
6
VCC
RON
4
5
FB
CVCC
Figure 10-1. Placement of Bypass Capacitors
26
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Product Folder Links: LM5019
LM5019
www.ti.com
SNVS788H – JANUARY 2012 – REVISED AUGUST 2021
11 Device and Documentation Support
11.1 Device Support
11.1.1 Third-Party Products Disclaimer
TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT
CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES
OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER
ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE.
11.1.2 Development Support
11.1.2.1 Custom Design With WEBENCH® Tools
Click here to create a custom design using the LM5019 device with the WEBENCH® Power Designer.
1. Start by entering the input voltage (VIN), output voltage (VOUT), and output current (IOUT) requirements.
2. Optimize the design for key parameters such as efficiency, footprint, and cost using the optimizer dial.
3. Compare the generated design with other possible solutions from Texas Instruments.
The WEBENCH Power Designer provides a customized schematic along with a list of materials with real-time
pricing and component availability.
In most cases, these actions are available:
• Run electrical simulations to see important waveforms and circuit performance
• Run thermal simulations to understand board thermal performance
• Export customized schematic and layout into popular CAD formats
• Print PDF reports for the design, and share the design with colleagues
Get more information about WEBENCH tools at www.ti.com/WEBENCH.
11.2 Documentation Support
11.2.1 Related Documentation
•
•
•
•
Texas Instruments, AN-2240 LM5019 Isolated Evaluation Board (SNOU100)
Texas Instruments, PowerPAD™ Layout Guidelines (SLOA120)
Texas Instruments, AN-1481 Controlling Output Ripple and Achieving ESR Independence in Constant OnTime (COT) Regulator Designs (SNVA166)
Texas Instruments, AN-2238 LM5019 Buck Evaluation Board (SNVA647)
11.3 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on
Subscribe to updates to register and receive a weekly digest of any product information that has changed. For
change details, review the revision history included in any revised document.
11.4 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
11.5 Trademarks
Fly-Buck™ and TI E2E™ are trademarks of Texas Instruments.
is a trademark of Texas Instruments.
Fly-Buck® are registered trademarks of TI.
WEBENCH® are registered trademarks of Texas Instruments.
All trademarks are the property of their respective owners.
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Product Folder Links: LM5019
27
LM5019
www.ti.com
SNVS788H – JANUARY 2012 – REVISED AUGUST 2021
11.6 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
11.7 Glossary
TI Glossary
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
28
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Product Folder Links: LM5019
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
LM5019MR/NOPB
ACTIVE SO PowerPAD
DDA
8
95
RoHS & Green
SN
Level-3-260C-168 HR
-40 to 125
L5019
MR
LM5019MRX/NOPB
ACTIVE SO PowerPAD
DDA
8
2500
RoHS & Green
SN
Level-3-260C-168 HR
-40 to 125
L5019
MR
LM5019SD/NOPB
ACTIVE
WSON
NGU
8
1000
RoHS & Green
SN
Level-1-260C-UNLIM
-40 to 125
L5019
LM5019SDX/NOPB
ACTIVE
WSON
NGU
8
4500
RoHS & Green
SN
Level-1-260C-UNLIM
-40 to 125
L5019
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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