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LM5025
SNVS265C – DECEMBER 2003 – REVISED JANUARY 2016
LM5025 Active Clamp Voltage Mode PWM Controller
1 Features
3 Description
•
•
•
The LM5025 PWM controller contains all of the
features necessary to implement power converters
using the active clamp and reset technique. The
device can be configured to control either a
P-channel clamp switch or an N-channel clamp
switch. With the active clamp technique, higher
efficiencies and greater power densities can be
realized compared to conventional catch winding or
RDC clamp and reset techniques.
1
•
•
•
•
•
•
•
•
•
•
Internal Start-Up Bias Regulator
3-A Compound Main Gate Driver
Programmable Line Undervoltage Lockout (UVLO)
With Adjustable Hysteresis
Voltage Mode Control With Feed-Forward
Adjustable Dual-Mode Overcurrent Protection
Programmable Overlap or Deadtime Between the
Main and Active Clamp Outputs
Volt × Second Clamp
Programmable Soft-Start
Leading Edge Blanking
Single Resistor Programmable Oscillator
Oscillator UP and DOWN Sync Capability
Precision 5-V Reference
Thermal Shutdown
2 Applications
•
•
•
•
Server Power Supplies
48-V Telecom Power Supplies
42-V Automotive Applications
High-Efficiency DC-to-DC Power Supplies
Two control outputs are provided, the main power
switch control (OUT_A), and the active clamp switch
control (OUT_B). The active clamp output can be
configured for either a specified overlap time
(for P-channel switch applications) or a specified
deadtime (for N_channel applications). The two
internal compound gate drivers parallel both MOS
and bipolar devices, providing superior gate drive
characteristics. This controller is designed for highspeed operation including an oscillator frequency
range up to 1 MHz and total PWM and current sense
propagation delays less than 100 ns.
The LM5025 includes a high-voltage start-up
regulator that operates over a wide input range of
13 V to 90 V. Additional features include: line
undervoltage lockout (UVLO), soft-start, oscillator UP
and DOWN sync capability, precision reference and
thermal shutdown.
Device Information(1)
PART NUMBER
LM5025
PACKAGE
BODY SIZE (NOM)
TSSOP (16)
5.00 mm × 4.40 mm
WSON (16)
5 00 mm × 5.00 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Simplified Schematic
VOUT
3.3V
VIN
35 - 78V
LM5025
CS1
CS2
VIN
VCC
UVLO
ERROR
AMP &
ISOLATION
OUT_A
OUT_B
RAMP
COMP
REF
Rt
SYNC
TIME
SS
PGND AGND
UP/DOWN
SYNC
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
LM5025
SNVS265C – DECEMBER 2003 – REVISED JANUARY 2016
www.ti.com
Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
4
6.1
6.2
6.3
6.4
6.5
6.6
4
4
4
5
5
8
Absolute Maximum Ratings ......................................
ESD Ratings..............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics...........................................
Typical Characteristics ..............................................
Detailed Description ............................................ 10
7.1 Overview ................................................................. 10
7.2 Functional Block Diagram ....................................... 11
7.3 Feature Description................................................. 12
7.4 Device Functional Modes........................................ 16
8
Application and Implementation ........................ 17
8.1 Application Information............................................ 17
8.2 Typical Application ................................................. 17
9 Power Supply Recommendations...................... 23
10 Layout................................................................... 23
10.1 Layout Guidelines ................................................. 23
10.2 Layout Example .................................................... 23
11 Device and Documentation Support ................. 24
11.1
11.2
11.3
11.4
11.5
Documentation Support ........................................
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
24
24
24
24
24
12 Mechanical, Packaging, and Orderable
Information ........................................................... 24
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision B (March 2013) to Revision C
•
2
Page
Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation
section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and
Mechanical, Packaging, and Orderable Information section .................................................................................................. 1
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SNVS265C – DECEMBER 2003 – REVISED JANUARY 2016
5 Pin Configuration and Functions
PW and NHQ Packages
16-Pin TSSOP and WSON
Top View
VIN
1
16
UVLO
RAMP
2
15
SYNC
CS1
3
14
RT
CS2
4
13
COMP
TIME
5
12
SS
REF
6
11
AGND
VCC
7
10
PGND
OUT_A
8
9
OUT_B
Pin Functions
PIN
NO.
NAME
I/O (1)
DESCRIPTION
APPLICATION INFORMATION
1
VIN
I
Source input voltage
Input to start-up regulator. Input 13 V to 90 V, with transient capability
to 100 V.
2
RAMP
I
Modulator ramp signal
An external RC circuit from Vin sets the ramp slope. This pin is
discharged at the conclusion of every cycle by an internal FET,
initiated by either the internal clock or the V*Sec Clamp comparator.
3
CS1
I
Current sense input for
cycle-by-cycle limiting
If CS1 exceeds 0.25 V the outputs goes into Cycle-by-Cycle current
limit. CS1 is held low for 50 ns after OUT_A switches high providing
leading edge blanking.
I
Current sense input for soft
restart
If CS2 exceeds 0.25 V the outputs are disabled and a soft-start
commences. The soft-start capacitor is fully discharged and then
released with a pullup current of 1 µA. After the first output pulse
(when SS = 1 V), the SS charge current reverts back to 20 µA. CS2 is
held low for 50 ns after OUT_A switches high, providing leading edge
blanking.
4
CS2
5
TIME
I
An external resistor (RSET) sets either the overlap time or dead time for
the active clamp output. An RSET resistor connected between TIME
Output overlap and deadtime
and GND produces in-phase OUT_A and OUT_B pulses with overlap.
control
An RSET resistor connected between TIME and REF produces out-ofphase OUT_A and OUT_B pulses with deadtime.
6
REF
O
Precision 5-V reference
output
Maximum output current: 10-mA locally decouple with a 0.1-µF
capacitor. Reference stays low until the line UVLO and the VCC UV
comparators are satisfied.
7
VCC
P
Output from the internal
If an auxiliary winding raises the voltage on this pin above the
high-voltage start-up
regulation setpoint, the internal start-up regulator shutdowns, reducing
regulator. The VCC voltage is
the IC power dissipation.
regulated to 7.6 V
8
OUT_A
O
Main output driver
Output of the main switch PWM output gate driver. Output capability of
3-A peak sink current.
9
OUT_B
O
Active clamp output driver
Output of the active clamp switch gate driver. Capable of 1.25-A peak
sink current..
10
PGND
G
Power ground
Connect directly to analog ground.
11
AGND
G
Analog ground
Connect directly to power ground. For the WSON package option the
exposed pad is electrically connected to AGND.
12
SS
I
Soft-start control
An external capacitor and an internal 20-µA current source set the softstart ramp. The SS current source is reduced to 1 µA initially following
a CS2 overcurrent event or an over temperature event.
(1)
P = power, G = ground, I = input, O = Output, I/O = Input/output
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Pin Functions (continued)
PIN
I/O (1)
DESCRIPTION
APPLICATION INFORMATION
NO.
NAME
13
COMP
I
Input to the pulse width
modulator
An internal 5-KΩ resistor pullup is provided on this pin. The external
opto-coupler sinks current from COMP to control the PWM duty cycle.
14
RT
I
Oscillator timing resistor pin
An external resistor connected from RT to ground sets the internal
oscillator frequency.
15
SYNC
I
Oscillator UP and DOWN
synchronization input
The internal oscillator can be synchronized to an external clock with a
frequency 20% lower than the internal oscillator’s free running
frequency. There is no constraint on the maximum sync frequency.
16
UVLO
I
Line undervoltage shutdown
An external voltage divider from the power source sets the shutdown
comparator levels. The comparator threshold is 2.5 V. Hysteresis is set
by an internal current source (20 µA) that is switched on or off as the
UVLO pin potential crosses the 2.5-V threshold.
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
MIN
MAX
VIN to GND
–0.3
100
VCC to GND
–0.3
16
CS1, CS2 to GND
–0.3
1
All other inputs to GND
–0.3
7
V
150
°C
150
°C
Input voltage
Junction temperature, TJ
Storage temperature, Tstg
(1)
–55
UNIT
V
V
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
6.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
(3)
Electrostatic discharge (1)
Human-body model (HBM), per ANSI/ESDA/JEDEC JS01
(2)
±2000
Charged-device model (CDM), per JEDEC specification JESD22-C101 (3)
±500
UNIT
V
For detailed information on soldering plastic TSSOP and WSON packages, refer to the Packaging Data Book.
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
VIN voltage
NOM
MAX
UNIT
13
90
External voltage applied to VCC
8
15
V
Operating junction temperature
–40
125
°C
4
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6.4 Thermal Information
LM5025
THERMAL METRIC (1)
PW (TSSOP)
NHQ (WSON)
16-PINS
16-PINS
UNIT
RθJA
Junction-to-ambient thermal resistance
98.7
30
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
27.8
25.9
°C/W
RθJB
Junction-to-board thermal resistance
44.3
9.3
°C/W
ψJT
Junction-to-top characterization parameter
1.2
0.2
°C/W
ψJB
Junction-to-board characterization parameter
43.6
9.5
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
—
2.3
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
6.5 Electrical Characteristics
Specifications are TJ = 25°C. Unless otherwise specified: VIN = 48 V, VCC = 10 V, RT = 31.3 kΩ, RSET = 27.4 kΩ (1)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
STARTUP REGULATOR
VCC Reg
VCC regulation
TJ = 25°C
No load
TJ = –40°C to 125°C
TJ = 25°C
VCC current limit (2)
I-VIN
7.6
7.3
TJ = –40°C to 125°C
Startup regulator leakage
(external Vcc Supply)
VIN = 100 V
Shutdown current (Iin)
UVLO = 0 V
7.9
25
mA
20
TJ = 25°C
165
TJ = –40°C to 125°C
500
TJ = 25°C
350
TJ = –40°C to 125°C
V
450
µA
µA
VCC SUPPLY
VCC undervoltage lockout voltage
(positive going Vcc)
VCC undervoltage hysteresis
VCC supply current (ICC)
VCC Reg –
120 mV
TJ = 25°C
V
VCC Reg – 220
mV
TJ = –40°C to 125°C
TJ = 25°C
1.5
TJ = –40°C to 125°C
Cgate = 0
1
2
TJ = –40°C to 125°C
4.2
V
mA
REFERENCE SUPPLY
VREF
TJ = 25°C
Ref voltage
IREF = 0 mA
Ref voltage regulation
IREF = 0 to 10 mA
Ref current limit
TJ = –40°C to 125°C
5
4.85
TJ = 25°C
5.15
25
TJ = –40°C to 125°C
50
TJ = 25°C
20
TJ = –40°C to 125°C
V
mV
mA
10
CURRENT LIMIT
CS1
Prop
CS1 step from 0 to 0.4 V,
Time to onset of OUT transition (90%),
Cgate = 0
40
CS1 delay to output
CS2
Prop
CS2 step from 0 to 0.4 V,
Time to onset of OUT transition (90%),
Cgate = 0
50
CS2 delay to output
ns
ns
Leading edge blanking time
(1)
(2)
50
Cycle by cycle threshold voltage
(CS1)
TJ = 25°C
Cycle skip threshold voltage
(CS2)
Resets SS capacitor; auto
restart
ns
0.25
TJ = –40°C to 125°C
0.22
TJ = 25°C
TJ = –40°C to 125°C
0.28
0.25
0.22
0.28
V
V
All electrical characteristics having room temperature limits are tested during production with TA = TJ = 25°C. All hot and cold limits are
specified by correlating the electrical characteristics to process and temperature variations and applying statistical process control.
Device thermal limitations may limit usable range.
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Electrical Characteristics (continued)
Specifications are TJ = 25°C. Unless otherwise specified: VIN = 48 V, VCC = 10 V, RT = 31.3 kΩ, RSET = 27.4 kΩ(1)
PARAMETER
CS sink impedance (clocked)
TEST CONDITIONS
MIN
TJ = 25°C
ICS = 10 mA
TYP
MAX
30
TJ = –40°C to 125°C
50
UNIT
Ω
SOFT-START
Soft-start current source normal
Soft-start current source following
a CS2 event
TJ = 25°C
22
TJ = –40°C to 125°C
17
TJ = 25°C
27
1
TJ = –40°C to 125°C
0.5
1.5
µA
µA
OSCILLATOR
Frequency1
TJ = 25°C
180
TJ = –40°C to 125°C
175
TJ = 25°C
Frequency2
RT = 10.4 KΩ
Sync frequency
TJ = –40°C to 125°C
TJ = –40°C to 125°C
220
225
580
500
660
160
Sync threshold
Minimum sync pulse width
200
kHz
kHz
kHz
2
TJ = –40°C to 125°C
V
100
ns
PWM COMPARATOR
Delay to output
COMP step 5 V to 0 V,
Time to onset of OUT_A transition low
Duty cycle
TJ = –40°C to 125°C
COMP to PWM offset
COMP open circuit voltage
COMP short circuit current
40
0%
TJ = 25°C
ns
80%
1
TJ = –40°C to 125°C
0.7
TJ = –40°C to 125°C
4.3
TJ = 25°C
COMP = 0 V
1.3
TJ = –40°C to 125°C
5.9
1
0.6
1.4
V
V
mA
VOLT × SECOND CLAMP
Ramp clamp level
Delta RAMP measured from
onset of OUT_A to Ramp
peak,
COMP = 5 V
TJ = 25°C
TJ = –40°C to 125°C
2.5
2.4
2.6
V
UVLO SHUTDOWN
Undervoltage shutdown threshold
Undervoltage shutdown
hysteresis
TJ = 25°C
2.5
TJ = –40°C to 125°C
2.44
TJ = 25°C
2.56
20
TJ = –40°C to 125°C
16
24
V
µA
OUTPUT SECTION
6
TJ = 25°C
5
Ω
OUT_A high saturation
MOS device at Iout = –10 mA
OUT_A low saturation
MOS device at Iout = 10 mA
OUT_B high saturation
MOS device at Iout = –10 mA
OUT_B low saturation
MOS device at Iout = 10 mA
OUTPUT_B peak current sink
Bipolar device at Vcc/2
1
OUTPUT_A peak current sink
Bipolar device at Vcc/2
3
A
OUTPUT_A rise time
Cgate = 2.2 nF
20
ns
OUTPUT_A fall time
Cgate = 2.2 nF
15
ns
OUTPUT_B rise time
Cgate = 1 nF
20
ns
OUTPUT_B fall time
Cgate = 1 nF
15
ns
TJ = –40°C to 125°C
TJ = 25°C
10
6
TJ = –40°C to 125°C
TJ = 25°C
9
10
TJ = –40°C to 125°C
TJ = 25°C
20
12
TJ = –40°C to 125°C
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Ω
Ω
Ω
A
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Electrical Characteristics (continued)
Specifications are TJ = 25°C. Unless otherwise specified: VIN = 48 V, VCC = 10 V, RT = 31.3 kΩ, RSET = 27.4 kΩ(1)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
OUTPUT TIMING CONTROL
Overlap time
RSET = 38 kΩ connected to
GND, 50% to 50% transitions
TJ = 25°C
Deadtime
RSET = 29.5 kΩ connected to
REF, 50% to 50% transitions
TJ = 25°C
TJ = –40°C to 125°C
TJ = –40°C to 125°C
105
75
135
105
75
135
ns
ns
THERMAL SHUTDOWN
TSD
Thermal shutdown threshold
165
°C
Thermal shutdown hysteresis
25
°C
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6.6 Typical Characteristics
16
10
VIN
14
8
12
6
VCC (V)
VCC (V)
10
VCC
8
4
6
4
2
2
0
0
0
2
4
6
8
10
12
14
16
0
5
10
15
20
VIN (V)
ICC (mA)
Figure 1. VCC Regulator Start-Up Characteristics, VCC vs Vin
Figure 2. VCC vs ICC
25
1000
6
FREQUENCY (kHz)
5
VREF (V)
4
3
2
1
100
0
0
5
10
15
20
1
25
10
IREF (mA)
RT (k:)
Figure 3. VREF vs IREF
Figure 4. Oscillator Frequency vs RT
400
140
350
130
300
OVERLAP TIME (ns)
OVERLAP TIME (ns)
100
250
200
150
120
110
100
100
90
50
80
-40
0
0
20
40
60
80
100
75
125
o
TEMPERATURE ( C)
RSET (k:)
Figure 5. Overlap Time vs RSET
8
25
120
Figure 6. Overlap Time vs Temperature RSET = 38 K
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Typical Characteristics (continued)
140
400
350
130
DEADTIME (ns)
DEADTIME (ns)
300
250
200
150
120
110
100
100
90
50
80
-40
0
0
20
40
60
80
100
120
RSET (k:)
25
75
125
o
TEMPERATURE ( C)
Figure 7. Dead Time vs RSET
Figure 8. Dead Time vs Temperature RSET = 29.5 K
26
SS CURRENT (PA)
24
22
20
18
16
14
-40
25
75
125
o
TEMPERATURE ( C)
Figure 9. SS Pin Current vs Temperature
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7 Detailed Description
7.1 Overview
The LM5025 PWM controller contains all of the features necessary to implement power converters using the
active clamp reset technique. The device can be configured to control either a P-channel clamp switch or an
N-channel clamp switch. With the active clamp technique higher efficiencies and greater power densities can be
realized compared to conventional catch winding or RDC clamp and reset techniques. Two control outputs are
provided, the main power switch control (OUT_A), and the active clamp switch control (OUT_B). The active
clamp output can be configured for either a specified overlap time (for P-channel switch applications) or a
specified dead time (for N_channel applications). The two internal compound gate drivers parallel both MOS and
bipolar devices, providing superior gate-drive characteristics. This controller is designed for high-speed operation
including an oscillator frequency range up to 1 MHz and total PWM and current sense propagation delays less
than 100 ns. The LM5025 includes a high-voltage start-up regulator that operates over a wide input of
13 V to 90 V. Additional features include: line undervoltage lockout (UVLO), soft-start, oscillator UP and DOWN
sync capability, precision reference and thermal shutdown.
10
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7.2 Functional Block Diagram
7.6V SERIES
REGULATOR
VIN
VCC
5V
REFERENCE
VCC
UVLO
UVLO
REF
LOGIC
+
-
2.5V
UVLO
HYSTERESIS
(20 PA)
VCC
OUT_A
CLK
RT
DRIVER
OSCILLATOR
SYNC
SLOPE D TO VIN
DEADTIME
OR
OVERLAP
CONTROL
FF RAMP
RAMP
VCC
5V
5k
COMP
+
-
OUT_B
PWM
1V
SS Amp
(Sink Only)
SS
TIME
LOGIC
S
Q
R
Q
DRIVER
+
2.5V
MAX V*S
CLAMP
CS1
PGND
+
-
0.25V
CS2
+
0.25V
CLK + LEB
SS
AGND
20 PA
SS
19 PA
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7.3 Feature Description
7.3.1 High-Voltage Start-Up Regulator
The LM5025 contains an internal high-voltage start-up regulator that allows the input pin (VIN) to be connected
directly to the line voltage. The regulator output is internally current limited to 20 mA. When power is applied, the
regulator is enabled and sources current into an external capacitor connected to the VCC pin. The recommended
capacitance for the VCC regulator is 0.1 µF to 100 µF. When the voltage on the VCC pin reaches the regulation
point of 7.6 V and the internal voltage reference (REF) reaches its regulation point of 5 V, the controller outputs
are enabled. The outputs remains enabled until VCC falls below 6.2 V or the line undervoltage lock out detector
indicates that VIN is out of range. In typical applications, an auxiliary transformer winding is connected through a
diode to the VCC pin. This winding must raise the VCC voltage above 8 V to shut off the internal start-up regulator.
Powering VCC from an auxiliary winding improves efficiency while reducing the controller power dissipation.
The external VCC capacitor must be sized such that the capacitor and VCC self-bias maintains a VCC voltage
greater than 6.2 V during the initial start-up. During a fault mode when the converter auxiliary winding is inactive,
external current draw on the VCC line must be limited so the power dissipated in the start-up regulator does not
exceed the maximum power dissipation of the controller.
An external start-up regulator or other bias rail can be used instead of the internal start-up regulator by
connecting the VCC and the VIN pins together and feeding the external bias voltage into the two pins.
7.3.2 Line Undervoltage Detector
The LM5025 contains a line undervoltage lock out (UVLO) circuit. An external set-point voltage divider from Vin
to GND, sets the operational range of the converter. The divider must be designed such that the voltage at the
UVLO pin is greater than 2.5 V when Vin is in the desired operating range. If the undervoltage threshold is not
met, all functions of the controller are disabled and the controller remains in a low-power standby state. UVLO
hysteresis is accomplished with an internal 20-µA current source that is switched on or off into the impedance of
the set-point divider. When the UVLO threshold is exceeded, the current source is activated to instantly raise the
voltage at the UVLO pin. When the UVLO pin voltage falls below the 2.5-V threshold, the current source is turned
off, causing the voltage at the UVLO pin to fall. The UVLO pin can also be used to implement a remote enable
and disable function. Pulling the UVLO pin below the 2.5-V threshold disables the converter.
7.3.3 PWM Outputs
The relative phase of the main (OUT_A) and active clamp outputs (OUT_B) can be configured for the specific
application. For active clamp configurations using a ground referenced P-channel clamp switch, the two outputs
must be in phase with the active clamp output overlapping the main output. For active clamp configurations using
a high side N-channel switch, the active clamp output must be out of phase with main output and there must be a
dead time between the two gate drive pulses. A distinguishing feature of the LM5025 is the ability to accurately
configure either dead time (both off) or overlap time (both on) of the gate driver outputs. The overlap and
deadtime magnitude is controlled by the resistor value connected to the TIME pin of the controller. The opposite
end of the resistor can be connected to either REF for deadtime control or GND for overlap control. The internal
configuration detector senses the connection and configures the phase relationship of the main and active clamp
outputs.
7.3.4 Compound Gate Drivers
The LM5025 contains two unique compound gate drivers, which parallel both MOS and bipolar devices to
provide high-drive current throughout the entire switching event. The bipolar device provides most of the drive
current capability and provides a relatively constant sink current that is ideal for driving large power MOSFETs.
As the switching event nears conclusion and the bipolar device saturates, the internal MOS device continues to
provide a low-impedance to compete the switching event.
During turnoff at the Miller plateau region, typically around 2 V to 3 V, is where gate driver current capability is
needed most. The resistive characteristics of all MOS gate drivers are adequate for turnon, because the supply
to output voltage differential is fairly large at the Miller region. During turnoff however, the voltage differential is
small and the current source characteristic of the bipolar gate driver is beneficial to provide fast drive capability.
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Feature Description (continued)
VCC
OUT
CNTRL
PGND
Figure 10. Compound Gate Drivers
7.3.5 PWM Comparator
The PWM comparator compares the ramp signal (RAMP) to the loop error signal (COMP). This comparator is
optimized for speed to achieve minimum controllable duty cycles. The internal 5-kΩ pullup resistor, connected
between the internal 5-V reference and COMP can be used as the pullup for an optocoupler. The comparator
polarity is such that 0 V on the COMP pin produces a zero-duty cycle on both gate driver outputs.
7.3.6 Volt Second Clamp
The volt × second clamp comparator compares the ramp signal (RAMP) to a fixed 2.5-V reference. By proper
selection of RFF and CFF, the maximum ON time of the main switch can be set to the desired duration. The ON
time set by volt × second clamp varies inversely with the line voltage because the RAMP capacitor is charged by
a resistor connected to Vin while the threshold of the clamp is a fixed voltage (2.5 V).
The CFF ramp capacitor is discharged at the conclusion of every cycle by an internal discharge switch controlled
by either the internal clock or by the V × S Clamp comparator, whichever event occurs first.
7.3.7 Current Limit
The LM5025 contains two modes of overcurrent protection. If the sense voltage at the CS1 input exceeds 0.25 V
the present power cycle is terminated (cycle-by-cycle current limit). If the sense voltage at the CS2 input exceeds
0.25 V, the controller terminates the present cycle, discharge the soft-start capacitor and reduce the soft-start
current source to 1 µA. The soft-start (SS) capacitor is released after being fully discharged and slowly charges
with a 1-µA current source. When the voltage at the SS pin reaches approximately 1 V, the PWM comparator
produces the first output pulse at OUT_A. After the first pulse occurs, the soft-start current source reverts to the
normal 20-µA level. Fully discharging and then slowly charging the SS capacitor protects a continuously
overloaded converter with a low-duty cycle hiccup mode.
These two modes of overcurrent protection allows the user great flexibility to configure the system behavior in
overload conditions. If it is desired for the system to act as a current source during an overload, then the CS1
cycle-by-cycle current limiting must be used. In this case the current sense signal must be applied to the CS1
input and the CS2 input must be grounded. If during an overload condition it is desired for the system to briefly
shutdown, followed by soft-start retry, then the CS2 hiccup current limiting mode must be used. In this case the
current sense signal must be applied to the CS2 input and the CS1 input must be grounded. This shutdown and
soft-start retry repeats indefinitely while the overload condition remains. The hiccup mode greatly reduces the
thermal stresses to the system during heavy overloads. The cycle-by-cycle mode has higher system thermal
dissipations during heavy overloads, but provides the advantage of continuous operation for short duration
overload conditions.
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Feature Description (continued)
In some systems it is possible use both modes concurrently, whereby slight overload conditions activate the CS1
cycle-by cycle mode, while more severe overloading activates the CS2 hiccup mode. Operating both modes
concurrently requires that the slope of the inductor current be sufficient to reach the CS2 threshold before the
CS1 function turns off the main output switch. This requires a high dv/dt at the current sense pin. The signal
must be fast enough to reach the second-level threshold before the first threshold detector (CS1) turns off the
gate driver. Excessive filtering on the CS pin, an extremely low-value current sense resistor or an inductor that
does not saturate with excessive loading may prevent the second-level threshold from ever being reached.
TI recommends a small RC filter, located near the controller, for each of the CS pins. Each CS input has an
internal FET that discharges the current sense filter capacitor at the conclusion of every cycle, to improve
dynamic performance. This same FET remains on an additional 50 ns at the start of each main switch cycle to
attenuate the leading edge spike in the current sense signal.
The LM5025 CS comparators are very fast and may respond to short duration noise pulses. Layout
considerations are critical for the current sense filter and sense resistor. The capacitor associated with the CS
filter must be placed very close to the device and connected directly to the pins of the IC (CS and GND). If a
current sense transformer is used, both leads of the transformer secondary must be routed to the filter network ,
which must be located close to the IC. If a sense resistor in the source of the main switch MOSFET is used for
current sensing, a low-inductance type of resistor is required. When designing with a current sense resistor, all of
the noise sensitive low-power ground connections must be connected together near the IC GND and a single
connection must be made to the power ground (sense resistor ground point).
CS2
SS
20 PA
1 PA
Figure 11. Current Limit
7.3.8 Oscillator and Sync Capability
The LM5025 oscillator is set by a single external resistor connected between the RT pin and GND.
The RT resistor must be located very close to the device and connected directly to the pins of the IC (RT and
GND).
A unique feature of LM5025 is the ability to synchronize the oscillator to an external clock with a frequency that is
either higher or lower than the frequency of the internal oscillator. The lower frequency sync frequency range is
80% of the free running internal oscillator frequency. There is no constraint on the maximum SYNC frequency. A
minimum pulse width of 100 ns is required for the synchronization clock . If the synchronization feature is not
required, the SYNC pin must be connected to GND to prevent any abnormal interference. The internal oscillator
can be completely disabled by connecting the RT pin to REF. Once disabled, the sync signal acts directly as the
master clock for the controller. Both the frequency and the maximum duty cycle of the PWM controller can be
controlled by the SYNC signal (within the limitations of the volt × second clamp). The maximum duty cycle (D) is
(1D) of the SYNC signal.
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Feature Description (continued)
7.3.9 Feed-Forward Ramp
An external resistor (RFF) and capacitor (CFF) connected to VIN and GND are required to create the PWM ramp
signal. The slope of the signal at the RAMP pin varies in proportion to the input line voltage. This varying slope
provides line feedforward information necessary to improve line transient response with voltage mode control.
The RAMP signal is compared to the error signal at the COMP pin by the pulse width modulator comparator to
control the duty cycle of the main switch output. The volt second clamp comparator also monitors the RAMP pin
and if the ramp amplitude exceeds 2.5 V the present cycle is terminated. The ramp signal is reset to GND at the
end of each cycle by either the internal clock or the volt second comparator, whichever occurs first.
7.3.10 Soft-Start
The soft-start feature allows the power converter to gradually reach the initial steady state operating point, thus
reducing start-up stresses and surges. At power on, a 20-µA current is sourced out of the soft-start pin (SS) into
an external capacitor. The capacitor voltage ramps up slowly and limits the COMP pin voltage and therefore the
PWM duty cycle. In the event of a fault as determined by VCC undervoltage, line undervoltage (UVLO), or
second-level current limit, the output gate drivers are disabled and the soft-start capacitor is fully discharged.
When the fault condition is no longer present a soft-start sequence is initiated. Following a second-level current
limit detection (CS2), the soft-start current source is reduced to 1 µA until the first output pulse is generated by
the PWM comparator. The current source returns to the nominal 20-µA level after the first output pulse
(approximately 1 V at the SS pin).
7.3.11 Thermal Protection
Internal thermal shutdown circuitry is provided to protect the integrated circuit in the event the maximum junction
temperature is exceeded. When activated, typically at 165°C, the controller is forced into a low-power standby
state with the output drivers and the bias regulator disabled. The device restarts after the thermal hysteresis
(typically 25°C). During a restart after thermal shutdown, the soft-start capacitor is fully discharged and then
charged in the low-current mode (1 µA) similar to a second-level current limit event. The thermal protection
feature is provided to prevent catastrophic failures from accidental device overheating.
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7.4 Device Functional Modes
The LM5025 active clamp voltage mode PWM controller has six functional modes. The modes transition diagram
is shown in Figure 12.
•
•
•
•
•
•
UVLO Mode
Soft-Start Mode
Normal Operation Mode
Cycle-by-Cycle Current Limit Mode
Hiccup Mode
Thermal Shut Down Mode
UVLO
CBC
Soft Start
Hiccup
Normal Operation
Thermal Shut Down
Figure 12. Functional Mode Transition Diagram
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8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers must
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The LM5025 PWM controller contains all of the features necessary to implement power converters using the
active clamp and reset technique. This section provides design guidance for a typical active clamp forward
converter design. An actual application schematic of a 36-V to 78-V input, 3.3-V, 30-A output active clamp
forward converter is also provided in Figure 21.
8.2 Typical Application
Figure 13 shows a simplified schematic of an active clamp forward power converter.
Power converters based on the forward topology offer high-efficiency and good power-handling capability in
applications up to several hundred Watts. The operation of the transformer in a forward topology does not
inherently self-reset each power switching cycle, a mechanism to reset the transformer is required. The active
clamp reset mechanism is presently finding extensive use in medium-level power converters in the 50 W to
200 W range.
The forward converter is derived from the Buck topology family, employing a single modulating power switch.
The main difference between the topologies is the forward topology employs a transformer to provide input and
output ground isolation and a step down or step up function.
Each cycle, the main primary switch turns on and applies the input voltage across the primary winding. The
transformer turns the voltage to a lower-level on the secondary side. The clamp capacitor along with the reset
switch reverse biases the transformer primary each cycle when the main switch turns off. This reverse voltage
resets the transformer. The clamp capacitor voltage is VIN / (1-D).
The secondary rectification employs self-driven synchronous rectification to maintain high-efficiency and ease of
drive.
Feedback from the output is processed by an amplifier and reference, generating an error voltage, which is
coupled back to the primary side control through an opto-coupler. The LM5025 voltage mode controller pulse
width modulates the error signal with a ramp signal derived from the input voltage. Deriving the ramp signal slope
from the input voltage provides line feed-forward, which improves line transient rejection. The LM5025 also
provides a controlled delay necessary for the reset switch.
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Typical Application (continued)
VOUT
3.3V
VIN
35 - 78V
LM5025
CS1
CS2
VIN
VCC
UVLO
ERROR
AMP &
ISOLATION
OUT_A
OUT_B
RAMP
COMP
REF
Rt
SYNC
TIME
SS
PGND AGND
UP/DOWN
SYNC
Figure 13. Simplified Active Clamp Forward Power Converter
8.2.1 Design Requirements
This typical application provides an example of a fully-functional power converter based on the active clamp
forward topology in an industry standard half-brick footprint.
The design requirements are:
•
•
•
•
•
•
•
•
•
Input: 36 V to 78 V (100-V peak)
Output Voltage: 3.3 V
Output Current: 0 A to 30 A
Measured Efficiency: 90.5% at 30 A, 92.5% at 15 A
Frequency of Operation: 230 kHz
Board Size: 2.3 × 2.4 × 0.5 inches
Load Regulation: 1%
Line Regulation: 0.1%
Line UVLO, Hiccup Current Limit
8.2.2 Detailed Design Procedure
Before the controller design begins, the power stage design must be completed. This section describes the
calculations needed to configure the LM5025 controller to meet the power stage design requirements.
8.2.2.1 Oscillator
The desired switching frequency F is set by a resistor connected between RT pin and ground. The resistance
value RT is calculated from Equation 1:
RT = (5725/F)1.026
where
•
18
F is in kHz and RT in kΩ.
(1)
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Typical Application (continued)
8.2.2.2 Soft-Start Ramp Time and Hiccup Interval
The soft-start ramp time and hiccup internal is programmed by a capacitor (CSS) on the SS pin to ground. The
soft-start ramp time is determined by comparing the SS pin voltage with COMP pin voltage. When the SS voltage
is less than COMP voltage, the COMP voltage is clamped by SS voltage. The PWM duty is limited by the
clamped COMP voltage, so that soft-start can be achieved. The first PWM pulse is generated after COMP
voltage reaches 1 V. So the soft-start ramp time of the output voltage can be estimated by Equation 2:
V
1V
TSS (ms) CSS (nF) u SS
20 PA
where
•
VSS is the steady state COMP pin voltage. This voltage is determined by the output voltage, voltage divider,
and the compensation network.
(2)
In hiccup mode, the SS current source is reduced to 1 µA. When the first PWM pulse is generated, the current
source switches to 20 µA, and the power supply tries to start up again. The hiccup interval can be calculated by
Equation 3:
1V
Thiccup (ms) CSS (nF) u
1 PA
(3)
8.2.2.3 Feed-Forward Ramp and Maximum On Time Clamp
An example illustrates the use of the Volt × Second Clamp comparator to achieve a 50% duty cycle limit, at 200
KHz, at a 48-V line input: A 50% duty cycle at a 200 KHz requires a 2.5 µs of ON time. At 48-V input the Volt ×
Second product is 120 V × µs (48 V × 2.5 µs). To achieve this clamp level, see Equation 4 and Equation 5:
RFF × CFF = VIN × TON / 2.5 V
48 × 2.5 µF / 2.5 = 48 µF
(4)
(5)
Select CFF = 470 pF
RFF = 102 kΩ
The recommended capacitor value range for CFF is 100 pF to 1000 pF.
8.2.2.4 Dead Times
The magnitude of the overlap and dead time can be calculated as follows in Equation 6 and Equation 7:
Overlap Time (ns) = 2.8 × RSET – 1.2
Dead Time (ns) = 2.9 × RSET + 20
(6)
where
•
RSET in kΩ, Time in ns
(7)
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Typical Application (continued)
OUT_A
K1 x RSET
P-Channel Active Clamp
(RSET to GND)
OUT_B
OUT_A
N-Channel Active Clamp
(RSET to REF)
K2 x RSET
OUT_B
Figure 14. PWM Outputs
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Typical Application (continued)
8.2.3 Application Curves
1
2
1
Conditions: input voltage = 48 VDC, output current = 5 A
Trace 1: output voltage Volts/div = 0.5 V
Horizontal resolution = 1 ms/div
Conditions: input voltage = 48 VDC, output current = 5 A to 25 A
Trace 1: output voltage Volts/div = 0.5 V
Trace 2: output current, Amps/div = 10 A
Horizontal resolution = 1 μs/div
Figure 15. Output Voltage During Typical Startup
Figure 16. Transient Response
1
1
Conditions: input voltage = 48 VDC, output current = 30 A
Bandwidth limit = 25 MHz
Trace 1: output ripple voltage Volts/div = 50 mV
Horizontal resolution = 2 μs/div
Conditions: input voltage = 38 VDC, output current = 25 A
Trace 1: Q1 drain voltage Volts/div = 20 V
Horizontal resolution = 1 μs/div
Figure 17. Output Ripple
Figure 18. Drain Voltage
1
2
1
Conditions: input voltage = 78 VDC, output current = 25 A
Trace 1: Q1 drain voltage Volts/div = 20 V
Horizontal resolution = 1 μs/div
Figure 19. Drain Voltage
Conditions: input voltage = 48 VDC, output current = 5 A
Synchronous rectifier, Q3 gate Volts/div = 5 V
Trace 1: synchronous rectifier, Q3 gate Volts/div = 5 V
Trace 2: synchronous rectifier, Q5 gate Volts/div = 5 V
Horizontal resolution = 1 μs/div
Figure 20. Gate Voltages of the Synchronous Rectifiers
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Typical Application (continued)
8.2.4 System Example
Figure 21 shows an application circuit with 36-V to 78-V input and 3.3-V, 30-A output capability.
Figure 21. Application Circuit
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9 Power Supply Recommendations
VCC pin is the power supply for the device. There must be a 0.1-µF to approximately 100-μF capacitor directly
from VCC to ground. REF pin must be bypassed to ground as close as possible to the device using a 0.1-μF
capacitor.
10 Layout
10.1 Layout Guidelines
•
•
•
•
•
•
Connect two grounds PGND (power ground) and AGND (analog ground) directly as device ground ICGND.
The connection must be as close to the pins as possible.
If there are multiple PCB layers and there is a inner ground layer, use two vias or one big via on GND and
connect them to the inner ground layer (ICGND).
The power stage ground PSGND should be separated with the ICGND. PSGND and ICGND should be
connected at a single point close to the device.
The bypass capacitors to the VCC pin and REF pin should be as close as possible to the pins and ground
(ICGND).
The filtering capacitors connected to CS1 and CS2 pins should have connections as short as possible to
ICGND; if an inner ground layer is available, use vias to connect the capacitors to the ground layer (ICGND).
The resistors and capacitors connected to the timing configuration pins should be as close as possible to the
pins and ground (ICGND).
10.2 Layout Example
Figure 22. LM5025 Layout Recommendation
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11 Device and Documentation Support
11.1 Documentation Support
11.1.1 Related Documentation
For related documentation, see the following:
• LM5025 Isolated Active Clamp Forward Converter Ref Design User Guide, SNVU096
11.2 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
11.3 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
11.4 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
11.5 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
LM5025MTC/NOPB
ACTIVE
TSSOP
PW
16
92
RoHS & Green
NIPDAU | SN
Level-1-260C-UNLIM
-40 to 125
LM5025
MTC
LM5025MTCX/NOPB
ACTIVE
TSSOP
PW
16
2500
RoHS & Green
NIPDAU | SN
Level-1-260C-UNLIM
-40 to 125
LM5025
MTC
LM5025SD/NOPB
ACTIVE
WSON
NHQ
16
1000
RoHS & Green
SN
Level-1-260C-UNLIM
-40 to 125
5025SD
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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