LM5064
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SNVS718E – JUNE 2011 – REVISED FEBRUARY 2013
LM5064 Negative Voltage System Power Management and Protection IC with PMBus
Check for Samples: LM5064
FEATURES
APPLICATIONS
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Input Voltage Range: -10V to -80V
Programmable 26 mV or 50 mV Current Limit
Threshold with Power Limiting (MOSFET
Power Dissipation Limiting)
Real Time Monitoring of VIN, VOUT, IIN, PIN, VAUX
with 12-Bit Resolution and 1 kHz Sampling
Rate
Configurable Circuit Breaker Protection for
Hard Shorts
Configurable Under-Voltage and Over-Voltage
Protection
Remote Temperature Sensing with
Programmable Warning and Shutdown
Thresholds
Detection and Notification of Damaged
MOSFET Condition
Power Measurement Accuracy: ±4.5% Over
Temperature
True Input Power Averages Dynamic Power
Readings
Averaging of VIN, IIN, PIN, and VOUT Over
Programmable Interval Ranging from 0.001 to
4 Seconds
Programmable WARN and FAULT Thresholds
with SMBA Notification
Black Box Capture of Telemetry
Measurements and Device Status Triggered by
WARN or FAULT Condition
I2C/SMBus Interface and PMBus Compliant
Command Structure
Full Featured Application Development
Software
HTSSOP-28 Package
Base Station Power Distribution Systems
Intelligent Solid State Circuit Breaker
-24V/-48V Industrial Systems
DESCRIPTION
The LM5064 combines a high performance hot swap
controller with a PMBusTM compliant SMBus/I2C
interface to accurately measure, protect and control
the electrical operating conditions of systems
connected to a backplane power bus. The LM5064
continuously supplies real-time power, voltage,
current, temperature and fault data to the system
management host via the SMBus interface.
The LM5064 control block includes a unique hot
swap architecture that provides current and power
limiting to protect sensitive circuitry during insertion of
boards into a live system backplane, or any other
"hot" power source. A fast acting circuit breaker
prevents damage in the event of a short circuit on the
output. The input under-voltage and over-voltage
levels and hysteresis are configurable, as well as the
insertion delay time and fault detection time. A
temperature monitoring block on the LM5064
interfaces with a low-cost external diode for
monitoring the temperature of the external MOSFET
or other thermally sensitive components. The PGD
output provides a fast indicator when the input and/or
output voltages are outside their programmed ranges.
The LM5064 monitoring circuit computes both the
real-time and average values of subsystem operating
parameters (VIN, IIN, PIN, VOUT) as well as the peak
power. Accurate power averaging is accomplished by
averaging the product of the input voltage and
current. A black box (Telemetry/Fault Snapshot)
function captures and stores telemetry data and
device status in the event of a warning or a fault.
1
2
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2011–2013, Texas Instruments Incorporated
LM5064
SNVS718E – JUNE 2011 – REVISED FEBRUARY 2013
www.ti.com
Typical Application Circuit
GND
GND
VDD
LOAD
R1
VAUXH
UVLO/EN
R2
PGD
Z1
0V-2.97V
Auxiliary
ADC Input
INPUT
RAIL
-48V
EN
OUT
OVLO
R3 SMBus
Interface
RPG
VCC
ADR0
ADR1
ADR2
+
GATE
SMBA
SCL
SDAI
SDAO
LM5064
D1
SENSE
VAUX
CL
RETRY
VEE TIMER VREF
SENSE_ K
VEE_K
VDD
1 µF
CT
COUT
PWR DIODE
1 µF
Q1
RPWR
QT
RS
OUTPUT
Connection Diagram
VCC
VAUXH
NC
GATE
UVLO/EN
OVLO
SENSE
SENSE_K
VEE_K
VEE
SDAI
SDAO
SCL
SMBA
1
2
3
4
5
6
7
Exposed
Pad
8
9
10
11
12
13
14
28 PGD
27
NC
26
OUT
25
PWR
24
TIMER
23
RETRY
22
CL
21
VDD
20
ADR0
19 ADR1
18 ADR2
17
VAUX
16
DIODE
15
VREF
Top View
28-Lead HTSSOP
9.7 mm × 4.4 mm × 0.9 mm
PWP0028A Package
PIN DESCRIPTIONS
Pin#
Name
1
VCC
2
VAUXH
3
NC
4
GATE
5
UVLO/EN
6
OVLO
2
Description
Positive supply input. Connect the VCC pin to the positive voltage rail.
High voltage auxiliary input. VCC with respect to VEE is measured by connecting the VAUXH pin to the VCC rail.
No connect. This pin is not internally connected and should not be connected to any signal or power rail.
MOSFET gate control signal for fault control of the output. The GATE pin is clamped to VEE through a 12.6V
internal zener diode.
Under-voltage lockout threshold input. Connecting the UVLO pin to a resistor divider from VCC to VEE will set the
under-voltage lockout threshold. After the UVLO pin voltage falls below 2.48V, an internal 20 µA current source is
switched to provide a user settable hysteresis. The UVLO pin can be toggled directly to act as a precision enable.
After the UVLO threshold voltage is exceeded, the output voltage will begin to transition to VVEE as the GATE pin
supplies 52 µA to turn on the MOSFET.
Over-voltage lockout threshold input. Connecting the OVLO pin to a resistor divider from VCC to VEE will set the
over-voltage lockout threshold. After the OVLO pin voltage exceeds 2.47V, an internal 21 µA current source is
switched to provide a user settable hysteresis. If the OVLO threshold is exceeded, the MOSFET will be immediately
disabled to protect the output.
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PIN DESCRIPTIONS (continued)
Pin#
Name
7
SENSE
Description
8
SENSE_K
9
VEE_K
10
VEE
Negative supply input. Connect the VEE pin to the negative voltage supply rail. Use a small ceramic bypass
capacitor (0.1 µF) from the VEE pin to the VCC pin to suppress transient current spikes when the load switch is
turned off. The operational voltage range for the VEE pin is -10V to -80V. The VEE pin absolute maximum voltage
is -100V.
11
SDAI
SMBus data input. The SDAI pin is designed to read PMBus commands using the SMBus communication protocol.
SDAI can be connected to SDAO if desired.
12
SDAO
SMBus data output. The SDAO pin is designed to transmit PMBus commands using the SMBus communication
protocol. SDAO can be connected to SDAI if desired.
Current limit and power limit sense input. SENSE provides a direct connection to the MOSFET source and current
sense resistor voltage to detect current limit and power limit events. This unfiltered signal will allow the LM5064 to
quickly respond during over-current or over-power events.
Current telemetry Kelvin sense positive input. SENSE_K is the positive input to a precision differential current sense
amplifier. Connecting SENSE_K to the positive terminal of the current sense resistor will provide an accurate
current telemetry signal.
Current telemetry Kelvin sense negative input. The VEE_K pin is the negative input to a precision differential
current sense amplifier. Connecting VEE_K to the negative terminal of the current sense resistor will provide an
accurate current signal.
13
SCL
14
SMBA
SMBus clock input.
SMBus alert. This pin is connected to an open drain MOSFET which pulls the pin to VEE if a fault is detected.
15
VREF
Internal ADC reference output. Connect a 1 µF capacitor from the VREF pin to VEE to filter noise imposed on the
internal reference output.
16
DIODE
Positive diode sense. The DIODE pin should be connected to the anode of a diode whose cathode is connected to
VEE for temperature monitoring.
17
VAUX
Auxiliary pin allows voltage telemetry from an external source. Full scale input of 2.97V.
18
ADR2
Address pin 2. The address pins can be connected to VDD, VEE, or left open to set the PMBus address of the
LM5064.
19
ADR1
Address pin 1 The address pins can be connected to VDD, VEE, or left open to set the PMBus address of the
LM5064.
20
ADR0
Address pin 0. The address pins can be connected to VDD, VEE, or left open to set the PMBus address of the
LM5064.
21
VDD
Internal 4.9V sub-regulator output. VDD must be connected and closely coupled to VEE through a 1 µF ceramic
bypass capacitor.
22
CL
23
RETRY
Retry selction pin. Connecting RETRY to VDD sets the LM5064 to lockout after a fault condition is detected.
Connecting RETRY to VEE sets the LM5064 to retry after a fault condition.
24
TIMER
Timing input. Set the insertion time delay and the fault timeout period by connecting a capacitor from the TIMER pin
to VEE. The restart time is also set through the TIMER pin when in restart mode.
25
PWR
Power limit input. Connecting a resistor from PWR to VEE sets the maximum power dissipation allowed in the
external MOSFET switch. Power is calculated using the current information through the current sense resistor and
voltage sensed across the MOSFET.
26
OUT
Output voltage sense input. The OUT pin is used to sense the output voltage and calculate the power across the
MOSFET switch.
27
NC
28
PGD
EP
EP
Current limit threshold input. The LM5064 detects current limit events by sensing the voltage across a series
resistor. The current limit threshold is set to 26 mV by connecting CL to VDD and 50 mV when CL is connected to
VEE.
No connect. This pin is not internally connected and should not be connected to any signal or power rail.
Power good monitor output. Open-drain output pulls low during over-current, UVLO, and OVLO. An external pull-up
resistor to VDD or external rail is required.
Exposed pad. Connect to PCB VEE plane using multiple thermal vias.
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
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LM5064
SNVS718E – JUNE 2011 – REVISED FEBRUARY 2013
Absolute Maximum Ratings
www.ti.com
(1)
VCC, UVLO/EN, OUT, VAUXH, PGD to VEE
-0.3V to 100V
GATE to VEE
-0.3V to 16V
OVLO, TIMER, PWR to VEE
-0.3V to 7V
SENSE_K, SENSE, VEE_K to VEE
-0.3V to +0.3V
SCL, SDAI, SDAO, SMBA, CL, ADR0, ADR1, ADR2, VDD, VAUX, DIODE, RETRY , VREF to
VEE
-0.3V to 6V
ESD Rating
Human Body Model (2)
2 kV
Storage Temperature
-65°C to 150°C
Junction Temperature
150°C
(1)
(2)
Absolute Maximum Ratings are limits beyond which damage to the device may occur. Operating Ratings are conditions under which
operation of the device is intended to be functional. For specifications and test conditions, see the Electrical Characteristics.
The human body model is a 100 pF capacitor discharged through a 1.5 kΩ resistor into each pin. 2 kV rating for all pins except GATE
and PGD which are rated at 1.5 kV and 1 kV respectively.
Operating Ratings
VCC supply voltage above VEE
10V to +80V
OUT voltage above VEE
0V to +80V
PGD off voltage above VEE
0V to +80V
−40°C to + 125°C
Junction temperature
4
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SNVS718E – JUNE 2011 – REVISED FEBRUARY 2013
Electrical Characteristics
Limits in standard type are for TJ = 25°C only; limits in boldface type apply over the junction temperature (TJ) range of -40°C
to +125°C. Minimum and Maximum limits are specified through test, design, or statistical correlation. Typical values represent
the most likely parametric norm at TJ = 25°C, and are provided for reference purposes only. Unless otherwise stated the
following conditions apply: VCC-VEE = 48V. See (1) (2).
Symbol
Parameter
Conditions
Min
Typ
Max
Units
Input (VCC)
IIN-EN
Input current, enabled
VCC - VEE = 48V, UVLO/EN = 5V
6
8
mA
PORIT
Threshold voltage to start
insertion timer
VCC - VEE increasing
8
9.2
V
POREN
Threshold voltage to enable
all functions
VCC - VEE increasing
8.7
9.9
V
POREN hysteresis
VCC - VEE decreasing
170
Enabled, OUT = VEE
-100
nA
Disabled, OUT = VEE + 48V
135
µA
POREN-HYS
mV
Output (OUT)
IOUT-EN
OUT bias current, enabled
IOUT-DIS
OUT bias current, disabled
(3)
OVLO/UVLO
UVLOTH
UVLO/EN threshold
UVLO/EN Falling
UVLOHYS
UVLO/EN hysteresis current
UVLO/EN = VEE + 2V
UVLODEL
UVLO delay
Delay to GATE high
9
Delay to GATE low
12
UVLOBIAS
UVLO/EN bias current
2.41
2.48
2.55
V
13
20
26
µA
UVLO/EN = VEE + 5V
µs
µs
1
µA
OVLOTH
OVLO threshold
OVLOHYS
OVLO hysteresis current
OVLO = VEE + 2.8V
OVLODEL
OVLO delay
Delay to GATE high
10
µs
Delay to GATE low
12
µs
OVLOBIAS
OVLO bias current
OVLO = 2.3V
Power limit sense voltage
(OUT-SENSE)
OUT – SENSE = 48V, RPWR = 145 kΩ
2.39
2.47
2.53
V
-26
-21
-13
µA
1
µA
29.5
mV
Power Limit (PWR)
PWRLIM-1
PWRLIM-2
IPWR
RSAT(PWR)
19.5
24.5
OUT - SENSE = 24V, RPWR = 75 kΩ
24.7
mV
PWR pin current
VPWR = 2.5V
-18
µA
PWR pin impedance when
disabled
UVLO/EN = 2.0V
140
Ω
Source current
Normal Operation
-72
Sink current
UVLO/EN < VEE+2V
3.4
SENSE - VEE =150 mV, VGATE =VEE+5V
50
Gate Control (GATE)
IGATE
VGATE
-52
-32
µA
4.1
5.3
mA
111
180
mA
Gate output voltage in normal
operation
GATE-VEE Voltage
12.6
V
VCL
Current limit threshold voltage
CL = VDD
VCL
Current limit threshold voltage
CL = VEE or FLOAT
tCL
Response time
SENSE-VEE stepped from 0 mV to 80 mV
54
µs
SENSE input current
Enabled, OUT = VEE
-5
µA
Disabled, OUT = VCC
-55
µA
-10
µA
Current Limit
ISENSE
ISENSE_K
(1)
(2)
(3)
(4)
(4)
(4)
SENSE_K input current
23
26
30
mV
47
50
53
mV
Absolute Maximum Ratings are limits beyond which damage to the device may occur. Operating Ratings are conditions under which
operation of the device is intended to be functional. For specifications and test conditions, see the Electrical Characteristics.
Current out of a pin is indicated as a negative value.
OUT bias current (disabled) due to leakage current through an internal 1 MΩ resistance from SENSE to OUT.
CL bit High or Low is set by either the CL pin on startup (if CL = VDD, then High, if CL = VEE or FLOAT, then Low) or by the current
limit setting bit in the device setup register.
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Electrical Characteristics (continued)
Limits in standard type are for TJ = 25°C only; limits in boldface type apply over the junction temperature (TJ) range of -40°C
to +125°C. Minimum and Maximum limits are specified through test, design, or statistical correlation. Typical values represent
the most likely parametric norm at TJ = 25°C, and are provided for reference purposes only. Unless otherwise stated the
following conditions apply: VCC-VEE = 48V. See (1) (2).
Symbol
IVEE_K
Parameter
Conditions
Min
VEE_K input current
Typ
Max
-10
Units
µA
Circuit Breaker
RTCB
VCB
tCB
Circuit breaker to current limit
ratio: (VSENSE-VVEE)/VCL
Circuit breaker threshold
voltage: (VSENSE-VVEE)
Circuit breaker response time
CB/CL ratio bit = 0, ILim = 50 mV
1.45
1.9
2.22
CB/CL ratio bit = 1, ILim = 50 mV
2.8
3.7
4.9
CB/CL ratio bit = 0, ILim = 26 mV
1.8
CB/CL ratio bit = 1, ILim = 26 mV
3.6
CB/CL ratio bit = 0, ILim = 50 mV
72
93
116
mV
CB/CL ratio bit = 1, ILim = 50 mV
144
187
230
mV
CB/CL ratio bit = 0, ILim = 26 mV
37
49
59
mV
CB/CL ratio bit = 1, ILim = 26 mV
72
93
116
mV
SENSE-VEE stepped from 0 mV to 150 mV, time
to GATE = VEE
800
ns
Timer (TIMER)
VTMRH
Upper threshold
VTMRL
Lower threshold
Restart cycles
3.74
3.9
4.07
V
1.09
1.2
1.39
V
End of 8th cycle
0.3
Re-enable threshold
ITIMER
0.3
Insertion time current
Sink current, end of insertion
time
TIMER pin = VEE+2V
Fault detection current
SENSE-VEE=VCL
Fault sink current
DCFAULT
tFAULT
V
-5.9
-4.8
-3.3
µA
1
1.5
2
mA
-95
-74
-50
µA
1.7
2.4
3.2
µA
Fault restart duty cycle
Fault to GATE = VEE delay
V
TIMER pin reaches the upper threshold
0.5
%
15
µs
Power Good (PGD)
PGDTH
Threshold measured at OUT - OUT – SENSE Decreasing
SENSE
OUT – SENSE Increasing
PGDVOL
Output low voltage
ISINK = 2 mA
PGDIOH
Off leakage current
VPGD = 80V
1.18
1.24
1.31
V
2.44
2.5
2.56
V
50
150
mV
5
µA
ADC and MUX
Resolution
INL
tACQUIRE
tRR
12
Bits
Integral non-linearity
ADC only
±4
LSB
Acquisition + conversion time
Any Channel
100
µs
Acquisition round robin time
Cycle all channels
1
ms
Internal Reference
VREF
Telemetry Accuracy
IINFSR
Reference voltage
2.93
Current input full scale range
CL= VEE
(6)
CL = VDD
IINLSB
Current input LSB
CL= VEE
(5)
(6)
6
(6)
(6)
CL = VDD
VAUXFSR
2.97
3.02
V
(5)
(6)
VAUX input full scale range
74.9
mV
38.1
mV
18.3
µV
9.3
µV
2.96
V
Full scale range depends on both the VREF value and the gain/attenuation of the current/voltage channel.
CL bit High or Low is set by either the CL pin on startup (if CL = VDD, then High, if CL = VEE or FLOAT, then Low) or by the current
limit setting bit in the device setup register.
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SNVS718E – JUNE 2011 – REVISED FEBRUARY 2013
Electrical Characteristics (continued)
Limits in standard type are for TJ = 25°C only; limits in boldface type apply over the junction temperature (TJ) range of -40°C
to +125°C. Minimum and Maximum limits are specified through test, design, or statistical correlation. Typical values represent
the most likely parametric norm at TJ = 25°C, and are provided for reference purposes only. Unless otherwise stated the
following conditions apply: VCC-VEE = 48V. See (1) (2).
Symbol
Parameter
VAUXLSB
Conditions
Min
Typ
Max
Units
VAUX input LSB
724
VAUXHFSR
VAUXH input full scale range
88.9
V
VAUXHLSB
VAUXH input LSB
21.7
mV
OUTLSB
OUT pin LSB
µV
21.7
mV
IINACC
Input current accuracy
SENSE_K-VEE_K = 50 mV, CL = VEE (Note 6)
-3.0
3.0
%
VACC
VAUX, VAUXH, OUT
VAUXH-VEE=48V,OUT - VEE= 48V, VAUX = 2.8V
-2.7
2.7
%
PINACC
Input power accuracy
VCC-VEE = 48V, SENSE_K-VEE_K = 50 mV, CL
= VDD
-4.5
4.5
%
Diode Temperature Sensor
TACC
Temperature accuracy using
local diode
TA = 25°C to 85°C
2
Remote diode resolution
IDIODE
°C
9
External diode current source
High Level
250
Low Level
bits
325
9.4
Diode current ratio
µA
µA
25.9
VAUX
IIN
Input current
VAUX = 3V
VDD regulated output
IDD = 0 mA
1
µA
5.15
V
VDD Regulation
VDDOUT
4.6
IDD = -10 mA
VDDILIM
VDD current limit
VDD = 0V
VDDPOR
VDD voltage reset threshold
VDD Rising
PMBus Pin Thresholds (SCL, SDAI/O, SMBA)
4.9
4.8
-25
-30
V
-42
4.1
mA
V
(7)
VIL
Data, clock input low voltage
With respect to VEE
VIH
Data, clock input high voltage
With respect to VEE
VOL
Data output low voltage
ISINK = 3 mA
ILEAK
Input leakage current
SDAI, SMBA, SCL = 5V above VEE
0.9
V
2.1
5.5
V
0
0.4
µA
1
µA
Pin Strappable Thresholds (CL, RETRY)
VIH
ILEAK
Thermal
(7)
(8)
Input high voltage
Input leakage current
3
CL,RETRY = 5V
V
5
µA
(8)
θJA
Junction to ambient
30
°C/W
θJC
Junction to case
4
°C/W
PMBus communication clock rate at final test is 400 kHz.
Junction to ambient thermal resistance is highly application and board layout dependent. Specified thermal resistance values for the
package specified is based on a 4-layer, 4"x3", 2/1/1/2 oz. Cu board as per JEDEC standards is used. For detailed information on
soldering plastic HTSSOP packages refer to the Packaging Data Book.
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Typical Performance Characteristics
Unless otherwise specified the following conditions apply: TJ = 25°C, VCC-VEE = 48V.
VCC Pin Current
SENSE Pin Current
-4.70
VCC = 80V
6.2
6.0
SENSE PIN CURRENT ( A)
VCC INPUT CURRENT (mA)
6.4
VCC = 48V
5.8
VCC = 9V
5.6
5.4
5.2
-50
-4.75
-4.80
-4.84
-4.90
-4.95
-5.00
-25
0
25 50 75
TEMPERATURE (°C)
100 125
-50
SENSE_K Pin Current (Enabled)
VEE_K PIN CURRENT ( A)
SENSE_K PIN CURRENT ( A)
-9.3
-9.6
-9.9
-10.2
-10.5
-10.8
-11.1
-11.4
-9.4
-9.6
-9.8
-10.0
-10.2
-10.4
-11.7
-10.6
-25
0
25 50 75
TEMPERATURE (°C)
100 125
-50
OUT Pin Current (Disabled)
-25
0
25 50 75 100 125
TEMPERATURE (°C)
GATE Output Voltage (VGATE)
240
15
210
180
VCC = 48V
150
120
90
60
VCC - VEE = 80V
14
VCC = 80V
GATE PIN VOLTAGE (V)
OUT PIN CURRENT ( A)
100 125
-9.2
-12.0
-50
VCC = 9V
30
13
12
VCC - VEE = 48V
11
10
9
8
VCC - VEE = 9V
7
0
6
-50
-25
0
25 50 75
TEMPERATURE (°C)
100 125
GATE Pin Source Current
-50
-25
0
25
50
75
TEMPERATURE (°C)
100 125
VSNS (SENSE_K-VEE_K) at Power Limit Threshold RPWR =
75 kΩ
-51.6
30
VCC-VEE=48V, CL = VEE
-51.7
VSNSVOLTAGE (mV)
GATE PIN SOURCE CURRENT ( A)
0
25 50 75
TEMPERATURE (°C)
VEE_K Pin Current (Enabled)
-9.0
-51.8
-51.9
-52.0
25
20
VCC-VEE=24V, CL = VDD
15
10
-52.1
-52.2
-50
8
-25
5
-25
0
25 50 75
TEMPERATURE (°C)
100 125
-50
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-25
0
25
50
75
TEMPERATURE (°C)
100 125
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SNVS718E – JUNE 2011 – REVISED FEBRUARY 2013
Typical Performance Characteristics (continued)
Unless otherwise specified the following conditions apply: TJ = 25°C, VCC-VEE = 48V.
UVLO Threshold
UVLO Hysteresis Current
20.4
UVLO HYSTERESIS CURRENT ( A)
2.490
UVLO THRESHOLD (V)
2.488
2.486
2.484
2.482
2.480
2.478
2.476
2.474
2.472
2.470
-50
-25
0
25 50 75 100 125
TEMPERATURE (°C)
20.2
20.0
19.8
19.6
19.4
19.2
-50
OVLO Threshold
-25
0
25 50 75
TEMPERATURE (°C)
100 125
OVLO Hysteresis Current
OVLO HYSTERESIS CURRENT ( A)
OVLO THRESHOLD (V)
2.480
2.475
2.470
2.465
2.460
2.455
2.450
-50
-25
-19.9
-20.0
-20.1
-20.2
-20.3
-20.4
-20.5
-20.6
-50
0
25 50 75 100 125
TEMPERATURE (°C)
Current Limit Threshold
CIRCUIT BREAKER THRESHOLD (mV)
CURRENT LIMIT THRESHOLD (V)
CL = VEE
50
45
40
35
CL = VDD
25
20
-50
-25
0
25
50
75
TEMPERATURE (°C)
100 125
Reference Voltage
180
160
CL = VEE, CB/CL BIT = HIGH
140
120
100
CL = VEE, CB/CL BIT = LOW
80
60
CL = VDD, CB/CL BIT = LOW
40
-50
-25
0
25 50 75
TEMPERATURE (°C)
100 125
IIN Measurement Accuracy (SENSE_K-VEE_K = 50 mV)
1.6
2.974
1.2
CL=VEE
0.8
IIN ERROR (%)
2.972
VREF (V)
100 125
200
2.976
2.970
2.968
2.966
0.4
0.0
-0.4
-0.8
2.964
-1.2
2.962
-50
0
25 50 75
TEMPERATURE (°C)
Circuit Breaker Threshold
55
30
-25
-1.6
-25
0
25 50 75 100 125
TEMPERATURE (°C)
-50
-25
0
25 50 75
TEMPERATURE (°C)
100 125
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Typical Performance Characteristics (continued)
Unless otherwise specified the following conditions apply: TJ = 25°C, VCC-VEE = 48V.
PIN Measurement Accuracy (SENSE_K-VEE_K = 50 mV)
Startup (Insertion Delay)
1.0
INSERTION
DELAY = 140 ms
0.8
PIN ERROR (%)
0.6
CL=VEE
VTIMER (2V/Div)
0.4
0.2
0.0
-0.2
-0.4
VOUT (20V/Div)
-0.6
VSYS (20V/Div)
-0.8
-1.0
-50
-25
0
25 50 75
TEMPERATURE (°C)
IIN (5A/Div)
100 125
Short Circuit VOUT
40 ms/div
Startup (1A Load)
VTIMER (2V/Div)
VOUT (20V/Div)
VOUT (20V/Div)
VSYS (20V/Div)
(-48V)
VSYS (5V/Div)
VTIMER (2V/Div)
VGATE (20V/Div)
IIN (5A/Div)
40 ms/div
1s/div
Startup (UVLO/EN, OVLO)
Startup (PGD)
VGATE (20V/Div)
VPGOOD (2V/Div)
VSYS (25V/Div)
VSYS (25V/Div)
VOUT (25V/Div)
VOUT (25V/Div)
400 ms/div
10
400 ms/div
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Typical Performance Characteristics (continued)
Unless otherwise specified the following conditions apply: TJ = 25°C, VCC-VEE = 48V.
Current Limit Event (CL = VDD)
Circuit Breaker Event (CL = VDD)
VTIMER (2V/Div)
VTIMER (2V/Div)
VGATE (5V/Div)
VOUT (20V/Div)
VGATE (5V/Div)
CL = 8.7A
CB=1.8 x CL
VOUT (20V/Div)
IIN (5A/Div)
IIN (5A/Div)
4 ms/div
400 µs/div
Retry Event (RETRY = VEE)
Latch Off (RETRY = VDD)
VTIMER (2V/Div)
VTIMER (2V/Div)
VOUT (20V/Div) (-48V)
VOUT (20V/Div) (-48V)
VGATE (10V/Div)
VIN (20V/Div)
IIN (1A/Div)
400 ms/div
100 ms/div
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PGD
OUT
VAUXH
VEE_K
SENSE_K
SENSE
BLOCK DIAGRAM
VCC
LM5064
VEE
1.24V/2.5V
VDD
REG
VDD
UV
OV
Ref
S/H
AMUX
12 bit
ADC
VCC
Current Limit
Threshold
1/30
VREF
1/30
IDS
26/50 mV
52 µA
DIODE
1 M:
Power Limit
Threshold
VAUX
VEE
Current Telemetry
Sense
Diode
Temp
Sense
VDS
GATE
CONTROL
4.1 mA
111
mA
VEE
Circuit Breaker
Threshold
Current Limit/
Power Limit
Control
VEE
(26|50) x (1.8,3.6|1.9,3.7) mV
4.8 µA
Insertion
Timer
MEASUREMENT/
FAULT REGISTERS
SCL
SDAI
SDAO
SMBUS
INTERFACE
GATE
12.6V
74 µA
Fault
Timer
18 µA
TIMER
21 µA
TELEMETRY
STATE
MACHINE
OV
2.4 µA
TIME AND GATE
LOGIC CONTROL
2.47V
Fault
Discharge
VEE
VEE
UV
SMBA
1.5 mA
End
Insertion
Time
3.9V
2.48V
1.2V
ADDRESS
DECODER
0.3V
20 µA
OVLO
PWR
ADR2
Enable
POR
UVLO
/EN
8.7V/8.53V
VCC
Insertion Timer
POR
8V
VCC
RETRY
VEE
ADR1
CL
ADR0
Figure 1. Block Diagram
12
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FUNCTIONAL DESCRIPTION
The LM5064 is designed to control the in-rush current to the load upon insertion of a circuit card into a live
backplane or other “hot” power source, thereby limiting the voltage sag on the backplane’s supply and the dv/dt
of the voltage applied to the load. The effect from the insertion event on other circuits in the system is minimized,
preventing possible unintended resets. A controlled shutdown when the circuit card is removed can also be
implemented using the LM5064.
In addition to a programmable current limit, the LM5064 monitors and limits the maximum power dissipation in
the series pass device (Q1) to maintain operation within the device’s Safe Operating Area (SOA). Either current
limiting or power limiting for an extended period of time (user defined) results in the shutdown of the series pass
device. In this event, the LM5064 can latch off or repetitively retry based on the hardware setting of the RETRY
pin. Once started, the number of retries can be set to 0, 1, 2, 4, 8, 16, or infinite. The circuit breaker function
quickly switches off the series pass device upon detection of a severe over-current condition. Programmable
under-voltage lockout (UVLO) and over-voltage lockout (OVLO) circuits shut down the LM5064 when the system
input voltage (VSYS) is outside the desired operating range.
The telemetry capability of the LM5064 provides intelligent monitoring of the input voltage, output voltage, input
current, input power, temperature, and an auxiliary input. The LM5064 also provides a peak capture of the input
power and programmable hardware averaging of the input voltage, current, power, and output voltage. Warning
thresholds which trigger the SMBA pin may be programmed for input and output voltage, current, power and
temperature via the PMBus interface. Additionally, the LM5064 is capable of detecting damage to the external
MOSFET, Q1.
Operating Voltage
The LM5064 operating voltage is the voltage supplied between VCC and VEE (VCC-VEE) which has an
operating range of 10V to 80V with a 100V transient capability. All signals to the IC are referenced to the VEE
voltage which acts as the effective return path for the IC.
Power Up Sequence
Referring to Figure 2, as the system voltage (VSYS) initially increases, the external N-channel MOSFET (Q1) is
held off by an internal 111 mA pull-down current at the GATE pin. The strong pull-down current at the GATE pin
prevents an inadvertent turn on as the MOSFET’s gate-to-drain (Miller) capacitance is charged. Additionally, the
TIMER pin is initially held at VEE. When the operating voltage of the LM5064 (VCC - VEE) reaches the PORIT
threshold, the insertion time begins. During the insertion time, the capacitor at the TIMER pin (CT) is charged by
a 4.8 µA current source, and Q1 is held off by a 4.1 mA pull-down current at the GATE pin regardless of the input
voltage. The insertion time delay allows ringing and transients on VSYS to settle before Q1 is enabled. The
insertion time ends when the TIMER pin voltage reaches 3.9V. CT is then quickly discharged by an internal 1.5
mA pull-down current. The GATE pin then switches on Q1 when the operating voltage exceeds the UVLO
threshold. If the operating voltage is above the UVLO threshold at the end of the insertion time,(t1 in Figure 2) the
GATE pin sources 52 µA to charge the gate capacitance of Q1. The maximum voltage on GATE is limited by an
internal 12.6V zener diode to VEE.
As the voltage at the OUT pin transitions to VSYS, the LM5064 monitors the drain current and power dissipation of
MOSFET Q1. In-rush current limiting and/or power limiting circuits actively control the current delivered to the
load. During the in-rush limiting interval (t2 in Figure 2), an internal 74 µA fault timer current source charges CT. If
Q1’s power dissipation and the input current reduce below their respective limiting thresholds before the TIMER
pin reaches 3.9V, the 74 µA current source is switched off, and CT is discharged by the internal 2.4 µA current
sink (t3 in Figure 2). The in-rush limiting will no longer engage unless a current-limit condition occurs.
If the TIMER pin voltage reaches 3.9V before in-rush current limiting or power limiting ceases during t2, a fault is
declared and Q1 is turned off. See the Fault Timer & Restart section for a complete description of the fault mode.
The LM5064 will assert the SMBA pin after the operating voltage has exceeded the POR threshold to indicate
that the volatile memory and device settings are in their default state. The CONFIG_PRESET bit within the
MFR_SPECIFIC_17 register (E1h) indicates default configuration of warning thresholds and device operation and
will remain high until a CLEAR_FAULTS command is received.
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0V
System
Input
Voltage
UVLO
VSYS
LM5064
Operating
Voltage
|VSYS|
POR IT
(VCC± VEE)
3.9 V
4.8 PA
2.4 PA
74 PA
TIMER Pin
GATE Pin
111 mA
pull-down
4.1 mA pull-down
52 PA source
I LIMIT
Load
Current
0V
Output
Voltage
(OUT Pin)
1.24V
VSYS
PGD
VEE
t1
Insertion Time
t2
t3
In-rush
Limiting
Normal Operation
Figure 2. Power Up Sequence
Gate Control
A current source provides the charge at the GATE pin to enhance the N-Channel MOSFET’s gate (Q1). During
normal operating conditions (t3 in Figure 2) the gate of Q1 is held charged by an internal 52 µA current source.
The GATE pin peak voltage is roughly 12.6V, which will force a VGS across Q1 of 12.6V under normal operation.
When the system voltage is initially applied, the GATE pin is held low by a 111 mA pull-down current. This helps
prevent an inadvertent turn on of Q1 through its drain-gate capacitance as the applied system voltage increases.
During the insertion time (t1 in Figure 2), the GATE pin is held low by a 4.1 mA pull-down current. This maintains
Q1 in the off-state until the end of t1, regardless of the voltage on VSYS or UVLO/EN. Following the insertion time,
during t2 in Figure 2, the gate voltage of Q1 is modulated to keep the current or power dissipation level from
exceeding the programmed levels. While in the current or power limiting mode, the TIMER pin capacitor is
charging. If the current and power limiting cease before the TIMER pin reaches 3.9V, the TIMER pin capacitor
then discharges, and the circuit begins normal operation. If the in-rush limiting condition persists such that the
TIMER pin reached 3.9V during t2, the GATE pin is then pulled low by the 4.1 mA pull-down current. The GATE
pin is then held low until either a power up sequence is initiated (RETRY pin to VDD), an automatic retry is
attempted (RETRY pin to VEE or floating), or a PMBus ON/OFF command is initiated. See the Fault Timer &
Restart section. If the operating voltage falls below the UVLO threshold, or rises above the OVLO threshold, the
GATE pin is pulled low by the 4.1 mA pull-down current to switch off Q1.
14
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Current Limit
The current limit threshold is reached when the voltage across the sense resistor RS (SENSE to VEE) exceeds
the internal voltage limit of 26 mV or 50 mV depending on whether the CL pin is connected to VDD or VEE,
respectively. In the current limiting condition, the GATE voltage is controlled to limit the current in MOSFET Q1.
While the current limit circuit is active, the fault timer is active as described in the Fault Timer & Restart section. If
the load current falls below the current limit threshold before the end of the Fault Timeout Period, the LM5064
resumes normal operation. If the current limit condition persists for longer than the Fault Timeout Period set by
CT, the IIN OC Fault bit in the STATUS_INPUT (7Ch) register, the INPUT bit in the STATUS_WORD (79h)
register, and IIN_OC/PFET_OP_FAULT bit in the DIAGNOSTIC_WORD (E1h) register will be toggled high and
SMBA pin will be asserted. SMBA toggling can be disabled using the ALERT_MASK (D8h) register. For proper
operation, the RS resistor value should be no higher than 200 mΩ. Higher values may create instability in the
current limit control loop. The current limit threshold pin value may be overridden by setting appropriate bits in
the DEVICE_SETUP register (D9h).
Circuit Breaker
If the load current increases rapidly (e.g., the load is short circuited), the current in the sense resistor (RS) may
exceed the current limit threshold before the current limit control loop is able to respond. If the current exceeds
1.9x or 3.7x (CL = VEE) the current limit threshold, Q1 is quickly switched off by the 111 mA pull-down current at
the GATE pin, and a Fault Timeout Period begins. When the voltage across RS falls below the circuit breaker
(CB) threshold, the 111 mA pull-down current at the GATE pin is switched off, and the gate voltage of Q1 is then
determined by the current limit or the power limit functions. If the TIMER pin reaches 3.9V before the current
limiting or power limiting condition ceases, Q1 is switched off by the 4.1 mA pull-down current at the GATE pin as
described in the Fault Timer & Restart section. A circuit breaker event will cause the
CIRCUIT_BREAKER_FAULT bit in the STATUS_MFR_SPECIFIC (80h) and DIAGNOSTIC_WORD (E1h)
registers to be toggled high, and SMBA pin will be asserted unless this feature is disabled using the
ALERT_MASK (D8h) register. The circuit breaker pin configuration may be overridden by setting appropriate bits
in the DEVICE_SETUP (D9h) register.
Power Limit
An important feature of the LM5064 is the MOSFET power limiting. The power limit function can be used to
maintain the maximum power dissipation of MOSFET Q1 within the device SOA rating. The LM5064 determines
the power dissipation in Q1 by monitoring its drain-source voltage (OUT to SENSE), and the drain current
through the RS (SENSE to VEE). The product of the current and voltage is compared to the power limit threshold
programmed by the resistor at the PWR pin. If the power dissipation reaches the limiting threshold, the GATE
voltage is modulated to regulate the current in Q1. While the power limiting circuit is active, the fault timer is
active as described in the Fault Timer & Restart section. If the power limit condition persists for longer than the
Fault Timeout Period set by the timer capacitor, CT, the IIN OC Fault bit in the STATUS_INPUT (7Ch) register,
the INPUT bit in the STATUS_WORD (79h) register, and the IIN_OC/PFET_OP_FAULT bit in the
DIAGNOSTIC_WORD (E1h) register will be toggled high and SMBA pin will be asserted unless this feature is
disabled using the ALERT_MASK (D8h) register.
Fault Timer & Restart
When the current limit or power limit threshold is reached during turn-on, or as a result of a fault condition, the
gate-to-source voltage of Q1 is modulated to regulate the load current and power dissipation in Q1. When either
limiting function is active, a 74 µA fault timer current source charges the external capacitor (CT) at the TIMER pin
as shown in Figure 2(Fault Timeout Period). If the fault condition subsides during the Fault Timeout Period before
the TIMER pin reaches 3.9V, the LM5064 returns to the normal operating mode and CT is discharged by the 1.5
mA current sink. If the TIMER pin reaches 3.9V during the Fault Timeout Period, Q1 is switched off by a 4.1 mA
pull-down current at the GATE pin. The subsequent restart procedure then depends on the selected retry
configuration.
If the RETRY pin is high (VDD), the LM5064 latches the GATE pin low at the end of the Fault Timeout Period. CT
is then discharged to VEE by the 2.4 µA fault current sink. The GATE pin is held low by the 4.1 mA pull-down
current until a power up sequence is externally initiated by cycling the operating voltage (VCC-VEE), or
momentarily pulling the UVLO/EN pin below its threshold with an open-collector or open-drain device as shown
in Figure 3. The voltage at the TIMER pin must be
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