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LM5104M-TI

LM5104M-TI

  • 厂商:

    BURR-BROWN(德州仪器)

  • 封装:

    SOIC8_150MIL

  • 描述:

    HALF BRIDGE BASED PERIPHERAL DRI

  • 数据手册
  • 价格&库存
LM5104M-TI 数据手册
National Semiconductor is now part of Texas Instruments. Search http://www.ti.com/ for the latest technical information and details on our current products and services. LM5104 High Voltage Half-Bridge Gate Driver with Adaptive Delay General Description Features The LM5104 High Voltage Gate Driver is designed to drive both the high side and the low side N-Channel MOSFETs in a synchronous buck configuration. The floating high-side driver is capable of working with supply voltages up to 100V. The high side and low side gate drivers are controlled from a single input. Each change in state is controlled in an adaptive manner to prevent shoot-through issues. In addition to the adaptive transition timing, an additional delay time can be added, proportional to an external setting resistor. An integrated high voltage diode is provided to charge high side gate drive bootstrap capacitor. A robust level shifter operates at high speed while consuming low power and providing clean level transitions from the control logic to the high side gate driver. Undervoltage lockout is provided on both the low side and the high side power rails. This device is available in the standard SOIC-8 pin and the LLP-10 pin packages. ■ Drives both a high side and low side N-channel MOSFET ■ Adaptive rising and falling edges with programmable ■ ■ ■ ■ ■ additional delay Single input control Bootstrap supply voltage range up to 118V DC Fast turn-off propagation delay (25 ns typical) Drives 1000 pF loads with 15 ns rise and fall times Supply rail under-voltage lockout Typical Applications ■ ■ ■ ■ Current Fed Push-Pull Power Converters High Voltage Buck Regulators Active Clamp Forward Power Converters Half and Full Bridge Converters Package ■ SOIC-8 ■ LLP-10 (4 mm x 4 mm) Simplified Block Diagram 20089003 FIGURE 1. © 2008 National Semiconductor Corporation 200890 www.national.com LM5104 High Voltage Half-Bridge Gate Driver with Adaptive Delay December 1, 2008 LM5104 Connection Diagram 20089001 8-Lead SOIC See NS Package Number M08A 20089002 10-Lead LLP See NS Package Number SDC10A FIGURE 2. Ordering Information Package Type NSC Package Drawing Supplied As LM5104M Ordering Number SOIC-8 M08A Shipped with Anti-Static Rails LM5104MX SOIC-8 M08A 2500 shipped as Tape & Reel LM5104SD LLP-10 SDC10A 1000 shipped as Tape & Reel LM5104SDX LLP-10 SDC10A 4500 shipped as Tape & Reel Pin Descriptions Pin Name Description Application Information SOIC-8 LLP-10 1 1 VDD Positive gate drive supply Locally decouple to VSS using low ESR/ESL capacitor, located as close to IC as possible. 2 2 HB High side gate driver bootstrap rail Connect the positive terminal of bootstrap capacitor to the HB pin and connect negative terminal to HS. The Bootstrap capacitor should be placed as close to IC as possible. 3 3 HO High side gate driver output Connect to gate of high side MOSFET with short low inductance path. 4 4 HS High side MOSFET source Connect to bootstrap capacitor negative terminal and source of high side connection MOSFET. 5 7 RT Deadtime programming pin Resistor from RT to ground programs the deadtime between high and low side transitions.The resistor should be located close to the IC to minimize noise coupling from adjacent traces. 6 8 IN Control input Logic 1 equals High Side ON and Low Side OFF. Logic 0 equals High Side OFF and Low Side ON. 7 9 VSS Ground return All signals are referenced to this ground. 8 10 LO Low side gate driver output Connect to the gate of the low side MOSFET with a short low inductance path. Note: For LLP-10 package, it is recommended that the exposed pad on the bottom of the LM5100 / LM5101 be soldered to ground plane on the PC board, and the ground plane should extend out from beneath the IC to help dissipate the heat. Pins 5 and 6 have no connection. www.national.com 2 If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. VDD to VSS VHB to VHS IN to VSS LO Output HO Output VHS to VSS VHB to VSS –0.3V to +18V –0.3V to +18V –0.3V to VDD + 0.3V –0.3V to VDD + 0.3V VHS – 0.3V to VHB + 0.3V −1V to +100V 118V –0.3V to 5V +150°C –55°C to +150°C 2 kV Recommended Operating Conditions VDD HS HB HS Slew Rate Junction Temperature +9V to +14V –1V to 100V VHS + 8V to VHS + 14V
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