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LM5105
SNVS349E – FEBRUARY 2005 – REVISED AUGUST 2016
LM5105 100-V Half-Bridge Gate Driver With Programmable Dead Time
1 Features
3 Description
•
The LM5105 is a high-voltage gate driver designed to
drive both the high-side and low-side N–Channel
MOSFETs in a synchronous buck or half-bridge
configuration. The floating high-side driver is capable
of working with rail voltages up to 100 V. The single
control input is compatible with TTL signal levels and
a single external resistor programs the switching
transition dead time through tightly matched turnon
delay circuits. A high-voltage diode is provided to
charge the high-side gate-drive bootstrap capacitor.
The robust level shift technology operates at high
speed while consuming low power and provides clean
output transitions. Undervoltage lockout disables the
gate driver when either the low-side or the
bootstrapped high-side supply voltage is below the
operating threshold. The LM5105 is offered in the
thermally enhanced WSON plastic package.
1
•
•
•
•
•
•
•
•
•
•
•
Drives Both a High-Side and Low-Side N-Channel
MOSFET
1.8-A Peak Gate Drive Current
Bootstrap Supply Voltage Range up to 118-V DC
Integrated Bootstrap Diode
Single TTL Compatible Input
Programmable Turnon Delays (Dead Time)
Enable Input Pin
Fast Turnoff Propagation Delays (26 ns Typical)
Drives 1000 pF With 15-ns Rise and Fall Time
Supply Rail Undervoltage Lockout
Low Power Consumption
Package: Thermally Enhanced 10-Pin WSON
(4 mm × 4 mm)
Device Information(1)
2 Applications
•
•
PART NUMBER
Solid-State Motor Drives
Half- and Full-Bridge Power Converters
LM5105
PACKAGE
WSON (10)
BODY SIZE (NOM)
4.00 mm × 4.00 mm
(1) For all available packages, see the orderable addendum at
the end of the datasheet.
Simplified Application Diagram
HB
VDD
HB
UVLO
HO
LEVEL
SHIFT
DRIVER
HS
VDD
UVLO
VSS
IN
LEADING
EDGE
DELAY
RDT
LEADING
EDGE
DELAY
EN
VDD
DRIVER
LO
Copyright © 2016, Texas Instruments Incorporated
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
LM5105
SNVS349E – FEBRUARY 2005 – REVISED AUGUST 2016
www.ti.com
Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
4
6.1
6.2
6.3
6.4
6.5
6.6
6.7
4
4
4
5
5
6
8
Absolute Maximum Ratings ......................................
ESD Ratings..............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics...........................................
Switching Characteristics ..........................................
Typical Characteristics ..............................................
Detailed Description ............................................ 11
7.1
7.2
7.3
7.4
Overview .................................................................
Functional Block Diagram .......................................
Feature Description.................................................
Device Functional Modes .......................................
11
11
11
12
8
Application and Implementation ........................ 13
8.1 Application Information............................................ 13
8.2 Typical Application .................................................. 13
9
Power Supply Recommendations...................... 16
9.1 Power Dissipation Considerations .......................... 16
9.2 HS Transient Voltages Below Ground .................... 16
10 Layout................................................................... 17
10.1 Layout Guidelines ................................................. 17
10.2 Layout Example ................................................... 17
11 Device and Documentation Support ................. 18
11.1
11.2
11.3
11.4
11.5
11.6
Documentation Support ........................................
Receiving Notification of Documentation Updates
Community Resource............................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
18
18
18
18
18
18
12 Mechanical, Packaging, and Orderable
Information ........................................................... 18
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision D (March 2016) to Revision E
•
Updated values in the Thermal Information table to align with JEDEC standards................................................................. 5
Changes from Revision C (March 2013) to Revision D
•
2
Page
Added Device Information table, ESD Ratings, Detailed Description section, Application and Implementation
section, Layout section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable
Information section ................................................................................................................................................................. 1
Changes from Revision B (March 2013) to Revision C
•
Page
Page
Changed layout of National Semiconductor Data Sheet to TI format .................................................................................. 13
Submit Documentation Feedback
Copyright © 2005–2016, Texas Instruments Incorporated
Product Folder Links: LM5105
LM5105
www.ti.com
SNVS349E – FEBRUARY 2005 – REVISED AUGUST 2016
5 Pin Configuration and Functions
DPR Package
10-Pin WSON
Top View
VDD
1
10
LO
HB
2
9
VSS
HO
3
8
IN
HS
4
7
EN
NC
5
6
RDT
Not to scale
Pin Functions
PIN
NO.
NAME
TYPE (1)
DESCRIPTION
1
VDD
P
Positive gate drive supply. Decouple VDD to VSS using a low ESR/ESL capacitor, placed as
close to the IC as possible.
2
HB
P
High-side gate driver bootstrap rail. Connect the positive terminal of bootstrap capacitor to the
HB pin and connect negative terminal to HS. The Bootstrap capacitor must be placed as
close to IC as possible.
3
HO
O
High-side gate driver output. Connect to the gate of high side N-MOS device through a short,
low inductance path.
4
HS
P
High-side MOSFET source connection. Connect to the negative terminal of the bootstrap
capacitor and to the source of the high side N-MOS device.
5
NC
—
Not connected.
6
RDT
I
Dead-time programming pin. A resistor from RDT to VSS programs the turnon delay of both
the high and low side MOSFETs. The resistor must be placed close to the IC to minimize
noise coupling from adjacent PCB traces.
7
EN
I
Logic input for driver disable or enable. TTL compatible threshold with hysteresis. LO and HO
are held in the low state when EN is low.
8
IN
I
Logic input for gate driver. TTL compatible threshold with hysteresis. The high side MOSFET
is turned on and the low side MOSFET turned off when IN is high.
9
VSS
G
Ground return. All signals are referenced to this ground.
10
LO
O
Low-side gate driver output. Connect to the gate of the low side N-MOS device with a short,
low inductance path.
—
Exposed Pad
—
It is recommended that the exposed pad on the bottom of the package be soldered to ground
plane on the PCB to aid thermal dissipation.
(1)
G = Ground, I = Input, O = Output, P = Power
Submit Documentation Feedback
Copyright © 2005–2016, Texas Instruments Incorporated
Product Folder Links: LM5105
3
LM5105
SNVS349E – FEBRUARY 2005 – REVISED AUGUST 2016
www.ti.com
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1) (2)
MIN
MAX
UNIT
VDD to VSS
–0.3
18
V
HB to HS
–0.3
18
V
IN and EN to VSS
–0.3
VDD + 0.3
V
LO to VSS
–0.3
VDD + 0.3
V
HO to VSS
HS – 0.3
HB + 0.3
V
−5
100
V
118
V
HS to VSS (3)
HB to VSS
RDT to VSS
–0.3
Junction temperature, TJ
Storage temperature, Tstg
(1)
(2)
(3)
–55
5
V
150
°C
150
°C
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/Distributors for availability and
specifications.
In the application the HS node is clamped by the body diode of the external lower N-MOSFET, therefore the HS voltage generally does
not exceed –1 V. However, in some applications, board resistance and inductance may result in the HS node exceeding this stated
voltage transiently. If negative transients occur on HS, the HS voltage must never be more negative than VDD – 15 V. For example, if
VDD = 10 V, the negative transients at HS must not exceed –5 V.
6.2 ESD Ratings
V(ESD)
(1)
(2)
Electrostatic discharge
Human-body model (HBM)
(1) (2)
VALUE
UNIT
±2000
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
The human-body model is a 100-pF capacitor discharged through a 1.5-kΩ resistor into each pin. Pin 2, Pin 3 and Pin 4 are rated at
500 V.
6.3 Recommended Operating Conditions
MIN
VDD
HS (1)
HB
HS
Slew rate
TJ
Junction temperature
(1)
4
NOM
MAX
UNIT
8
14
V
–1
100
V
HS + 8
HS + 14
V
–40
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