LM5105

LM5105 100V Half Bridge Gate Driver with Programmable Dead-time February 2005 LM5105 100V Half Bridge Gate Driver with Programmable Dead-time General Description The LM5105 is a high voltage gate driver designed to drive both the high side and low side N –Channel MOSFETs in a synchronous buck or half bridge configuration. The floating high-side driver is capable of working with rail voltages up to 100V. The single control input is compatible with TTL signal levels and a single external resistor programs the switching transition dead-time through tightly matched turn-on delay circuits. A high voltage diode is provided to charge the high side gate drive bootstrap capacitor. The robust level shift technology operates at high speed while consuming low power and provides clean output transitions. Under-voltage lockout disables the gate driver when either the low side or the bootstrapped high side supply voltage is below the operating threshold. The LM5105 is offered in the thermally enhanced 10-pin LLP plastic package. n n n n n n n n n n 1.8A peak gate drive current Bootstrap supply voltage range up to 118V DC Integrated bootstrap diode Single TTL compatible Input Programmable turn-on delays (Dead-time) Enable Input pin Fast turn-off propagation delays (26ns typical) Drives 1000pF with 15ns rise and fall time Supply rail under-voltage lockout Low power consumption Typical Applications n Solid State motor drives n Half and Full Bridge power converters n Two switch forward power converters Features n Drives both a high side and low side N-channel MOSFET Package n LLP-10 (4 mm x 4 mm) Simplified Block Diagram 20137502 FIGURE 1. © 2005 National Semiconductor Corporation DS201375 www.national.com LM5105 Connection Diagram 20137501 10-Lead LLP See NS Number SDC10A Ordering Information Ordering Number LM5105SD LM5105SDX Package Type LLP-10 LLP-10 NSC Package Drawing SDC10A SDC10A Supplied As 1000 shipped as Tape & Reel 4500 shipped as Tape & Reel Pin Descriptions Pin 1 2 Name VDD HB Description Positive gate drive supply High side gate driver bootstrap rail High side gate driver output High side MOSFET source connection Not Connected Deadtime programming pin A resistor from RDT to VSS programs the turn-on delay of both the high and low side MOSFETs. The resistor should be placed close to the IC to minimize noise coupling from adjacent PC board traces. TTL compatible threshold with hysteresis. LO and HO are held in the low state when EN is low. TTL compatible threshold with hysteresis. The high side MOSFET is turned on and the low side MOSFET turned off when IN is high. All signals are referenced to this ground. Connect to the gate of the low side N-MOS device with a short, low inductance path. Application Information Decouple VDD to VSS using a low ESR/ESL capacitor, placed as close to the IC as possible. Connect the positive terminal of bootstrap capacitor to the HB pin and connect negative terminal to HS. The Bootstrap capacitor should be placed as close to IC as possible. Connect to the gate of high side N-MOS device through a short, low inductance path. Connect to the negative terminal of the bootststrap capacitor and to the source of the high side N-MOS device. 3 4 5 6 HO HS NC RDT 7 8 9 10 EN IN VSS LO Logic input for driver Disable/Enable Logic input for gate driver Ground return Low side gate driver output www.national.com 2 LM5105 Absolute Maximum Ratings (Note 1) If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. VDD to VSS HB to HS IN and EN to VSS LO to VSS HO to VSS HS to VSS (Note 6) HB to VSS RDT to VSS Junction Temperature –0.3V to +18V –0.3V to +18V –0.3V to VDD + 0.3V –0.3V to VDD + 0.3V HS – 0.3V to HB + 0.3V −5V to +100V 118V –0.3V to 5V +150˚C Storage Temperature Range ESD Rating HBM (Note 2) –55˚C to +150˚C 2 kV Recommended Operating Conditions VDD HS (Note 6) HB HS Slew Rate Junction Temperature +8V to +14V –1V to 100V HS + 8V to HS + 14V < 50V/ns –40˚C to +125˚C Electrical Characteristics Specifications in standard typeface are for TJ = +25˚C, and those in boldface type apply over the full operating junction temperature range. Unless otherwise specified, VDD = HB = 12V, VSS = HS = 0V, EN = 5V. No load on LO or HO. RDT= 100kΩ(Note 4). Symbol SUPPLY CURRENTS IDD IDDO IHB IHBO IHBS IHBSO VIL VIH Rpd VRDT IRDT VDDR VDDH VHBR VHBH VDL VDH RD VOLL VOHL IOHL IOLL VOLH VOHH IOHH VDD Quiescent Current VDD Operating Current Total HB Quiescent Current Total HB Operating Current HB to VSS Current, Quiescent HB to VSS Current, Operating Low Level Input Voltage Threshold High Level Input Voltage Threshold Input Pulldown Resistance Pin IN and EN Nominal Voltage at RDT RDT Pin Current Limit VDD Rising Threshold VDD Threshold Hysteresis HB Rising Threshold HB Threshold Hysteresis Low-Current Forward Voltage High-Current Forward Voltage Dynamic Resistance Low-Level Output Voltage High-Level Output Voltage Peak Pullup Current Peak Pulldown Current Low-Level Output Voltage High-Level Output Voltage Peak Pullup Current IVDD-HB = 100 µA IVDD-HB = 100 mA IVDD-HB = 100 mA ILO = 100 mA ILO = –100 mA, VOHL = VDD – VLO LO = 0V LO = 12V IHO = 100 mA IHO = –100 mA, VOHH = HB – HO HO = 0V 5.7 RDT = 0V 100 2.7 0.75 6.0 IN = EN = 0V f = 500 kHz IN = EN = 0V f = 500 kHz HS = HB = 100V f = 500 kHz 0.8 0.34 1.65 0.06 1.3 0.05 0.1 1.8 1.8 200 3 1.5 6.9 0.5 6.6 0.4 0.6 0.85 0.8 0.25 0.35 1.8 1.6 0.25 0.35 1.8 0.4 0.55 0.9 1.1 1.5 0.4 0.55 7.1 2.2 500 3.3 2.25 7.4 0.6 3 0.2 3 10 mA mA mA mA µA mA V V kΩ V mA V V V V V V Ω V V A A V V A Parameter Conditions Min Typ Max Units INPUT IN and EN DEAD-TIME CONTROLS UNDER VOLTAGE PROTECTION BOOT STRAP DIODE LO GATE DRIVER HO GATE DRIVER 3 www.national.com LM5105 Electrical Characteristics Specifications in standard typeface are for TJ = +25˚C, and those in boldface type apply over the full operating junction temperature range. Unless otherwise specified, VDD = HB = 12V, VSS = HS = 0V, EN = 5V. No load on LO or HO. RDT= 100kΩ(Note 4). (Continued) Symbol IOLH θJA THERMAL RESISTANCE Junction to Ambient (Note 3), (Note 5) 40 ˚C/W Parameter Peak Pulldown Current Conditions HO = 12V Min Typ 1.6 Max Units A Switching Characteristics Specifications in standard typeface are for TJ = +25˚C, and those in boldface type apply over the full operating junction temperature range. Unless otherwise specified, VDD = HB = 12V, VSS = HS = 0V, No Load on LO or HO (Note 4). Symbol tLPHL tHPHL tLPLH tHPLH tLPLH tHPLH ten, tsd DT1, DT2 MDT t R , tF tBS Parameter Lower Turn-Off Propagation Delay Upper Turn-Off Propagation Delay Lower Turn-On Propagation Delay Upper Turn-On Propagation Delay Lower Turn-On Propagation Delay Upper Turn-On Propagation Delay Enable and Shutdown propagation delay Dead-time LO OFF to HO ON & HO OFF to LO ON Dead-time matching Either Output Rise/Fall Time Bootstrap Diode Turn-On or Turn-Off Time RDT = 100k RDT = 10k RDT = 100k CL = 1000pF IF = 20 mA, IR = 200 mA RDT = 100k RDT = 100k RDT = 10k RDT = 10k 485 485 75 75 Conditions Min Typ 26 26 595 595 105 105 28 570 80 50 15 50 ns Max 56 56 705 705 150 150 Units ns ns ns ns ns ns ns µs Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the component may occur. Operating Ratings are conditions under which operation of the device is guaranteed. Operating Ratings do not imply guaranteed performance limits. For guaranteed performance limits and associated test conditions, see the Electrical Characteristics tables. Note 2: The human body model is a 100 pF capacitor discharged through a 1.5kΩ resistor into each pin. Pin 2, Pin 3 and Pin 4 are rated at 500V. Note 3: 4 layer board with Cu finished thickness 1.5/1.0/1.0/1.5 oz. Maximum die size used. 5x body length of Cu trace on PCB top. 50 x 50mm ground and power planes embedded in PCB. See Application Note AN-1187. Note 4: Min and Max limits are 100% production tested at 25˚C. Limits over the operating temperature range are guaranteed through correlation using Statistical Quality Control (SQC) methods. Limits are used to calculate National’s Average Outgoing Quality Level (AOQL). Note 5: The θJA is not a constant for the package and depends on the printed circuit board design and the operating conditions. Note 6: In the application the HS node is clamped by the body diode of the external lower N-MOSFET, therefore the HS voltage will generally not exceed -1V. However in some applications, board resistance and inductance may result in the HS node exceeding this stated voltage transiently. If negative transients occur on HS, the HS voltage must never be more negative than VDD - 15V. For example, if VDD = 10V, the negative transients at HS must not exceed -5V. www.national.com 4 LM5105 Typical Performance Characteristics VDD Operating Current vs Frequency Operating Current vs Temperature 20137510 20137511 Quiescent Current vs Supply Voltage Quiescent Current vs Temperature 20137512 20137513 HB Operating Current vs Frequency HO & LO Peak Output Current vs Output Voltage 20137517 20137516 5 www.national.com LM5105 Typical Performance Characteristics Diode Forward Voltage (Continued) Undervoltage Hysteresis vs Temperature 20137515 20137518 Undervoltage Rising Threshold vs Temperature LO & HO - High Level Output Voltage vs Temperature 20137519 20137520 LO & HO - Low Level Output Voltage vs Temperature Input Threshold vs Temperature 20137521 20137522 www.national.com 6 LM5105 Typical Performance Characteristics Dead-Time vs RT Resistor Value (Continued) Dead-Time vs Temperature (RT = 10k) 20137514 20137526 Dead-Time vs Temperature (RT = 100k) 20137527 7 www.national.com LM5105 Timing Diagrams 20137503 LM5105 Input - Output Waveforms FIGURE 2. 20137504 LM5105 Switching Time Definitions: tLPLH, tLPHL, tHPLH, tHPHL FIGURE 3. Operational Notes The LM5105 is a single PWM input Gate Driver with Enable that offers a programmable deadtime. The deadtime is set with a resistor at the RDT pin and can be adjusted from 100ns to 600ns. The wide deadtime programming range provides the flexibility to optimize drive signal timing for a wide range of MOSFETS and applications. The RDT pin is biased at 3V and current limited to 1 mA maximum programming current. The time delay generator will accommodate resistor values from 5k to 100k with a deadtime time that is proportional to the RDT resistance. Grounding the RDT pin programs the LM5105 to drive both outputs with minimum deadtime. STARTUP AND UVLO Both top and bottom drivers include under-voltage lockout (UVLO) protection circuitry which monitors the supply voltage (VDD) and bootstrap capacitor voltage (HB – HS) independently. The UVLO circuit inhibits each driver until sufficient supply voltage is available to turn-on the external MOSFETs, and the UVLO hysteresis prevents chattering during supply voltage transitions. When the supply voltage is applied to the VDD pin of LM5105, the top and bottom gates are held low until VDD exceeds the UVLO threshold, typically about 6.9V. Any UVLO condition on the bootstrap capacitor will disable only the high side output (HO). 20137530 LM5105 Enable: tsd FIGURE 4. 20137531 LM5105 Dead-time: DT FIGURE 5. www.national.com 8 LM5105 Operational Notes LAYOUT CONSIDERATIONS (Continued) POWER DISSIPATION CONSIDERATIONS The total IC power dissipation is the sum of the gate driver losses and the bootstrap diode losses. The gate driver losses are related to the switching frequency (f), output load capacitance on LO and HO (CL), and supply voltage (VDD) and can be roughly calculated as: PDGATES = 2 • f • CL • VDD2 There are some additional losses in the gate drivers due to the internal CMOS stages used to buffer the LO and HO outputs. The following plot shows the measured gate driver power dissipation versus frequency and load capacitance. At higher frequencies and load capacitance values, the power dissipation is dominated by the power losses driving the output loads and agrees well with the above equation. This plot can be used to approximate the power losses due to the gate drivers. Gate Driver Power Dissipation (LO + HO) VCC = 12V, Neglecting Diode Losses The optimum performance of high and low side gate drivers cannot be achieved without taking due considerations during circuit board layout. Following points are emphasized. 1. A low ESR/ESL capacitor must be connected close to the IC, and between VDD and VSS pins and between HB and HS pins to support high peak currents being drawn from VDD during turn-on of the external MOSFET. To prevent large voltage transients at the drain of the top MOSFET, a low ESR electrolytic capacitor must be connected between MOSFET drain and ground (VSS). 3. In order to avoid large negative transients on the switch node (HS) pin, the parasitic inductances in the source of top MOSFET and in the drain of the bottom MOSFET (synchronous rectifier) must be minimized. 4. Grounding considerations: a) The first priority in designing grounding connections is to confine the high peak currents from charging and discharging the MOSFET gate in a minimal physical area. This will decrease the loop inductance and minimize noise issues on the gate terminal of the MOSFET. The MOSFETs should be placed as close as possible to the gate driver. b) The second high current path includes the bootstrap capacitor, the bootstrap diode, the local ground referenced bypass capacitor and low side MOSFET body diode. The bootstrap capacitor is recharged on the cycle-by-cycle basis through the bootstrap diode from the ground referenced VDD bypass capacitor. The recharging occurs in a short time interval and involves high peak current. Minimizing this loop length and area on the circuit board is important to ensure reliable operation. 5. The resistor on the RDT pin must be placed very close to the IC and seperated from high current paths to avoid noise coupling to the time delay generator which could disrupt timer operation. 2. 20137505 The bootstrap diode power loss is the sum of the forward bias power loss that occurs while charging the bootstrap capacitor and the reverse bias power loss that occurs during reverse recovery. Since each of these events happens once per cycle, the diode power loss is proportional to frequency. Larger capacitive loads require more current to recharge the bootstrap capacitor resulting in more losses. Higher input voltages (VIN) to the half bridge result in higher reverse recovery losses. The following plot was generated based on calculations and lab measurements of the diode recovery time and current under several operating conditions. This can be useful for approximating the diode power dissipation. 9 www.national.com LM5105 Operational Notes (Continued) Diode Power Dissipation VIN = 80V The total IC power dissipation can be estimated from the above plots by summing the gate drive losses with the bootstrap diode losses for the intended application. Because the diode losses can be significant, an external diode placed in parallel with the internal bootstrap diode (refer to Figure 6) and can be helpful in removing power from the IC. For this to be effective, the external diode must be placed close to the IC to minimize series inductance and have a significantly lower forward voltage drop than the internal diode. HS Transient Voltages Below Ground The HS node will always be clamped by the body diode of the lower external FET. In some situations, board resistances and inductances can cause the HS node to transiently swing several volts below ground. The HS node can swing below ground provided: 1. HS must always be at a lower potential than HO. Pulling HO more than -0.3V below HS can activate parasitic transistors resulting in excessive current to flow from the HB supply possibly resulting in damage to the IC. The same relationship is true with LO and VSS. If necessary, a Schottky diode can be placed externally between HO and HS or LO and GND to protect the IC from this type of transient. The diode must be placed as close to the IC pins as possible in order to be effective. 20137506 Diode Power Dissipation VIN = 40V 2. HB to HS operating voltage should be 15V or less . Hence, if the HS pin transient voltage is -5V, VDD should be ideally limited to 10V to keep HB to HS below 15V. 3. A low ESR bypass capacitor between HB to HS as well as VCC to VSS is essential for proper operation. The capacitor should be located at the leads of the IC to minimize series inductance. The peak currents from LO and HO can be quite large. Any series inductances with the bypass capacitor will cause voltage ringing at the leads of the IC which must be avoided for reliable operation. 20137507 www.national.com 10 LM5105 Operational Notes (Continued) LM5105 Driving MOSFETs Connected in Half-Bridge Configuration 20137508 FIGURE 6. 11 www.national.com LM5105 100V Half Bridge Gate Driver with Programmable Dead-time Physical Dimensions inches (millimeters) unless otherwise noted Notes: Unless otherwise specified 1. 2. 3. Standard lead finish to be 200 microinches/5.00 micrometers minimum tin/lead (solder) on copper. Pin 1 identification to have half of full circle option. No JEDEC registration as of Feb. 2000. LLP-10 Outline Drawing NS Package Number SDC10A National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications. 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