LM8328
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LM8328 Mobile I/O Companion Supporting Keyscan, I/O Expansion, PWM, and
ACCESS.bus Host Interface
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FEATURES
1
•
2
•
KEY FEATURES
– Internal RC Oscillator, No External Clock
Required
– Internal PWM Clock Generation, No
External Clock Required
– External Reset for System Control
– Programmable I2C-compatible ACCESS.bus
Address (Default 0x88)
– Support for Keypad Matrices of up to of 8 x
12 Keys, Plus 8 Special Function (SF) Keys,
for a Full 104 Key Support
– I2C-compatible ACCESS.bus Slave Interface
at 100 kHz (Standard-Mode) and 400 kHz
(Fast-Mode)
– Three Host-programmable PWM Outputs
for Smooth LED Brightness Modulation
– Supports General-purpose I/O Expansion
on Pins Not Otherwise Used for Keypad or
PWM Output
– 15 byte Key Event Buffer
– Multiple Key Event Storage
– Key Events, Errors, and Dedicated
Hardware Interrupts Request Host Service
by Asserting an IRQ Output
– Automatic HALT Mode for Low Power
Operation
– Wake-up from HALT Mode on Any Interface
(Rising Edge, Falling Edge or Pulse)
– Three PWM Outputs with Dedicated Script
Buffer for up to 32 Commands
– Register-based Command Interpreter with
Auto Increment Address
HOST-CONTROLLED FEATURES
– Reset Input for System Control
– PWM Scripting for Three PWM Outputs
– Period of Inactivity that Triggers Entry into
HALT Mode
– Debounce Time for Reliable Key Event
Polling
•
– Configuration of General Purpose I/O Ports
– Various Initialization Options (Keypad Size,
etc.)
KEY DEVICE FEATURES
– 1.8V ± 10% Single-supply Operation
– On-chip Power-on Reset (POR)
– Watchdog Timer
– −40°C to +85°C Temperature Range
– 25-pin DSBGA Package
APPLICATIONS:
•
•
•
Cordless Phones
Smart Handheld Devices
Keyboard Applications
DESCRIPTION
The LM8328 GenI/O - Expander and Keypad
Controller is a dedicated device to unburden a host
processor from scanning a matrix-addressed keypad
and to provide flexible and general purpose, host
programmable
input/output
functions.
Three
independent PWM timer outputs are provided for
dynamic LED brightness modulation.
It communicates with a host processor through an
I2C-compatible ACCESS.bus serial interface. It can
communicate in Standard (100 kHz) - and Fast-Mode
(400 kHz) in slave Mode only.
All available input/output pins can alternately be used
as an input or an output in a keypad matrix or as a
host programmable general purpose input or output.
Any pin programmed as an input can also sense
hardware interrupts. The interrupt polarity (“high to
low” or “low to high” transition) is thereby
programmable.
The LM8328 follows a predefined register based set
of commands. Upon start-up (power - on) a
configuration file must be sent from the host to setup
the hardware of the device.
1
2
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
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LM8328 FUNCTION BLOCKS
PIN ASSIGNMENTS
Figure 1. LM8328 Pinout - Top View (balls underneath): Y = Outputs; X = Inputs
2
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SIGNAL DESCRIPTIONS
DEVICE PIN FUNCTIONS
KEY AND ALTERNATE FUNCTIONS OF ALL DEVICE PINS
Ball
Function 0
Pin Count
Ball Name
C1
Reset Active Low
Input
Function 1
Function 2
Function 3
1
RESETN
C4
Supply Voltage
1
VCC
D1
2
Main I C - Clk
1
SCL
E1
Main I2C - Data
1
SDA
A5
Keypad-I/O X0
Genio0
1
KPX0
B4
Keypad-I/O X1
Genio1
1
KPX1
D2
Keypad-I/O X2
Genio2
1
KPX2
E2
Keypad-I/O X3
Genio3
1
KPX3
A1
Keypad-I/O X4
Genio4
1
KPX4
B1
Keypad-I/O X5
Genio5
1
KPX5
A3
Keypad-I/O X6
Genio6
1
KPX6
A4
Keypad-I/O X7
Genio7
1
KPX7
D5
Keypad-I/O Y0
Genio8
1
KPY0
C5
Keypad-I/O Y1
Genio9
1
KPY1
B5
Keypad-I/O Y2
Genio10
1
KPY2
D4
Keypad-I/O Y3
Genio11
1
KPY3
B2
Keypad-I/O Y4
Genio12
1
KPY4
A2
Keypad-I/O Y5
Genio13
1
KPY5
B3
Keypad-I/O Y6
Genio14
1
KPY6
C2
Keypad-I/O Y7
Genio15
1
KPY7
D3
Keypad-I/O Y8
Genio16
ClockOut
PWM2
1
KPY8
PWM2
E4
Keypad-I/O Y9
Genio17
PWM1
1
KPY9
PWM1
E5
Keypad-I/O Y10
Genio18
E3
Interrupt
Keypad-I/O Y11
PWM0
1
PWM2
1
KPY10
PWM0
Genio19
IRQN
KPY11
PWM2
C3
Ground
1
TOTAL
25
GND
PIN CONFIGURATION AFTER RESET
Upon power-up or RESET the LM8328 will have defined states on all pins. Pin configuration after reset provides
a comprehensive overview on the states of all functional pins.
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PIN CONFIGURATION AFTER RESET
Pins
Pin States
KPX0
KPX1
KPX2
KPX3
KPX4
Full Buffer mode with an on-chip pull up resistor enabled.
KPX5
KPX6
KPX7
KPY0
KPY1
KPY2
KPY3
KPY4
KPY5
Full Buffer mode with an on-chip pull down resistor enabled.
KPY6
KPY7
KPY8 / PWM2
KPY9 / PWM1
KPY10 / PWM0
KPY11 / IRQN / PWM2
SCL
SDA
(1)
4
Open Drain mode with no pull resistor enabled, driven low (IRQN). (1)
Open Drain mode with no pull resistor enabled.
The IRQN is driven low after Power-On Reset due to PORIRQ signal. The value 0x01 must be written to the RSTINTCLR register (0x84)
to release the IRQN pin.
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TYPICAL APPLICATION SETUP
Figure 2. LM8328 in a Typical Setup with Standard Handset Keypad
FEATURES
The following features are supported with the application example shown in example above:
Hardware
Hardware
• 4 x 8 keys and 8 Special Function (SF) keys for 40 keys.
• ACCESS.bus interface for communication with a host device.
– - communication speeds supported are: 100 kHz and 400 kHz fast mode of operation.
• Interrupt signal (IRQN) to indicate any keypad or hardware interrupt events to the host.
• Sophisticated PWM function block with 3 independent channels to control color LED.
• External reset input for system control.
• Two host programmable dedicated general-purpose output pins (GPIOs) supporting IO-expansion capabilities
for host device.
• Two host programmable dedicated general-purpose input pins with wake-up supporting IO-expansion
capabilities for host device.
Communication Layer
• Versatile register-based command integration supported from on-chip command interpreter.
• Keypad event storage.
• Individual PWM script file storage and execution control for 3 PWM channels.
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HALT MODE
HALT MODE DESCRIPTION
The fully static architecture of the LM8328 allows stopping the internal RC clock in Halt mode, which reduces
power consumption to the minimum level. Figure 3 shows the current in Halt mode at the maximum VCC (1.98V)
from 25°C to +85°C.
Figure 3. Halt Current vs. Temperature at 1.98V
Halt mode is entered when no key-press event, key-release event, or ACCESS.bus activity is detected for a
certain period of time (by default, 1020 milliseconds). The mechanism for entering Halt mode is always enabled
in hardware, but the host can program the period of inactivity which triggers entry into Halt mode using the
autosleep function. (See Table 47.)
ACCESS.BUS ACTIVITY
When the LM8328 is in Halt mode, only activity on the ACCESS.bus interface that matches its Slave Address will
cause the LM8328 to exit from Halt mode. However, the LM8328 will not be able to acknowledge the first bus
cycle immediately following wake-up from Halt mode. It will respond with a negative acknowledgement, and the
host should then repeat the cycle. A peripheral that is continuously active can share the bus since this activity will
not prevent the LM8328 from entering Halt mode.
LM8328 PROGRAMMING INTERFACE
The LM8328 operation is controlled from a host device by a complete register set, accessed via the I2Ccompatible ACCESS.bus interface. The ACCESS.bus communication is based on a READ/WRITE structure,
following the I2C transmission protocol. All functions can be controlled by configuring one or multiple registers.
Please refer to LM8328 REGISTER SET for the complete register set.
ACCESS.BUS COMMUNICATION
Figure 4 shows a typical read cycle initiated by the host.)
Figure 4. Master/Slave Serial Communication (Host to LM8328)
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Table 1. Definition of Terms used in Serial Command Example
Term
Bits
S
Description
START Condition (always generated from the master device)
ADDRESS
7
Slave address of LM8328 sent from the host
R/W
1
This bit determines if the following data transfer is from master to slave (data write) or from slave to
master (data read).
0: Write
1: Read
ACK
1
An acknowledge bit is mandatory and must be appended on each byte transfer. The Acknowledge status
is actually provided from the slave and indicates to the master, that the byte transfer was successful.
REG
8
The first byte after sending the slave address is the REGISTER byte which contains the physical address
the host wants to read from or write to.
RS
Repeated START condition
DATA
8
The DATA field contains information to be stored into a register or information read from a register.
NACK
1
Not Acknowledge Bit. The Not Acknowledge status is assigned from the Master receiving data from a
slave. The NACK status will actually be assigned from the master in order to signal the end of a
communication cycle transfer
P
STOP condition (always generated from the master device)
All actions associated with the non-shaded boxes in Figure 4 are controlled from the master (host) device.
All actions associated with the shaded boxes in Figure 4 are controlled from the slave (LM8328) device.
The master device can send subsequent REGISTER addresses separated by Repeated START conditions. A
STOP condition must be set from the master at the very end of a communication cycle.
It is recommended to use Repeated START conditions in multi-Master systems when sending subsequent
REGISTER addresses. This technique will make sure that the master device communicating with the LM8328
will not loose bus arbitration.
Starting a Communication Cycle
There are two reasons for the host device to start communication to the LM8328:
1. The LM8328 device has set the IRQN line low in order to signal a key - event or any other condition which
initializes a hardware interrupt from LM8328 to the host.
2. The host device wants to set a GENIO port, read from a GENIO port, configure a GENIO port, and read the
status from a register or initialize any other function which is supported from the LM8328. In case a GENIO
shall be read it will be most likely, that the LM8328 device will be residing in “sleep mode”. In this mode the
system clock will be off to establish the lowest possible current consumption. If the host device starts the
communication under this condition the LM8328 device will not be able to acknowledge the first attempt of
sending the slave address. The LM8328 will wake up because of the START condition but it can’t establish
the internal timing to scan the first byte received. The master device must therefore apply a second attempt
to start the communication with the LM8328 device.
Communication Initialized from Host (Restart from Sleep Mode)
Figure 5. Host Starts Communication While LM8328 is in Sleep Mode
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In the timing diagram shown in Figure 5 the LM8328 resides in sleep mode. Since the LM8328 device can’t
acknowledge the slave address the host must generate a STOP condition followed by a second START
condition.
On the second attempt the slave address is being acknowledged from the LM8328 device because it is in
active mode now.
The host can send different WRITE and/or READ commands subsequently after each other.
The host must finally free the bus by generating a STOP condition.
ACCESS.Bus Communication Flow
The LM8328 will only be driven in slave mode. The maximum communication speed supported is Fast Mode
(FS) which is 400 kHz. The device can be heavily loaded as it is processing different kind of events caused from
the human interface and the host device. In such cases the LM8328 may temporarily be unable to accept new
commands and data sent from the host device.
NOTE
“It is a legitimate measure of the slave device to hold SCL line low in such cases in order
to force the master device into a waiting state. It is therefore the obligation of the host
device to detect such cases. Typically there is a control bit set in the master device
indicating the Busy status of the bus. As soon as the SCL line is released the host can
continue sending commands and data.”
Further Remarks:
• In systems with multiple masters it is recommended to separate commands with Repeat START conditions
rather than sending a STOP - and another START - condition to communicate with the LM8328 device.
• Delays enforced by the LM8328 during very busy phases of operation should typically not exceed a duration
of 100 usec.
• Normally the LM8328 will clock stretch after the acknowledge bit Is transmitted; however, there are some
conditions where the LM8328 will clock stretch between the SDA Start bit and the first rising edge of SCL.
Auto Increment
In order to improve multi-byte register access, the LM8328 supports the auto increment of the address pointer.
A typical protocol access sequence to the LM8328 starts with the I2C-compatible ACCESS.bus address, followed
by REG, the register to access (see Figure 4). After a REPEATED START condition the host reads/writes a data
byte from/to this address location. If more than one byte is transmitted, the LM8328 automatically increments the
address pointer for each data byte by 1. The address pointer keeps the status until the STOP condition is
received.
The LM8328 always uses auto increments unless otherwise noted.
Please refer to Table 2 and Table 3 for the typical ACCESS.bus flow of reading and writing multiple data bytes.
Reserved Registers and Bits
The LM8328 includes reserved registers for future implementation options. Please use value 0 on a write to all
reserved register bits.
Global Call Reset
The LM8328 supports the Global Call Reset as defined in the I2C Specification, which can be used by the host to
reset all devices connected to interface. The Global call reset is a single byte ACCESS.bus/I2C write of data byte
0x06 to slave address 0x00.
The Global Call Reset changes the I2C-compatible ACCESS.bus Slave address of the LM8328 back to its default
value of 0x88.
8
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Table 2. Multi-Byte Write with Auto Increment
2
Step
Master/Slave
I C Com.
1
M
S
Value
2
M
ADDR.
0x88
3
M
R/W
0
4
S
ACK
5
M
REG
Address Pointer
Comment
START condition
I2C-compatible ACCESS.bus Address
Write
Acknowledge
0xAA
0xAA
Register Address, used as Address Pointer
6
S
ACK
0xAA
Acknowledge
7
M
DATA
0x01
0xAA
Write Data to Address in Pointer
8
S
ACK
0
0xAB
Acknowledge, Address pointer incremented
9
M
DATA
0x05
0xAB
Write Data to address 0xAB
10
S
ACK
0
0xAC
Acknowledge, Address pointer incremented
11
M
P
STOP condition
Table 3. Multi-Byte Read with Auto Increment
2
Step
Master/Slave
I C Com.
1
M
S
Value
2
M
ADDR.
0x88
3
M
R/W
0
Address Pointer
Comment
START condition
I2C-compatible ACCESS.bus Address
Write
4
S
ACK
5
M
REG
Acknowledge
6
S
ACK
7
M
RS
8
M
ADDR.
0x88
9
M
R/W
1
10
S
ACK
0
0xAA
Acknowledge
11
S
DATA
0x01
0xAA
Read Data from Address in Pointer
12
M
ACK
0
0xAB
Acknowledge, Address Pointer incremented
13
S
DATA
0x05
0xAB
Read Data from Address in Pointer
14
M
NACK
0
0xAC
No Acknowledge, stops transmission
15
M
P
0xAA
0xAA
Register Address, used as Address pointer
0xAA
Acknowledge
0xAA
Repeated Start
0xAA
I2C-compatible ACCESS.bus Address
Read
STOP condition
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KEYSCAN OPERATION
KEYSCAN INITIALIZATION
Figure 6. Keyscan Initialization
KEYSCAN INITIALIZATION EXAMPLE
Table 4 shows all the LM8328 register configurations to initialize keyscan:
• Keypad matrix configuration is 8 rows x 8 columns.
Table 4. Keyscan Initialization Example
10
Register name
adress
Access Type
Value
Comment
CLKEN
0x8A
byte
0x01
enable keyscan clock
KBDSETTLE
0x01
byte
0x80
set the keyscan settle time to 12 msec
KBDBOUNCE
0x02
byte
0x80
set the keyscan debounce time to 12 msec
KBDSIZE
0x03
byte
0x88
set the keyscan matrix size to 8 rows x 8 columns
KBDDEDCFG
0x04
word
0xFC3F
IOCFG
0xA7
byte
0xF8
IOPC0
0xAA
word
0xAAAA
configure pull-up resistors for KPX[7:0]
configure pull-down resistors for KPY[7:0]
configure KPX[7:2] and KPY[7:2] pins as keyboard matrix
write default value to enable all pins as keyboard matrix
IOPC1
0xAC
word
0x5555
KBDIC
0x08
byte
0x03
clear any pending interrupts
KBDMSK
0x09
byte
0x03
enable keyboard interrupts
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KEYSCAN PROCESS
The LM8328 keyscan functionality is based on a specific scanning procedure performed in a 4ms interval. On
each scan all assigned key matrix pins are evaluated for state changes.
In case a key event has been identified, the event is stored in the key event FIFO, accessible via the EVTCODE
register. A key event can either be a key press or a key release. In addition, key presses are also stored in the
KBDCODE[3:0] registers. As soon as the EVTCODE FIFO includes a event, the device sets the RAW keyboard
event interrupt REVTINT. The RSINT interrupt is set anytime the keyboard status has changed.
Depending on the interrupt masking for the keyboard events (KBDMSK) and the masked interrupt handling
(KBDMIS), the pin IRQN/KPY11/PWM2 will follow the IRQST.KBDIRQ status, which is set as soon as one
interrupt in KBDRIS is set.
Figure 7 shows the basic flow of a scanning process and which registers are affected.
Figure 7. Example Keyscan Operation for
1 Key Press and Release
READING KEYSCAN STATUS BY THE HOST
In order to keep track of the keyscan status, the host either needs to regularly poll the EVTCODE register or
needs to react on the Interrupt signaled by the IRQN/KPY11/PWM2 pin, in case the ball is configured for
interrupt functionality. (See GPIO Feature Mapping).
Figure 8 gives an example on which registers to read to get the keyboard events from the LM8328 and how they
influence the interrupt event registers. The example is based on the assumption that the LM8328 has indicated
the keyboard event by the IRQN/KPY11/PWM2 pin.
Since the interrupt pin has various sources, the host first checks the IRQST register for the interrupt source. If
KBDIRQ is set, the host can check the KBDMIS register to define the exact interrupt source. KBDMIS contains
the masked status of KBDRIS and reflects the source for raising the interrupt pin. The interrupt mask is defined
by KBDMSK. The complete status of all pending keyboard interrupts is available in the raw interrupt register
KBDRIS.
After evaluating the interrupt source the host starts reading the EVTCODE or KBDCODE register. In this
example the host first reads the KBDCODE to get possible key press events and afterwards reads the complete
event list by reading the EVTCODE register until all events are captured (0x7F indicates end of buffer).
Reading KBDCODE clears the RSINT interrupt bit if all keyboards events are emptied. In the same way,
REVTINT is cleared in case the EVTCODE FIFO reaches its empty state on read.
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The event buffer content and the REVTINT and RELINT (lost event) interrupt bits are also cleared if the
KBDIC.EVTIC bit is set.
Interrupt bits in the masked interrupt register KBDMIS follow the masked KBDRIS status.
In order to support efficient Multi-byte reads from EVTCODE, the autoincrement feature is turned off for this
register. Therefore the host can continuously read the complete EVTCODE buffer by sending one command.
Figure 8. Example Host Reacting to
Interrupt for Keypad Event
MULTIPLE KEY PRESSES
The LM8328 supports up to four simultaneous key presses. Any time a single key is pressed KBDCODE0 is set
with the appropriate key code. If a second key is pressed, the key is stored in KBDCODE1 and the MULTIKEY
flag of KBDCODE0 is set. Additional key presses are stored in KBDCODE2 and KBDCODE3 accordingly. The
four registers signal the last multi key press events.
All events are stored in parallel in the EVTCODE register for the complete set of events.
All KBDCODE[3:0] registers are cleared on read.
12
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Figure 9. Example Keyscan Operation for 2 Key Press Events
and 1 Key Release Event
PWM TIMER
The LM8328 supports a timer module dedicated to smooth LED control techniques (lighting controls).
The PWM timer module consists of three independent timer units of which each can generate a PWM output with
a fixed period and automatically incrementing or decrementing variable duty cycle. The timer units are all clocked
with a slow (32.768 kHz) clock whereas the interface operates with the main system clock.
OVERVIEW OF PWM FEATURES
• Each PWM can establish fixed — or variable — duty-cycle signal sequences on its output.
• Each PWM can trigger execution of any pre-programmed task on another PWM channel.
• The execution of any pre-programmed task is self-sustaining and does not require further interaction from the
host.
• 64-byte script buffer for each PWM for up to 32 consecutive instructions.
• Direct addressing within script buffer to support multiple PWM tasks in one buffer.
OVERVIEW ON PWM SCRIPT COMMANDS
The commands listed in Table 5 are dedicated to the slow PWM timers.
NOTE
The PWM Script commands are not part of the command set supported by the LM8328
command interpreter. These commands must be transferred from the host with help of the
register-based command set.
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Table 5. PWM Script Commands
Command
RAMP
SET_PWM
GO_TO_
START
BRANCH
END
TRIGGER
15
0
0
14
PRESCALE
1
13
12
11
10
STEPTIME
0
9
8
7
SIGN
6
5
4
3
INCREMENT
PWMVALUE
2
1
0
0
1
1
1
0
1
1
1
0
1
LOOPCOUNT
INT
WAITTRIGGER
1
ADDR
STEPNUMBER
X
SENDTRIGGER
0
RAMP COMMAND
A RAMP command will vary the duty cycle of a PWM output in either direction (up or down). The INCREMENT
field specifies the amount of steps for the RAMP. The maximum amount of steps which can be executed with
one RAMP Command is 126 which is equivalent to 50%. The SIGN bit field determines the direction of a RAMP
(up or down). The STEPTIME field and the PRESCALE bit determine the duration of one step. Based on a
32.768 kHz clock, the minimum time resulting from these options would be 0.49 milliseconds and the maximum
time for one step would be 1 second.
Table 6. RAMP Command Bit and Building Fields
15
0
14
PRESCALE
13
12
11
10
STEPTIME
9
8
7
SIGN
6
5
4
3
2
INCREMENT
1
0
Table 7. Description of Bit and Building Fields of the RAMP Command
Bit or Field
Value
PRESCALE
STEPTIME
Description
0
Divide the 32.768 kHz clock by 16
1
Divide the 32.768 kHz clock by 512
1 - 63
SIGN
INCREMENT
Number of prescaled clock cycles per step
0
Increment ramp counter
1
Decrement ramp counter
Number of steps executed by this instruction; a value of 0 functions as a WAIT
determined by STEPTIME.
0 - 126
SET_PWM COMMAND
The SET_PWM command will set the starting duty cycle MIN SCALE or FULL SCALE (0% or 100%). A RAMP
command following the SET_PWM command will finally establish the desired duty cycle on the PWM output.
Table 8. SET_PWM Command Bit and Building Fields
15
0
14
1
13
0
12
0
11
0
10
0
9
0
8
0
7
6
5
4
3
DUTYCYCLE
2
1
0
Table 9. Description of Bit and Building Fields of the SET_PWM Command
Bit or Field
DUTYCYCLE
Value
0
255
Description
Duty cycle is 0%.
Duty cycle is 100%.
GO_TO_START COMMAND
The GO_TO_START command jumps to the first command in the script command file.
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Table 10. GO_TO_START Command Bit and Building Fields
15
14
13
12
11
10
9
8
0
7
6
5
4
3
2
1
0
BRANCH COMMAND
The BRANCH command jumps to the specified command in the script command file. The branch is executed
with either absolute or relative addressing. In addition, the command gives the option of looping for a specified
number of repetitions.
NOTE
Nested loops are not allowed.
Table 11. BRANCH Command Bit and Building Fields
15
1
14
0
13
1
12
11
10
9
LOOPCOUNT
8
7
6
ADDR
5
4
3
2
STEPNUMBER
1
0
Table 12. Description of Bit and Building Fields of the BRANCH Command
Bit or Field
Value
Description
0
LOOPCOUNT
Loop until a STOP PWM SCRIPT command is issued by the host.
1 - 63
ADDR
STEPNUMBER
Number of loops to perform.
0
Absolute addressing
1
Relative addressing
Depending on ADDR:
ADDR=0: Addr to jump to
ADDR=1: Number of backward steps
0 - 63
TRIGGER COMMAND
Triggers are used to synchronize operations between PWM channels. A TRIGGER command that sends a
trigger takes sixteen 32.768 kHz clock cycles, and a command that waits for a trigger takes at least sixteen
32.768 kHz clock cycles.
A TRIGGER command that waits for a trigger (or triggers) will stall script execution until the trigger conditions are
satisfied. On trigger it will clear the trigger(s) and continue to the next command.
When a trigger is sent, it is stored by the receiving channel and can only be cleared when the receiving channel
executes a TRIGGER command that waits for the trigger.
Table 13. TRIGGER Command Bit and Building Fields
15
1
14
1
13
1
12
11
10
9
WAITTRIGGER
8
7
6
5
4
3
SENDTRIGGER
2
1
0
0
Table 14. Description of Bit and Building Fields
Field
WAITTRIGGER
SENDTRIGGER
Value
Description
000xx1
Wait for trigger from channel 0
000x1x
Wait for trigger from channel 1
0001xx
Wait for trigger from channel 2
000xx1
Send trigger to channel 0
000x1x
Send trigger to channel 1
0001xx
Send trigger to channel 2
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END COMMAND
The END command terminates script execution. It will only assert an interrupt to the host if the INT bit is set to
“1”.
When the END command is executed, the PWM output will be set to the level defined by PWMCFG.PWMPOL
for this channel. Also, the script counter is reset back to the beginning of the script command buffer.
NOTE
If a PWM channel is waiting for the trigger (last executed command was "TRIGGER") and
the script execution is halted then the "END" command can’t be executed because the
previous command is still pending. This is an exception - in this case the IRQ signal will
not be asserted.
Table 15. END Command Bit and Building Fields
15
1
14
1
13
0
12
1
11
INT
10
9
8
7
6
5
4
3
2
1
0
0
Table 16. Description of Bit and Building Fields of the END Command
Field
Value
INT
Description
0
No interrupt will be sent.
1
Set TIMRIS.CDIRQ for this PWM channel to notify that program has ended.
LM8328 REGISTER SET
KEYBOARD REGISTERS AND KEYBOARD CONTROL
Keyboard selection and control registers are mapped in the address range from 0x01 to 0x10. This paragraph
describes the functions of the associated registers down to the bit level.
KBDSETTLE - Keypad Settle Time Register
Table 17. KBDSETTLE - Keypad Settle Time Register
Register - Name
Address
Type
KBDSETTLE
0x01
R/W
Bit - Name
Bit
Default
Register Function
Initial time for keys to settle, before the key-scan process is started.
Bit Function
The default value 0x80 : 0xBF sets a time target of 12 msec
Further time targets are as follows:
0xC0 - 0xFF: 16 msec
WAIT[7:0]
7:0
0x80
0x80 - 0xBF: 12 msec
0x40 - 0x7F: 8 msec
0x01 - 0x3F: 4 msec
0x00 : no settle time
KBDBOUNCE - Debounce Time Register
Table 18. KBDBOUNCE - Debounce Time Register
16
Register - Name
Address
Type
KBDBOUNCE
0x02
R/W
Bit - Name
Bit
Default
Register Function
Time between first detection of key and final sampling of key
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Table 18. KBDBOUNCE - Debounce Time Register (continued)
Register - Name
Address
Type
Register Function
The default value 0x80 : 0xBF sets a time target of 12 msec
Further time targets are as follows:
0xC0 - 0xFF: 16 msec
WAIT[7:0]
7:0
0x80
0x80 - 0xBF: 12 msec
0x40 - 0x7F: 8 msec
0x01 - 0x3F: 4 msec
0x00: no debouncing time
KBDSIZE - Set Keypad Size Register
Table 19. KBDSIZE - Set Keypad Size Register
Register - Name
Address
Type
KBDSIZE
0x03
R/W
Bit - Name
Bit
Default
Register Function
Defines the physical keyboard matrix size
Bit Function
Number of rows in the keyboard matrix
ROWSIZE[3:0]
7:4
0x2
0x0: free all rows to become GPIO, KPX[1:0] used as dedicated key inputs
if scanning is enabled by CLKEN.KBEN
0x1: (illegal value)
0x2 - 0x8: Number of rows in the matrix
Number of columns in the keyboard matrix
COLSIZE[3:0]
3:0
0x2
0x0: free all rows to become GPIO, KPY[1:0] used as dedicated key inputs
if scanning is enabled by CLKEN.KBEN
0x1: (illegal value)
0x2 - 0xC: Number of columns in the matrix
KBDDEDCFG - Dedicated Key Register
Table 20. KBDDEDCFG - Dedicated Key Register
Register - Name
Address
Type
KBDDEDCFG
0x04
R/W
Bit - Name
Bit
Default
Register Function
Defines if a key is used as a standard keyboard/GPIO pin or whether it is
used as dedicated key input.
Bit Function
Each bit in ROW [7:2] corresponds to ball KPX7 : KPX2.
Bit=0: the dedicated key function applies.
ROW[7:2]
15:10
0x3F
Bit=1: no dedicated key function is selected. The standard GPIO
functionality applies according to register IOCFG or defined keyboard
matrix.
Each bit in COL [11:10] corresponds to ball KPY11 : KPY10.
Bit=0: the dedicated key function applies.
COL[11:10]
9:8
0x03
Bit=1: no dedicated key function is selected. The standard GPIO
functionality applies according to register IOCFG or defined keyboard
matrix.
Each bit in COL [9:2] corresponds to ball KPY9 : KPY2 and can be
configured individually.
COL[9:2]
7:0
0xFF
Bit=0: the dedicated key function applies.
Bit=1: no dedicated key function is selected. The standard GPIO
functionality applies according to register IOCFG or defined keyboard
matrix.
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KBDRIS - Keyboard Raw Interrupt Status Register
Table 21. KBDRIS - Keyboard Raw Interrupt Status Register
Register - Name
Address
Type
KBDRIS
0x06
R
Bit - Name
Bit
Default
(reserved)
7:4
Register Function
Returns the status of stored keyboard interrupts.
Bit Function
(reserved)
Raw event lost interrupt.
RELINT
3
0x0
REVTINT
2
0x0
More than 8 keyboard events have been detected and caused the event
buffer to overflow. This bit is cleared by setting bit EVTIC of the KBDIC
register.
Raw keyboard event interrupt.
At least one key press or key release is in the keyboard event buffer.
Reading from EVTCODE until the buffer is empty will clear this interrupt.
Raw key lost interrupt indicates a lost key-code.
RKLINT
1
0x0
RSINT
0
0x0
This interrupt is asserted when RSINT has not been cleared upon
detection of a new key press or key release, or when more than 4 keys
are pressed simultaneously.
Raw scan interrupt.
Interrupt generated after keyboard scan, if the keyboard status has
changed.
KBDMIS - Keypad Masked Interrupt Status Register
Table 22. KBDMIS - Keypad Masked Interrupt Status Register
Register - Name
KBDMIS
Address
Type
0x07
R
Bit - Name
Bit
Default
(reserved)
7:4
MELINT
3
0x0
MEVTINT
2
0x0
MKLINT
1
0x0
MSINT
0
0x0
Register Function
Returns the status on masked keyboard interrupts after masking with the
KBDMSK register.
Bit Functions
(reserved)
Masked event lost interrupt.
More than 8 keyboard events have been detected and caused the event
buffer to overflow. This bit is cleared by setting bit EVTIC of the KBDIC
register.
Masked keyboard event interrupt.
At least one key press or key release is in the keyboard event buffer.
Reading from EVTCODE until the buffer is empty will clear this interrupt.
Masked key lost interrupt.
Indicates a lost key-code. This interrupt is asserted when RSINT has not
been cleared upon detection of a new key press or key release, or when
more than 4 keys are pressed simultaneously.
Masked scan interrupt.
Interrupt generated after keyboard scan, if the keyboard status has
changed, after masking process.
KBDIC - Keypad Interrupt Clear Register
Table 23. KBDIC - Keypad Interrupt Clear Register
18
Register - Name
Address
Default
KBDIC
0x08
W
Bit - Name
Bit
Default
Register Function
Setting these bits clears Keypad active Interrupts
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Table 23. KBDIC - Keypad Interrupt Clear Register (continued)
Register - Name
Address
Default
Register Function
Switches off scanning of special function (SF) keys, when keyboard has
no special function layout.
SFOFF
7
0: keyboard layout and SF keys are scanned
1: only keyboard layout is scanned, SF keys are not scanned
(reserved)
6:2
(reserved)
EVTIC
1
Clear event buffer and corresponding interrupts REVTINT and RELINT by
writing a 1 to this bit position
KBDIC
0
Clear RSINT and RKLINT interrupt bits by writing a 1 to this bit position.
KBDMSK - Keypad Interrupt Mask Register
Table 24. KBDMSK - Keypad Interrupt Mask Register
Register - Name
Address
Type
Register Function
Configures masking of keyboard interrupts. Masked interrupts do not
trigger an event on the Interrupt output.
KBDMSK
0x09
R/W
Bit - Name
Bit
Default
(reserved)
7:4
MSKELINT
3
0x0
MSKEINT
2
0x0
MSKLINT
1
0x1
MSKSINT
0
0x1
In case the interrupt processes registers KBDCODE[3:0], MSKELINT and
MSKEINT should be set to 1. When the Event FIFO is processed,
MSKLINT and MSKSINT should be set. For keyboard polling operations,
all bits should be set and the polling operation consists of reading out the
EVTCODE.
Bit Function
(reserved)
0: keyboard event lost interrupt RELINT triggers IRQ line
1: keyboard event lost interrupt RELINT is masked
0: keyboard event interrupt REVINT triggers IRQ line
1: keyboard event interrupt REVINT is masked
0: keyboard lost interrupt RKLINT triggers IRQ line
1: keyboard lost interrupt RKLINT is masked
0: keyboard status interrupt RSINT triggers IRQ line
1: keyboard status interrupt RSINT is masked
KBDCODE0 - Keyboard Code Register 0
The key code detected by the keyboard scan can be read from the registers KBDCODE0: KBDCODE3. Up to 4
keys can be detected simultaneously. Each KBDCODE register includes a bit (MULTIKEY) indicating if another
key has been detected.
NOTE
Reading out all key code registers (KBDCODE0 to KBDCODE3) will automatically reset
the keyboard scan interrupt RSINT the same way as an active write access into bit KBDIC
of the interrupt clear register does. Reading 0x7F from the KBDCODE0 register means
that no key was pressed.
Table 25. KBDCODE0 - Keyboard Code Register 0
Register - Name
Address
Default
KBDCODE0
0x0B
R
Register Function
Holds the row and column information of the first detected key
Bit - Name
Bit
Default
MULTIKEY
7
0x0
if this bit is 1 another key is available in KBDCODE1 register
Bit Function
KEYROW[2:0]
6:4
0x7
ROW index of detected key (0 to 7)
KEYCOL[3:0]
3:0
0xF
Column index of detected (0 to 11, 12 for special function key.
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KBDCODE1 - Keyboard Code Register 1
Table 26. KBDCODE1 - Keyboard Code Register 1
Register - Name
Address
Default
KBDCODE1
0x0C
R
Register Function
Holds the row and column information of the second detected key
Bit - Name
Bit
Default
MULTIKEY
7
0x0
if this bit is 1 another key is available in KBDCODE2 register
Bit Function
KEYROW[2:0]
6:4
0x7
ROW index of detected key (0 to 7)
KEYCOL[3:0]
3:0
0xF
Column index of detected key (0 to 11, 12 for special function key).
KBDCODE2 - Keyboard Code Register 2
Table 27. KBDCODE2 - Keyboard Code Register 2
Register - Name
Address
Default
KBDCODE2
0x0D
R
Bit - Name
Bit
Default
Register Function
Holds the row and column information of the third detected key
Bit Function
MULTIKEY
7
0x0
if this bit is 1 another key is available in KBDCODE3 register
KEYROW[2:0]
6:4
0x7
ROW index of detected key (0 to 7)
KEYCOL[3:0]
3:0
0xF
Column index of detected key (0 to 11, 12 for special function key).
KBDCODE3 - Keyboard Code Register 3
Table 28. KBDCODE3 - Keyboard Code Register 3
Register - Name
Address
Default
KBDCODE3
0x0E
R
Register Function
Holds the row and column information of the forth detected key
Bit - Name
Bit
Default
MULTIKEY
7
0x0
if this bit is set to “1” then more than 4 keys are pressed simultaneously.
Bit Function
KEYROW[2:0]
6:4
0x7
ROW index of detected key (0 to 7)
KEYCOL[3:0]
3:0
0xF
Column index of detected key (0 to 11, 12 for special function key).
EVTCODE - Key Event Code Register
Table 29. EVTCODE - Key Event Code Register
Register - Name
Address
Default
Bit Function
With this register a FIFO buffer is addressed storing up to 15 consecutive
events.
EVTCODE
0x10
R
Reading the value 0x7F from this address means that the FIFO buffer is
empty. See further details below.
NOTE: Auto increment is disabled on this register. Multi-byte read will
always read from the same address.
Bit - Name
Bit
Default
Bit Function
This bit indicates, whether the keyboard event was a key press or a key
release event.
RELEASE
7
0x0
KEYROW[2:0]
6:4
0x7
Row index of key that is pressed or released.
KEYCOL[3:0]
3:0
0xF
Column index of key that is pressed (0...11, 12 for special function key) or
released.
0: key was pressed
1: key was released
20
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PWM TIMER CONTROL REGISTERS
The LM8328 provides three host-programmable PWM outputs useful for smooth LED brightness modulation. All
PWM timer control registers are mapped in the range from 0x60 to 0x7F. This paragraph describes the functions
of the associated registers down to the bit level.
TIMCFGx - PWM Timer 0, 1 and 2 Configuration Registers
Table 30. TIMCFGx - PWM Timer 0, 1 and 2 Configuration Registers
Register - Name
Address
TIMCFG0
0x60
TIMCFG1
0x68
TIMCFG2
0x70
Bit - Name
(x = 0, 1 or 2)
Bit
Type
R/W
Register Function
This register configures interrupt masking and handles PWM start/stop
control of the associated PWM channel.
Default
Bit Function
Interrupt mask for PWM CYCIRQx (see register TIMRIS)
CYCIRQxMSK
4
0x0
(reserved)
3:0
0x0
0: interrupt enabled
1: interrupt masked
(reserved)
PWMCFGx - PWM Timer 0, 1 and 2 Configuration Control Registers
Table 31. PWMCFGx - PWM Timer 0, 1 and 2 Configuration Control Registers
Register - Name
Address
PWMCFG0
0x61
PWMCFG1
0x69
PWMCFG2
0x71
Bit - Name
(x = 0, 1 or 2)
Bit
Type
Register Function
This register defines interrupt masking and the output behavior for the
associated PWM channel.
R/W
PGEx is used to start and stop the PWM script execution.
PWMENx sets the PWM output to either reflect the generated pattern or
the value configured in PWMPOLx.
Default
Bit Function
Mask for CDIRQx
CDIRQxMSK
3
0x0
0: CDIRQx enabled
1: CDIRQx disabled/masked
Pattern Generator Enable. Start/Stop PWM command processing for this
channel. Script execution is started always from beginning.
PGEx
2
0x0
0: Pattern Generator disabled
1: Pattern Generator enabled
PWMENx
1
0x0
0: PWM disabled. PWM timer output assumes value programmed in
PWMPOL.
1: PWM enabled
Off-state of PWM output, when PWMEN=0.
PWMPOLx
0
0x0
0: PWM off-state is low
1: PWM off-state is high
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TIMSWRES - PWM Timer Software Reset Registers
Table 32. TIMSWRES - PWM Timer Software Reset Registers
Register - Name
Address
Type
Register Function
Reset control on all PWM timers
TIMSWRES
0x78
W
A reset forces the pattern generator to fetch the first pattern and stops it.
Each reset stops all state-machines and timer.
Patterns stored in the pattern configuration register remain unaffected.
Interrupts on each timer are not cleared, they need to be cleared writing
into register TIMIC
Bit - Name
Bit
(reserved)
7:3
SWRES2
2
Default
Bit Function
(reserved)
Software reset of timer 2.
0: no action
1: Software reset on timer 2, needs not to be written back to 0.
Software reset of timer 1.
SWRES1
1
0: no action
1: Software reset on timer 1, needs not to be written back to 0.
Software reset of timer 0.
SWRES0
0
0: no action
1: software reset on timer 0, needs not to be written back to 0.
TIMRIS - PWM Timer Interrupt Status Register
Table 33. TIMRIS - PWM Timer Interrupt Status Register
Register - Name
Address
Type
Register Function
This register returns the raw interrupt status from the PMW timers 0,1 and
2.
TIMRIS
0x7A
R
CYCIRQx - Interrupt from the timers when PWM cycle is complete (applies
to the current PWM command residing in the active command register of a
PWM block).
CDIRQx - Interrupt from the pattern generator when PWM pattern code is
complete (applies to a completed task residing in the script buffer of a
PWM block).
Bit - Name
Bit
(reserved)
7:6
Default
Bit Functions
(reserved)
Raw interrupt status for CDIRQ timer2
CDIRQ2
5
0x0
0: no interrupt pending
1: unmasked interrupt generated
Raw interrupt status for CDIRQ timer1
CDIRQ1
4
0x0
0: no interrupt pending
1: unmasked interrupt generated
Raw interrupt status for CDIRQ timer0
CDIRQ0
3
0x0
0: no interrupt pending
1: unmasked interrupt generated
Raw interrupt status for CYCIRQ timer2
CYCIRQ2
2
0x0
0: no interrupt pending
1: unmasked interrupt generated
Raw interrupt status for CYCIRQ timer1
CYCIRQ1
1
0x0
0: no interrupt pending
1: unmasked interrupt generated
22
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Table 33. TIMRIS - PWM Timer Interrupt Status Register (continued)
Register - Name
Address
Type
Register Function
Raw interrupt status for CYCIRQ timer0
CYCIRQ0
0
0x0
0: no interrupt pending
1: unmasked interrupt generated
TIMMIS - PWM Timer Masked Interrupt Status Register
Table 34. TIMMIS - PWM Timer Masked Interrupt Status Register
Register - Name
Address
Type
Register Function
This register returns the masked interrupt status from the PMW timers 0,1
and 2. The raw interrupt status (TIMRIS) is masked with the associated
TIMCFGx.CYCIRQxMSK and PWMCFGx.CDIRQxMSK bits to get the
masked interrupt status of this register.
TIMMIS
0x7B
R
CYCIRQ - Interrupt from the timers when PWM cycle is complete (applies
to the current PWM command residing in the active command register of a
PWM block)
CDIRQ - Interrupt from the pattern generator when PWM pattern code is
complete (applies to a completed task residing in the script buffer of a
PWM block)
Bit - Name
Bit
(reserved)
7:6
Default
Bit Function
(reserved)
Interrupt after masking, indicates active contribution to the interrupt ball,
when set. Status for CDIRQ timer2.
CDIRQ2
5
0x0
0: no interrupt pending
1: interrupt generated
Interrupt after masking, indicates active contribution to the interrupt ball,
when set. Status for CDIRQ timer1.
CDIRQ1
4
0x0
0: no interrupt pending
1: interrupt generated
Interrupt after masking, indicates active contribution to the interrupt ball,
when set. Status for CDIRQ timer0.
CDIRQ0
3
0x0
0: no interrupt pending
1: interrupt generated
Interrupt after masking, indicates active contribution to the interrupt ball,
when set. Status for CYCIRQ timer2.
CYCIRQ2
2
0x0
0: no interrupt pending
1: interrupt generated
Interrupt after masking, indicates active contribution to the interrupt ball,
when set. Status for CYCIRQ timer1.
CYCIRQ1
1
0x0
0: no interrupt pending
1: interrupt generated
Interrupt after masking, indicates active contribution to the interrupt ball,
when set. Status for CYCIRQ timer0.
CYCIRQ0
0
0x0
0: no interrupt pending
1: interrupt generated
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TIMIC - PWM Timer Interrupt Clear Register
Table 35. TIMIC - PWM Timer Interrupt Clear Register
Register - Name
Address
Type
Register Function
This register clears timer and pattern interrupts.
TIMIC
0x7C
W
CYCIRQ - Interrupt from the timers when PWM cycle is complete (applies
to the current PWM command residing in the active command register of a
PWM block).
CDIRQ - Interrupt from the pattern generator when PWM pattern code is
complete (applies to a completed task residing in the script buffer of a
PWM block)
Bit - Name
Bit
(reserved)
7:6
Default
Bit Function
(reserved)
Clears interrupt CDIRQ timer2.
CDIRQ2
5
0: no effect
1: interrupt is cleared. Does not need to be written back to 0
Clears interrupt CDIRQ timer1.
CDIRQ1
4
0: no effect
1: interrupt is cleared. Does not need to be written back to 0
Clears interrupt CDIRQ timer0.
CDIRQ0
3
0: no effect
1: interrupt is cleared. Does not need to be written back to 0
Clears interrupt CYCIRQ timer2.
CYCIRQ2
2
0: no effect
1: interrupt is cleared. Does not need to be written back to 0
Clears interrupt CYCIRQ timer1.
CYCIRQ1
1
0: no effect
1: interrupt is cleared. Does not need to be written back to 0
Clears interrupt CYCIRQ timer0.
CYCIRQ0
0
0: no effect
1: interrupt is cleared. Does not need to be written back to 0
PWMWP - PWM Timer Pattern Pointer Register
Table 36. PWMWP - PWM Timer Pattern Pointer Register
Register - Name
Address
Type
Register Function
Pointer to the pattern position inside the configuration register, which will
be overwritten by the next write access to be PWMCFG register.
PWMWP
0x7D
R/W
Bit - Name
Bit
Default
(reserved)
7
0x0
NOTE: 1 pattern consist of 2 bytes and not the byte position (low or high).
It is incremented by 1 every time a full PWMCFG register access (word) is
performed.
Bit Function
(reserved)
0 ≤ POINTER < 32 : timer0 patterns 0 to 31
POINTER[6:0]
6:0
0x0
32 ≤ POINTER < 64 : timer1 patterns 0 to 31
64 ≤ POINTER < 96 : timer2 patterns 0 to 31
96 ≤ POINTER < 128: not valid
24
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PWMCFG - PWM Script Register
Table 37. PWMCFG - PWM Script Register
Register - Name
Address
Type
Register Function
Two byte pattern storage register for a PWM script command indexed by
PWMWP. PWMWP is automatically incremented.
PWMCFG
0x7E
W
To be applied by two consecutive parameter bytes in one I2C Write
Transaction.
NOTE:
Autoincrement is disabled on this register. Address will stay at 0x7E for
each word access.
Bit - Name
Bit
CMD[15:8]
15:8
Default
High byte portion of a PWM script command
Bit Function
CMD[7:0]
7:0
Low byte portion of a PWM script command
INTERFACE CONTROL REGISTERS
The following section describes the functions of special control registers provided for the main controller.
The manufacturer code MFGCODE and the software revision number SWREV tell the main device which
configuration file has to be used for this device.
NOTE
I2CSA and MFGCODE use the same address. They just differentiate in the access type:
•
•
Write - I2CSA
Read - MFGCODE
I2CSA - I2C-Compatible ACCESS.bus Slave Address Register
Table 38. I2CSA - I2C-Compatible ACCESS.bus Slave Address Register
Register - Name
Address
Type
Register Function
2
I2CSA
0x80
W
Bit - Name
Bit
Default
SLAVEADDR[7:1]
7:1
0x44
(reserved)
0
I C-compatible ACCESS.bus Slave Address.
The address is internally applied after the next I2C STOP.
Bit Function
7-bit address field for the I2C-compatible ACCESS.bus slave address.
(reserved)
MFGCODE - Manufacturer Code Register
Table 39. MFGCODE - Manufacturer Code Register
Register - Name
Address
Type
MFGCODE
0x80
R
Bit - Name
Bit
Default
MFGBIT
7:0
0x00
Register Function
Manufacturer code of the LM8328
Bit Function
8 - bit field containing the manufacturer code
SWREV - Software Revision Register
Table 40. SWREV - Software Revision Register
Register - Name
Address
Type
SWREV
0x81
R
Register Function
Software revision code of the LM8328.
NOTE: writing the SW revision with the inverted value triggers a reset (see
SWRESET)
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Table 40. SWREV - Software Revision Register (continued)
Register - Name
Address
Type
Register Function
Bit - Name
Bit
Default
Bit Function
SWBIT
7:0
0x84
8 - bit field containing the SW Revision number.
SWRESET - Software Reset
Table 41. SWRESET - Software Reset Register
Register - Name
Address
Type
Register Function
Software reset
SWRESET
0x81
W
NOTE: the reset is only applied if the supplied parameter has the inverted
value as SWBIT.
Reading this register provides the software revision. (see SWREV)
Bit - Name
Bit
SWBIT
7:0
Default
Bit Function
Reapply inverted value for software reset.
RSTCTRL - System Reset Register
This register allows to reset specific blocks of the LM8328. For global reset of the IOExpander the I2C command
'General Call reset' is used (see Global Call Reset). This will reset the slave address back to 0x88. During an
active reset of a module, the LM8328 blocks the access to the module registers. A read will return 0, write
commands are ignored.
Table 42. RSTCTRL - System Reset Register
Register - Name
Address
Type
RSTCTRL
0x82
R/W
Bit - Name
Bit
Default
(reserved)
7:5
IRQRST
4
Register Function
Software reset of specific parts of the LM8328
Bit Function
(reserved)
0x0
Interrupt controller reset. Does not change status on IRQN ball. Only
controls IRQ module register. Interrupt status read out is not possible
when this bit is set.
0: interrupt controller not reset
1: interrupt controller reset
Timer reset for Timers 0, 1, 2
TIMRST
3
0x0
(reserved)
2
0x0
KBDRST
1
0x0
0: timer not reset
1: timer is reset
(reserved)
Keyboard interface reset
0: keyboard is not reset
1: keyboard is reset
GENIO reset
GPIRST
0
0x0
0: GENIO not reset
1: GENIO is reset.
RSTINTCLR - Clear NO Init/Power-On Interrupt Register
Table 43. RSTINTCLR - Clear NO Init/Power-On Interrupt Register
Register - Name
26
Address
Type
Register Function
RSTINTCLR
0x84
W
This register allows to de-assert the POR/No Init Interrupt set every time
the device returns from RESET (either POR, HW or SW Reset), the IRQN
line is assigned active (low) and the IRQST.PORIRQ bit is set.
Bit - Name
Bit
Default
Bit Function
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Table 43. RSTINTCLR - Clear NO Init/Power-On Interrupt Register (continued)
Register - Name
Address
reserved
7:1
IRQCLR
0
Type
Register Function
(reserved)
1: Clears the PORIRQ Interrupt signalled in IRQST register.
0: is ignored
CLKMODE - Clock Mode Register
Table 44. CLKMODE - Clock Mode Register
Register - Name
Address
Type
CLKMODE
0x88
R/W
Bit - Name
Bit
Default
(reserved)
7:2
Register Function
This register controls the current operating mode of the LM8328 device
Bit Function
(reserved)
Writing to 00 forces the device to immediately enter sleep mode,
regardless of any autosleep configuration. Reading this bit returns the
current operating mode, which should always be 01.
MODCTL[1:0]
1:0
0x01
00: SLEEP Mode
01: Operation Mode
1x: Future modes
CLKEN - Clock Enable Register
Table 45. CLKEN - Clock Enable Register
Register - Name
Address
Type
CLKEN
0x8A
R/W
Bit - Name
Bit
Default
(reserved)
7:3
TIMEN
2
Register Function
Controls the clock to different functional units. It shall be used to enable
the functional blocks globally and independently.
Bit Function
(reserved)
PWM Timer 0, 1, 2 clock enable
0x0
0: Timer 0, 1, 2 clock disabled
1: Timer 0, 1, 2 clock enabled.
(reserved)
1
KBDEN
0
(reserved)
Keyboard clock enable (starts/stops key scan)
0x0
0: Keyboard clock disabled
1: Keyboard clock enabled
AUTOSLIP - Autosleep Enable Register
Table 46. AUTOSLIP - Autosleep Enable Register
Register - Name
Address
Type
AUTOSLP
0x8B
R/W
Bit - Name
Bit
Default
(reserved)
7:1
Register Function
This register controls the Auto Sleep function of the LM8328 device
Bit Function
(reserved)
Enables automatic sleep mode after a defined activity time stored in the
AUTOSLPTI register
ENABLE
0
0x00
1: Enable entering auto sleep mode
0: Disable entering auto sleep mode
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AUTOSLPTI - Auto Sleep Time Register
Table 47. AUTOSLPTI - Auto Sleep Time Register
Register - Name
Address
Type
AUTOSLPTIL
AUTOSLPTIH
0x8C
0x8D
R/W
Bit - Name
Bit
Default
(reserved)
15:11
(reserved)
10:8
7:0
Values of UPTIME[10:0] match to multiples of 4ms:
0x00: no autosleep, regardless if AUTOSLP.ENABLE is set
0x01: 4ms
0x02: 8ms
0x7A: 500 ms
0xFF: 1020 ms (default after reset)
0x100: 1024 ms
0x7FF: 8188 ms
UPTIME[10:8]
UPTIME[7:0]
0x00
0xFF
Register Function
This register defines the activity time. If this time passes without any
processing events then the device enters into sleep-mode, but only if
AUTOSLP.ENABLE bit is set to 1.
Bit Function
IRQST - Global Interrupt Status Register
Table 48. IRQST - Global Interrupt Status Register
Register - Name
Address
Type
IRQST
0x91
R
Bit - Name
Bit
Default
Register Function
Returns the interrupt status from various on-chip function blocks. If any of
the bits is set and an IRQN line is configured, the IRQN line is asserted
active
Bit Function
Supply failure on VCC.
PORIRQ
7
0x1
Also power-on is considered as an initial supply failure. Therefore, after
power-on, the bit is set.
0: no failure recorded
1: Failure, device was completely reset and requires re-programming.
Keyboard interrupt (further key selection in keyboard module)
KBDIRQ
6
0x0
0: inactive
1: active
(reserved)
5:4
TIM2IRQ
3
(reserved)
Timer2 expiry (CDIRQ or CYCIRQ)
0x0
0: inactive
1: active
Timer1 expiry (CDIRQ or CYCIRQ)
TIM1IRQ
2
0x0
0: inactive
1: active
Timer0 expiry (CDIRQ or CYCIRQ)
TIM0IRQ
1
0x0
0: inactive
1: active
GPIO interrupt (further selection in GPIO module)
GPIOIRQ
0
0x0
0: inactive
1: active
GPIO FEATURE CONFIGURATION
GPIO Feature Mapping
The LM8328 has a flexible IO structure which allows to dynamically assign different functionality to each ball. The
functionality of each ball is determined by the complete configuration of the balls.
28
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In general the following priority is given:
• Keypad
• GPIO/PWM/Interrupt
With this, each ball will be available as GPIO, PWM or interrupt unless it is specified to be part of the keypad
matrix. The configuration for keypad or PWM/interrupt usage is defined by the following registers:
• KBDSIZE and KBDDEDCFG
– Both registers define a ball as either part of the keypad matrix or as dedicated key input. These settings
have highest priority and will overwrite settings made in other registers.
• IOCFG
– This register is used to define the usage of KPY[11:8] if not configured to be part of the keymatrix, to be
used as GPIO.
Table 49. Ball Configuration Options
BALL
Module connectivity
GPIOSEL
BALLCFG
0x0
KPX[7:0]
not used
KPY[7:0]
not used
0x1
0x2
0x3
0x4
0x5
0x6
0x7
GPIO[7:0]
GPIO[15:8]
KPY8/PWM2
not used
GPIO16
(reserved)
-
-
-
-
-
KPY9/PWM1
not used
GPIO17
PWM1
-
-
-
-
-
-
KPY10/PWM0
not used
GPIO18
PWM0
-
-
-
-
-
-
IRQN/KPY11/PW
M2
see IOCFG
GPIO19
PWM2 (1)
PWM2
-
-
-
-
-
(1)
PWM2
(1)
Note 1: PWM2 functionality is mutally exclusive — one pin at a time only (KPY8 or KPY11) depending on interrupt enable Bit 4 of
IOCFG.
IOCGF - Input/Output Pin Mapping Configuration Register
Table 50. IOCGF - Input/Output Pin Mapping Configuration Register
Register - Name
Address
Type
IOCFG
0xA7
W
Bit - Name
Bit
Default
Register Function
Configures usage of KPY[11:8] if not used for Keypad. On each write to
this register, BALLCFG defines the column of Table 49 to configure.
Bit Function
Configures the IRQN/KPY11/PWM2 ball
GPIOSEL
7:4
(reserved)
3
BALLCFG
2:0
Bit 4: Interrupt enabled
Bit [7:5]: not used
(reserved)
Select column to configure, see Ball configuration options
IOPC0 - Pull Resistor Configuration Register 0
Table 51. IOPC0 - Pull Resistor Configuration Register 0
Register - Name
Address
Type
IOPC0*
OxAA
R/W
Bit - Name
Bit
Default
Register Function
Defines the pull resistor configuration for balls KPX[7:0]
Bit Function
Resistor enable for KPX7 ball
KPX7PR[1:0]
15:14
0x2
00: no pull resistor at ball
01:pull down resistor programmed
1x: pull up resistor programmed
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Table 51. IOPC0 - Pull Resistor Configuration Register 0 (continued)
Register - Name
Address
Type
Register Function
Resistor enable for KPX6 ball
KPX6PR[1:0]
13:12
0x2
00: no pull resistor at ball
01:pull down resistor programmed
1x: pull up resistor programmed
Resistor enable for KPX5 ball
KPX5PR[1:0]
11:10
0x2
00: no pull resistor at ball
01:pull down resistor programmed
1x: pull up resistor programmed
Resistor enable for KPX4 ball
KPX4PR[1:0]
9:8
0x2
00: no pull resistor at ball
01:pull down resistor programmed
1x: pull up resistor programmed
Resistor enable for KPX3 ball
KPX3PR[1:0]
7:6
0x2
00: no pull resistor at ball
01:pull down resistor programmed
1x: pull up resistor programmed
Resistor enable for KPX2 ball
KPX2PR[1:0]
5:4
0x2
00: no pull resistor at ball
01:pull down resistor programmed
1x: pull up resistor programmed
Resistor enable for KPX1 ball
KPX1PR[1:0]
3:2
0x2
00: no pull resistor at ball
01:pull down resistor programmed
1x: pull up resistor programmed
Resistor enable for KPX0 ball
KPX0PR[1:0]
1:0
0x2
00: no pull resistor at ball
01:pull down resistor programmed
1x: pull up resistor programmed
IOPC1 - Pull Resistor Configuration Register 1
Table 52. IOPC1 - Pull Resistor Configuration Register 1
Register - Name
Address
Type
IOPC1**
0xAC
R/W
Bit - Name
Bit
Default
Register Function
Defines the pull resistor configuration for balls KPY[7:0]
Bit Function
Resistor enable for KPY7 ball
KPY7PR[1:0]
15:14
0x1
00: no pull resistor at ball
01:pull down resistor programmed
1x: pull up resistor programmed
Resistor enable for KPY6 ball
KPY6PR[1:0]
13:12
0x1
00: no pull resistor at ball
01:pull down resistor programmed
1x: pull up resistor programmed
Resistor enable for KPY5 ball
KPY5PR[1:0]
11:10
0x1
00: no pull resistor at ball
01:pull down resistor programmed
1x: pull up resistor programmed
30
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Table 52. IOPC1 - Pull Resistor Configuration Register 1 (continued)
Register - Name
Address
Type
Register Function
Resistor enable for KPY4 ball
KPY4PR[1:0]
9:8
0x1
00: no pull resistor at ball
01:pull down resistor programmed
1x: pull up resistor programmed
Resistor enable for KPY3 ball
KPY3PR[1:0]
7:6
0x1
00: no pull resistor at ball
01:pull down resistor programmed
1x: pull up resistor programmed
Resistor enable for KPY2 ball
KPY2PR[1:0]
5:4
0x1
00: no pull resistor at ball
01:pull down resistor programmed
1x: pull up resistor programmed
Resistor enable for KPY1 ball
KPY1PR[1:0]
3:2
0x1
00: no pull resistor at ball
01:pull down resistor programmed
1x: pull up resistor programmed
Resistor enable for KPY0 ball
KPY0PR[1:0]
1:0
0x1
00: no pull resistor at ball
01:pull down resistor programmed
1x: pull up resistor programmed
IOPC2 - Pull Resistor Configuration Register 2
Table 53. IOPC2 - Pull Resistor Configuration Register 2
Register - Name
Address
Type
Register Function
IOPC2***
0xAE
R/W
Defines the pull resistor configuration for balls KPY[11:8]
Bit - Name
Bit
Default
(reserved)
15:8
0x5A
Bit Function
(reserved)
Resistor enable for KPY11 ball
KPY11PR[1:0]
7:6
0x0
00: no pull resistor at ball
01:pull down resistor programmed
1x: pull up resistor programmed
Resistor enable for KPY10 ball
KPY10PR[1:0]
5:4
0x1
00: no pull resistor at ball
01:pull down resistor programmed
1x: pull up resistor programmed
Resistor enable for KPY9 ball
KPY9PR[1:0]
3:2
0x1
00: no pull resistor at ball
01:pull down resistor programmed
1x: pull up resistor programmed
Resistor enable for KPY8 ball
KPY8PR[1:0]
1:0
0x1
00: no pull resistor at ball
01:pull down resistor programmed
1x: pull up resistor programmed
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GPIOOME0 - GPIO Open Drain Mode Enable Register 0
Table 54. GPIOOME0 - GPIO Open Drain Mode Enable Register 0
Register - Name
Address
Type
GPIOOME0
0xE0
R/W
Bit - Name
Bit
Default
KPX[7:0]ODE
7:0
0x0
Register Function
Configures KPX[7:0] for Open Drain or standard output functionality. The
Open Drain drive source is configured by GPIOOMS0.
Bit Function
Open Drain Enable on KPX[7:0]
0: full buffer
1: open drain functionality
GPIOOMS0 - GPIO Open Drain Mode Select Register 0
Table 55. GPIOOMS0 - GPIO Open Drain Mode Select Register 0
Register - Name
Address
Type
GPIOOMS0
0xE1
R/W
Bit - Name
Bit
Default
KPX[7:0]ODM
7:0
0x0
Register Function
Configures the Open Drain drive source on KPX[7:0] if selected by
GPIOOME0.
Bit Function
0: Only nmos transistor is active in output driver stage. Output can be
driven to gnd or Hi-Z
1: Only pmos transistor is active in output driver stage. Output can be
driven to VCC or Hi-Z
GPIOOME1 - GPIO Open Drain Mode Enable Register 1
Table 56. GPIOOME1 - GPIO Open Drain Mode Enable Register 1
Register - Name
Address
Type
GPIOOME1
0xE2
R/W
Bit - Name
Bit
Default
Register Function
Configures KPY[7:0] for Open Drain or standard output functionality. The
Open Drain drive source is configured by GPIOOMS1.
Bit Function
Open Drain Enable on KPY[7:0]
KPY[7:0]ODE
7:0
0x0
0: full buffer
1: open drain functionality
GPIOOMS1 - GPIO Open Drain Mode Select Register 1
Table 57. GPIOOMS1 - GPIO Open Drain Mode Select Register 1
Register - Name
Address
Type
GPIOOMS1
0xE3
R/W
Bit - Name
Bit
Default
KPY[7:0]ODM
7:0
0x0
Register Function
Configures the Open Drain drive source on KPY[7:0] if selected by
GPIOOME1.
Bit Function
0: Only nmos transistor is active in output driver stage. Output can be
driven to gnd or Hi-Z
1: Only pmos transistor is active in output driver stage. Output can be
driven to VCC or Hi-Z
GPIOOME2 - GPIO Open Drain Mode Enable Register 2
Table 58. GPIOOME2 - GPIO Open Drain Mode Enable Register 2
32
Register - Name
Address
Type
Register Function
GPIOOME2
0xE4
R/W
Configures KPY[11:8] for Open Drain or standard output functionality. The
Open Drain drive source is configured by GPIOOMS2.
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Table 58. GPIOOME2 - GPIO Open Drain Mode Enable Register 2 (continued)
Register - Name
Address
Type
Register Function
Bit - Name
Bit
Default
Bit Function
(reserved)
7:4
0x0
(reserved)
Open Drain Enable on KPY[11:8]
KPY[11:8]ODE
3:0
0x8
0: full buffer
1: open drain functionality
Note: KPY11/IRQN ball defaults to Open Drain Mode Enable after reset.
GPIOOMS2 - GPIO Open Drain Mode Select Register 2
Table 59. GPIOOMS2 - GPIO Open Drain Mode Select Register 2
Register - Name
GPIOOMS2
Address
Type
0xE5
R/W
Bit - Name
Bit
Default
(reserved
7:4
KPY[11:8]ODM
Register Function
Configures the Open Drain drive source on KPY[11:8] if selected by
GPIOOME2.
Bit Function
(reserved
3:0
0x0
0: Only nmos transistor is active in output driver stage. Output can be
driven to gnd or Hi-Z
1: Only pmos transistor is active in output driver stage. Output can be
driven to VCC or Hi-Z
GPIO DATA INPUT/OUTPUT
GPIOPDATA0 - GPIO Data Register 0
Table 60. GPIOPDATA0 - GPIO Data Register 0
Register - Name
Address
Type
Register Function
This register is used for data input/output of KPX[7:0]. Every data I/O is
masked with the associated MASK register.
GPIODATA0
0xC0
R/W
If one of the I/Os is defined as output (see Table 63) values written to this
register are masked with MASK and then applied to the associated pin.
If one of the I/Os is defined as input (see Table 63) values read from this
register hold the masked input value of the associated pin.
Bit - Name
Bit
Default
Bit Function
Mask Status for KPX7 when enabled as GPIO
MASK7
15
0x0
1: KPX7 enabled
0: KPX7 disabled
Mask Status for KPX6 when enabled as GPIO
MASK6
14
0x0
1: KPX6 enabled
0: KPX6 disabled
Mask Status for KPX5 when enabled as GPIO
MASK5
13
0x0
1: KPX5 enabled
0: KPX5 disabled
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Table 60. GPIOPDATA0 - GPIO Data Register 0 (continued)
Register - Name
Address
Type
Register Function
Mask Status for KPX4 when enabled as GPIO
MASK4
12
0x0
1: KPX4 enabled
0: KPX4 disabled
Mask Status for KPX3 when enabled as GPIO
MASK3
11
0x0
1: KPX3 enabled
0: KPX3 disabled
Mask Status for KPX2 when enabled as GPIO
MASK2
10
0x0
1: KPX2 enabled
0: KPX2 disabled
Mask Status for KPX1 when enabled as GPIO
MASK1
9
0x0
1: KPX1 enabled
0: KPX1 disabled
Mask Status for KPX0 when enabled as GPIO
MASK0
8
0x0
1: KPX0 enabled
DATA7
7
0x0
Pin Status for KPX7 when enabled as GPIO
DATA6
6
0x0
Pin Status for KPX6 when enabled as GPIO
DATA5
5
0x0
Pin Status for KPX5 when enabled as GPIO
DATA4
4
0x0
Pin Status for KPX4 when enabled as GPIO
DATA3
3
0x0
Pin Status for KPX3 when enabled as GPIO
DATA2
2
0x0
Pin Status for KPX2 when enabled as GPIO
DATA1
1
0x0
Pin Status for KPX1 when enabled as GPIO
DATA0
0
0x0
Pin Status for KPX0 when enabled as GPIO
0: KPX0 disabled
GPIOPDATA1 - GPIO Data Register 1
Table 61. GPIOPDATA1 - GPIO Data Register 1
Register - Name
Address
Type
Register Function
This register is used for data input/output of KPY[7:0]. Every data I/O is
masked with the associated MASK register.
GPIODATA1
0xC2
R/W
If one of the I/Os is defined as output (see Table 64) values written to this
register are masked with MASK and then applied to the associated pin.
If one of the I/Os is defined as input (see Table 64) values read from this
register hold the masked input value of the associated pin.
Bit - Name
Bit
Default
Bit Function
Mask Status for KPY7 when enabled as GPIO
MASK15
15
0x0
1: KPY7 enabled
0: KPY7 disabled
Mask Status for KPY6 when enabled as GPIO
MASK14
14
0x0
1: KPY6 enabled
0: KPY6 disabled
Mask Status for KPY5 when enabled as GPIO
MASK13
13
0x0
1: KPY5 enabled
0: KPY5 disabled
Mask Status for KPY4 when enabled as GPIO
MASK12
12
0x0
1: KPY4 enabled
0: KPY4 disabled
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Table 61. GPIOPDATA1 - GPIO Data Register 1 (continued)
Register - Name
Address
Type
Register Function
Mask Status for KPY3 when enabled as GPIO
MASK11
11
0x0
1: KPY3 enabled
0: KPY3 disabled
Mask Status for KPY2 when enabled as GPIO
MASK10
10
0x0
1: KPY2 enabled
0: KPY2 disabled
Mask Status for KPY1 when enabled as GPIO
MASK9
9
0x0
1: KPY1 enabled
0: KPY1 disabled
Mask Status for KPY0 when enabled as GPIO
MASK8
8
0x0
1: KPY0 enabled
DATA15
7
0x0
Pin Status for KPY7 when enabled as GPIO
DATA14
6
0x0
Pin Status for KPY6 when enabled as GPIO
DATA13
5
0x0
Pin Status for KPY5 when enabled as GPIO
DATA12
4
0x0
Pin Status for KPY4 when enabled as GPIO
DATA11
3
0x0
Pin Status for KPY3 when enabled as GPIO
DATA10
2
0x0
Pin Status for KPY2 when enabled as GPIO
DATA9
1
0x0
Pin Status for KPY1 when enabled as GPIO
DATA8
0
0x0
Pin Status for KPY0 when enabled as GPIO
0: KPY0 disabled
GPIOPDATA2 - GPIO Data Register 2
Table 62. GPIOPDATA2 - GPIO Data Register 2
Register - Name
Address
Type
Register Function
This register is used for data input/output of KPY[11:8]. Every data I/O is
masked with the associated MASK register.
GPIODATA2
0xC4
R/W
If one of the I/Os is defined as output (see Table 65) values written to this
register are masked with MASK and then applied to the associated pin.
If one of the I/Os is defined as input (see Table 65) values read from this
register hold the masked input value of the associated pin.
Bit - Name
Bit
Default
(reserved)
15:12
0x0
MASK19
11
0x0
Bit Function
(reserved)
Mask Status for KPY11 when enabled as GPIO
1: KPY11 enabled
0: KPY11 disabled
Mask Status for KPY10 when enabled as GPIO
MASK18
10
0x0
1: KPY10 enabled
0: KPY10 disabled
Mask Status for KPY9 when enabled as GPIO
MASK17
9
0x0
1: KPY9 enabled
0: KPY9 disabled
Mask Status for KPY8 when enabled as GPIO
MASK16
8
0x0
1: KPY8 enabled
reserved
7:4
0x0
(reserved)
DATA19
3
0x0
Pin Status for KPY11 when enabled as GPIO
DATA18
2
0x0
Pin Status for KPY10 when enabled as GPIO
0: KPY8 disabled
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Table 62. GPIOPDATA2 - GPIO Data Register 2 (continued)
Register - Name
Address
Type
DATA17
1
0x0
Register Function
Pin Status for KPY9 when enabled as GPIO
DATA16
0
0x0
Pin Status for KPY8 when enabled as GPIO
GPIOPDIR0 - GPIO Port Direction Register 0
Table 63. GPIOPDIR0 - GPIO Port Direction Register 0
Register - Name
Address
Type
GPIODIR0
0xC6
R/W
Bit - Name
Bit
Default
KPX[7:0]DIR
7:0
0x00
Register Function
Port direction for KPX[7:0]
Bit Function
Direction bits for KPX[7:0]
0: input mode
1: output mode
GPIOPDIR1 - GPIO Port Direction Register 1
Table 64. GPIOPDIR1 - GPIO Port Direction Register 1
Register - Name
Address
Type
Register Function
GPIODIR1
0xC7
R/W
Port direction for KPY[7:0]
Bit - Name
Bit
Default
Bit Function
Direction bits for KPY[7:0]
KPY[7:0]DIR
7:0
0x00
0: input mode
1: output mode
GPIOPDIR2 - GPIO Port Direction Register 2
Table 65. GPIOPDIR2 - GPIO Port Direction Register 2
Register - Name
Address
Type
GPIODIR2
0xC8
R/W
Bit - Name
Bit
Default
(reserved)
7:4
KPY[11:8]DIR
3:0
Register Function
Port direction for KPY[11:8]
Bit Function
(reserved)
Direction bits for KPY[11:8]
0x08
0: input mode
1: output mode
GPIO INTERRUPT CONTROL
GPIOIS0 - Interrupt Sense Configuration Register 0
Table 66. GPIOIS0 - Interrupt Sense Configuration Register 0
Register - Name
Address
Type
GPIOIS0
0xC9
R/W
Bit - Name
Bit
Default
Register Function
Interrupt type on KPX[7:0]
Bit Function
Interrupt type bits for KPX[7:0]
KPX[7:0]IS
7:0
0x0
0: edge sensitive interrupt
1: level sensitive interrupt
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GPIOIS1 - Interrupt Sense Configuration Register 1
Table 67. GPIOIS1 - Interrupt Sense Configuration Register 1
Register - Name
Address
Type
GPIOIS1
0xCA
R/W
Bit - Name
Bit
Default
Register Function
Interrupt type on KPY[7:0]
Bit Function
Interrupt type bits for KPY[7:0]
KPY[7:0]IS
7:0
0x0
0: edge sensitive interrupt
1: level sensitive interrupt
GPIOIS2 - Interrupt Sense Configuration Register 2
Table 68. GPIOIS2 - Interrupt Sense Configuration Register 2
Register - Name
Address
Type
GPIOIS2
0xCB
R/W
Bit - Name
Bit
Default
(reserved)
7:4
KPY[11:8]IS
3:0
Register Function
Interrupt type on KPY[11:8]
Bit Function
(reserved)
Interrupt type bits for KPY[11:8]
0x0
0: edge sensitive interrupt
1: level sensitive interrupt
GPIOIBE0 - GPIO Interrupt Edge Configuration Register 0
Table 69. GPIOIBE0 - GPIO Interrupt Edge Configuration Register 0
Register - Name
Address
Type
Register Function
GPIOIBE0
0xCC
R/W
Defines whether an interrupt on KPX[7:0] is triggered on both edges or on
a single edge. See Table 72 for the edge configuration.
Bit - Name
Bit
Default
Bit Function
KPX[7:0]IBE
7:0
0x0
Interrupt both edges bits for KPX[7:0]
0: interrupt generated at the active edge
1: interrupt generated after both edges
GPIOIBE1 - GPIO Interrupt Edge Configuration Register 1
Table 70. GPIOIBE1 - GPIO Interrupt Edge Configuration Register 1
Register - Name
Address
Type
Register Function
Defines whether an interrupt on KPY[7:0] is triggered on both edges or on
a single edge. See Table 73 for the edge configuration.
GPIOIBE1
0xCD
R/W
Bit - Name
Bit
Default
Bit Function
Interrupt both edges bits for KPY[7:0]
KPY[7:0]IBE
7:0
0x0
0: interrupt generated at the configured edge
1: interrupt generated after both edges
GPIOIBE2 - GPIO Interrupt Edge Configuration Register 2
Table 71. GPIOIBE2 - GPIO Interrupt Edge Configuration Register 2
Register - Name
Address
Type
GPIOIBE2
0xCE
R/W
Bit - Name
Bit
Default
Register Function
Defines whether an interrupt on KPY[11:8] is triggered on both edges or
on a single edge. See Table 74 for the edge configuration.
Bit Function
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Table 71. GPIOIBE2 - GPIO Interrupt Edge Configuration Register 2 (continued)
Register - Name
Address
(reserved
7:4
KPY[11:8]IBE
3:0
Type
Register Function
(reserved)
Interrupt both edges bits for KPY[11:8]
0x0
0: interrupt generated at the active edge
1: interrupt generated after both edges
GPIOIEV0 - GPIO Interrupt Edge Select Register 0
Table 72. GPIOIEV0 - GPIO Interrupt Edge Select Register 0
Register - Name
Address
Type
Register Function
GPIOIEV0
0xCF
R/W
Select Interrupt edge for KPX[7:0].
Bit - Name
Bit
Default
Bit Function
Interrupt edge select from KPX[7:0]
KPX[7:0]EV
7:0
0xFF
0: interrupt at low level or falling edge
1: interrupt at high level or rising edge
GPIOIEV1 - GPIO Interrupt Edge Select Register 1
Table 73. GPIOIEV1 - GPIO Interrupt Edge Select Register 1
Register - Name
Address
Type
Register Function
GPIOIEV1
0xD0
R/W
Select Interrupt edge for KPY[7:0].
Bit - Name
Bit
Default
Bit Function
Interrupt edge select from KPY[7:0]
KPY[7:0]EV
7:0
0xFF
0: interrupt at low level or falling edge
1: interrupt at high level or rising edge
GPIOIEV2 - GPIO Interrupt Edge Select Register 2
Table 74. GPIOIEV2 - GPIO Interrupt Edge Select Register 2
Register - Name
Address
Type
Register Function
GPIOIEV2
0xD1
R/W
Select Interrupt edge for KPY[11:8].
Bit - Name
Bit
Default
(reserved)
7:4
KPY[11:8]EV
3:0
Bit Function
(reserved)
Interrupt edge select from KPY[11:8]
0xFF
0: interrupt at low level or falling edge
1: interrupt at high level or rising edge
GPIOIE0 - GPIO Interrupt Enable Register 0
Table 75. GPIOIE0 - GPIO Interrupt Enable Register 0
Register - Name
Address
Type
GPIOIE0
0xD2
R/W
Bit - Name
Bit
Default
Register Function
Enable/disable interrupts on KPX[7:0]
Bit Function
Interrupt enable on KPX[7:0]
KPX[7:0]IE
7:0
0x0
0: disable interrupt
1: enable interrupt
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GPIOIE1 - GPIO Interrupt Enable Register 1
Table 76. GPIOIE1 - GPIO Interrupt Enable Register 1
Register - Name
Address
Type
GPIOIE1
0xD3
R/W
Bit - Name
Bit
Default
Register Function
Enable/disable interrupts on KPY[7:0]
Bit Function
Interrupt enable on KPY[7:0]
KPY[7:0]IE
7:0
0x0
0: disable interrupt
1: enable interrupt
GPIOIE2 - GPIO Interrupt Enable Register 2
Table 77. GPIOIE2 - GPIO Interrupt Enable Register 2
Register - Name
Address
Type
GPIOIE2
0xD4
R/W
Bit - Name
Bit
Default
(reserved)
7:4
KPY[11:8]IE
3:0
Register Function
Enable/disable interrupts on KPY[11:8]
Bit Function
(reserved)
Interrupt enable on KPY[11:8]
0x0
0: disable interrupt
1: enable interrupt
GPIOIC0 - GPIO Clear Interrupt Register 0
Table 78. GPIOIC0 - GPIO Clear Interrupt Register 0
Register - Name
Address
Type
GPIOIC0
0xDC
W
Bit - Name
Bit
Default
Register Function
Clears the interrupt on KPX[7:0]
Bit Function
Clear Interrupt on KPX[7:0]
KPX[7:0]IC
7:0
0: no effect
1: Clear corresponding interrupt
GPIOIC1 - GPIO Clear Interrupt Register 1
Table 79. GPIOIC1 - GPIO Clear Interrupt Register 1
Register - Name
Address
Type
GPIOIC1
0xDD
W
Bit - Name
Bit
Default
KPY[7:0]IC
7:0
Register Function
Clears the interrupt on KPY[7:0]
Bit Function
Clear Interrupt on KPY[7:0]
0: no effect
1: Clear corresponding interrupt
GPIOIC2 - GPIO Clear Interrupt Register 2
Table 80. GPIOIC2 - GPIO Clear Interrupt Register 2
Register - Name
Address
Type
GPIOIC2
0xDE
W
Bit - Name
Bit
Default
(reserved)
7:4
Register Function
Clears the interrupt on KPY[11:8]
Bit Function
(reserved)
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Table 80. GPIOIC2 - GPIO Clear Interrupt Register 2 (continued)
Register - Name
Address
Type
Register Function
Clear Interrupt on KPY[11:8]
KPY[11:8]IC
3:0
0: no effect
1: Clear corresponding interrupt
GPIO INTERRUPT STATUS
GPIORIS0 - Raw Interrupt Status Register 0
Table 81. GPIORIS0 - Raw Interrupt Status Register 0
Register - Name
Address
Type
GPIORIS0
0xD6
R
Bit - Name
Bit
Default
Register Function
Raw interrupt status on KPX[7:0]
Bit Function
Raw Interrupt status data on KPX[7:0]
KPX[7:0]RIS
7:0
0x0
0: no interrupt condition at GPIO
1: interrupt condition at GPIO
GPIORIS1 - Raw Interrupt Status Register 1
Table 82. GPIORIS1 - Raw Interrupt Status Register 1
Register - Name
Address
Type
GPIORIS1
0xD7
R
Bit - Name
Bit
Default
KPY[7:0]RIS
7:0
0x0
Register Function
Raw interrupt status on KPY[7:0]
Bit Function
Raw Interrupt status data on KPY[7:0]
0: no interrupt condition at GPIO
1: interrupt condition at GPIO
GPIORIS2 - Raw Interrupt Status Register 2
Table 83. GPIORIS2 - Raw Interrupt Status Register 2
Register - Name
Address
Type
GPIORIS2
0xD8
R
Bit - Name
Bit
Default
(reserved)
7:4
Register Function
Raw interrupt status on KPY[11:8]
Bit Function
(reserved)
Raw Interrupt status data on KPY[11:8]
KPY[11:8]RIS
3:0
0x0
0: no interrupt condition at GPIO
1: interrupt condition at GPIO
GPIOMIS0 - Masked Interrupt Status Register 0
Table 84. GPIOMIS0 - Masked Interrupt Status Register 0
Register - Name
Address
Type
GPIOMIS0
0xD9
R
Bit - Name
Bit
Default
KPX[7:0]MIS
7:0
0x0
Register Function
Masked interrupt status on KPX[7:0]
Bit Function
Masked Interrupt status data on KPX[7:0]
0: no interrupt contribution from GPIO
1: interrupt GPIO is active
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GPIOMIS1 - Masked Interrupt Status Register 1
Table 85. GPIOMIS1 - Masked Interrupt Status Register 1
Register - Name
Address
Type
GPIOMIS1
0xDA
R
Bit - Name
Bit
Default
Register Function
Masked interrupt status on KPY[7:0]
Bit Function
Masked Interrupt status data on KPY[7:0]
KPY[7:0]MIS
7:0
0x0
0: no interrupt contribution from GPIO
1: interrupt GPIO is active
GPIOMIS2 - Masked Interrupt Status Register 2
Table 86. GPIOMIS2 - Masked Interrupt Status Register 2
Register - Name
Address
Type
GPIOMIS2
0xDB
R
Bit - Name
Bit
Default
(reserved)
7:4
KPY[11:8]MIS
3:0
Register Function
Masked interrupt status on KPY[11:8]
Bit Function
(reserved)
Masked Interrupt status data on KPY[11:8]
0x0
0: no interrupt contribution from GPIO
1: interrupt GPIO is active
GPIO WAKE-UP CONTROL
GPIOWAKE0 - GPIO Wake-Up Register 0
Table 87. GPIOWAKE0 - GPIO Wake-Up Register 0
Register - Name
Address
Type
Register Function
Configures wake-up conditions for KPX[7:0]
GPIOWAKE0
0xE9
R/W
Bit - Name
Bit
Default
KPX[7:0]WAKE
7:0
0x0
Each bit corresponds to a ball. When bit set, the corresponding ball
contributes to wakeup from auto sleep mode.
Bit Function
Bit 7: KPX7
...
Bit 0: KPX0
GPIOWAKE1 - GPIO Wake-Up Register 1
Table 88. GPIOWAKE1 - GPIO Wake-Up Register 1
Register - Name
Address
Type
Register Function
Configures wake-up conditions for KPY[7:0]
GPIOWAKE1
0xEA
R/W
Bit - Name
Bit
Default
KPY[7:0]WAKE
7:00
0x0
Each bit corresponds to a ball. When bit set, the corresponding ball
contributes to wakeup from auto sleep mode.
Bit Function
Bit 7: KPY7
...
Bit 0: KPY0
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GPIOWAKE2 - GPIO Wake-Up Register 2
Table 89. GPIOWAKE2 - GPIO Wake-Up Register 2
Register - Name
Address
Type
GPIOWAKE2
0xEB
R/W
Bit - Name
Bit
Default
(reserved)
7:4
KPY[11:8]WAKE
3:0
Register Function
Configures wake-up conditions for KPY[11:8]
Each bit corresponds to a ball. When bit set, the corresponding ball
contributes to wakeup from auto sleep mode.
Bit Function
(reserved)
0x0
Bit 3: KPY11
...
Bit 0: KPY8
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
ABSOLUTE MAXIMUM RATINGS
(1) (2)
−0.3V to 2.2V
Supply Voltage (VCC)
−0.2V to VCC +0.2V
Voltage at Generic IOs
−0.3V to +.4.25V
Voltage at Backdrive/Overvoltage IOs
Maximum Input Current Without Latchup
ESD Protection Level
±100 mA
(Human Body Model)
2kV
(Machine Model)
200V
(Charge Device Model)
750V
Total Current into VCC Pin (Source)
100 mA
Total Current out of GND Pin (Sink)
100 mA
−65°C to +140°C
Storage Temperature Range
(1)
(2)
Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for
which the device is intended to be functional, but specific performance is not ensured. For ensured specifications and test conditions,
see the Electrical Characteristics tables.
If Military/Aerospace specified devices are required, please contact the TI Sales Office/ Distributors for availability and specifications.
DC ELECTRICAL CHARACTERISTICS
Datasheet min/max specification limits are specified by design, test, or statistical analysis.
(Temperature: −40°C ≤ TA ≤ +85°C, unless otherwise specified)
Parameter
Operating Voltage (VCC)
Conditions
Min
Max
Units
1.98
V
3.60
V
1.9
3.0
mA
VCC = 1.8V, TA = 25°C; Internal Clock =
OFF, no internal functional blocks running
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