User's Guide
SNVA472A – March 2011 – Revised May 2013
AN-2119 LM8850 Evaluation Board Application Note
1
General Description
The LM8850 evaluation board is a working demonstration of a step-up DC-DC converter that has been
optimized for use with a super-capacitor. The super-capacitor protects a battery from power surges and
enables new high-power applications in mobile device architectures. The LM8850 creates an ideal rail
from 3.6V to 5.7V from an input voltage range of 2.3V to 5.5V, VIN must be 10% lower than expected VOUT.
An I2C interface controlling multiple output voltage settings, input current limits, and load currents up to 1A
provides superior user flexibility. The LM8850 operates in Auto mode, where the converter is in PFM
mode at light loads and switches to PWM mode at heavy loads or in forced PWM mode. Hysteretic PFM
extends the battery life by reducing the quiescent current to 7µA (typ.) during light load and standby
conditions. Synchronous operation provides true shutdown isolation and improves the efficiency at
medium to full load conditions.
High switching frequency enables smaller passive components. Internal compensation is used for a
broader range of inductor and output capacitor values to meet system demand and achieve small system
solution size.
2
Typical Application Circuit with Super-Capacitor
3.6V
4.7 PF
VIN
1 PH
5V
VOUT
SW
LM8850
4.7 PF
PG
BAL
0.05F to 1.0F
SDA
SCLK
EN
GND
Figure 1. Typical Application
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AN-2119 LM8850 Evaluation Board Application Note
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1
Connection Diagram and Package Mark Information
3
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Connection Diagram and Package Mark Information
(Bottom View)
(Top View)
A3
A2
A1
A1
A2
A3
B3
B2
B1
B1
B2
B3
C3
C2
C1
C1
C2
C3
Figure 2. 9-Bump DSBGA Package
4
Block Diagram
SW
VOUT
VIN
Amp
BAL
SCL
PFM Generator
SDA
Control Logic
Error Amp
PG
VREF
EN
+
-
2.5 MHz
Oscillator
Ramp Generator
GND
Figure 3. Block Diagram
2
AN-2119 LM8850 Evaluation Board Application Note
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SNVA472A – March 2011 – Revised May 2013
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Pin Descriptions
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5
Pin Descriptions
Table 1. Pin Descriptions
6
Pin #
Name
Description
A1
VIN
Power Supply Input. Connect to input filter capacitor (see Typical Application Circuit).
A2
SW
Switching node. Connection to the internal NFET switch and PFET synchronous
rectifier.
A3
GND
Ground Pin
B1
SDA
I2C data (Use a 2kΩ pullup resistor.)
B2
PG
B3
VOUT
Power Good indicator
Output pin.
C1
SCLK
I2C Clock (Use a 2KΩ pull up resistor.)
C2
EN
Enable pin. The device is in shutdown when voltage to this pin is < 0.4V and enabled
when > 1.2V. Do not leave this pin floating.
C3
BAL
Balancing pin for active voltage balancing of super-capacitor.
Board Operation
To operate the LM8850, connections to VIN, Ground and the jumper on the enable pin must be in the H
position. To start out, supply 3.6V to VIN. With a valid supply, Vout should power up to 5V within 5
seconds.
Once enabled, the LM8850 charges the supercapacitor utilizing all of the default settings in the registers.
The I2C must be used to change the default settings and this can only be done with the LM8850 enabled.
Once a register is written to, the changes will transition immediately. Every time the EN pin transitions
from VIL to VIH, registers 0 and 1 are reset to their defaults settings and any settings needed bust
rewritten into the appropriate registers.
7
I2C-Compatible Chip Address
The device address for LM8850 is 60 (HEX).
Register Name
Location
Type
CONTROL
00
R/W
Control Register 0 (Figure 4)
CONTROL
01
R/W
Control Register 1 (Figure 5)
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Register
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Copyright © 2011–2013, Texas Instruments Incorporated
3
I2C-Compatible Chip Address
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MSB
7
LSB
6
5
4
3
2
1
0
Register location = 00
Output Voltage Change
0 0 0 = 3.6V
0 0 1 = 3.9V
0 1 0 = 4.2V
0 1 1 = 4.5V
1 0 0 = 4.7V
1 0 1 = 5.0V (default)
1 1 0 = 5.3V
1 1 1 = 5.7V
`
FromRegister Location
01, bit 5
From Register
Location 00, bits 0
and 1
PFM Voltage Ripple
0 0 = 50 mV
0 1 = 100 mV (default)
1 0 = 200 mV
1 1 = 250 mV
Balance Circuit
0 = OFF
1 = ON (default)
Effective when part is enabled
Mode
0 = AUTO (PFM/PWM ± default)
1 = FORCED PWM
Ton Time
0 0 = 5s (default)
0 1 = 7.5s
1 0 = 10s
1 1 = 12.5s
30150504
Figure 4. CONTROL Register 0
Register Location = 00
4
AN-2119 LM8850 Evaluation Board Application Note
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I2C-Compatible Chip Address
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MS B
7
LS B
6
5
4
3
2
1
0
Register location = 01
Switch Current Limit ± (Max values)
111 = 1500 mA (default)
101 = 1025 mA
001 = 740 mA
000 = 530 mA
Balmode
0 = OFF (default)
1 = ON
Effective when part is disabled
Enable
0 = OFF
1 = ON (default)
Bit 5 used to determine output voltage
0 0 0 = 3.6V
0 0 1 = 3.9V
0 1 0 = 4.2V
0 1 1 = 4.5V
1 0 0 = 4.7V
1 0 1 = 5.0V (default)
1 1 0 = 5.3V
1 1 1 = 5.7V
From Register
Location 01, bit 5
From Register
Location 00,
bits 0 and 1
PGOOD (Read only)
Figure 5. CONTROL Register 1
Register Location = 01
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LM8850 Evaluation Board Schematic
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8
LM8850 Evaluation Board Schematic
9
LM8850 Evaluation Board Bill of Materials
Table 2. Bill of Materials
Item
6
Qty
Value
C1 (CIN)
1
10 µF
C1608X5R0J106M
0603, 6.3V, TDK
C2 (COUT)
1
4.7 µF
CL10A475KP8NNNB
0603, 10V, SAMSUNG
C3 = C4 (FILTER CAP)
2
100 µF
TPSC107M006R0075
0805, 10V, AVX
C5 (AC FILTER CAP)
1
100 nF
CL05F104Z05NNB
0402, 10V, SAMSUNG
L1
1
1µF
KSLI-252012AG-1R0
2520, 1.5A, HITACHI
VDD CONNECTOR
1
-
93K4533
NEWARK
GND CONNECTOR
1
-
80P3616
NEWARK
SuperCapacitor
1
500Mf
EDLC272020-501-2F-50
Super Capacitor
LM8850
Boost Regulator
U1
1
Total
10
Part Number
AN-2119 LM8850 Evaluation Board Application Note
Copyright © 2011–2013, Texas Instruments Incorporated
Description
SNVA472A – March 2011 – Revised May 2013
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LM8850 Evaluation Board Layers
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10
LM8850 Evaluation Board Layers
There are a few solder mask openings for various supercapacitor packages. If you plan on changing to a
different supercapacitor than what is initially assembled, be sure assemble using the best solder pad
openings for your supercapacitor footprint. Below, in the circled areas, are the initial pads used for the
TDK supercap initially assembled. If the given pads aren’t acceptable, the solder mask can be removed to
expose the copper for any footprint needed.
Figure 6. Top Layer
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LM8850 Evaluation Board Layers
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Figure 7. Mid- Layer 1
Figure 8. Mid- Layer 2
8
AN-2119 LM8850 Evaluation Board Application Note
Copyright © 2011–2013, Texas Instruments Incorporated
SNVA472A – March 2011 – Revised May 2013
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LM8850 Evaluation Board Layers
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Figure 9. Bottom Layer
SNVA472A – March 2011 – Revised May 2013
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AN-2119 LM8850 Evaluation Board Application Note
Copyright © 2011–2013, Texas Instruments Incorporated
9
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