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LMH6550
SNOSAK0I – DECEMBER 2004 – REVISED JANUARY 2015
LMH6550 Differential, High-Speed Operational Amplifier
1 Features
•
•
•
•
•
•
1
3 Description
The LMH6550 device is a high-performance voltage
feedback differential amplifier. The LMH6550 has the
high speed and low distortion necessary for driving
high-performance ADCs as well as the current
handling capability to drive signals over balanced
transmission lines like CAT 5 data cables. The
LMH6550 can handle a wide range of video and data
formats.
400 MHz −3-dB Bandwidth (VOUT = 0.5 VPP)
90 MHz 0.1-dB Bandwidth
3000 V/µs Slew Rate
8 ns Settling Time to 0.1%
−92/−103 dB HD2/HD3 at 5 MHz
10 ns Shutdown/Enable
With external gain set resistors, the LMH6550 can be
used at any desired gain. Gain flexibility coupled with
high speed makes the LMH6550 suitable for use as
an IF amplifier in high-performance communications
equipment.
2 Applications
•
•
•
•
•
•
•
Differential AD Driver
Video Over Twisted-Pair
Differential Line Driver
Single End to Differential Converter
High-Speed Differential Signaling
IF/RF Amplifier
SAW Filter Buffer/Driver
The LMH6550 is available in the space-saving SOIC
and VSSOP packages.
Device Information(1)
PART NUMBER
LMH6550
PACKAGE
BODY SIZE (NOM)
SOIC (8)
4.90 mm × 3.91 mm
VSSOP (8)
3.00 mm × 3.00 mm
(1) For all available packages, see the orderable addendum at
the end of the datasheet.
4 Typical Application Schematic
RF
AV, RIN
RS
VS
a
VI
+
V
RO
RG
+
-
VCM
RT
+
RM
RG
IN-
ADC
VO
IN+
RO
-
V
RF
For R M R G :
Av
RIN #
DesignTarget :
VO RF
#
VI R G
1) Set R T
2R G (1 A v )
2 Av
2) Set RM
1
1
1
R S RIN
R T || R S
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
LMH6550
SNOSAK0I – DECEMBER 2004 – REVISED JANUARY 2015
www.ti.com
Table of Contents
1
2
3
4
5
6
7
8
Features ..................................................................
Applications ...........................................................
Description .............................................................
Typical Application Schematic.............................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
1
2
3
3
7.1
7.2
7.3
7.4
7.5
7.6
7.7
3
3
4
4
4
6
8
Absolute Maximum Ratings ......................................
ESD Ratings..............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics: ±5 V .................................
Electrical Characteristics: 5 V ...................................
Typical Characteristics ..............................................
Detailed Description ............................................ 12
8.1 Overview ................................................................. 12
8.2 Functional Block Diagram ....................................... 12
8.3 Feature Description................................................. 12
8.4 Device Functional Modes........................................ 13
9
Application and Implementation ........................ 14
9.1 Application Information............................................ 14
9.2 Typical Applications ................................................ 14
10 Power Supply Recommendations ..................... 22
11 Layout................................................................... 22
11.1
11.2
11.3
11.4
Layout Guidelines .................................................
Layout Example ....................................................
Power Dissipation .................................................
ESD Protection......................................................
22
22
24
24
12 Device and Documentation Support ................. 25
12.1
12.2
12.3
12.4
12.5
Device Support......................................................
Documentation Support ........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
25
25
25
25
25
13 Mechanical, Packaging, and Orderable
Information ........................................................... 25
5 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision H (March 2013) to Revision I
•
Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation
section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and
Mechanical, Packaging, and Orderable Information section .................................................................................................. 1
Changes from Revision G (March 2013) to Revision H
•
2
Page
Page
Changed layout of National Data Sheet to TI format ........................................................................................................... 22
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SNOSAK0I – DECEMBER 2004 – REVISED JANUARY 2015
6 Pin Configuration and Functions
D Package / DGK Package
8 Pins
Top View
1
8
+IN
-IN
-
2
+
VCM
7
3
6
4
5
EN
V-
V+
+OUT
-OUT
Pin Functions
PIN
NAME
NO.
I/O
DESCRIPTION
EN
7
I
Enable
-IN
1
I
Negative Input
+IN
8
I
Positive Input
-OUT
5
O
Negative Output
+OUT
4
O
Positive Output
V-
6
P
Negative Supply
V+
3
P
Positive Supply
VCM
2
I
Output Common-Mode Input
7 Specifications
7.1 Absolute Maximum Ratings (1) (2) (3)
MAX
UNIT
Supply Voltage
MIN
13.2
V
Common-Mode Input Voltage
±VS
V
30
mA
150
°C
150
°C
Maximum Input Current (pins 1, 2, 7, 8)
(4)
Maximum Output Current (pins 4, 5)
Maximum Junction Temperature
−65
Storage Temperature, Tstg
(1)
(2)
(3)
(4)
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/ Distributors for availability and
specifications.
For Soldering Information, see Product Folder at www.ti.com and SNOA549.
The maximum output current (IOUT) is determined by device power dissipation limitations.
7.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic discharge (1)
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001
Machine model (MM)
(2)
UNIT
±2000
±200
V
Human body model: 1.5 kΩ in series with 100 pF. Machine model: 0 Ω in series with 200 pF.
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
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7.3 Recommended Operating Conditions
MIN
NOM
MAX
UNIT
Operating Temperature
−40
85
°C
Total Supply Voltage
4.5
12
V
7.4 Thermal Information
LMH6550
THERMAL METRIC (1)
RθJA
(1)
(2)
Junction-to-ambient thermal resistance
(2)
D
DGK
UNIT
8 PINS
8 PINS
150
235
°C/W
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
The maximum power dissipation is a function of TJ(MAX), θJA and TA. The maximum allowable power dissipation at any ambient
temperature is P D= (TJ(MAX) — TA)/ θJA. All numbers apply for package soldered directly into a 2 layer PC board with zero air flow.
7.5 Electrical Characteristics: ±5 V (1)
Single-ended in differential out, TA = 25°C, VS = ±5 V, VCM = 0 V, RF = RG = 365 Ω, RL = 500 Ω; unless specified.
PARAMETER
TEST CONDITIONS
MIN
(2)
TYP
(3)
MAX
(2)
UNIT
AC PERFORMANCE (DIFFERENTIAL)
SSBW
Small Signal −3 dB Bandwidth
VOUT = 0.5 VPP
400
MHz
LSBW
Large Signal −3 dB Bandwidth
VOUT = 2 VPP
380
MHz
Large Signal −3 dB Bandwidth
VOUT = 4 VPP
320
MHz
0.1 dB Bandwidth
VOUT = 0.5 VPP
90
MHz
Slew Rate
4-V Step
3000
V/μs
Rise/Fall Time
2-V Step
1
ns
Settling Time
2-V Step, 0.1%
8
ns
(4)
2000
VCM PIN AC PERFORMANCE (COMMON-MODE FEEDBACK AMPLIFIER)
Common-Mode Small Signal
Bandwidth
VCM Bypass Capacitor Removed
210
MHz
Slew Rate
VCM Bypass Capacitor Removed
200
V/µs
VO = 2 VPP, f = 5 MHz, RL = 800 Ω
−92
VO = 2 VPP, f = 20 MHz, RL = 800 Ω
−78
VO = 2 VPP, f = 70 MHz, RL = 800 Ω
−59
VO = 2 VPP, f = 5 MHz, RL = 800 Ω
−103
VO = 2 VPP, f = 20 MHz, RL = 800 Ω
−88
VO = 2 VPP, f = 70 MHz, RL = 800 Ω
−50
DISTORTION AND NOISE RESPONSE
HD2
HD3
2nd Harmonic Distortion
3rd Harmonic Distortion
dBc
dBc
en
Input Referred Voltage Noise
f ≥ 1 MHz
6.0
nV/√Hz
in
Input Referred Noise Current
f ≥ 1 MHz
1.5
pA/√Hz
INPUT CHARACTERISTICS (DIFFERENTIAL)
VOSD
IBI
(1)
(2)
(3)
(4)
(5)
(6)
4
Input Offset Voltage
Differential Mode, VID =
0, VCM = 0
Input Offset Voltage Average
Temperature Drift
(5)
Input Bias Current
(6)
1
At extreme
temperatures
±4
mV
±6
1.6
0
-8
µV/°C
−16
µA
Electrical Table values apply only for factory testing conditions at the temperature indicated. Factory testing conditions result in very
limited self-heating of the device such that TJ = TA.
Limits are 100% production tested at 25°C. Limits over the operating temperature range are guaranteed through correlation using
Statistical Quality Control (SQC) methods.
Typical numbers are the most likely parametric norm.
Slew Rate is the average of the rising and falling edges.
Drift determined by dividing the change in parameter at temperature extremes by the total temperature change.
Negative input current implies current flowing out of the device.
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Electrical Characteristics: ±5 V(1) (continued)
Single-ended in differential out, TA = 25°C, VS = ±5 V, VCM = 0 V, RF = RG = 365 Ω, RL = 500 Ω; unless specified.
PARAMETER
Input Bias Current Average
Temperature Drift
TEST CONDITIONS
MIN
(2)
(5)
TYP
(3)
MAX
(2)
UNIT
9.6
nA/°C
0.3
µA
Input Bias Difference
Difference in Bias Currents Between the
Two Inputs
CMRR
Common-Mode Rejection Ratio
DC, VCM = 0 V, VID = 0 V
82
dBc
RIN
Input Resistance
Differential
5
MΩ
CIN
Input Capacitance
Differential
1
pF
CMVR
Input Common-Mode Voltage Range
CMRR > 53 dB
+3.2
−4.7
V
72
+3.1
−4.6
VCM PIN INPUT CHARACTERISTICS (COMMON-MODE FEEDBACK AMPLIFIER)
VOSC
Input Offset Voltage
Common Mode, VID = 0
1
At extreme
temperatures
Input Offset Voltage Average
Temperature Drift
(5)
Input Bias Current
(6)
VCM CMRR
VID = 0 V, 1-V Step on VCM Pin, Measure
VOD
mV
±8
25
µV/°C
−2
μA
70
75
dB
0.995
0.997
7.38
7.8
V
±3.8
V
Input Resistance
Common-Mode Gain
±5
25
ΔVO,CM/ΔVCM
kΩ
1.005
V/V
OUTPUT PERFORMANCE
Output Voltage Swing
Peak to Peak,
Differential
At extreme
temperatures
Output Common-Mode Voltage
Range
VID = 0 V,
IOUT
Linear Output Current
VOUT = 0 V
ISC
Short Circuit Current
Output Shorted to Ground
VIN = 3 V Single-Ended (7)
Output Balance Error
ΔVOUT Common Mode /ΔVOUT
Differential, VOUT = 1 VPP Differential, f =
10 MHz
7.18
±3.69
±63
±75
mA
±200
mA
−68
dB
MISCELLANEOUS PERFORMANCE
Enable Voltage Threshold
Pin 7
Disable Voltage Threshold
Pin 7
Enable Pin Current
2.0
V
1.5
VEN =0 V
(6)
-250
VEN =4 V
(6)
55
Enable/Disable Time
ns
70
dB
Open Loop Gain
Differential
PSRR
Power Supply Rejection Ratio
DC, ΔVS = ±1 V
74
90
Supply Current
RL = ∞
18
20
At extreme
temperatures
(7)
µA
10
AVOL
Disabled Supply Current
V
dB
24
mA
27
1
1.2
mA
The maximum output current (IOUT) is determined by device power dissipation limitations.
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7.6 Electrical Characteristics: 5 V (1)
Single-ended in differential out, TA = 25°C, AV = +1, VS = 5 V, VCM = 2.5 V, RF = RG = 365 Ω, RL = 500 Ω; unless specified.
PARAMETER
TEST CONDITIONS
MIN
(2)
TYP
(3)
MAX
(2)
UNIT
SSBW
Small Signal −3 dB Bandwidth
RL = 500 Ω, VOUT = 0.5 VPP
350
MHz
LSBW
Large Signal −3 dB Bandwidth
RL = 500 Ω, VOUT = 2 VPP
330
MHz
60
MHz
1500
V/μs
0.1 dB Bandwidth
(4)
Slew Rate
2-V Step
Rise/Fall Time, 10% to 90%
1-V Step
Settling Time
1-V Step, 0.05%
1
ns
12
ns
Common-Mode Small Signal
Bandwidth
185
MHz
Slew Rate
180
V/μs
VCM PIN AC PERFORMANCE (COMMON-MODE FEEDBACK AMPLIFIER)
DISTORTION AND NOISE RESPONSE
HD2
HD3
2nd Harmonic Distortion
3rd Harmonic Distortion
VO = 2 VPP, f = 5 MHz, RL = 800 Ω
−89
VO = 2 VPP, f = 20 MHz, RL = 800 Ω
−88
VO = 2 VPP, f = 5 MHz, RL = 800 Ω
−85
VO = 2 VPP, f = 20 MHz, RL = 800 Ω
−70
dBc
dBc
en
Input Referred Noise Voltage
f ≥ 1 MHz
6.0
nV/√Hz
in
Input Referred Noise Current
f ≥ 1 MHz
1.5
pA/√Hz
INPUT CHARACTERISTICS (DIFFERENTIAL)
VOSD
IBIAS
CMRR
VICM
Input Offset Voltage
Differential Mode, VID =
0, VCM = 0
Input Offset Voltage Average
Temperature Drift
(5)
Input Bias Current
(6)
Input Bias Current Average
Temperature Drift
(5)
1
At extreme
temperatures
±4
mV
±6
1.6
0
−8
µV/°C
−16
μA
9.5
nA/°C
0.3
µA
Input Bias Current Difference
Difference in Bias Currents Between the
Two Inputs
Common-Mode Rejection Ratio
DC, VID = 0 V
80
dBc
Input Resistance
Differential
5
MΩ
Input Capacitance
Differential
1
pF
Input Common-Mode Range
CMRR > 53 dB
70
+3.1
+0.4
+3.2
+0.3
VCM PIN INPUT CHARACTERISTICS (COMMON-MODE FEEDBACK AMPLIFIER)
Input Offset Voltage
Common-Mode, VID = 0
1
At extreme
temperatures
18.6
Input Bias Current
(1)
(2)
(3)
(4)
(5)
(6)
6
VID = 0,
1-V Step on VCM Pin, Measure VOD
Input Resistance
VCM Pin to Ground
mV
±8
Input Offset Voltage Average
Temperature Drift
VCM CMRR
±5
70
µV/°C
3
μA
75
dB
25
kΩ
Electrical Table values apply only for factory testing conditions at the temperature indicated. Factory testing conditions result in very
limited self-heating of the device such that TJ = TA.
Limits are 100% production tested at 25°C. Limits over the operating temperature range are guaranteed through correlation using
Statistical Quality Control (SQC) methods.
Typical numbers are the most likely parametric norm.
Slew Rate is the average of the rising and falling edges.
Drift determined by dividing the change in parameter at temperature extremes by the total temperature change.
Negative input current implies current flowing out of the device.
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LMH6550
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Electrical Characteristics: 5 V(1) (continued)
Single-ended in differential out, TA = 25°C, AV = +1, VS = 5 V, VCM = 2.5 V, RF = RG = 365 Ω, RL = 500 Ω; unless specified.
PARAMETER
Common-Mode Gain
TEST CONDITIONS
MIN
(2)
ΔVO,CM/ΔVCM
TYP
(3)
MAX
(2)
UNIT
0.991
V/V
OUTPUT PERFORMANCE
VOUT
Output Voltage Swing
Peak to Peak, Differential,
VS = ±2.5 V, VCM = 0 V
2.4
IOUT
Linear Output Current
VOUT = 0-V Differential
±54
ISC
Output Short Circuit Current
Output Shorted to Ground
VIN = 3 V Single-Ended (7)
CMVR
Common-Mode Voltage Range
VID = 0, VCM Pin = 1.2 V and 3.8 V
Output Balance Error
ΔVOUT Common Mode /ΔVOUT
DIfferential, VOUT = 1 VPP Differential, f =
10 MHz
3.72
1.23
2.8
V
±70
mA
250
mA
3.8
1.2
V
−65
dB
MISCELLANEOUS PERFORMANCE
Enable Voltage Threshold
Pin 7
2.0
V
Disable Voltage Threshold
Pin 7
Enable Pin Current
VEN =0 V
(6)
-250
VEN =4 V
(6)
55
1.5
Enable/Disable Time
Open Loop Gain
DC, Differential
PSRR
Power Supply Rejection Ratio
DC, ΔVS = ±0.5 V
IS
Supply Current
RL = ∞
10
ns
70
dB
72
77
16.5
19
At extreme
temperatures
ISD
(7)
Disabled Supply Current
V
µA
dB
23.5
mA
26.5
1
1.2
mA
The maximum output current (IOUT) is determined by device power dissipation limitations.
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7.7 Typical Characteristics
(TA = 25°C, VS = ±5 V, RL = 500 Ω, RF = RG = 365 Ω; unless specified).
1
1
0
0
VS = 5V
-1
-2
VS = ±5V
GAIN (dB)
GAIN (dB)
-2
VS = 5V
-1
-3
-4
-5
VS = ±5V
-3
-4
-5
-6
-6
VOD = 0.5VPP
-7
-8
VOD = 1VPP
-7
AV = 1
AV = 1
-8
DIFFERENTIAL INPUT
SINGLE ENDED INPUT
-9
-9
1
10
100
1
1000
10
100
1000
FREQUENCY (MHz)
FREQUENCY (MHz)
Figure 1. Frequency Response vs Supply Voltage
Figure 2. Frequency Response
1
0
-1
VOD = 4.0VPP
-2
GAIN (dB)
NORMALIZED GAIN (dB)
1
0
-3
VOD = 0.5VPP
-4
-5
VOD = 2.0VPP
-6
Vs = ±5V
-7
AV = 1
-8
GAIN = 2
-1
-2
-3
GAIN = 4
-4
-5
GAIN = 6
-6
-7
VOUT = 0.5 VPP
SINGLE ENDED INPUT
-8
SINGLE ENDED INPUT
-9
-9
1
10
100
1
1000
10
100
FREQUENCY (MHz)
FREQUENCY (MHz)
Figure 4. Frequency Response vs Gain
Figure 3. Frequency Response vs VOUT
2
1
CL = 5.7 pF, ROUT = 40:
1000
70
VS = ±5V
60
-1
CL = 10 pF, ROUT = 30:
-2
CL = 22 pF, ROUT = 22:
-3
-4
SUGGESTED RO (:)
GAIN (dB)
0
CL = 47 pF, ROUT = 13:
-5
VOD = 210 mVPP
-6 A = 1
V
-7 LOAD = (CL || 1 k:) IN
SERIES WITH 2 ROUTS
-8
1
10
100
40
30
20
LOAD = 1 k: || CAP LOAD
10
VS = ±5V
0
1000
FREQUENCY (MHz)
1
10
100
CAPACITIVE LOAD (pF)
Figure 5. Frequency Response vs Capacitive Load
8
50
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Figure 6. Suggested ROUT vs Cap Load
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Typical Characteristics (continued)
(TA = 25°C, VS = ±5 V, RL = 500 Ω, RF = RG = 365 Ω; unless specified).
1.5
2.5
2
1
1.5
1
VOUT (V)
VOUT (V)
0.5
0
-0.5
VS = ±5
-1
RL = 500:
0.5
0
-0.5
-1
RL = 500:
-1.5
RF = 360:
SINGLE ENDED
INPUT
-2
RF = 360:
-1.5
-2.5
0
10 20 30 40 50 60 70 80 90 100
0
10 20 30 40 50 60 70 80 90 100
TIME (ns)
TIME (ns)
Figure 7. 2 VPP Pulse Response Single-Ended Input
Figure 8. Large Signal Pulse Response
-30
40
-40
20
HD3
DISTORTION (dBc)
COMMON MODE VOUT (mV)
30
10
0
-10
-20
-30
RL = 500:
-40
-60
-70
VS = 5V
-80
RL = 800:
HD2
RF = 360:
-50
-50
VOD = 2 VPP
-90
VOD = 4 VPP
VOCM = 2.5V
-100
-60
0
10 20 30 40 50 60 70 80 90 100
0
10
20
30
40
50
60
70
TIME (ns)
FREQUENCY (MHz)
Figure 9. Output Common-Mode Pulse Response
Figure 10. Distortion vs Frequency Single-Ended Input
4
-40
3.9
-50
3.8
MAXIMUM VOUT (V)
DISTORTION (dBc)
HD3
-60
-70
-80
HD2
-90
VS = ±5V
RL = 800:
3.6
3.5
3.4
3.3
3.2
VOD = 2 VPP
-100
3.7
3.1
VOCM = 0V
-110
VS = ±5V
AV = 2
RF = 730:
VIN = 3.88V SINGLE ENDED
3
0
10
20
30
40
50
60
70
0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100
FREQUENCY (MHz)
OUTPUT CURRENT (mA)
Figure 11. Distortion vs Frequency Single-Ended Input
Figure 12. Maximum VOUT vs IOUT
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Typical Characteristics (continued)
(TA = 25°C, VS = ±5 V, RL = 500 Ω, RF = RG = 365 Ω; unless specified).
100
-3
VS = ±5V
VS = ±5V
AV = 2
VIN = 0V
-3.2
RF = 730:
-3.3
VIN = 3.88V SINGLE ENDED
AV = 1
10
-3.4
|Z| (:)
MINIMUM VOUT (V)
-3.1
-3.5
1
-3.6
-3.7
0.1
-3.8
-3.9
0.01
-4
0.01
10 20 30 40 50 60 70 80 90 100
0
100
90
PSRR -
PSRR (dBc DIFFERENTIAL)
|Z| (:)
1000
Figure 14. Closed-Loop Output Impedance
VIN = 0V
AV = 1
1
0.1
80
70
PSRR +
60
50
40
30
20
10
0.01
1
0.1
10
100
VS = ±5V
RL = 500:
AV = 1
VIN = 0V
0
0.01
0.1
0.01
1000
10
1
100
1000
FREQUENCY (MHz)
FREQUENCY (MHz)
Figure 15. Closed-Loop Output Impedance
Figure 16. PSRR
100
85
90
80
PSRR -
80
75
70
CMRR (dB)
PSRR (dBc DIFFERENTIAL)
100
Figure 13. Minimum VOUT vs IOUT
VS = 5V
PSRR +
60
50
40
70
65
60
30
VS = 5V
55
20
RL = 500:
50
10
AV = 1
VIN = 2.5V
0
0.01
0.1
10
10
FREQUENCY (MHz)
100
10
1
0.1
OUTPUT CURRENT (mA)
45
1
10
100
1000
40
0.1
1
10
100
FREQUENCY (MHz)
FREQUENCY (MHz)
Figure 17. PSRR
Figure 18. CMRR
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Typical Characteristics (continued)
(TA = 25°C, VS = ±5 V, RL = 500 Ω, RF = RG = 365 Ω; unless specified).
-40
-30
RL = 500:
-35
-40
-45
-50
RF = 360:
VS = 5V
AV = 1
-55
IMD 3 (dBc)
BALANCE ERROR (dBc)
-25
VS = ±5V
-60
-65
-70
-75
VS = ±5V
-45
AV = 2 V/V
-50
RL = 200:
f = 40 MHz
-55
f = 20 MHz
-60
-65
-70
f = 5 MHz
-75
-80
-85
-90
-80
-85
1
10
100
0
1000
1
2
3
4
5
6
7
FREQUENCY (MHz)
DIFFERENTIAL VOUT (VPP)
Figure 19. Balance Error
Figure 20. Third-Order Intermodulation Products vs VOUT
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8 Detailed Description
8.1 Overview
The LMH6550 is a fully differential amplifier designed to provide low distortion amplification to wide bandwidth
differential signals. The LMH6550, though fully integrated for ultimate balance and distortion performance,
functionally provides three channels. Two of these channels are the V+ and V− signal path channels, which
function similarly to inverting mode operational amplifiers and are the primary signal paths. The third channel is
the common-mode feedback circuit. This is the circuit that sets the output common mode as well as driving the
V+ and V− outputs to be equal magnitude and opposite phase, even when only one of the two input channels is
driven. The common-mode feedback circuit allows single-ended to differential operation.
8.2 Functional Block Diagram
V+
+OUT
-IN
±
2.5 k
High-Aol +
Differential I/O
Amplifier ±
+IN
2.5 k
+
-OUT
V+
50 k
±
Vcm
Error
Amplifier
+
EN
Vcm
Buffer
50 k
V±
8.3 Feature Description
The LMH6550 combines a core differential I/O, high-gain block with an output common-mode sense that is
compared to a reference voltage and then fed back into the main amplifier block to control the average output to
that reference. The differential I/O block is a classic, high open-loop gain stage. The high-speed differential
outputs include an internal averaging resistor network to sense the output common-mode voltage. This voltage is
compared by a separate Vcm error amplifier to the voltage on the Vocm pin. If floated, this reference is at half
the total supply voltage across the device using two 50-kΩ resistors. This Vcm error amplifier transmits a
correction signal into the main amplifier to force the output average voltage to meet the target voltage on the
Vocm pin.
12
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8.4 Device Functional Modes
This wideband FDA requires external resistors for correct signal-path operation. When configured for the desired
input impedance and gain setting with these external resistors, the amplifier can be either on with the PD pin
asserted to a voltage greater than Vs– + 1.7 V, or turned off by asserting PD low. Disabling the amplifier shuts
off the quiescent current and stops correct amplifier operation. The signal path is still present for the source
signal through the external resistors. The Vocm control pin sets the output average voltage. Left open, Vocm
defaults to an internal midsupply value. Driving this high-impedance input with a voltage reference within its valid
range sets a target for the internal Vcm error amplifier.
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9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
The LMH6550 is a fully differential amplifier designed to provide low distortion amplification to wide bandwidth
differential signals. The LMH6550, though fully integrated for ultimate balance and distortion performance,
functionally provides three channels. Two of these channels are the V+ and V− signal path channels, which
function similarly to inverting mode operational amplifiers and are the primary signal paths. The third channel is
the common-mode feedback circuit. This is the circuit that sets the output common mode as well as driving the
V+ and V− outputs to be equal magnitude and opposite phase, even when only one of the two input channels is
driven. The common-mode feedback circuit allows single-ended to differential operation.
The LMH6550 is a voltage feedback amplifier with gain set by external resistors. Output common-mode voltage
is set by the VCM pin. This pin should be driven by a low impedance reference and should be bypassed to ground
with a 0.1-µF ceramic capacitor. Any signal coupling into the VCM will be passed along to the output and will
reduce the dynamic range of the amplifier.
The LMH6550 is equipped with a ENABLE pin to reduce power consumption when not in use. The ENABLE pin
floats to logic high. If this pin is not used it can be left floating. The amplifier output stage goes into a high
impedance state when the amplifier is disabled. The feedback and gain set resistors will then set the impedance
of the circuit. For this reason input to output isolation will be poor in the disabled state.
9.2 Typical Applications
9.2.1 Typical Fully Differential Application
The LMH6550 performs best when used with split supplies and in a fully differential configuration. See Figure 21
and Figure 22 for recommend circuits.
RF1
RO
RG1
+
VI
a
CL
VCM
RL
VO
RG2
RO
RF2
ENABLE
Figure 21. Typical Fully Differential Application Schematic
9.2.1.1 Design Requirements
Applications using fully differential amplifiers have several requirements. The main requirements are high linearity
and good signal amplitude. Linearity is accomplished by using well matched feedback and gain set resistors as
well as an appropriate supply voltage. The signal amplitude can be tailored by using an appropriate gain. In this
design the gain is set for a gain of 2 (RF=500/ RG=250) and the distortion criteria is better than -90 dBc at a
frequency of 5 Mhz. The supply voltages are set to +5 V and -5 V and the output common mode is 0 V. The
LMH6550 can be placed into shutdown to reduce power dissipation to 10 mW.
14
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Typical Applications (continued)
9.2.1.2 Detailed Design Procedure
The power supplies for this design are symmetrical ±5-V supplies (not shown for simplicity). The ADC input
common mode is 1 V which is within the optimum operating range for the LMH6550 when used on ±5-V split
supplies. The gain of this circuit is equal to RF/RG and due to the split supplies can be set to gains of 15 V/V or
less. Higher gains will result in values of RF that are too large for high speed operation.
9.2.1.2.1 Fully Differential Operation
The circuit shown in is a typical fully differential application as might be used to drive an ADC. In this circuit
closed loop gain, (AV) = VOUT/ VIN = RF/RG. For all the applications in this data sheet VIN is presumed to be the
voltage presented to the circuit by the signal source. For differential signals this will be the difference of the
signals on each input (which will be double the magnitude of each individual signal), while in single-ended inputs
it will just be the driven input signal.
The resistors RO help keep the amplifier stable when presented with a load CL as is typical in an analog to digital
converter (ADC). When fed with a differential signal, the LMH6550 provides excellent distortion, balance and
common-mode rejection provided the resistors RF, RG and RO are well matched and strict symmetry is observed
in board layout. With a DC CMRR of over 80 dB, the DC and low frequency CMRR of most circuits will be
dominated by the external resistors and board trace resistance. At higher frequencies board layout symmetry
becomes a factor as well. Precision resistors of at least 0.1% accuracy are recommended and careful board
layout will also be required.
500
50:
100:
TWISTED PAIR
250
+
2 VPP
a
VCM
250
2 VPP
50:
500
GAIN = 2
ENABLE
Figure 22. Fully Differential Cable Driver
With up to 15 VPP differential output voltage swing and 80 mA of linear drive current the LMH6550 makes an
excellent cable driver as shown in Figure 22. The LMH6550 is also suitable for driving differential cables from a
single-ended source.
The LMH6550 requires supply bypassing capacitors as shown in Figure 23 and Figure 24. The 0.01 µF and 0.1
µF capacitors should be leadless SMT ceramic capacitors and should be no more than 3 mm from the supply
pins. The SMT capacitors should be connected directly to a ground plane. Thin traces or small vias will reduce
the effectiveness of bypass capacitors. Also shown in both figures is a capacitor from the VCM pin to ground. The
VCM pin is a high impedance input to a buffer which sets the output common-mode voltage. Any noise on this
input is transferred directly to the output. Output common-mode noise will result in loss of dynamic range,
degraded CMRR, degraded Balance and higher distortion. The VCM pin should be bypassed even if the pin in not
used. There is an internal resistive divider on chip to set the output common-mode voltage to the mid point of the
supply pins. The impedance looking into this pin is approximately 25 kΩ. If a different output common-mode
voltage is desired drive this pin with a clean, accurate voltage reference.
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Typical Applications (continued)
+
V
V
+
0.01 PF 0.01 PF
10 PF
10 PF
0.01 PF
+
VCM
+
0.1 PF
VCM
-
0.1 PF
0.1 PF
0.01 PF
10 PF
V
-
Figure 23. Split Supply Bypassing Capacitors
Figure 24. Single Supply Bypassing Capacitors
9.2.1.2.2 Capacitive Drive
As noted in Driving Analog-to-Digital Converters, capacitive loads should be isolated from the amplifier output
with small valued resistors. This is particularly the case when the load has a resistive component that is 500 Ω or
higher. A typical ADC has capacitive components of around 10 pF and the resistive component could be 1000 Ω
or higher. If driving a transmission line, such as 50-Ω coaxial or 100-Ω twisted pair, using matching resistors will
be sufficient to isolate any subsequent capacitance. For other applications see Figure 6 and Figure 25 in Typical
Characteristics.
9.2.1.2.3 Application Curves
Many application circuits have capacitive loading. As shown in Figure 25, amplifier bandwidth is reduced with
increasing capacitive load, so parasitic capacitance should be strictly limited.
70
0.8
60
0.6
50
0.4
VOUT (V)
SUGGESTED RO (:)
To ensure stability, resistance should be added between the capacitive load and the amplifier output pins. The
value of the resistor is dependent on the amount of capacitive load as shown in Figure 26. This resistive value is
a suggestion. System testing will be required to determine the optimal value. Using a smaller resistor will retain
more system bandwidth at the expense of overshoot and ringing, while larger values of resistance will reduce
overshoot but will also reduce system bandwidth.
40
30
20
VS = 5V
RL = 500:
-0.6
VS = 5V
RF = 360:
-0.8
1
10
100
0
10 20 30 40 50 60 70 80 90 100
TIME (ns)
CAPACITIVE LOAD (pF)
Figure 25. Suggested ROUT vs Cap Load
16
0
-0.2
-0.4
LOAD = 1 k: || CAP LOAD
10
0
0.2
Figure 26. 1 VPP Pulse Response Single-Ended Input
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Typical Applications (continued)
9.2.2 Driving Analog-to-Digital Converters
Analog-to-digital converters (ADC) present challenging load conditions. They typically have high-impedance
inputs with large and often variable capacitive components. As well, there are usually current spikes associated
with switched capacitor or sample and hold circuits. Figure 27 shows a typical circuit for driving an ADC. The two
56-Ω resistors serve to isolate the capacitive loading of the ADC from the amplifier and ensure stability. In
addition, the resistors form part of a low pass filter which helps to provide anti alias and noise reduction
functions. The two 39-pF capacitors help to smooth the current spikes associated with the internal switching
circuits of the ADC and also are a key component in the low pass filtering of the ADC input. In the circuit of
Figure 27 the cutoff frequency of the filter is 1/ (2*π*56 Ω *(39 pF + 14 pF)) = 53 MHz (which is slightly less than
the sampling frequency). Note that the ADC input capacitance must be factored into the frequency response of
the input filter, and that being a differential input the effective input capacitance is double. Also as shown in
Figure 27 the input capacitance to many ADCs is variable based on the clock cycle. See the data sheet for your
particular ADC for details.
The amplifier and ADC should be located as closely together as possible. Both devices require that the filter
components be in close proximity to them. The amplifier needs to have minimal parasitic loading on the output
traces and the ADC is sensitive to high frequency noise that may couple in on its input lines. Some high
performance ADCs have an input stage that has a bandwidth of several times its sample rate. The sampling
process results in all input signals presented to the input stage mixing down into the Nyquist range (DC to Fs/2).
See AN-236 for more details on the subsampling process and the requirements this imposes on the filtering
necessary in your system.
RF1
56
RG1
ADC12LO66
39 pF
+
VI
a
VCM
-
7 - 8 pF
39 pF
RG2
56
VREF
RF2
ENABLE
1V LOW IMPEDANCE
VOLTAGE REFERENCE
Figure 27. Driving an ADC
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Typical Applications (continued)
9.2.3 Single-Ended Input to Differential Output
The LMH6550 provides excellent performance as an active balun transformer. Figure 28 shows a typical
application where an LMH6550 is used to produce a differential signal from a single-ended source.
In single-ended input operation the output common-mode voltage is set by the VCM pin as in fully differential
mode. Also, in this mode the common-mode feedback circuit must recreate the signal that is not present on the
unused differential input pin. Figure 19 is the measurement of the effectiveness of this process. The commonmode feedback circuit is responsible for ensuring balanced output with a single-ended input. Balance error is
defined as the amount of input signal that couples into the output common mode. It is measured as a the
undesired output common-mode swing divided by the signal on the input. Balance error can be caused by either
a channel to channel gain error, or phase error. Either condition will produce a common-mode shift. Figure 19
measures the balance error with a single-ended input as that is the most demanding mode of operation for the
amplifier.
Supply and VCM pin bypassing are also critical in this mode of operation. See the above section on for bypassing
recommendations and also see Figure 23 and Figure 24 for recommended supply bypassing configurations.
RF
AV, RIN
RS
VS
a
+
V
RG
VI
VI1
-
VCM
RT
RM
IN-
VO
+
-
VI2
RG
RO
VO1
+
VO2
ADC
IN+
RO
-
+-
V
RF
Definitions :
Conditions :
R S R T || RIN
RM
RT || RS
1
RG
R G RF
2
R G RM
R G RM RF
2(1 1 ) R F
for R M R G
#
1 2
RG
Av
VO
VI
RIN
2R G RM (1 2 )
1 2
RG (1
2
)
1
1 2
#
2R G (1 A v )
for RM RG
2 Av
VO1 VO2
(by design)
2
VOCM
VCM
VICM
VI1 VI2
2
VOCM . 2 #
VOCM
1 Av
for R M R G
Figure 28. Single-Ended Input to Differential Output Schematic
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Typical Applications (continued)
9.2.4 Single Supply Operation
The input stage of the LMH6550 has a built in offset of 0.7 V towards the lower supply to accommodate single
supply operation with single-ended inputs. As shown in Figure 28, the input common-mode voltage is less than
the output common voltage. It is set by current flowing through the feedback network from the device output. The
input common-mode range of 0.4 V to 3.2 V places constraints on gain settings. Possible solutions to this
limitation include AC coupling the input signal, using split power supplies and limiting stage gain. AC coupling
with single supply is shown in Figure 29.
In Figure 28 closed loop gain = VO / VI ≊ RF / RG, where VI =VS / 2, as long as RM
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