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LMH6703
SNOSAF2E – FEBRUARY 2005 – REVISED MAY 2016
LMH6703 1.2 GHz, Low Distortion Op Amp with Shutdown
1 Features
•
1
•
•
•
•
•
•
3 Description
The LMH™6703 is a very wideband, DC coupled
monolithic operational amplifier designed specifically
for ultra high resolution video systems as well as wide
dynamic range systems requiring exceptional signal
fidelity.
Benefitting
from
current
feedback
architecture, the LMH6703 offers a practical gain
range of ±1 to ±10 while providing stable operation
without external compensation, even at unity gain. At
a gain of 2, the LMH6703 supports ultra high
resolution video systems with a 750-MHz, 2 VPP, −3dB Bandwidth. With 12-bit distortion levels through 10
MHz (RL = 100 Ω), and a 2.3-nV/√Hz input referred
noise, the LMH6703 is the ideal driver or buffer for
high speed flash A/D and D/A converters. Wide
dynamic range systems such as radar and
communication receivers requiring a wideband
amplifier offering exceptional signal purity will find the
LMH6703 low input referred noise and low harmonic
distortion an attractive solution.
−3-dB bandwidth (VOUT = 0.5 VPP, AV = 2)
1.2 GHz
2nd/3rd Harmonics (20 MHz, SOT-23)
−69/−90 dBc
Low Noise: 2.3 nV/√Hz
Fast Slew Rate: 4500 V/μs
Supply Current: 11 mA
Output Current: 90 mA
Low Differential Gain and Phase 0.01%/0.02°
2 Applications
•
•
•
•
•
•
•
•
RGB Video Driver
High Resolution Projectors
Flash A/D Driver
D/A Transimpedance Buffer
Wide Dynamic Range IF Amp
Radar/Communication Receivers
DDS Post-Amps
Line Driver
Device Information(1)
PART NUMBER
LMH6703
PACKAGE
BODY SIZE (NOM)
SOIC (8)
4.90 mm × 3.91 mm
SOT-23 (6)
2.90 mm × 1.60 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Harmonic Distortion vs Frequency
-50
HARMONIC DISTORTION (dBc)
VOUT = 2 VPP
-60
2ND, SOT23-6
-70
2ND, SOIC
-80
-90
-100
-110
3RD, SOT23-6
-120
0.1
1
3RD, SOIC
10
100
FREQUENCY (MHz)
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
LMH6703
SNOSAF2E – FEBRUARY 2005 – REVISED MAY 2016
www.ti.com
Table of Contents
1
2
3
4
5
6
7
8
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
4
6.1
6.2
6.3
6.4
6.5
4
4
4
4
5
Absolute Maximum Ratings ......................................
ESD Ratings ............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics ..........................................
Typical Characteristics.......................................... 7
Detailed Description ............................................ 12
8.1 Overview ................................................................. 12
8.2 Feature Description................................................. 12
8.3 Device Functional Modes........................................ 12
9
Application and Implementation ........................ 15
9.1 Typical Application ................................................. 15
10 Power Supply Recommendations ..................... 17
11 Layout................................................................... 17
11.1 Layout Guidelines ................................................. 17
11.2 Layout Example .................................................... 18
12 Device and Documentation Support ................. 19
12.1
12.2
12.3
12.4
12.5
Documentation Support ........................................
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
19
19
19
19
19
13 Mechanical, Packaging, and Orderable
Information ........................................................... 19
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision D (March 2013) to Revision E
Page
•
Added Pin Functions table, ESD Ratings table, Thermal Information table, Detailed Description section, Application
and Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation
Support section, and Mechanical, Packaging, and Orderable Information section................................................................ 1
•
Updated maximum value of Input Bias Current (non-inverting) from ±20 to –20 in Electrical Characteristics ...................... 5
•
Updated boldface maximum value (temperature extreme) of Input Bias Current (non-inverting) from ±23 to –23 in
Electrical Characteristics ........................................................................................................................................................ 5
Changes from Revision C (March 2013) to Revision D
•
2
Page
Changed layout of National Data Sheet to TI format ........................................................................................................... 14
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5 Pin Configuration and Functions
D Package
8-Pin SOIC
Top View
N/C
1
D Package
6-Pin SOT-23
Top View
8
SD
-IN
2
7
-
6
1
OUTPUT
+IN
6
+
+
V
-
2
-
4
5
SD
OUTPUT
+
V
+
V
5
3
V
N/C
+IN
-
4
3
-IN
Pin Functions
PIN
NAME
NO.
I/O
DESCRIPTION
D
DBV
- IN
2
4
I
Inverting input voltage
+ IN
3
3
I
Non-inverting input voltage
N/C
1, 5
—
—
No connection
OUT
6
1
O
Output
V-
4
2
I
Negative supply
V+
7
6
I
Positive supply
SD
8
5
I
Shutdown (active low)
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
MIN
VS
IOUT
See
MAX
UNIT
±6.75
V
(2)
V−
Common mode input voltage
Maximum junction temperature
−65
Storage temperature
Soldering Information
(1)
(2)
V+
V
150
°C
150
°C
Infrared or convection (20 sec.)
235
Wave soldering (10 sec.)
260
°C
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
The maximum output current (IOUT) is determined by device power dissipation limitations.
6.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001
Electrostatic discharge
(1)
±2000
Machine model (MM), per JEDEC specification JESD22-C101, all pins (2)
±200
UNIT
V
Human body model: 1.5 kΩ in series with 100 pF. JEDEC document JEP155 states that 2000-V HBM allows safe manufacturing with a
standard ESD control process. Manufacturing with less than 2000-V HBM is possible with the necessary precautions. Pins listed as
±2000 V may actually have higher performance.
Machine model: 0 Ω in series with 200 pF. JEDEC document JEP157 states that 200-V MM allows safe manufacturing with a standard
ESD control process. Manufacturing with less than 200-V MM is possible with the necessary precautions. Pins listed as ±200 V may
actually have higher performance.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted) (1)
MIN
Operating temperature
Supply voltage
(1)
NOM
MAX
UNIT
–40
85
°C
±4
±6
V
Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Recommended Operating Conditions indicate
conditions for which the device is intended to be functional, but specific performance is not ensured. For ensured specifications, see
Electrical Characteristics .
6.4 Thermal Information
LMH6703
THERMAL METRIC (1)
DBV (SOT-23)
D (SOIC)
UNIT
6 PINS
8 PINS
RθJA
Junction-to-ambient thermal resistance
182
133
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
139
79
°C/W
RθJB
Junction-to-board thermal resistance
40
73
°C/W
ψJT
Junction-to-top characterization parameter
28
28
°C/W
ψJB
Junction-to-board characterization parameter
40
73
°C/W
(1)
4
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report (SPRA953).
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6.5 Electrical Characteristics
at TJ = 25°C, AV = 2, VS = ±5 V, RL = 100 Ω, RF = 560 Ω, SD = Floating (unless otherwise noted) (1)
Boldface limits apply at the temperature extremes.
PARAMETER
CONDITIONS
MIN
(2)
TYP
(3)
MAX
(2)
UNIT
FREQUENCY DOMAIN PERFORMANCE
SSBW
–3-dB bandwidth
LSBW
VOUT = 0.5 VPP, AV = +1
1800
VOUT = 0.5 VPP, AV = +2
1200
VOUT = 2 VPP
750
VOUT = 4 VPP
500
VOUT = 0.5 VPP
150
VOUT = 2 VPP
150
MHz
GF
0.1-dB gain flatness
MHz
DG
Differential gain
RL = 150 Ω, 4.43 MHz
0.01%
DP
Differential phase
RL = 150 Ω, 4.43 MHz
0.02
deg
2-V step, 10% to 90%
0.5
ns
6-V step, 10% to 90%
1.05
ns
2-V step, 10% to 90%
0.5
ns
6-V step, 10% to 90%
1.05
ns
TIME DOMAIN RESPONSE
tr
Rise time
tf
Fall time
SR
Slew rate
ts
Settling time
4-V step, 10% to 90%
(4)
4200
6-V step, 10% to 90%
(4)
4500
2-V step, VOUT within 0.1%
V/µs
10
ns
DISTORTION AND NOISE RESPONSE
HD2
HD3
2nd harmonic distortion
3rd harmonic distortion
2 VPP, 5 MHz, SOT-23-6
−87
2 VPP, 20 MHz, SOT-23-6
−69
2 VPP, 50 MHz, SOT-23-6
−60
2 VPP, 5 MHz, SOT-23-6
−100
2 VPP, 20 MHz, SOT-23-6
−90
2 VPP, 50 MHz, SOT-23-6
−70
dBc
dBc
IMD
3rd order intermodulation products
50 MHz, PO = 5 dBm/ tone
−80
dBc
en
Input referred voltage noise
>1 MHz
2.3
nV/√Hz
Input referred noise current
Inverting Pin
>1 MHz
Input referred noise current
Non-Inverting Pin
>1 MHz
in
pA/√Hz
18.5
pA/√Hz
3
u
VOS
Input offset voltage
TCVOS
Input offset voltage average drift
±1.5
(5)
22
Non-Inverting
IB
Input bias current
TCIB
(1)
(2)
(3)
(4)
(5)
(6)
Input bias current average drift
Inverting
(6)
(5)
(5)
−7
−2
±35
±44
+30
−70
mV
µV/°C
–20
–23
(6)
Non-Inverting
Inverting
±7
±9
µA
nA/°C
Electrical Characteristics values apply only for factory testing conditions at the temperature indicated. Factory testing conditions result in
very limited self-heating of the device such that TJ = TA. Parametric performance is indicated in the electrical tables under conditions of
internal self-heating where TJ > TA.
Limits are 100% production tested at 25°C. Limits over the operating temperature range are specified through correlation using
Statistical Quality Control (SQC) methods.
Typical numbers are the most likely parametric norm.
Slew rate is the average of the rising and falling edges.
Drift determined by dividing the change in parameter at temperature extremes by the total temperature change.
Negative input current implies current flowing out of the device.
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Electrical Characteristics (continued)
at TJ = 25°C, AV = 2, VS = ±5 V, RL = 100 Ω, RF = 560 Ω, SD = Floating (unless otherwise noted)(1)
Boldface limits apply at the temperature extremes.
PARAMETER
CONDITIONS
RL = ∞
MIN
(2)
TYP
(3)
±3.3
±3.45
±3.2
±3.14
±3.4
MAX
(2)
UNIT
VO
Output voltage range
RL = 100 Ω
PSRR
Power supply rejection ratio
VS = ± 4.0 V to ±6.0 V
48
46
52
dB
CMRR
Common mode rejection ratio
VCM = −1.0 V to +1.0 V
45
44
47
dB
Supply current (enabled)
SD = 2 V, RL = ∞
11
12.5
15.0
mA
Supply current (disabled)
SD = 0.8 V, RL = ∞
0.2
0.900
0.935
mA
Output Impedance of Input Buffer
30
Ω
0.8
pF
0.05
Ω
±90
mA
ns
IS
V
MISCELLANEOUS PERFORMANCE
RIN+
Non-inverting input resistance
RIN−
Inverting input resistance
1
CIN
Non-inverting input capacitance
RO
Output resistance
Closed Loop
CMVR
Input common mode voltage range
CMRR ≥ 40 dB
±1.9
IO
Linear output current
VIN = 0 V, VOUT ≤ ±80 mV
±55
MΩ
V
ENABLE/DISABLE PERFORMANCE (DISABLED LOW)
TON
Enable time
10
TOFF
Disable time
10
ns
Output glitch
50
mVPP
VIH
Enable voltage
SD ≥ VIH
VIL
Disable voltage
SD ≤ VIL
IIH
Disable pin bias current, high
SD = V+ (6)
IIL
Disable pin bias current, low
SD = 0 V
Disabled output leakage current
VOUT = ±1.8 V
IOZ
6
2.0
(6)
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−50
V
0.8
V
−7
±70
µA
−240
−400
µA
0.07
±25
±40
µA
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7 Typical Characteristics
at AV = 2, RL = 100 Ω, VS = ±5 V, RF = 560 Ω, TA = 25°C, SOT-23-6 (unless otherwise noted)
4
4
VOUT = 0.5 VPP
2
1
0
-1
AV = +10, RF = 300:
-2
-3
AV = +5, RF = 390:
-4
AV = +2
3
AV = +2, RF = 560:
NORMALIZED GAIN (dB)
NORMALIZED GAIN (dB)
3
-5
RF = 560:
2
VOUT = 0.5 VPP
1
0
-1
VOUT = 4 VPP
-2
-3
VOUT = 2 VPP
-4
-5
-6
-6
1
10
100
1
1000
10
FREQUENCY (MHz)
(SOT-23)
4
3
3
VOUT = 0.5 VPP
0
VOUT = 4 VPP
-1
-2
VOUT = 2 VPP
-3
-4
NORMALIZED GAIN (dB)
NORMALIZED GAIN (dB)
Figure 2. Large Signal Frequency Response
4
1
AV = +10
-5
AV = -10, RF = 390:
2
1
AV = -5, RF = 470:
0
-1
AV = -1, RF = 560:
-2
-3
-4
-5
RF = 300:
-6
VOUT = 0.5 VPP
-6
1
10
100
1
1000
10
FREQUENCY (MHz)
Figure 4. Small Signal Inverting Frequency Response
4
4
VOUT = 0.5 VPP
AV = +2, RF = 390:
1
0
-1
-2
AV = +10, RF = 180:
-3
-4
AV = +5, RF = 200:
-5
AV = +2
3
NORMALIZED GAIN (dB)
2
1000
(SOT-23)
Figure 3. Large Signal Frequency Response
3
100
FREQUENCY (MHz)
(SOT-23)
NORMALIZED GAIN (dB)
1000
(SOT-23)
Figure 1. Small Signal Non-Inverting Frequency Response
2
100
FREQUENCY (MHz)
RF = 390:
2
VOUT = 0.5 VPP
1
0
-1
-2
VOUT = 4 VPP
-3
-4
VOUT = 2 VPP
-5
-6
-6
1
10
100
1
1000
FREQUENCY (MHz)
10
100
1000
FREQUENCY (MHz)
(SOIC)
(SOIC)
Figure 5. Small Signal Non-Inverting Frequency Response
Figure 6. Large Signal Frequency Response
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Typical Characteristics (continued)
at AV = 2, RL = 100 Ω, VS = ±5 V, RF = 560 Ω, TA = 25°C, SOT-23-6 (unless otherwise noted)
0.5
4
0.4
2
VOUT = 0.5 VPP, 2 VPP, and 4 VPP
0.3
1
0.2
0
0.1
VOUT (V)
NORMALIZED GAIN (dB)
3
-1
-2
0
-0.1
-3
-0.2
-4
AV = +10
-5
-0.3
RF = 180:
-0.4
-6
1
10
100
1000
-0.5
TIME (2 ns/DIV)
FREQUENCY (MHz)
(SOIC)
Figure 7. Large Signal Frequency Response
Figure 8. Small Signal Pulse Response
5
-50
VOUT = 2 VPP
HARMONIC DISTORTION (dBc)
4
3
VOUT (V)
2
1
0
-1
-2
-3
-60
2ND, SOT23-6
-70
2ND, SOIC
-80
-90
-100
-110
-120
0.1
-5
1
TIME (2 ns/DIV)
10
100
FREQUENCY (MHz)
Figure 10. Harmonic Distortion vs Frequency
Figure 9. Large Signal Pulse Response
-45
-50
f = 10 MHz
f = 10 MHz
RL = 100:
-55
HARMONIC DISTORTION (dBc)
HARMONIC DISTORTION (dBc)
3RD, SOIC
3RD, SOT23-6
-4
2ND
-65
-75
-85
-95
3
RD
-105
VOUT = 2 VPP
-60
2ND
-70
-80
-90
-100
3RD
-115
-110
0
1
2
3
4
5
6
7
OUTPUT VOLTAGE PEAK TO PEAK
200
400
600
800
1000
LOAD RESISTANCE (:)
Figure 11. Harmonic Distortion vs Output Voltage
8
0
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Figure 12. Harmonic Distortion vs. Load
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Typical Characteristics (continued)
at AV = 2, RL = 100 Ω, VS = ±5 V, RF = 560 Ω, TA = 25°C, SOT-23-6 (unless otherwise noted)
0.03
-60
RL = 100:
-65
RLOAD = 150:
0.01
-70
50 MHz
-75
0
-80
-0.01
DG (%)
IMD3 (dBc)
RLOAD = 75:
0.02
-85
-90
-0.02
RLOAD = 37.5
-0.03
10 MHz
-95
-0.04
-100
-0.05
-105
-0.06
RLOAD = 50:
f = 4.43 MHz
-0.07
-1.5
-110
-5
-2.5
0
2.5
5
7.5
-1
-0.5
Figure 13. 2-Tone 3rd Order Intermodulation
0.5
1
1.5
Figure 14. Differential Gain
1000
0.1
NOISE VOLTAGE (nV/
RLOAD = 150:
0.04
0.02
0
-0.02
-0.04
RLOAD = 37.5:
-0.06
-0.08
RLOAD = 50:
-0.1
-1.5
-1
-0.5
Hz)
0.06
NOISE CURRENT (pA/
Hz)
RLOAD = 75:
0.08
DP (°)
0
VOUT (VDC)
TEST TONE POWER INTO 100: LOAD (dBm)
100
INVERTING CURRENT
10
NON-INVERTING
CURRENT
VOLTAGE
f = 4.43 MHz
0
0.5
1
1
1.5
100
1k
10k
VOUT (VDC)
100k
1M
10M
FREQUENCY (Hz)
Figure 15. Differential Phase
Figure 16. Noise
60
70
PSRR+
60
50
PSRR (dB)
CMRR (dB)
50
40
PSRR40
30
20
30
10
0
20
10k
100k
1M
10M
100
1G
10k
100k
1M
10M
100M
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 17. CMRR vs Frequency
Figure 18. PSRR vs Frequency
1G
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Typical Characteristics (continued)
at AV = 2, RL = 100 Ω, VS = ±5 V, RF = 560 Ω, TA = 25°C, SOT-23-6 (unless otherwise noted)
50 mV
VO
VO
1V
0V
-1V
-50 mV
3V
2V
1V
0V
3V
2V
1V
0V
SD
SD
0V
TIME (20 ns/DIV)
TIME (20 ns/DIV)
Figure 20. Disable Output Glitch
Figure 19. Disable Timing
70
-4
-5
50
40
IBN (PA)
RECOMMENDED RISO (:)
60
30
-6
-7
20
-8
10
-9
-50
0
0
25
50
100
75
125
150
-25
CAPACITIVE LOAD (pF)
0
25
50
75
100
125
TEMPERATURE (°C)
(See Application and Implementation)
Figure 22. Non-Inverting Input Bias vs Temperature
0
5
-4
4
-8
3
VOS (mV)
IBI (PA)
Figure 21. RISO vs CLOAD
-12
-16
-20
-50
10
2
1
-25
0
25
50
75
100
125
0
-50
-25
0
25
50
75
100
125
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 23. Inverting Input Bias vs Temperature
Figure 24. Input Offset vs Temperature
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Typical Characteristics (continued)
at AV = 2, RL = 100 Ω, VS = ±5 V, RF = 560 Ω, TA = 25°C, SOT-23-6 (unless otherwise noted)
4
14
3.75
3.5
13
12
VO (V)
IS (mA)
3.25
3
|
-3
11
-3.25
-3.5
10
-3.75
9
-50
-25
0
25
50
75
100
125
TEMPERATURE (°C)
-4
-50
-25
0
25
50
75
100
125
TEMPERATURE (°C)
Figure 25. Supply Current vs Temperature
Figure 26. Voltage Swing vs Temperature
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8 Detailed Description
8.1 Overview
The LMH6703 has been optimized for exceptionally low harmonic distortion while driving very demanding
resistive or capacitive loads. Generally, when used as the input amplifier to very high speed flash ADCs, the
distortions introduced by the converter will dominate over the low LMH6703 distortions shown in Typical
Characteristics.
8.2 Feature Description
The LMH6703 is a high speed current feedback amplifier, optimized for excellent bandwidth, gain flatness, and
low distortion. The loop gain for a current feedback op amp, and hence the frequency response, is predominantly
set by the feedback resistor value. The LMH6703 in the SOT-23-6 package is optimized for use with a 560-Ω
feedback resistor. The LMH6703 in the SOIC package is optimized for use with a 390-Ω feedback resistor. Using
lower values can lead to excessive ringing in the pulse response while a higher value will limit the bandwidth.
Application Note OA-13 (SNOA366) discusses this in detail along with the occasions where a different RF might
be advantageous.
8.3 Device Functional Modes
8.3.1 Feedback Resistor Selection
One of the key benefits of a current feedback operational amplifier is the ability to maintain optimum frequency
response independent of gain by using appropriate values for the feedback resistor (RF). The Electrical
Characteristics and Typical Characteristics plots specify an RF of 560 Ω (390 Ω for the SOIC package), a gain of
2 V/V, and ±5-V power supplies (unless otherwise specified). Generally, lowering RF from it’s recommended
value will peak the frequency response and extend the bandwidth while increasing the value of RF will cause the
frequency response to roll off faster. Reducing the value of RF too far below it’s recommended value will cause
overshoot, ringing and, eventually, oscillation.
800
RECOMMENDED RF (:)
700
INVERTING (SOT23-6)
600
NON
-INVE
RTING
500
( SO T 2
3-6)
400
INVERT
ING
300
(SOIC)
200
NON-INVERTING (SOIC)
100
1
2
3
4
5
6
7
8
9
10
GAIN (V/V)
Figure 27. Recommended RF vs. Gain
Since a current feedback amplifier is dependant on the value of RF to provide frequency compensation and since
the value of RF can be used to optimize the frequency response, different packages use different RF values. As
shown in Figure 27, the SOT-23-6 and the SOIC package use different values for the feedback resistor, RF.
Since each application is slightly different, it is worth some experimentation to find the optimal RF for a given
circuit. In general, a value of RF that produces ≈0.1 dB of peaking is the best compromise between stability and
maximum bandwidth. Note that it is not possible to use a current feedback amplifier with the output shorted
directly to the inverting input. The buffer configuration of the LMH6703 requires a 560 Ω (390 Ω for SOIC
package) feedback resistor for stable operation.
12
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Device Functional Modes (continued)
The LMH6703 was optimized for high speed operation. As shown in Figure 27, the suggested value for RF
decreases for higher gains. Due to the output impedance of the input buffer, there is a practical limit for how
small RF can go, based on the lowest practical value of RG. This limitation applies to both inverting and non
inverting configurations. For the LMH6703 the input resistance of the inverting input is approximately 30Ω and
20Ω is a practical (but not hard and fast) lower limit for RG. The LMH6703 begins to operate in a gain bandwidth
limited fashion in the region when RG is nearly equal to the input buffer impedance. Note that the amplifier will
operate with RG values well below 20 Ω, however results may be substantially different than predicted from ideal
models. In particular the voltage potential between the Inverting and Non-Inverting inputs cannot be expected to
remain small.
Inverting gain applications that require impedance matched inputs may limit gain flexibility somewhat (especially
if maximum bandwidth is required). The impedance seen by the source is RG || RT (RT is optional). The value of
RG is RF /Gain. Thus for a SOT-23 in a gain of —5V/V, an RF of 460 Ω is optimum and RG is 92 Ω. Without a
termination resistor, RT, the input impedance would equal RG, 92 Ω. Using an RT of 109Ω will set the input
resistance to match a 50-Ω source. Note that source impedances greater then RG cannot be matched in the
inverting configuration.
For more information see Application Note OA-13 (SNOA366) which describes the relationship between RF and
closed-loop frequency response for current feedback operational amplifiers. The value for the inverting input
impedance for the LMH6703 is approximately 30 Ω. The LMH6703 is designed for optimum performance at gains
of 1 to 10 V/V and −1 to −9 V/V. Higher gain configurations are still useful, however, the bandwidth will fall as
gain is increased, much like a typical voltage feedback amplifier.
The LMH6703 data sheet shows both SOT-23-6 and SOIC data in the Electrical Characteristic section to aid in
selecting the right package. The Typical Characteristics section shows SOT-23-6 package plots only.
8.3.2 DC Accuracy and Noise
Example below shows the output offset computation equation for the non-inverting configuration (see Figure 29)
using the typical bias current and offset specifications for AV = 2:
Output Offset : VO = (IBN × RIN ± VOS) (1 + RF/RG) ± IBI × RF
Where RIN is the equivalent input impedance on the non-inverting input.
Example computation for AV = 2, RF = 560 Ω, RIN = 25 Ω:
VO = (7 μA × 25 Ω ± 1.5 mV) (1 + 560/560) ± 2 μA × 560≈ −3.7 mV to 4.5 mV
A good design, however, should include a worst case calculation using Min/Max numbers in the data sheet
tables, in order to ensure "worst case" operation.
Further improvement in the output offset voltage and drift is possible using the composite amplifiers described in
Application Note OA-07 (SNOA365). The two input bias currents are physically unrelated in both magnitude and
polarity for the current feedback topology. It is not possible, therefore, to cancel their effects by matching the
source impedance for the two inputs (as is commonly done for matched input bias current devices).
The total output noise is computed in a similar fashion to the output offset voltage. Using the input noise voltage
and the two input noise currents, the output noise is developed through the same gain equations for each term
but combined as the square root of the sum of squared contributing elements. See Application Note OA-12
(SNOA375) for a full discussion of noise calculations for current feedback amplifiers.
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Device Functional Modes (continued)
8.3.3 Enable/Disable
PIN 6
+
V
20 k:
SUPPLY
MID-POINT
BIAS CIRCUITRY
20 k: PULL-UP
RESISTOR
PIN 5
+
V -V
2
Q2
-
Q1
SD
20 k:
I TAIL
PIN 2
-
V
NOTE: PINS 2, 5, 6 ARE EXTERNAL
Figure 28. SD Pin Simplified Schematic
(SOT-23 Pinout Shown)
For 5-V supplies only, the LMH6703 has a TTL logic compatible disable function. Apply a logic low (< 0.8 V) to
the SD pin and the LMH6703 is disabled. Apply a logic high (> 2.0 V), or let the pin float and the LMH6703 is
enabled. Voltage, not current, at the Shutdown pin (SD) determines the enable/disable state. Care must be
exercised to prevent the shutdown pin voltage from going more than 0.8 V below the midpoint of the supply
voltages (0V with split supplies, V+/2 with single supply biasing). Doing so could cause transistor Q1 to Zener
resulting in damage to the disable circuit (See Figure 28). The core amplifier is unaffected by this, but the
shutdown operation could become permanently slower as a result.
Disabled, the LMH6703 inputs and output become high impedances. While disabled the LMH6703 quiescent
current is approximately 200 µA. Because of the pull up resistor on the shutdown circuit, the ICC and IEE currents
(positive and negative supply currents respectively) are not balanced in the disabled state. The positive supply
current (ICC) is approximately 300 µA while the negative supply current (IEE) is only 200 µA. The remaining IEE
current of 100 µA flows through the shutdown pin.
The disable function can be used to create analog switches or multiplexers. Implement a single analog switch
with one LMH6703 positioned between an input and output. Create an analog multiplexer with several
LMH6703s and tie the outputs together.
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9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Typical Application
+5V
6.8 PF
AV = 1 +RF/RG = VOUT/VIN
0.1 PF
VIN
3
CSS
0.01 PF
RIN
7 CPOS
+
VOUT
6
LMH6703
2
-
4 CNEG
RF
0.1 PF
RG
6.8 PF
-5V
Figure 29. Recommended Non-Inverting Gain Circuit
(SOIC Pinout Shown)
+5V
6.8 PF
RF
0.1 PF
+
CSS
0.01 PF
=
VOUT
VIN
VOUT
6
LMH6703
-
2
VIN
RG
7 CPOS
3
25:
AV =
4 CNEG
RG
0.1 PF
RT
6.8 PF
-5V
RF
SELECT RT TO
YIELD DESIRED
RIN = RT||RG
Figure 30. Recommended Inverting Gain Circuit
(SOIC Pinout Shown)
9.1.1 Capacitive Load Drive
X1
+
VIN
RIN
51:
RG
560:
-
+
-
RISO
51:
CL
10 pF
RL
1 k:
RF
560:
Figure 31. Decoupling Capacitive Loads
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Typical Application (continued)
Capacitive output loading applications will benefit from the use of a series output resistor RISO. Figure 31 shows
the use of a series output resistor, RISO, to stabilize the amplifier output under capacitive loading. Capacitive
loads from 5 to 120 pF are the most critical, causing ringing, frequency response peaking and possible
oscillation. Figure 21 gives a recommended value for selecting a series output resistor for mitigating capacitive
loads. The values suggested in the charts are selected for 0.5 dB or less of peaking in the frequency response.
This produces a good compromise between settling time and bandwidth. For applications where maximum
frequency response is needed and some peaking is tolerable, the value of RISO can be reduced slightly from the
recommended values.
9.1.2 Video Performance
6.8 PF
C2
0.01 PF
+5V
C1
RIN
75:
X1
VIN
+
+
VOUT
RG
560:
ROUT
75:
-
RF
560:
0.01 PF
-5V
C3
6.8 PF
C4
Figure 32. Typical Video Application
The LMH6703 has been designed to provide excellent performance with production quality video signals in a
wide variety of formats such as HDTV and High Resolution VGA. NTSC and PAL performance is nearly flawless
with DG of 0.01% and DP of 0.02°. Best performance will be obtained with back terminated loads. The back
termination reduces reflections from the transmission line and effectively masks transmission line and other
parasitic capacitance from the amplifier output stage. Figure 32 shows a typical configuration for driving 75Ω
cable. The amplifier is configured for a gain of two compensating for the 6 dB loss due to ROUT.
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10 Power Supply Recommendations
The LMH6703 can operate off a single supply or with dual supplies as long as the input CM voltage range
(CMIR) has the required headroom to either supply rail. Supplies should be decoupled with low inductance, often
ceramic, capacitors to ground less than 0.5 inches from the device pins. The use of ground plane is
recommended, and as in most high speed devices, it is advisable to remove ground plane close to device
sensitive pins such as the inputs.
11 Layout
11.1 Layout Guidelines
Whenever questions about layout arise, use the evaluation board (see Table 1) as a guide. The LMH730216 is
the evaluation board for SOT-23-6 samples and the LMH730227 is the evaluation board for SOIC samples.
To reduce parasitic capacitances, ground and power planes should be removed near the input and output pins.
Components in the feedback path should be placed as close to the device as possible to minimize parasitic
capacitance. For long signal paths controlled impedance lines should be used, along with impedance matching
elements at both ends.
Bypass capacitors should be placed as close to the device as possible. Bypass capacitors from each voltage rail
to ground are applied in pairs. The larger electrolytic bypass capacitors can be located further from the device,
the smaller ceramic bypass capacitors should be placed as close to the device as possible. In Figure 29 and
Figure 30, CSS is optional, but is recommended for best second order harmonic distortion.
Generally, a good high frequency layout will keep power supply and ground traces away from the inverting input
and output pins. Parasitic capacitances on these nodes to ground will cause frequency response peaking and
possible circuit oscillations. See Frequent Faux Pas in Applying Wideband Current Feedback Amplifiers,
Application Note OA-15 (SNOA367). The evaluation board(s) is a good example of high frequency layout
techniques as a reference.
General high-speed, signal-path layout suggestions include:
• Continuous ground planes are preferred for signal routing, as shown in Figure 33 and Figure 34, with
matched impedance traces for longer runs. However, open up both ground and power planes around the
capacitive sensitive input and output device pins.
• Use good, high-frequency decoupling capacitors (0.1 μF) on the ground plane at the device power pins as
shown in Figure 33. Higher value capacitors (2.2 μF) are required, but may be placed further from the device
power pins and shared among devices. For best high-frequency decoupling, consider X2Y supply-decoupling
capacitors that offer a much higher self-resonance frequency over standard capacitors.
• When using differential signal routing over any appreciable distance, use microstrip layout techniques with
matched impedance traces.
• The input summing junction is very sensitive to parasitic capacitance. Connect any Rf, and Rg elements into
the summing junction with minimal trace length to the device pin side of the resistor, as shown in Figure 34.
The other side of these elements can have more trace length if needed to the source or to ground.
Table 1. Evaluation Boards
DEVICE
PACKAGE
EVALUATION BOARD PART NUMBER
LMH6703MF
SOT-23-6
LMH730216
LMH6703MA
SOIC
LMH730227
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11.2 Layout Example
Figure 33. Evaluation Board Layer 1
Figure 34. Evaluation Board Layer 2
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12 Device and Documentation Support
12.1 Documentation Support
12.1.1 Related Documentation
For related documentation see the following:
• Absolute Maximum Ratings for Soldering (SNOA549)
• Current Feedback Op Amp Applications Circuit Guide, Application Note OA--07 (SNOA365)
• Frequent Faux Pas in Applying Wideband Current Feedback Amplifiers, Application Note OA-15 (SNOA367)
• Noise Analysis for Comlinear Amplifiers, Application Note OA-12 (SNOA375)
• Semiconductor and IC Package Thermal Metrics (SPRA953)
12.2 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
12.3 Trademarks
LMH, E2E are trademarks of Texas Instruments.
All other trademarks are the property of their respective owners.
12.4 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
12.5 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
LMH6703MA/NOPB
ACTIVE
SOIC
D
8
95
RoHS & Green
SN
Level-1-260C-UNLIM
-40 to 85
LMH67
03MA
LMH6703MAX/NOPB
ACTIVE
SOIC
D
8
2500
RoHS & Green
SN
Level-1-260C-UNLIM
-40 to 85
LMH67
03MA
LMH6703MF/NOPB
ACTIVE
SOT-23
DBV
6
1000
RoHS & Green
SN
Level-1-260C-UNLIM
-40 to 85
AR1A
LMH6703MFX/NOPB
ACTIVE
SOT-23
DBV
6
3000
RoHS & Green
SN
Level-1-260C-UNLIM
-40 to 85
AR1A
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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