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LMK04208
SNAS684 – SEPTEMBER 2016
LMK04208 Low-Noise Clock Jitter Cleaner with Dual Loop PLLs
1 Features
3 Description
•
The LMK04208 is a high performance clock
conditioner with superior clock jitter cleaning,
generation, and distribution with advanced features to
meet next generation system requirements. The dual
loop PLLatinum™ architecture is capable of 111 fs,
RMS jitter (12 kHz to 20 MHz) using a low-noise
VCXO module or sub-200 fs rms jitter (12 kHz to 20
MHz) using a low cost external crystal and varactor
diode.
1
•
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•
•
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2
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Ultra-Low RMS Jitter Performance
– 111 fs, RMS Jitter (12 kHz to 20 MHz)
– 123 fs, RMS Jitter (100 Hz to 20 MHz)
Dual Loop PLLatinum™ PLL Architecture
PLL1
– Integrated Low-Noise Crystal Oscillator Circuit
– Holdover Mode when Input Clocks are Lost
– Automatic or Manual Triggering/Recovery
PLL2
– Normalized PLL Noise Floor of –227 dBc/Hz
– Phase Detector Rate of Up to 155 MHz
– OSCin Frequency-Doubler
– Integrated Low-Noise VCO or External VCO
Mode
Two Redundant Input Clocks with LOS
– Automatic and Manual Switch-Over Modes
50 % Duty Cycle Output Divides, 1 to 1045 (Even
and Odd)
6 LVPECL, LVDS, or LVCMOS Programmable
Outputs
Digital Delay: Fixed or Dynamically Adjustable
25 ps Step Analog Delay Control
7 Differential Outputs, Up to 14 Single-Ended
– Up to 6 VCXO/Crystal Buffered Outputs
Clock Rates of Up to 1536 MHz
0-Delay Mode
Three Default Clock Outputs at Power Up
Multi-Mode: Dual PLL, Single PLL, and Clock
Distribution
Industrial Temperature Range: –40°C to +85°C
3.15-V to 3.45-V Operation
64-Pin WQFN Package (9.0 × 9.0 × 0.8 mm)
The dual loop architecture consists of two highperformance phase-locked loops (PLL), a low-noise
crystal oscillator circuit, and a high-performance
voltage controlled oscillator (VCO). The first PLL
(PLL1) provides low-noise jitter cleaner functionality
while the second PLL (PLL2) performs the clock
generation. PLL1 can be configured to either work
with an external VCXO module or the integrated
crystal oscillator with an external tunable crystal and
varactor diode. When paired with a very narrow loop
bandwidth, PLL1 uses the superior close-in phase
noise (offsets below 50 kHz) of the VCXO module or
the tunable crystal to clean the input clock. The
output of PLL1 is used as the clean input reference to
PLL2 where it locks the integrated VCO. The loop
bandwidth of PLL2 can be optimized to clean the farout phase noise (offsets above 50 kHz) where the
integrated VCO outperforms the VCXO module or
tunable crystal used in PLL1.
Device Information(1)
PART NUMBER
VCO FREQUENCY
CLOCK
INPUTS
LMK04208
2750 to 3072 MHz
2
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Simplified Schematic
Crystal or
VCXO
Applications
Data Converter Clocking
Wireless Infrastructure
Networking, SONET/SDH, DSLAM
Medical, Video, Military, Aerospace
Test and Measurement
LMX2582
OSCout
PLL+VCO
Recovered
³GLUW\´ FORFNV
or clean clocks
CLKout0
CLKin0
CLKin1
LMK04208
Precision Clock
Conditioner
Serializer/
Deserializer
CLKout1
CLKout2
CLKout3
CLKout4
Backup
Reference
Clock
ADC
CLKout5
FPGA
CPLD
DAC
0XOWLSOH ³FOHDQ´ FORFNV DW GLIIHUHQW
frequencies
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
LMK04208
SNAS684 – SEPTEMBER 2016
www.ti.com
Table of Contents
1
2
3
4
5
6
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
6.1
6.2
6.3
6.4
6.5
6.6
6.7
7
1
1
1
2
3
5
9
9.1
9.2
9.3
9.4
10.1 Pin Connection Recommendations..................... 124
10.2 Current Consumption and Power Dissipation
Calculations............................................................ 126
11 Layout................................................................. 128
11.1 Layout Guidelines ............................................... 128
11.2 Layout Example .................................................. 129
12 Device and Documentation Support ............... 130
12.1 Device Support....................................................
12.2 Documentation Support ......................................
12.3 Receiving Notification of Documentation
Updates..................................................................
12.4 Community Resources........................................
12.5 Trademarks .........................................................
12.6 Electrostatic Discharge Caution ..........................
12.7 Glossary ..............................................................
Parameter Measurement Information ................ 16
Detailed Description ............................................ 18
8.1
8.2
8.3
8.4
8.5
8.6
Overview .................................................................
Functional Block Diagram .......................................
Feature Description.................................................
Device Functional Modes........................................
Programming...........................................................
Register Maps .........................................................
Application Information............................................ 96
Typical Applications .............................................. 113
System Examples ................................................. 121
Do's and Don'ts ..................................................... 123
10 Power Supply Recommendations ................... 124
Absolute Maximum Ratings ...................................... 5
ESD Ratings.............................................................. 5
Recommended Operating Conditions....................... 5
Thermal Information .................................................. 6
Electrical Characteristics........................................... 7
Timing Requirements .............................................. 13
Typical Characteristics ........................................... 15
7.1 Charge Pump Current Specification Definitions...... 16
7.2 Differential Voltage Measurement Terminology...... 17
8
Application and Implementation ........................ 96
18
22
23
43
48
52
130
130
130
130
130
130
130
13 Mechanical, Packaging, and Orderable
Information ......................................................... 130
4 Revision History
2
DATE
REVISION
NOTES
September 2016
*
Initial release.
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5 Pin Configuration and Functions
53
52
CLKout3*
54
NC
Vcc11
55
NC
CLKout4
56
NC
57
CLKout4*
58
Vcc12
59
NC
60
CLKout5*
61
CLKout5
62
NC
63
NC
Status_CLKin1
64
Status_CLKin0
Vcc13
NKD Package
64-Pin WQFN with Exposed Pad
Top View
51
50
49
NC
1
48
CLKout3
NC
2
47
Vcc10
CLKout0*
3
46
DATAuWire
CLKout0
4
45
CLKuWire
NC
5
44
LEuWire
SYNC
6
43
Vcc9
NC
7
42
CPout2
NC
8
41
Vcc8
Top Down View
NC
9
40
OSCout*
Vcc1
10
39
OSCout
LDObyp1
11
38
Vcc7
LDObyp2
12
37
OSCin*
CLKout1
13
36
OSCin
CLKout1*
14
35
Vcc6
34
CPout1
33
Status_LD
25
26
27
28
29
30
31
32
Vcc5
NC
NC
CLKout2
24
CLKin0
NC
23
CLKin0*
22
Status_Holdover
21
FBCLKin*/Fin*/CLKin1*
20
Vcc4
19
FBCLKin/Fin/CLKin1
18
GND
17
CLKout2*
DAP
NC
16
Vcc3
15
NC
Vcc2
NC
Pin Functions (1)
PIN
NO.
NAME
I/O
TYPE
DESCRIPTION
1, 2
NC
–
–
No Connection. These pins must be left floating.
3, 4
CLKout0*, CLKout0
O
Programmable
Clock output 0.
5
NC
–
–
No Connection. These pins must be left floating.
6
SYNC
Programmable
CLKout Synchronization input or programmable status pin.
7, 8, 9
NC
–
No Connection. These pins must be left floating.
10
Vcc1
PWR
Power supply for VCO LDO.
11
LDObyp1
ANLG
LDO Bypass, bypassed to ground with 10-µF capacitor.
12
LDObyp2
ANLG
LDO Bypass, bypassed to ground with a 0.1-µF capacitor.
13, 14
CLKout1, CLKout1*
O
Programmable
Clock output 1.
15, 16
NC
–
–
No Connection. These pins must be left floating.
17
Vcc2
PWR
Power supply for clock output 1.
(1)
I/O
–
See Pin Connection Recommendations.
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Pin Functions(1) (continued)
PIN
NO.
NAME
I/O
TYPE
DESCRIPTION
18
Vcc3
PWR
Power supply for clock output 2.
19, 20
NC
–
–
No Connection. These pins must be left floating.
21, 22
CLKout2*, CLKout2
O
Programmable
Clock output 2.
23
GND
PWR
Ground.
24
Vcc4
PWR
Power supply for digital.
CLKin1, CLKin1*
25, 26
FBCLKin, FBCLKin*
Reference Clock Input Port 1 for PLL1. AC or DC Coupled.
I
ANLG
External VCO input (External VCO mode). AC or DC
Coupled.
Fin/Fin*
Programmable
Programmable status pin, default readback output.
Programmable to holdover mode indicator. Other options
available by programming.
ANLG
Reference Clock Input Port 0 for PLL1.
AC or DC Coupled.
PWR
Power supply for clock inputs.
–
No Connection. These pins must be left floating.
I/O
Programmable
Programmable status pin, default lock detect for PLL1 and
PLL2. Other options available by programming.
O
ANLG
Charge pump 1 output.
PWR
Power supply for PLL1, charge pump 1.
ANLG
Feedback to PLL1, Reference input to PLL2.
AC Coupled.
PWR
Power supply for OSCin, OSCout, and PLL2 circuitry. (2)
Programmable
Buffered output of OSCin port. (2)
PWR
Power supply for PLL2, charge pump 2.
ANLG
Charge pump 2 output.
PWR
Power supply for PLL2.
CMOS
MICROWIRE Latch Enable Input.
I
CMOS
MICROWIRE Clock Input.
I
CMOS
MICROWIRE Data Input.
PWR
Power supply for clock output 3.
Programmable
Clock output 3.
–
No Connection. These pins must be left floating.
PWR
Power supply for clock output 4.
Programmable
Clock output 4.
–
No Connection. These pins must be left floating.
PWR
Power supply for clock output 5.
Programmable
Clock output 5.
–
No Connection. These pins must be left floating.
I/O
Programmable
NC. Programmable status pin. Default is input for pin control
of PLL1 reference clock selection. CLKin0 LOS status and
other options available by programming.
I/O
Programmable
Programmable status pin. Default is input for pin control of
PLL1 reference clock selection. CLKin1 LOS status and
other options available by programming.
PWR
Power supply for clock output 0.
GND
DIE ATTACH PAD, connect to GND.
27
Status_Holdover
I/O
28, 29
CLKin0, CLKin0*
I
30
Vcc5
31, 32
NC
33
Status_LD
34
CPout1
35
Vcc6
36, 37
OSCin, OSCin*
38
Vcc7
39, 40
OSCout, OSCout*
41
Vcc8
42
CPout2
43
Vcc9
44
LEuWire
I
45
CLKuWire
46
DATAuWire
47
Vcc10
48, 49
CLKout3, CLKout3*
O
50, 51
NC
–
52
Vcc11
53, 54
CLKout4, CLKout4*
O
55, 56
NC
–
57
Vcc12
58, 59
CLKout5, CLKout5*
O
60, 61
NC
–
62
Status_CLKin0
63
Status_CLKin1
64
Vcc13
DAP
DAP
(2)
4
Feedback input for external clock feedback input (0-delay
mode). AC or DC Coupled.
–
I
O
O
–
See Vcc5 (CLKin), Vcc7 (OSCin and OSCout) for information on configuring device for optimum performance.
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1) (2) (1)
MIN
MAX
UNIT
–0.3
3.6
V
–0.3
VCC + 0.3
V
260
°C
Junction temperature
150
°C
IIN
Differential input current (CLKinX/X*,
OSCin/OSCin*, FBCLKin/FBCLKin*, Fin/Fin*)
±5
mA
MSL
Moisture Sensitivity Level
Tstg
Storage temperature
(3)
VCC
Supply voltage
VIN
Input voltage
TL
Lead temperature (solder 4 seconds)
TJ
(1)
(2)
(3)
3
-65
150
°C
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
If Military/Aerospace specified devices are required, contact the Texas Instruments Sales Office/Distributors for availability and
specifications.
Never to exceed 3.6 V.
6.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1)
±2000
Charged-device model (CDM), per JEDEC specification JESD22C101 (2)
±750
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Manufacturing with
less than 500-V HBM is possible with the necessary precautions. Pins listed as ±2000 V may actually have higher performance.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Manufacturing with
less than 250-V CDM is possible with the necessary precautions. Pins listed as ±750 V may actually have higher performance.
6.3 Recommended Operating Conditions
MIN
TJ
Junction temperature
TA
Ambient temperature
VCC
Supply voltage
VCC = 3.3 V
NOM
MAX
UNIT
125
°C
–40
25
85
°C
3.15
3.3
3.45
V
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6.4 Thermal Information
LMK04208
THERMAL METRIC (1)
NKD (WQFN)
UNIT
64 PINS
Junction-to-ambient thermal resistance on 4-layer JEDEC PCB (2) (3)
RθJA
(4) (5)
25.2
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
6.9
°C/W
RθJB
Junction-to-board thermal resistance (6)
4.0
°C/W
ψJT
Junction-to-top characterization parameter (7)
0.1
°C/W
ψJB
Junction-to-board characterization parameter
(8)
4.0
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance (9)
0.8
°C/W
(1)
(2)
(3)
(4)
(5)
(6)
(7)
(8)
(9)
6
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, High-K board, as
specified in JESD51-7, in an environment described in JESD51-2a.
Specification assumes 32 thermal vias connect the die attach pad to the embedded copper plane on the 4-layer JEDEC PCB. These
vias play a key role in improving the thermal performance of the WQFN. Note that the JEDEC PCB is a standard thermal measurement
PCB and does not represent best performance a PCB can achieve. TI recommends that the maximum number of vias be used in the
board layout. R θJA is unique for each PCB.
The junction-to-case(top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific JEDEC standard
test exists, but a close description can be found in the ANSI SEMI standard G30-88.
Case is defined as the DAP (die attach pad)
The junction-to-board thermal resistance is obtained by simulating an environment with a ring cold plate fixture to control the PCB
temperature, as described in JESD51-8.
The junction-to-top characterization parameter, ψJT, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining RθJA, using a procedure described in JESD51-2a (sections 6 and 7).
The junction-to-board characterization parameter, ψJB, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining RθJA, using a procedure described in JESD51-2a (sections 6 and 7).
The junction-to-case(bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific
JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
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6.5 Electrical Characteristics
3.15 V ≤ VCC ≤ 3.45 V, –40 °C ≤ TA ≤ 85°C. Typical values represent most likely parametric norms at VCC = 3.3 V, TA = 25°C,
at the Recommended Operating Conditions at the time of product characterization and are not specified. (1)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
1
3
mA
445
535
mA
500
MHz
CURRENT CONSUMPTION
ICC_PD
Power down supply current
Supply current with all clocks (CLKoutX)
and OSCout enabled as LVDS. (2)
ICC_CLKS
All clock delays disabled,
CLKoutX_DIV = 1045,
EN_SYNC=0
PLL1 and PLL2 locked.
CLKin0/0* and CLKin1/1* INPUT CLOCK SPECIFICATIONS
Clock input frequency (3)
fCLKin
SLEWCLKin
(1)
Clock input slew rate
0.001
(4)
VIDCLKin
VSSCLKin
VIDCLKin
Clock input
Differential input voltage (see
Figure 8)
(5)
VCLKin0-offset
Clock input
Single-ended input voltage (4)
DC offset voltage between
CLKin0/CLKin0*
CLKin0* - CLKin0
VCLKin1-offset
DC offset voltage between
CLKin1/CLKin1*
CLKin1* - CLKin1
VCLKinX-offset
DC offset voltage between
CLKinX/CLKinX*
CLKinX* - CLKinX
VCLKin- VIH
High input voltage
VCLKin- VIL
Low input voltage
0.15
AC coupled
CLKinX_BUF_TYPE = 0 (Bipolar)
0.25
1.55
|V|
0.5
3.1
Vpp
AC coupled
CLKinX_BUF_TYPE = 1 (MOS)
0.25
1.55
|V|
and
VSSCLKin
VCLKin
20% to 80%
0.5
V/ns
0.5
3.1
Vpp
AC coupled to CLKinX; CLKinX* AC
coupled to Ground
CLKinX_BUF_TYPE = 0 (Bipolar)
0.25
2.4
Vpp
AC coupled to CLKinX; CLKinX* AC
coupled to Ground
CLKinX_BUF_TYPE = 1 (MOS)
0.25
2.4
Vpp
20
mV
0
mV
55
mV
Each pin AC coupled
CLKin0_BUF_TYPE = 0 (Bipolar)
Each pin AC coupled
CLKinX_BUF_TYPE = 1 (MOS)
DC coupled to CLKinX; CLKinX* AC
coupled to Ground
CLKinX_BUF_TYPE = 1 (MOS)
2.0
VCC
V
0.0
0.4
V
FBCLKin/FBCLKin* and Fin/Fin* INPUT SPECIFICATIONS
fFBCLKin
Clock input frequency (4)
AC coupled
(CLKinX_BUF_TYPE = 0)
MODE = 2 or 8; FEEDBACK_MUX =
6
0.001
1000
MHz
fFin
Clock input frequency (4)
AC coupled
(CLKinX_BUF_TYPE = 0)
MODE = 3 or 11
0.001
3100
MHz
VFBCLKin/Fin
Single Ended
Clock input voltage (4)
AC coupled;
(CLKinX_BUF_TYPE = 0)
0.25
2.0
Vpp
SLEWFBCLKin/Fin
Slew rate on CLKin (4) (1)
AC coupled; 20% to 80%;
(CLKinX_BUF_TYPE = 0)
0.15
(1)
(2)
(3)
(4)
(5)
0.5
V/ns
In order to meet the jitter performance listed in the subsequent sections of this data sheet, the minimum recommended slew rate for all
input clocks is 0.5 V/ns. This is especially true for single-ended clocks. Phase noise performance begins to degrade as the clock input
slew rate is reduced. However, the device functions at slew rates down to the minimum listed. When compared to single-ended clocks,
differential clocks (LVDS, LVPECL) are less susceptible to degradation in phase noise performance at lower slew rates due to their
common mode noise rejection. However, it is also recommended to use the highest possible slew rate for differential clocks to achieve
optimal phase noise performance at the device outputs.
Load conditions for output clocks: LVDS: 100 Ω differential. See Current Consumption and Power Dissipation Calculations for Icc for
specific part configuration and how to calculate Icc for a specific design.
CLKin0, CLKin1 maximum is specified by characterization, production tested at 200 MHz.
Specified by characterization.
See Differential Voltage Measurement Terminology for definition of VID and VOD voltages.
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Electrical Characteristics (continued)
3.15 V ≤ VCC ≤ 3.45 V, –40 °C ≤ TA ≤ 85°C. Typical values represent most likely parametric norms at VCC = 3.3 V, TA = 25°C,
at the Recommended Operating Conditions at the time of product characterization and are not specified.(1)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
40
MHz
PLL1 SPECIFICATIONS
fPD1
PLL1 phase detector frequency
ICPout1SOURCE
PLL1 charge
Pump source current (6)
VCPout1 = VCC/2, PLL1_CP_GAIN = 0
100
VCPout1 = VCC/2, PLL1_CP_GAIN = 1
200
VCPout1 = VCC/2, PLL1_CP_GAIN = 2
400
VCPout1 = VCC/2, PLL1_CP_GAIN = 3
1600
VCPout1=VCC/2, PLL1_CP_GAIN = 0
–100
VCPout1=VCC/2, PLL1_CP_GAIN = 1
–200
VCPout1=VCC/2, PLL1_CP_GAIN = 2
–400
VCPout1=VCC/2, PLL1_CP_GAIN = 3
–1600
ICPout1SINK
PLL1 charge
Pump sink current (6)
ICPout1%MIS
Charge pump
Sink/source mismatch
VCPout1 = VCC/2, T = 25 °C
3%
ICPout1VTUNE
Magnitude of charge pump current
variation vs. charge pump voltage
0.5 V < VCPout1 < VCC - 0.5 V
TA = 25 °C
4%
ICPout1%TEMP
Charge pump current vs.
temperature variation
ICPout1 TRI
Charge Pump TRI-STATE leakage
current
PN10kHz
PLL 1/f noise at 10 kHz offset. (7)
Normalized to 1 GHz Output Frequency
PN1Hz
Normalized phase noise contribution (8)
µA
µA
10%
4%
0.5 V < VCPout < VCC - 0.5 V
5
PLL1_CP_GAIN = 400 µA
–117
PLL1_CP_GAIN = 1600 µA
–118
PLL1_CP_GAIN = 400 µA
dBc/Hz
–221.5
PLL1_CP_GAIN = 1600 µA
nA
dBc/Hz
–223
PLL2 REFERENCE INPUT (OSCin) SPECIFICATIONS
fOSCin
PLL2 reference input (9)
SLEWOSCin
PLL2 reference clock minimum slew rate
20% to 80%
on OSCin (4)
VOSCin
Input voltage for OSCin or OSCin* (4)
AC coupled; Single-ended (Unused
pin AC coupled to GND)
Differential voltage swing (see Figure 8)
AC coupled
VOSCin-offset
DC offset voltage between
OSCin/OSCin*
OSCinX* - OSCinX
Each pin AC coupled
fdoubler_max
Doubler input frequency (4)
EN_PLL2_REF_2X = 1; (10)
OSCin Duty Cycle 40% to 60%
VIDOSCin
VSSOSCin
500
0.15
0.5
MHz
V/ns
0.2
2.4
Vpp
0.2
1.55
|V|
0.4
3.1
Vpp
20
mV
155
MHz
(6)
(7)
This parameter is programmable
A specification in modeling PLL in-band phase noise is the 1/f flicker noise, LPLL_flicker(f), which is dominant close to the carrier. Flicker
noise has a 10 dB/decade slope. PN10kHz is normalized to a 10 kHz offset and a 1 GHz carrier frequency. PN10kHz = LPLL_flicker(10
kHz) - 20log(Fout / 1 GHz), where LPLL_flicker(f) is the single side band phase noise of only the flicker noise's contribution to total noise,
L(f). To measure LPLL_flicker(f) it is important to be on the 10 dB/decade slope close to the carrier. A high compare frequency and a clean
crystal are important to isolating this noise source from the total phase noise, L(f). LPLL_flicker(f) can be masked by the reference
oscillator performance if a low power or noisy source is used. The total PLL in-band phase noise performance is the sum of LPLL_flicker(f)
and LPLL_flat(f).
(8) A specification modeling PLL in-band phase noise. The normalized phase noise contribution of the PLL, LPLL_flat(f), is defined as:
PN1HZ=LPLL_flat(f) - 20log(N) - 10log(fPDX). LPLL_flat(f) is the single side band phase noise measured at an offset frequency, f, in a 1 Hz
bandwidth and fPDX is the phase detector frequency of the synthesizer. LPLL_flat(f) contributes to the total noise, L(f).
(9) FOSCin maximum frequency specified by characterization. Production tested at 200 MHz.
(10) The EN_PLL2_REF_2X bit (Register 13) enables/disables a frequency doubler mode for the PLL2 OSCin path.
8
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Electrical Characteristics (continued)
3.15 V ≤ VCC ≤ 3.45 V, –40 °C ≤ TA ≤ 85°C. Typical values represent most likely parametric norms at VCC = 3.3 V, TA = 25°C,
at the Recommended Operating Conditions at the time of product characterization and are not specified.(1)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
20.5
MHz
CRYSTAL OSCILLATOR MODE SPECIFICATIONS
Crystal frequency range (4)
RESR < 40 Ω
PXTAL
Crystal power dissipation (11)
Vectron VXB1 crystal, 20.48 MHz,
RESR < 40 Ω
XTAL_LVL = 0
CIN
Input capacitance of
LMK04208 OSCin port
-40 to +85 °C
fXTAL
6
100
µW
6
pF
PLL2 PHASE DETECTOR and CHARGE PUMP SPECIFICATIONS
fPD2
ICPoutSOURCE
Phase detector frequency
155
PLL2 charge pump source current (6)
VCPout2=VCC/2, PLL2_CP_GAIN = 0
100
VCPout2=VCC/2, PLL2_CP_GAIN = 1
400
VCPout2=VCC/2, PLL2_CP_GAIN = 2
1600
VCPout2=VCC/2, PLL2_CP_GAIN = 3
3200
VCPout2=VCC/2, PLL2_CP_GAIN = 0
–100
VCPout2=VCC/2, PLL2_CP_GAIN = 1
–400
VCPout2=VCC/2, PLL2_CP_GAIN = 2
–1600
VCPout2=VCC/2, PLL2_CP_GAIN = 3
–3200
ICPoutSINK
PLL2 charge pump sink current (6)
ICPout2%MIS
Charge pump sink/source mismatch
VCPout2=VCC/2, TA = 25 °C
3%
ICPout2VTUNE
Magnitude of charge pump current vs.
charge pump voltage variation
0.5 V < VCPout2 < VCC - 0.5 V
TA = 25 °C
4%
ICPout2%TEMP
Charge pump current vs.
Temperature variation
ICPout2TRI
Charge pump leakage
MHz
µA
µA
10%
4%
0.5 V < VCPout2 < VCC - 0.5 V
(7)
PN10kHz
PLL 1/f Noise at 10 kHz offset
Normalized to 1 GHz output frequency
PN1Hz
Normalized Phase Noise Contribution (8)
10
PLL2_CP_GAIN = 400 µA
–118
PLL2_CP_GAIN = 3200 µA
–121
PLL2_CP_GAIN = 400 µA
dBc/Hz
–222.5
PLL2_CP_GAIN = 3200 µA
nA
dBc/Hz
–227
INTERNAL VCO SPECIFICATIONS
fVCO
VCO tuning range
KVCO
Fine tuning sensitivity
(The range displayed in the typical
column indicates the lower sensitivity is
typical at the lower end of the tuning
LMK04208
range, and the higher tuning sensitivity is
typical at the higher end of the tuning
range).
LMK04208
|ΔTCL|
Allowable Temperature Drift for
Continuous Lock (12) (4)
After programming R30 for lock, no
changes to output configuration are
permitted to ensure continuous lock
2750
3072
20 to 36
MHz
MHz/V
125
°C
(11) See Application Section discussion of Optional Crystal Oscillator Implementation (OSCin/OSCin*).
(12) Maximum Allowable Temperature Drift for Continuous Lock is how far the temperature can drift in either direction from the value it was
at the time that the R30 register was last programmed, and still have the part stay in lock. The action of programming the R30 register,
even to the same value, activates a frequency calibration routine. This implies the part works over the entire frequency range, but if the
temperature drifts more than the maximum allowable drift for continuous lock, then it is necessary to reload the R30 register to ensure it
stays in lock. Regardless of what temperature the part was initially programmed at, the temperature can never drift outside the
frequency range of -40 °C to 85 °C without violating specifications.
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Electrical Characteristics (continued)
3.15 V ≤ VCC ≤ 3.45 V, –40 °C ≤ TA ≤ 85°C. Typical values represent most likely parametric norms at VCC = 3.3 V, TA = 25°C,
at the Recommended Operating Conditions at the time of product characterization and are not specified.(1)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
CLKout CLOSED LOOP JITTER SPECIFICATIONS USING a COMMERCIAL QUALITY VCXO (13)
L(f)CLKout
JCLKout
LVDS/LVPECL/
LVCMOS
LMK04208
fCLKout = 245.76 MHz
SSB Phase noise
Measured at clock outputs
Value is average for all output types (14)
LMK04208 (14)
fCLKout = 245.76 MHz
Integrated RMS jitter
Offset = 1 kHz
–122.5
Offset = 10 kHz
–132.9
Offset = 100 kHz
–135.2
Offset = 800 kHz
–143.9
Offset = 10 MHz; LVDS
–156.0
Offset = 10 MHz; LVPECL 1600
mVpp
–157.5
Offset = 10 MHz; LVCMOS
–157.1
BW = 12 kHz to 20 MHz
111
BW = 100 Hz to 20 MHz
123
dBc/Hz
fs, RMS
CLKout CLOSED LOOP JITTER SPECIFICATIONS USING THE INTEGRATED LOW NOISE CRYSTAL OSCILLATOR CIRCUIT
LMK04208
fCLKout = 245.76 MHz
Integrated RMS jitter
BW = 12 kHz to 20 MHz
XTAL_LVL = 3
192
BW = 100 Hz to 20 MHz
XTAL_LVL = 3
450
(15)
fs rms
DEFAULT POWER ON RESET CLOCK OUTPUT FREQUENCY
fCLKout-startup
Default output clock frequency at device
power on (16)
CLKout4, LVDS, LMK04208
90
110
130
MHz
(13) VCXO used is a 122.88-MHz Crystek CVHD-950-122.880.
(14) fVCO = 2949.12 MHz, PLL1 parameters: FPD1 = 1.024 MHz, ICP1 = 100 μA, loop bandwidth = 10 Hz. 122.88 MHz Crystek CVHD950–122.880. PLL2 parameters: PLL2_R = 1, FPD2 = 122.88 MHz, ICP2 = 3200 μA, C1 = 47 pF, C2 = 3.9 nF, R2 = 620 Ω, PLL2_C3_LF
= 0, PLL2_R3_LF = 0, PLL2_C4_LF = 0, PLL2_R4_LF = 0, CLKoutX_DIV = 12, and CLKoutX_ADLY_SEL = 0.
(15) Crystal used is a 20.48-MHz Vectron VXB1-1150-20M480 and Skyworks varactor diode, SMV-1249-074LF.
(16) CLKout3 and OSCout also oscillate at start-up at the frequency of the VCXO attached to OSCin port.
10
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Electrical Characteristics (continued)
3.15 V ≤ VCC ≤ 3.45 V, –40 °C ≤ TA ≤ 85°C. Typical values represent most likely parametric norms at VCC = 3.3 V, TA = 25°C,
at the Recommended Operating Conditions at the time of product characterization and are not specified.(1)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
CLOCK SKEW and DELAY
LVDS-to-LVDS, T = 25 °C,
FCLK = 800 MHz, RL= 100 Ω
AC coupled
30
LVPECL-to-LVPECL,
T = 25 °C,
FCLK = 800 MHz, RL= 100 Ω
emitter resistors =
240 Ω to GND
AC coupled
30
Maximum skew between any two
LVCMOS outputs, same CLKout or
different CLKout (4) (17)
RL = 50 Ω, CL = 5 pF,
T = 25 °C, FCLK = 100 MHz.
100
LVDS or LVPECL to LVCMOS
Same device, T = 25 °C,
250 MHz
750
Maximum CLKoutX to CLKoutY (4) (17)
|TSKEW|
MixedTSKEW
td0-DELAY
CLKin to CLKoutX delay (17)
MODE = 2
PLL1_R_DLY = 0; PLL1_N_DLY = 0
1850
MODE = 2
PLL1_R_DLY = 0; PLL1_N_DLY = 0;
VCO Frequency = 2949.12 MHz
Analog delay select = 0;
Feedback clock digital delay = 11;
Feedback clock half step = 1;
Output clock digital delay = 5;
Output clock half step = 0;
0
ps
ps
ps
LVDS CLOCK OUTPUTS (CLKoutX), CLKoutX_TYPE = 1
fCLKout
VOD
VSS
Maximum frequency (4) (18)
RL = 100 Ω
Differential output voltage (see Figure 9)
ΔVOD
Change in magnitude of VOD for
complementary output states
T = 25 °C, DC measurement
AC coupled to receiver input
R = 100-Ω differential termination
VOS
Output offset voltage
ΔVOS
Change in VOS for complementary output
states
1536
MHz
250
400
450
|mV|
500
800
900
mVpp
50
mV
–50
1.125
1.25
1.375
35
V
|mV|
Output rise time
20% to 80%, RL = 100 Ω
Output fall time
80% to 20%, RL = 100 Ω
ISA
ISB
Output short circuit current
single-ended
Single-ended output shorted to GND
T = 25 °C
–24
24
mA
ISAB
Output short circuit current - differential
Complimentary outputs tied together
–12
12
mA
TR / TF
200
ps
(17) Equal loading and identical clock output configuration on each clock output is required for specification to be valid. Specification is not
valid for CLKoutX or CLKoutY in analog delay mode.
(18) Refer to Typical Characteristics for output operation performance at higher frequencies than the minimum maximum output frequency.
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Electrical Characteristics (continued)
3.15 V ≤ VCC ≤ 3.45 V, –40 °C ≤ TA ≤ 85°C. Typical values represent most likely parametric norms at VCC = 3.3 V, TA = 25°C,
at the Recommended Operating Conditions at the time of product characterization and are not specified.(1)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
LVPECL CLOCK OUTPUTS (CLKoutX)
Maximum frequency (4) (18)
fCLKout
20% to 80% output rise
TR / TF
80% to 20% output fall time
1536
RL = 100 Ω, emitter resistors = 240 Ω
to GND
CLKoutX_TYPE = 4 or 5
(1600 or 2000 mVpp)
MHz
150
ps
VCC –
1.03
V
VCC –
1.41
V
700-mVpp LVPECL CLOCK OUTPUTS (CLKoutX), CLKoutX_TYPE = 2
VOH
Output high voltage
VOL
Output low voltage
VOD
T = 25 °C, DC measurement
Termination = 50 Ω to
VCC - 1.4 V
Output voltage (see Figure 9)
VSS
305
380
440
|mV|
610
760
880
mVpp
1200-mVpp LVPECL CLOCK OUTPUTS (CLKoutX), CLKoutX_TYPE = 3
VOH
Output high voltage
VOL
Output low voltage
VOD
T = 25 °C, DC measurement
Termination = 50 Ω to
VCC - 1.7 V
Output voltage (see Figure 9)
VSS
VCC –
1.07
V
VCC –
1.69
V
545
625
705
|mV|
1090
1250
1410
mVpp
1600-mVpp LVPECL CLOCK OUTPUTS (CLKoutX), CLKoutX_TYPE = 4
VOH
Output high voltage
VOL
Output low voltage
VOD
T = 25 °C, DC Measurement
Termination = 50 Ω to
VCC - 2.0 V
Output voltage (see Figure 9)
VSS
VCC –
1.10
V
VCC –
1.97
V
660
870
965
|mV|
1320
1740
1930
mVpp
2000-mVpp LVPECL (2VPECL) CLOCK OUTPUTS (CLKoutX), CLKoutX_TYPE = 5
VOH
Output high voltage
VOL
Output low voltage
VOD
T = 25 °C, DC Measurement
Termination = 50 Ω to
VCC - 2.3 V
Output voltage Figure 9
VSS
VCC –
1.13
V
VCC –
2.20
V
800
1070
1200
|mV|
1600
2140
2400
mVpp
LVCMOS CLOCK OUTPUTS (CLKoutX)
fCLKout
Maximum frequency (4) (18)
5 pF Load
VOH
Output high voltage
1 mA Load
VOL
Output low voltage
1 mA Load
IOH
Output high current (source)
VCC = 3.3 V, VO = 1.65 V
28
mA
IOL
Output low current (sink)
VCC = 3.3 V, VO = 1.65 V
28
mA
(4)
VCC/2 to VCC/2, FCLK = 100 MHz
T = 25 °C
250
MHz
VCC –
0.1
V
0.1
DUTYCLK
Output duty cycle
TR
Output rise time
20% to 80%, RL = 50 Ω,
CL = 5 pF
400
ps
TF
Output fall time
80% to 20%, RL = 50 Ω,
CL = 5 pF
400
ps
12
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45%
50%
V
55%
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Electrical Characteristics (continued)
3.15 V ≤ VCC ≤ 3.45 V, –40 °C ≤ TA ≤ 85°C. Typical values represent most likely parametric norms at VCC = 3.3 V, TA = 25°C,
at the Recommended Operating Conditions at the time of product characterization and are not specified.(1)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
DIGITAL OUTPUTS (Status_CLKinX, Status_LD, Status_Holdover, SYNC)
VOH
High-level output voltage
IOH = -500 µA
VOL
Low-level output voltage
IOL = 500 µA
VCC –
0.4
V
0.4
V
VCC
V
0.4
V
DIGITAL INPUTS (Status_CLKinX, SYNC)
VIH
High-level input voltage
VIL
Low-level input voltage
IIH
IIL
1.6
High-level input current
VIH = VCC
Low-level input current
VIL = 0 V
Status_CLKinX_TYPE = 0
(High Impedance)
–5
5
Status_CLKinX_TYPE = 1
(Pull-up)
–5
5
Status_CLKinX_TYPE = 2
(Pull-down)
10
80
Status_CLKinX_TYPE = 0
(High Impedance)
–5
5
Status_CLKinX_TYPE = 1
(Pull-up)
–40
-5
Status_CLKinX_TYPE = 2
(Pull-down)
–5
5
1.6
VCC
V
0.4
V
5
25
µA
–5
5
µA
µA
µA
DIGITAL INPUTS (CLKuWire, DATAuWire, LEuWire)
VIH
High-level input voltage
VIL
Low-level input voltage
IIH
High-level input current
VIH = VCC
IIL
Low-level input current
VIL = 0
6.6 Timing Requirements
See Programming for additional information
MIN
NOM
MAX
UNIT
TECS
LE to clock set up time
See Figure 1 through Figure 4
25
ns
TDCS
Data to clock set up time
See Figure 1
25
ns
TCDH
Clock to data hold time
See Figure 1
8
ns
TCWH
Clock pulse width high
See Figure 1, Figure 2, and Figure 4
25
ns
TCWL
Clock pulse width low
See Figure 1, Figure 2, and Figure 4
25
ns
TCES
Clock to LE set up time
See Figure 1 through Figure 4
25
ns
TEWH
LE pulse width
See Figure 1, Figure 2, and Figure 4
25
ns
TCR
Falling clock to readback time
See Figure 4
25
ns
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MSB
DATAuWire
D26
LSB
D25
D24
D23
D22
D0
A4
A1
A0
CLKuWire
tECS
tCES
tDCS
tCWH
tCDH
tECS
tCWL
LEuWire
tEWH
Figure 1. MICROWIRE Input Timing Diagram
DATAuWire
MSB
LSB
D26
A0
CLKuWire
tECS
tCES
tCWL
LEuWire
tCWH
tEWH
Figure 2. MICROWIRE Timing Diagram: Extra CLKuWire Pulses for R0 to R5
DATAuWire
MSB
LSB
D26
A0
CLKuWire
tECS
tCES
tCES
LEuWire
Figure 3. MICROWIRE Timing Diagram: Extra CLKuWire Pulses for R0 to R5 with LEuWire Asserted
DATAuWire
MSB
LSB
D26
A0
CLKuWire
tCR
tECS
LEuWire
READBACK_LE = 0
tCWH
tCR
tCWL
tCES
tEWH
tECS
LEuWire
READBACK_LE = 1
Readback Pin
RD26
Register Write
RD25
RD24
RD23
RD0
Register Read
Figure 4. MICROWIRE Readback Timing Diagram
14
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6.7 Typical Characteristics
1200
500
2000 mVpp
1600 mVpp
1200 mVpp
700 mVpp
450
1000
400
VOD(mV)
VOD(mV)
350
300
250
200
800
600
400
150
100
200
50
0
0
0
500
1000 1500 2000 2500 3000
FREQUENCY (MHz)
0
Figure 5. LVDS VOD vs Frequency
500 1000 1500 2000 2500 3000
FREQUENCY (MHz)
Figure 6. LVPECL with 240-Ω Emitter Resistors
VOD vs Frequency
1200
VOD(mV)
1000
2000 mVpp
800
600
1600 mVpp
400
200
0
0
500 1000 1500 2000 2500 3000
FREQUENCY (MHz)
Figure 7. LVPECL with 120-Ω Emitter Resistors
VOD vs Frequency
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7 Parameter Measurement Information
7.1 Charge Pump Current Specification Definitions
I1 = Charge Pump Sink Current at VCPout = VCC - ΔV
I2 = Charge Pump Sink Current at VCPout = VCC/2
I3 = Charge Pump Sink Current at VCPout = ΔV
I4 = Charge Pump Source Current at VCPout = VCC - ΔV
I5 = Charge Pump Source Current at VCPout = VCC/2
I6 = Charge Pump Source Current at VCPout = ΔV
ΔV = Voltage offset from the positive and negative supply rails. Defined to be 0.5 V for this device.
7.1.1 Charge Pump Output Current Magnitude Variation Vs. Charge Pump Output Voltage
7.1.2 Charge Pump Sink Current Vs. Charge Pump Output Source Current Mismatch
7.1.3 Charge Pump Output Current Magnitude Variation vs. Ambient Temperature
16
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7.2 Differential Voltage Measurement Terminology
The differential voltage of a differential signal can be described by two different definitions causing confusion
when reading datasheets or communicating with other engineers. This section will address the measurement and
description of a differential signal so that the reader will be able to understand and discern between the two
different definitions when used.
The first definition used to describe a differential signal is the absolute value of the voltage potential between the
inverting and non-inverting signal. The symbol for this first measurement is typically VID or VOD depending on if
an input or output voltage is being described.
The second definition used to describe a differential signal is to measure the potential of the non-inverting signal
with respect to the inverting signal. The symbol for this second measurement is VSS and is a calculated
parameter. Nowhere in the IC does this signal exist with respect to ground, it only exists in reference to its
differential pair. VSS can be measured directly by oscilloscopes with floating references, otherwise this value can
be calculated as twice the value of VOD as described in the first description.
Figure 8 illustrates the two different definitions side-by-side for inputs and Figure 9 illustrates the two different
definitions side-by-side for outputs. The VID and VOD definitions show VA and VB DC levels that the non-inverting
and inverting signals toggle between with respect to ground. VSS input and output definitions show that if the
inverting signal is considered the voltage potential reference, the non-inverting signal voltage potential is now
increasing and decreasing above and below the non-inverting reference. Thus the peak-to-peak voltage of the
differential signal can be measured.
VID and VOD are often defined as volts (V) and VSS is often defined as volts peak-to-peak (VPP).
VID Definition
VSS Definition for Input
Non-Inverting Clock
VA
2· VID
VID
VB
Inverting Clock
VSS = 2· VID
VID = | VA - VB |
GND
Figure 8. Two Different Definitions for Differential Input Signals
VOD Definition
VSS Definition for Output
Non-Inverting Clock
VA
2· VOD
VOD
VB
Inverting Clock
VOD = | VA - VB |
VSS = 2· VOD
GND
Figure 9. Two Different Definitions for Differential Output Signals
See AN-912, Common Data Transmission Parameters and their Definitions SNLA036, for more information.
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8 Detailed Description
8.1 Overview
In default mode of operation, dual PLL mode with internal VCO, the Phase Frequency Detector in PLL1
compares the active CLKinX reference divided by CLKinX_PreR_DIV and PLL1 R divider with the external
VCXO or crystal attached to the PLL2 OSCin port divided by PLL1 N divider. The external loop filter for PLL1
should be narrow to provide an ultra clean reference clock from the external VCXO or crystal to the
OSCin/OSCin* pins for PLL2.
The Phase Frequency Detector in PLL2 compares the external VCXO or crystal to the internal VCO after the
reference and feedback dividers. The VCXO or crystal on the OSCin input is divided by PLL2 R divider. The
feedback from the internal VCO is divided by the PLL2 Prescaler, the PLL2 N divider, and optionally the VCO
divider.
The bandwidth of the external loop filter for PLL2 should be designed to be wide enough to take advantage of
the low in-band phase noise of PLL2 and the low high offset phase noise of the internal VCO. The VCO output is
also placed on the distribution path for the Clock Distribution section. The clock distribution consists of 6 outputs.
Each clock output allows the user to select a divide value, a digital delay value, and an analog delay. The 6 clock
outputs drive programmable output buffers. Two clock outputs allow their input signal to be from the OSCin port
directly.
When a 0-delay mode is used, a clock output will be passed through the feedback mux to the PLL1 N Divider for
synchronization and 0-delay.
When an external VCO mode is used, the Fin port will be used to input an external VCO signal. PLL2 Phase
comparison will now be with this signal divided by the PLL2 N divider and N2 pre-scaler. The VCO divider may
not be used. One less clock input is available when using an external VCO mode.
When a single PLL mode is used, PLL1 is powered down. OSCin is used as a reference to PLL2.
8.1.1 System Architecture
The dual loop PLL architecture of the LMK04208 provides the lowest jitter performance over the widest range of
output frequencies and phase noise integration bandwidths. The first stage PLL (PLL1) is driven by an external
reference clock and uses an external VCXO or tunable crystal to provide a frequency accurate, low phase noise
reference clock for the second stage frequency multiplication PLL (PLL2). PLL1 typically uses a narrow loop
bandwidth (10 Hz to 200 Hz) to retain the frequency accuracy of the reference clock input signal while at the
same time suppressing the higher offset frequency phase noise that the reference clock may have accumulated
along its path or from other circuits. This cleaned reference clock provides the reference input to PLL2.
The low phase noise reference provided to PLL2 allows PLL2 to operate with a wide loop bandwidth (50 kHz to
200 kHz). The loop bandwidth for PLL2 is chosen to take advantage of the superior high offset frequency phase
noise profile of the internal VCO and the good low offset frequency phase noise of the reference VCXO or
tunable crystal.
Ultra low jitter is achieved by allowing the external VCXO or crystal’s phase noise to dominate the final output
phase noise at low offset frequencies and the internal (or external) VCO’s phase noise to dominate the final
output phase noise at high offset frequencies. This results in best overall phase noise and jitter performance.
The LMK04208 allows subsets of the device to be used to increase the flexibility of device. These different
modes are selected using MODE: Device Mode. For instance:
• Dual Loop Mode - Typical use case of LMK04208. CLKinX used as reference input to PLL1, OSCin port is
connected to VCXO or tunable crystal.
• Single Loop Mode - Powers down PLL1. OSCin port is used as reference input.
• Clock Distribution Mode - Allows input of CLKin1 to be distributed to output with division, digital delay, and
analog delay.
See Device Functional Modes for more information on these modes.
18
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Overview (continued)
8.1.2 PLL1 Redundant Reference Inputs (CLKin0/CLKin0* and CLKin1/CLKin1*)
The LMK04208 has two reference clock inputs for PLL1: CLKin0 and CLKin1. Ref Mux selects CLKin0 or
CLKin1. Automatic or manual switching occurs between the inputs.
CLKin0 and CLKin1 each have input dividers. The input divider allows different clock input frequencies to be
normalized so that the frequency input to the PLL1 R divider remains constant during automatic switching. By
programming these dividers such that the frequency presented to the input of the PLL1 R divider is the same
prevents the user from needing to reprogram the PLL1 R divider when the input reference is changed to another
CLKin port with a different frequency.
CLKin1 is shared for use as an external 0-delay feedback (FBCLKin), or for use with an external VCO (Fin).
Fast manual switching between reference clocks is possible with external pins Status_CLKin0 and
Status_CLKin1.
8.1.3 PLL1 Tunable Crystal Support
The LMK04208 integrates a crystal oscillator on PLL1 for use with an external crystal and varactor diode to
perform jitter cleaning.
The LMK04208 must be programmed to enable Crystal mode.
8.1.4 VCXO/Crystal Buffered Output
The LMK04208 provides a dedicated output, OSCout, which is a buffered copy of the PLL2 reference input (see
Functional Block Diagram for a block diagram of this implementation). The PLL2 reference input is typically a low
noise VCXO or Crystal. When using a VCXO, this output can be used to clock external devices such as
microcontrollers, FPGAs, CPLDs, and so forth, before the LMK04208 is programmed. See Clock Output
Synchronization and MODE: Device Mode for further reference of these outputs
The OSCout buffer output type is programmable to LVDS, LVPECL, or LVCMOS.
The dedicated output buffer OSCout can output frequency lower than the VCXO or Crystal frequency by
programming the OSC Divider. The OSC Divider value range is 2 to 8.
Two clock outputs can also be programmed to be driven by OSCin. This allows a total of 2 additional differential
outputs to be buffered outputs of OSCin. When programmed in this way, a total of 3 differential or 6 single-ended
outputs can be driven by a buffered copy of OSCin.
VCXO/Crystal buffered outputs cannot be synchronized to the VCO clock distribution outputs. The assertion of
SYNC will still cause these outputs to become low temporarily. Since these outputs will turn off and on
asynchronously with respect to the VCO sourced clock outputs during a SYNC, it is possible for glitches to occur
on the buffered clock outputs when SYNC is asserted and unasserted. If the NO_SYNC_CLKoutX bits are set
these outputs will not be affected by the SYNC event except that the phase relationship will change with the
other synchronized clocks unless a buffered clock output is used as a qualification clock during SYNC.
8.1.5 Frequency Holdover
The LMK04208 supports holdover operation to keep the clock outputs on frequency with minimum drift when the
reference is lost until a valid reference clock signal is re-established.
8.1.6 Integrated Loop Filter Poles
The LMK04208 features programmable 3rd and 4th order loop filter poles for PLL2. These internal resistors and
capacitor values may be selected from a fixed range of values to achieve either a 3rd or 4th order loop filter
response. The integrated programmable resistors and capacitors compliment external components mounted near
the chip.
These integrated components can be effectively disabled by programming the integrated resistors and capacitors
to their minimum values.
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Overview (continued)
8.1.7 Internal VCO
The output of the internal VCO is routed to a mux which allows the user to select either the direct VCO output or
a divided version of the VCO for the Clock Distribution Path. This same selection is also fed back to the PLL2
phase detector through a prescaler and N-divider.
The mux selectable VCO divider has a divide range of 2 to 8 with 50% output duty cycle for both even and odd
divide values.
The primary use of the VCO divider is to achieve divides greater than the clock output divider supports alone.
8.1.8 External VCO Mode
The Fin/Fin* input allows an external VCO to be used with PLL2 of the LMK04208. An external VCO may be
needed to meet stringent output phase noise/jitter requirements in some applications, such as multi-carrier GSM.
An external VCO is permitted in single PLL, dual PLL, or 0-delay dual PLL mode. In 0-delay dual PLL mode, the
clock outputs driven from the external VCO can have deterministic phase with the clock input.
Using an external VCO reduces the number of available clock inputs by one. The VCO divider cannot be used
with an external VCO.
8.1.9 Clock Distribution
The LMK04208 features a total of 6 differential outputs driven from the internal or external VCO.
All VCO driven outputs have programmable output types. They can be programmed to LVPECL, LVDS, or
LVCMOS. When all distribution outputs are configured for LVCMOS or single ended LVPECL a total of 12
outputs are available.
If the buffered OSCin output OSCout is included in the total number of clock outputs the LMK04208 is able to
distribute, then up to 7 differential clocks or up to 14 single-ended clocks may be generated with the LMK04208.
The following sections discuss specific features of the clock distribution channels that allow the user to control
various aspects of the output clocks.
8.1.9.1 CLKout DIVIDER
Each clock has a single clock output divider. The divider supports a divide range of 1 to 1045 (even and odd)
with 50% output duty cycle. When divides of 26 or greater are used, the divider/delay block uses extended mode.
The VCO Divider may be used to reduce the divide needed by the clock group divider so that it may operate in
normal mode instead of extended mode. This can result in a small current saving if enabling the VCO Divider
allows 3 or more clock output divides to change from extended to normal mode.
8.1.9.2 CLKout Delay
See Clock Distribution section for details on both a fine (analog) and coarse (digital) delay for phase adjustment
of the clock outputs.
The fine (analog) delay allows a nominal 25-ps step size and range from 0 to 475 ps of total delay. Enabling the
analog delay adds a nominal 500 ps of delay in addition to the programmed value. When adjusting analog delay,
glitches may occur on the clock outputs being adjusted. Analog delay may not operate at frequencies above the
minimum-ensured maximum output frequency of 1536 MHz.
The coarse (digital) delay allows a group of outputs to be delayed by 4.5 to 12 clock distribution path cycles in
normal mode, or from 12.5 to 522 VCO cycles in extended mode. The delay step can be as small as half the
period of the clock distribution path by using the CLKoutX_HS bit provided the output divide value is greater than
1. For example, a 2-GHz VCO frequency without the use of the VCO divider results in 250 ps coarse tuning
steps. The coarse (digital) delay value takes effect on the clock outputs after a SYNC event.
20
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Overview (continued)
There are 3 different ways to use the digital (coarse) delay:
1. Fixed Digital Delay
2. Absolute Dynamic Digital Delay
3. Relative Dynamic Digital Delay
These are further discussed in Clock Distribution.
8.1.9.3 Programmable Output Type
For increased flexibility all LMK04208 clock outputs (CLKoutX) and OSCout can be programmed to an LVDS,
LVPECL, or LVCMOS output type.
Any LVPECL output type can be programmed to 700-, 1200-, 1600-, or 2000-mVpp amplitude levels. The 2000mVpp LVPECL output type is a Texas Instruments proprietary configuration that produces a 2000-mVpp
differential swing for compatibility with many data converters and is also known as 2VPECL.
8.1.9.4 Clock Output Synchronization
Using the SYNC input causes all active clock outputs to share a rising edge. See Clock Output Synchronization
(SYNC) for more information.
The SYNC event also causes the digital delay values to take effect.
8.1.10 0-Delay
The 0-delay mode synchronizes the input clock phase to the output clock phase. The 0-delay feedback may be
performed with an internal feedback loop from any of the clock groups or with an external feedback loop into the
FBCLKin port as selected by the FEEDBACK_MUX.
Without using 0-delay mode, there will be D possible fixed phase relationships from clock input to clock output
depending on the clock output divide value.
Using an external 0-delay feedback reduces the number of available clock inputs by one.
8.1.11 Default Startup Clocks
Before the LMK04208 is programmed, CLKout4 is enabled and operating at a nominal frequency and CLKout3
and OSCout are enabled and operating at the OSCin frequency. These clocks can be used to clock external
devices such as microcontrollers, FPGAs, CPLDs, and so forth, before the LMK04208 is programmed.
For CLKout3 and OSCout to work before the LMK04208 is programmed, the device must not be using Crystal
mode.
8.1.12 Status Pins
The LMK04208 provides status pins which can be monitored for feedback or in some cases used for input
depending upon device programming. For example:
• The Status_Holdover pin may indicate if the device is in hold-over mode.
• The Status_CLKin0 pin may indicate the LOS (loss-of-signal) for CLKin0.
• The Status_CLKin0 pin may be an input for selecting the active clock input.
• The Status_LD pin may indicate if the device is locked.
The status pins can be programmed to a variety of other outputs including analog lock detect, PLL divider
outputs, combined PLL lock detect signals, PLL1 Vtune railing, readback, and so forth. Refer to the Programming
of this datasheet for more information. Default pin programming is captured in Table 17.
8.1.13 Register Readback
Programmed registers may be read back using the MICROWIRE interface. For readback, one of the status pins
must be programmed for readback mode.
At no time may registers be programed to values other than the valid states defined in the datasheet.
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CLKin0 Divider
(1, 2, 4, or 8)
CLKin1*/Fin*
FBCLKin*
CLKin1/
Fin/FBCLKin
CLKin1 Divider
(1, 2, 4, or 8)
Fin/Fin*
CLKout0
CLKout1
CLKout2
CLKout3
CLKout4
CLKout5
OSCout
OSCout*
Ref
Mux
OSCout_
OSCout
MUX
_MUX
R Delay
R1 Divider
(1 to 16,383)
Phase
Detector
PLL1
N1 Divider
(1 to 16,383)
N Delay
Status_LD
Status_Holdover
Status_CLKin0
Status_CLKin1
CLKuWire
FBMux
PWire
Port
DATAuWire
Holdover
FB
Mux
Device
Control
SYNC
Control
Registers
LEuWire
Mode
Mux2
CPout2
CLKin0*
CLKin0
CPout1
8.2 Functional Block Diagram
2X
2X
Mux
OSC Divider
(2 to 8)
N2 Divider
(1 to 262,143)
Mode
Mux3
FBMux
R2 Divider
(1 to 4,095)
N2 Prescaler
(2 to 8)
OSCin*
OSCin
Phase
Detector
PLL2
Clock Distribution Path
Mode
Mux1
Partially
Integrated
Loop Filter
VCO
Mux
Internal VCO
VCO Divider
(2 to 8)
Fin/Fin*
CLKout0
CLKout0*
Mux
Delay
Divider
(1 to 1045)
Digital
Delay
Osc
Mux1
Digital
Delay
Divider
(1 to 1045)
Delay
Digital
Delay
Divider
(1 to 1045)
Delay
Divider
(1 to 1045)
Delay
Mux
CLKout3
CLKout3*
Mux
CLKout4
CLKout4*
Mux
CLKout5
CLKout5*
Clock Buffer 1
CLKout1
CLKout1*
Mux
Delay
Divider
(1 to 1045)
Digital
Delay
Osc
Mux2
Clock Buffer 3
CLKout2
CLKout2*
Mux
Delay
Divider
(1 to 1045)
Digital
Delay
Clock Buffer 2
22
Digital
Delay
Clock Buffer 1
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8.3 Feature Description
8.3.1 Inputs / Outputs
8.3.1.1 PLL1 Reference Inputs (CLKin0 and CLKin1)
The reference clock inputs for PLL1 may be selected from either CLKin0 or CLKin1. The user has the capability
to manually select one of the inputs or to configure an automatic switching mode of operation. See Input Clock
Switching for more info.
CLKin0 and CLKin1 have dividers which allow the device to switch between reference inputs of different
frequencies automatically without needing to reprogram the PLL1 R divider. The CLKin pre-divider values are 1,
2, 4, and 8.
CLKin1 input can alternatively be used for external feedback in 0-delay mode (FBCLKin) or for an external VCO
input port (Fin).
8.3.1.2 PLL2 OSCin / OSCin* Port
The feedback from the external oscillator being locked with PLL1 drives the OSCin/OSCin* pins. Internally this
signal is routed to the PLL1 N Divider and to the reference input for PLL2.
This input may be driven with either a single-ended or differential signal and must be AC coupled. If operated in
single ended mode, the unused input must be connected to GND with a 0.1-µF capacitor.
8.3.1.3 Crystal Oscillator
The internal circuitry of the OSCin port also supports the optional implementation of a crystal based oscillator
circuit. A crystal, a varactor diode, and a small number of other external components may be used to implement
the oscillator. The internal oscillator circuit is enabled by setting the EN_PLL2_XTAL bit. See EN_PLL2_XTAL.
8.3.2 Input Clock Switching
Manual, pin select, and automatic are three different kinds clock input switching modes can be set with the
CLKin_SELECT_MODE register.
Below is information about how the active input clock is selected and what causes a switching event in the
various clock input selection modes.
8.3.2.1 Input Clock Switching - Manual Mode
When CLKin_SELECT_MODE is 0 or 1 then CLKin0 or CLKin1 respectively is always selected as the active
input clock. Manual mode will also override the EN_CLKinX bits such that the CLKinX buffer will operate even if
CLKinX is disabled with EN_CLKinX = 0.
• Entering Holdover: If holdover mode is enabled, then holdover mode is entered if Digital lock detect of PLL1
goes low and DISABLE_DLD1_DET = 0.
• Exiting Holdover: The active clock for automatic exit of holdover mode is the manually selected clock input.
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Feature Description (continued)
8.3.2.2 Input Clock Switching - Pin Select Mode
When CLKin_SELECT_MODE is 3, the pins Status_CLKin0 and Status_CLKin1 select which clock input is
active.
• Clock Switch Event: Pins: Changing the state of Status_CLKin0 or Status_CLKin1 pins causes an input
clock switch event.
• Clock Switch Event: PLL1 DLD: To prevent PLL1 DLD high to low transition from causing a input clock
switch event and causing the device to enter holdover mode, disable the PLL1 DLD detect by setting
DISABLE_DLD1_DET = 1. This is the preferred behavior for Pin Select Mode.
• Configuring Pin Select Mode:
– The Status_CLKin0_TYPE must be programmed to an input value for the Status_CLKin0 pin to function
as an input for pin select mode.
– The Status_CLKin1_TYPE must be programmed to an input value for the Status_CLKin1 pin to function
as an input for pin select mode.
– If the Status_CLKinX_TYPE is set as output, the input value is considered 0.
– The polarity of Status_CLKin1 and Status_CLKin0 input pins cannot be inverted with the CLKin_SEL_INV
bit.
– Table 1 defines which input clock is active depending on Status_CLKin0 and Status_CLKin1 state.
Table 1. Active Clock Input - Pin Select Mode
STATUS_CLKin1
STATUS_CLKin0
ACTIVE CLOCK
0
0
CLKin0
0
1
CLKin1
1
0
Reserved
1
1
Holdover
The pin select mode will override the EN_CLKinX bits such that the CLKinX buffer will operate even if CLKinX is
disabled with EN_CLKinX = 0. To switch as fast as possible, keep the clock input buffers enabled (EN_CLKinX =
1) that could be switched to.
8.3.2.2.1 Pin Select Mode and Host
When in the pin select mode, the host can monitor conditions of the clocking system which could cause the host
to switch the active clock input. The LMK04208 device can also provide indicators on the Status_LD and
Status_HOLDOVER like DAC Rail, PLL1 DLD, PLL1 and PLL2 DLD which the host can use in determining which
clock input to use as active clock input.
8.3.2.2.2 Switch Event without Holdover
When an input clock switch event is triggered and holdover mode is disabled, the active clock input immediately
switches to the selected clock. When PLL1 is designed with a narrow loop bandwidth, the switching transient is
minimized.
8.3.2.2.3 Switch Event with Holdover
When an input clock switch event is triggered and holdover mode is enabled, the device will enter holdover mode
and remain in holdover until a holdover exit condition is met as described in Holdover Mode. Then the device will
complete the reference switch to the pin selected clock input.
8.3.2.3 Input Clock Switching - Automatic Mode
When CLKin_SELECT_MODE is 4, the active clock is selected in priority order of enabled clock inputs starting
upon an input clock switch event. The priority order of the clocks is CLKin0 → CLKin1 → CLKin0, and so forth.
For a clock input to be eligible to be switched through, it must be enabled using EN_CLKinX.
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8.3.2.3.1 Starting Active Clock
Upon programming this mode, the currently active clock remains active if PLL1 lock detect is high. To ensure a
particular clock input is the active clock when starting this mode, program CLKin_SELECT_MODE to the manual
mode which selects the desired clock input (CLKin0 or 1). Wait for PLL1 to lock PLL1_DLD = 1, then select this
mode with CLKin_SELECT_MODE = 4.
8.3.2.3.2 Clock Switch Event: PLL1 DLD
A loss of lock as indicated by PLL1’s DLD signal (PLL1_DLD = 0) will cause an input clock switch event if
DISABLE_DLD1_DET = 0. PLL1 DLD must go high (PLL1_DLD = 1) in between input clock switching events.
8.3.2.3.3 Clock Switch Event: PLL1 Vtune Rail
If Vtune_RAIL_DET_EN is set and the PLL1 Vtune voltage crosses the DAC high or low threshold, holdover
mode will be entered. Since PLL1_DLD = 0 in holdover a clock input switching event will occur.
8.3.2.3.4 Clock Switch Event with Holdover
Clock switch event with holdover enabled is recommended in this input clock switching mode. When an input
clock switch event occurs, holdover mode is entered and the active clock is set to the clock input defined by the
Status_CLKinX pins. When the new active clock meets the holdover exit conditions, holdover is exited and the
active clock will continue to be used as a reference until another input clock switch event. PLL1 DLD must go
high in between input clock switching events.
8.3.2.4 Input Clock Switching - Automatic Mode with Pin Select
When CLKin_SELECT_MODE is 6, the active clock is selected using the Status_CLKinX pins upon an input
clock switch event according to Table 2.
8.3.2.4.1 Starting Active Clock
Upon programming this mode, the currently active clock remains active if PLL1 lock detect is high. To ensure a
particular clock input is the active clock when starting this mode, program CLKin_SELECT_MODE to the manual
mode which selects the desired clock input (CLKin0 or 1). Wait for PLL1 to lock PLL1_DLD = 1, then select this
mode with CLKin_SELECT_MODE = 6.
8.3.2.4.2 Clock Switch Event: PLL1 DLD
An input clock switch event is generated by a loss of lock as indicated by PLL1's DLD signal (PLL1 DLD = 0).
8.3.2.4.3 Clock Switch Event: PLL1 Vtune Rail
If Vtune_RAIL_DET_EN is set and the PLL1 Vtune voltage crosses the DAC threshold, holdover mode will be
entered. Since PLL1_DLD = 0 in holdover, a clock input switching event will occur.
8.3.2.4.4 Clock Switch Event with Holdover
Clock switch event with holdover enabled is recommended in this input clock switching mode. When an input
clock switch event occurs, holdover mode is entered and the active clock is set to the clock input defined by the
Status_CLKinX pins. When the new active clock meets the holdover exit conditions, holdover is exited and the
active clock will continue to be used as a reference until another input clock switch event. PLL1 DLD must go
high in between input clock switching events."
Table 2. Active Clock Input - Auto Pin Mode
STATUS_CLKin1
(1)
(1)
STATUS_CLKin0
ACTIVE CLOCK
X
1
CLKin0
1
0
CLKin1
0
0
Reserved
The polarity of Status_CLKin1 and Status_CLKin0 input pins can be inverted with the CLKin_SEL_INV bit.
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8.3.3 Holdover Mode
Holdover mode causes PLL2 to stay locked on frequency with minimal frequency drift when an input clock
reference to PLL1 becomes invalid. While in holdover mode, the PLL1 charge pump is TRI-STATED and a fixed
tuning voltage is set on CPout1 to operate PLL1 in open loop.
8.3.3.1 Enable Holdover
Program HOLDOVER_MODE to enable holdover mode. Holdover mode can be manually enabled by
programming the FORCE_HOLDOVER bit.
The holdover mode can be set to operate in 2 different sub-modes.
• Fixed CPout1 (EN_TRACK = 0 or 1, EN_MAN_DAC = 1).
• Tracked CPout1 (EN_TRACK = 1, EN_MAN_DAC = 0).
– Not valid when EN_VTUNE_RAIL_DET = 1.
Updates to the DAC value for the Tracked CPout1 sub-mode occurs at the rate of the PLL1 phase detector
frequency divided by DAC_CLK_DIV. These updates occur any time EN_TRACK = 1.
The DAC update rate should be programmed for > CTUNE), so that CTUNE becomes the dominant capacitance.
For a specific value of CL, the corresponding resonant frequency (FL) of the parallel resonant mode circuit is:
1
FL = FS À
C1
2(C0 + CL1)
+ 1 = FS À
§C0
2¨
© C1
+
CL ·
+1
¸
C1 ¹
where
•
•
•
•
FS = Series resonant frequency
C1 = Motional capacitance of the crystal
CL = Load capacitance
C0 = Shunt capacitance of the crystal, specified on the crystal datasheet
(11)
The normalized tuning range of the circuit is closely approximated by:
1
'F FCL1 - FCL2 C1
=
=
F
2
FFCL1
À
1
1
1
=
(C0 + CL1) (C0 + CL2)
2
À
§C0
¨ C1
©
+
CL1·
-
1
§C0
¸ ¨
C1 ¹ © C1
+
CL2·
¸
C1 ¹
(12)
CL1, CL2 = The endpoints of the circuit’s load capacitance range, assuming a variable capacitance element is one
component of the load. FCL1, FCL2 = parallel resonant frequencies at the extremes of the circuit’s load
capacitance range.
A common range for the pullability ratio, C0/C1, is 250 to 280. The ratio of the load capacitance to the shunt
capacitance is ~(n * 1000), n < 10. Hence, picking a crystal with a smaller pullability ratio supports a wider tuning
range because this allows the scale factors related to the load capacitance to dominate.
9.1.8.1 Examples of Phase Noise and Jitter Performance
Examples of the phase noise and jitter performance of the LMK04208 with a crystal oscillator are shown in
Table 116. This table illustrates the clock output phase noise when a 20.48-MHz crystal is paired with PLL1.
Performance of other LMK04208 devices will be similar.
Table 116. Example RMS Jitter and Clock Output Phase Noise for LMK04208
with a 20.48 MHz Crystal Driving OSCin (T = 25 °C, VCC = 3.3 V) (1)
INTEGRATION
BANDWIDTH
CLOCK OUTPUT TYPE
PLL2 PDF = 20.48 MHz
(EN_PLL2_REF2X = 0,
XTAL_LVL = 3)
PLL2 PDF = 40.96 MHz
(EN_PLL2_REF2X = 1, XTAL_LVL = 3)
fCLK = 245.76 MHz
fCLK = 122.88 MHz
fCLK = 245.76 MHz
LVCMOS
374
412
382
LVDS
419
421
372
LVPECL 1.6 Vpp
460
448
440
LVCMOS
226
195
190
LVDS
231
205
194
LVPECL 1.6 Vpp
226
191
188
RMS JITTER (fs, RMS)
100 Hz – 20 MHz
10 kHz – 20 MHz
(1)
Performance data and crystal specifications contained in this section are based on Vectron model VXB1-1150-20M480, 20.48 MHz.
PLL1 has a narrow loop bandwidth, PLL2 loop parameters are: C1 = 150 pF, C2 = 120 nF, R2 = 470 Ω, Charge Pump current = 3.2 mA,
Phase detector frequency = 20.48 MHz or 40.96 MHz, VCO frequency = 2949.12 MHz. Loop filter was optimized for 40.96 MHz phase
detector performance.
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Table 116. Example RMS Jitter and Clock Output Phase Noise for LMK04208
with a 20.48 MHz Crystal Driving OSCin (T = 25 °C, VCC = 3.3 V) (1) (continued)
INTEGRATION
BANDWIDTH
CLOCK OUTPUT TYPE
PLL2 PDF = 20.48 MHz
(EN_PLL2_REF2X = 0,
XTAL_LVL = 3)
fCLK = 245.76 MHz
PLL2 PDF = 40.96 MHz
(EN_PLL2_REF2X = 1, XTAL_LVL = 3)
fCLK = 122.88 MHz
fCLK = 245.76 MHz
PHASE NOISE (dBc/Hz)
Offset
100 Hz
1 kHz
10 kHz
100 kHz
1 MHz
40 MHz
110
Clock Output Type
PLL2 PDF = 20.48 MHz
(EN_PLL2_REF2X = 0,
XTAL_LVL = 3)
PLL2 PDF = 40.96 MHz
(EN_PLL2_REF2X = 1, XTAL_LVL = 3)
fCLK = 245.76 MHz
fCLK = 122.88 MHz
fCLK = 245.76 MHz
LVCMOS
-87
-93
-87
-86
LVDS
-86
-91
LVPECL 1.6 Vpp
-86
-92
-85
LVCMOS
-115
-121
-115
LVDS
-115
-123
-116
LVPECL 1.6 Vpp
-114
-122
-116
LVCMOS
-117
-128
-122
LVDS
-117
-128
-122
LVPECL 1.6 Vpp
-117
-128
-122
LVCMOS
-130
-135
-129
LVDS
-130
-135
-129
LVPECL 1.6 Vpp
-129
-135
-129
LVCMOS
-150
-154
-148
LVDS
-149
-153
-148
LVPECL 1.6 Vpp
-150
-154
-148
LVCMOS
-159
-162
-159
LVDS
-157
-159
-157
LVPECL 1.6 Vpp
-159
-161
-159
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Example crystal specifications are presented in Table 117.
Table 117. Example Crystal Specifications
PARAMETER
VALUE
Nominal Frequency (MHz)
20.48
Frequency Stability, T = 25 °C
± 10 ppm
Operating temperature range
-40 °C to +85 °C
Frequency Stability, -40 °C to +85 °C
± 15 ppm
Load Capacitance
14 pF
Shunt Capacitance (C0)
5 pF Maximum
Motional Capacitance (C1)
20 fF ± 30%
Equivalent Series Resistance
25 Ω Maximum
Drive level
2 mWatts Maximum
C0/C1 ratio
225 typical, 250 Maximum
See Figure 37 for a representative tuning curve.
180
140
100
PPM
60
20
-20
-60
-100
-140
-180
0.0 0.4 0.8 1.2 1.6 2.0 2.4 2.8 3.2
VTUNE(V)
Figure 37. Example Tuning Curve, 20.48-MHz Crystal
The tuning curve achieved in the user's application may differ from the curve shown above due to differences in
PCB layout and component selection.
This data is measured on the bench with the crystal integrated with the LMK04208. Using a voltmeter to monitor
the VTUNE node for the crystal, the PLL1 reference clock input frequency is swept in frequency and the resulting
tuning voltage generated by PLL1 is measured at each frequency. At each value of the reference clock
frequency, the lock state of PLL1 should be monitored to ensure that the tuning voltage applied to the crystal is
valid.
The curve shows over the tuning voltage range of 0.3 VDC to 3.0 VDC, the frequency range is -140 to +91 ppm;
or equivalently, a tuning range of -2850 Hz to +1850 Hz. The measured tuning voltage at the nominal crystal
frequency (20.48 MHz) is 1.7 V. Using the diode data sheet tuning characteristics, this voltage results in a tuning
capacitance of approximately 6.5 pF.
The tuning curve data can be used to calculate the gain of the oscillator (KVCO). The data used in the calculations
is taken from the most linear portion of the curve, a region centered on the crossover point at the nominal
frequency (20.48 MHz). For a well designed circuit, this is the most likely operating range. In this case, the tuning
range used for the calculations is ± 1000 Hz (± 0.001 MHz), or ± 81.4 ppm. The simplest method is to calculate
the ratio:
KVCO =
'F
=
'V
§ 'F2 - 'F1 · MHz
¨ VTUNE2 - VTUNE1¸ , V
©
¹
(13)
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ΔF2 and ΔF1 are in units of MHz. Using data from the curve this becomes:
0.001 - (-0.001)
MHz
= 0.00164
2.03 - 0.814
V
(14)
A second method uses the tuning data in units of ppm:
KVCO =
FNOM À ('ppm2 - 'ppm1)
'V À 10
6
(15)
FNOM is the nominal frequency of the crystal and is in units of MHz. Using the data, this becomes:
12.288 À (81.4 - (-81.4))
(2.03 - 0.814) À 10
6
= 0.00164,
MHz
V
(16)
In order to ensure startup of the oscillator circuit, the equivalent series resistance (ESR) of the selected crystal
should conform to the specifications listed in the table of Electrical Characteristics.
It is also important to select a crystal with adequate power dissipation capability, or drive level. If the drive level
supplied by the oscillator exceeds the maximum specified by the crystal manufacturer, the crystal will undergo
excessive aging and possibly become damaged. Drive level is directly proportional to resonant frequency,
capacitive load seen by the crystal, voltage and equivalent series resistance (ESR).
For more complete coverage of crystal oscillator design, see:
Clocks and Timers or AN-1939 Crystal Based Oscillator Design with the LMK04000 Family.
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9.2 Typical Applications
Normal use case of the LMK04208 device is as a dual loop jitter cleaner. This section will discuss a design
example to illustrate the various functional aspects of the LMK04208 device.
R
N
Phase
Detector
PLL1
PLL2
External VCXO
or Tunable
Crystal
External
Loop Filter
OSCout
OSCout*
OSCin
CLKinX
CLKinX*
2 inputs
CPout1
PLL1
External
Loop Filter
CPout2
R
Input
Buffer
N
Phase
Detector
PLL2
Divider
Digital Delay
Analog Delay
Partially
Integrated
Loop Filter
Internal
VCO
CLKoutX
CLKoutX*
6 outputs
6 blocks
LMK04208
Figure 38. Simplified Functional Block Diagram for Dual Loop Mode
9.2.1 Design Requirements
Given a remote radio head (RRU) type application which needs to clock some ADCs, DACs, FPGA, SERDES,
and an LO. The input clock will be a recovered clock which needs jitter cleaning. The FPGA clock should have a
clock output on power up. A summary of clock input and output requirements are as follows:
Clock Input:
• 30.72-MHz recovered clock.
Clock Outputs:
• 1x 245.76-MHz clock
• 2x 983.04-MHz clock
• 1x 122.88-MHz clock
• 1x 122.88-MHz clock
• 2x 122.88-MHz clock
for ADC, LVPECL
for DAC, LVPECL
for FPGA, LVDS. POR clock
for SERDES, LVPECL
for LO, LVCMOS
It is also desirable to have the holdover feature engage if the recovered clock reference is ever lost. The
following information reviews the steps to produce this design.
9.2.2 Detailed Design Procedure
Design of all aspects of the LMK04208 are quite involved and software has been written to assist in part
selection, part programming, loop filter design, and simulation. This design procedure will give a quick outline of
the process.
Note that this information is current as of the date of the release of this datasheet. Design tools receive
continuous improvements to add features and improve model accuracy. Refer to software instructions or training
for latest features.
1. Device Selection
– the key to device selection is required VCO frequency given required output frequencies. The device
must be able to produce the VCO frequency that can be divided down to required output frequencies.
– The software design tools will take into account VCO frequency range for specific devices based on the
application's required output frequencies. Using an external VCO provides increased flexibility regarding
valid designs.
– To understand the process better, refer to Frequency Planning with the LMK04208 for more detail on
calculating valid VCO frequency when using integer dividers using the least common multiple (LCM) of
the output frequencies.
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Typical Applications (continued)
2. Device Configuration
– There are many possible permutations of dividers and other registers to get same input and output
frequencies from a device. However there are some optimizations and trade-offs to be considered.
– If more than one divider is in series, for instance VCO divider to CLKout divider, or VCO divider to PLL
prescaler to PLL N. It is possible although not assured that some crosstalk/mixing could be created
when using some divides.
– The design software normally attempts to maximize phase detector frequency, use smallest dividers, and
maximizes PLL charge pump current.
– When an external VCXO or crystal is used for jitter cleaning, the design software will choose the
maximum frequency value, depending on design software options, this max frequency may be limited to
standard value VCXOs/Crystals. Note, depending on application, different frequency VCXOs may be
chosen to generate some of the required output frequencies.
– Refer to PLL Programming for divider equations need to ensure PLL is locked. The design software is
able to configure the device for most cases, but at this time for advanced features like 0-delay, the
user must take care to ensure proper PLL programming.
– These guidelines may be followed when configuring PLL related dividers or other related registers:
– For lowest possible in-band PLL flat noise, maximize phase detector frequency to minimize N divide
value.
– For lowest possible in-band PLL flat noise, maximize charge pump current. The highest value charge
pump currents often have similar performance due to diminishing returns.
– To reduce loop filter component sizes, increase N value and/or reduce charge pump current.
– Large capacitors help reduce phase detector spurs at phase detector frequency caused by external
VCOs/VCXOs with low input impedance.
– As rule of thumb, keeping the phase detector frequency approximately between 10 * PLL loop
bandwidth and 100 * PLL loop bandwidth. A phase detector frequency less than 5 * PLL bandwidth
may be unstable and a phase detector frequency > 100 * loop bandwidth may experience increased
lock time due to cycle slipping. However for clock generation/jitter cleaning applications, lock time is
typically not critical and large phase detector frequencies typically result in reduced PLL noise, so
cycle-slipping during lock is acceptable.
3. PLL Loop Filter Design
– TI recommends using Clock Architect to design your loop filter.
– Best loop filter design and simulation can be achieved when:
– Custom reference and VCXO phase noise profiles are loaded into the software.
– VCO gain of the external VCXO or possible external VCO device are entered.
– The design tool will return solutions with high reference/phase detector frequencies and high charge
pump currents by default. It is possible to reduce the phase detector frequency charge pump current in
Clock Architect. Due to the narrow loop bandwidth used on PLL1, it is common to lower the phase
detector frequency and/or charge pump current on PLL1 to reduce component size.
– While designing loop filter, adjusting the charge pump current or N value can help with loop filter
component selection. Lower charge pump currents and larger N values result in smaller component
values but may increase impacts of leakage and reduce PLL phase noise performance.
– More detailed understanding of loop filter design can found in Dean Banerjee's PLL Performance,
Simulation, and Design (www.ti.com/tool/pll_book).
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Typical Applications (continued)
4. Clock Output Assignment
– At this time the design software does not take into account frequency assignment to specific outputs
except to ensure that the output frequencies can be achieved. It is best to consider proximity of each
clock output to each other and other PLL circuitry when choosing final clock output locations. Here are
some guidelines to help achieve best performance when assigning outputs to specific CLKout/OSCout
pins.
– Group common frequencies together.
– PLL charge pump circuitry can cause crosstalk at charge pump frequency. Place outputs sharing
charge pump frequency or lower priority outputs not sensitive to charge pump frequency spurs
together.
– Muxes can create a path for noise coupling. Consider all frequencies which may have some bleed
through from non-selected mux inputs.
– For example, LMK04208 CLKout3 and CLKout4 share a mux with OSCin.
– Some clock targets require low close-in phase noise. If possible, use a VCXO based PLL1 output from
CLKout3 or CLKout4 for such a clock target. An example is a clock to a PLL reference.
– Some clock targets require excellent noise floor performance. Outputs driven by the internal VCO have
the best noise floor performance. An example is an ADC or DAC.
5. Other device specific configuration. For LMK04208, consider the following:
– PLL lock time based on programming:
– In addition to the time it takes the device to lock to frequency, there is a digital filter to avoid false lock
time detects which can also be used to ensure a specific PPM frequency accuracy. This also impacts
the time it takes for the digital lock detect (DLD) pin to be asserted. Refer to Digital Lock Detect
Frequency Accuracy for more information.
– Holdover configuration:
– Specific PPM frequency accuracy required to exit holdover can be programmed. Refer to Digital Lock
Detect Frequency Accuracy for more information.
– Digital delay: phase alignment of the output clocks.
– Analog delay: another method to shift phases of clocks with finer resolution with the penalty of increase
noise floor.
– Dynamic digital delay: ability to shift phase alignment of clocks with minimum disruption during operation.
6. Device Programming
– The software tool TICS Pro for EVM programming can be used to setup the device in the desired
configuration, then export a hex register map suitable for use in application.
Some additional information on each part of the design procedure for the RRU example is below.
9.2.2.1 Device Selection
Use the WEBENCH Clock Architect Tool. Enter the required frequencies and formats into the tool. To use this
device, find a solution using the LMK04208.
9.2.2.1.1 Clock Architect
When viewing resulting solutions, it is possible to narrow the parts used in the solution by setting a filter.
Filtering of a specific device can be done by selecting the device from the filter combo box. Also, regular
expressions can be typed into filter combo box. LMK04208 will filter for only the LMK04208 device.
To simulate single loop solutions with dual loop device, set PLL1 loop filter to a very narrow or "0 Hz LBW."
9.2.2.1.2 Calculation Using LCM
In this example, the LCM(245.76 MHz, 983.04 MHz, 122.88 MHz) = 983.04 MHz. A valid VCO frequency for
LMK04208 is 2949.12 MHz = 3 * 983.04 MHz. Therefore the LMK04208 may be used to produce these output
frequencies.
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Typical Applications (continued)
9.2.2.2 Device Configuration
The tools automatically configure the simulation to meet the input and output frequency requirements given and
make assumptions about other parameters to give some default simulations. The assumptions made are to
maximize input frequencies, phase detector frequencies, and charge pump currents while minimizing VCO
frequency and divider values.
9.2.2.2.1 PLL LO Reference
PLL1 outputs have the best phase noise performance for LO references. As such OSCout, or CLKout3/CLKout4
(with CLKout#_OSCin_Sel field selecting OSCin clock source) can be used to provide the 122.88 MHz LO
reference clock. To achieve this with a 245.76 MHz VCXO the OSCout_DIV can be set to 2 to provide 122.88
MHz at OSCout. CLKout3/4_DIV can be set to 2 for 122.88 MHz output if LO references are clocked from
CLKout3/4.
In the next section it is determined that for the POR clock, a 122.88 MHz VCXO will be used. This means no
division will be needed to provide 122.88 MHz.
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Typical Applications (continued)
9.2.2.2.2 POR Clock
If OSCout is to be used for LVDS POR 122.88 MHz clock, the POR value of the OSCout_DIV is 1, so a 122.88
MHz VCXO frequency must be chosen. This may be desired anyway since the phase detector frequency is
limited to 122.88 MHz and lower frequency VCXOs tend to cost less. With this change the OSCin frequency and
phase detector frequency are the same, so the doubler must be enabled and the PLL2 R divider programmed =
2 to follow the rule stated in PLL2 Frequency Doubler.
Note: it is possible to set the PLL2 R = 0.5 to simulate the doubler in-case lower frequency VCXOs would like to
be simulated. For example a 61.44 MHz VCXO could be used while retaining a 122.88 MHz phase detector
frequency. However, it would reduce the LO reference frequency and POR clock frequency to 61.44 MHz.
At this time, the VCXO frequency and phase detector frequency is chosen, so loop filter design may begin.
9.2.2.3 PLL Loop Filter Design
The PLL structure for the LMK04208 is illustrated in Loop Filter.
At this time the user may choose to make adjustments to the simulation tools for more accurate simulations to
their application. For example:
• Clock Architect allows loading a custom phase noise plot for any block. Typically, a custom phase noise plot
is entered for CLKin to match the reference phase noise to the device; a phase noise plot for the VCXO can
additionally be provided to match the performance of VCXO used. For improved accuracy in simulation and
optimum loop filter design, be sure to load these custom noise profiles for use in application. After loading a
phase noise plot, user should recalculate the recommended loop filter design.
• The Clock Architect will return solutions with high reference/phase detector frequencies by default. The user
may decrease the phase detector frequency if desired. Be sure to decrease by integer relationships with the
reference as an integer divider will be used. Due to the narrow loop bandwidth used on PLL1, it is common to
reduce the phase detector frequency on PLL1 by increasing PLL1 R.
For this example, for PLL1 to perform jitter cleaning and to minimize jitter from PLL2 used for frequency
multiplication:
• PLL1: A narrow loop bandwidth PLL1 filter was design by updating the loop bandwidth to 50 Hz and phase
margin to 50 degrees.
• PLL2:
– VCXO noise profile is measured, then loaded into VCXO phase noise profile in Clock Architect. Be sure
that the VCO frequency of PLL1 is as desired. If changing the VC(X)O frequency of PLL1, be sure to the
PLL2 Phase Detector frequency aligns with an integer divider.
– The recommended loop filter is redesigned. Updates to the PLL1 loop filter and VCXO phase noise may
change the loop filter recommendation, so PLL2 loop filter may need to be recalculated.
The next two sections will discuss PLL1 and PLL2 loop filter design specific to this example using default phase
noise profiles.
NOTE
Clock Architect provides some recommend loop filters upon first load of the simulation.
Anytime PLL related inputs change like an input phase noise, charge pump current,
divider values, and so forth. it is best to re-design the PLL1 loop filter to the recommended
design or your desired parameters. After PLL1, then update the PLL2 loop filter in the
same way to keep the loop filters designed and optimized for the application. Since PLL1
loop filter design may impact PLL2 loop filter design, be sure to update the designs in
order.
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Typical Applications (continued)
9.2.2.3.1 PLL1 Loop Filter Design
For this example, in the Clock Architect tool update the loop bandwidth for 0.05 kHz and the phase margin for 50
degrees and press "Choose RC Components for me." With the 30.72 MHz phase detector frequency and 1.6 mA
charge pump; the designed loop filter's largest capacitor, C2, is 27 µF. Supposing a goal of < 10 µF; setting PLL1
R = 4 and pressing the calculate again shows that C2 is 6.8 µF. Suppose that a reduction to < 1 µF is desired,
continuing to increase the PLL1 R to 8 resulting in a phase detector frequency of 3.84 MHz and reducing the
charge pump current from 1.6 mA to 0.4 mA and calculating again shows that C2 is 820 nF. As N was increased
and charge pump decreased, this final design has R2 = 12 kΩ. The first design with low N value and high charge
pump current result in R2 = 390 Ω. The impact of the thermal resistance is calculated in the tool. Viewing the
simulation of the loop filter with the 12-kΩ resistor shows that the thermal noise in the loop is not impacting
performance.
It may be desired to design a 3rd order loop filter for additional attenuation input noise and spurs
With the PLL1 loop filter design complete, PLL2's loop filter is ready to be designed.
9.2.2.3.2 PLL2 Loop Filter Design
In Clock Architect, select LOOPFILTER2 tab under Loop Filters tab. Click "Choose RC Components for me." For
PLL2's loop filter maximum phase detector frequency and maximum charge pump current are typically used.
Typically the jitter integration bandwidth includes the loop filter bandwidth for PLL2. The recommended loop filter
by the tools are designed to minimize jitter. The integrated loop filter components are minimized with this
recommendation as to allow maximum flexibility in achieve wide loop bandwidths for low PLL noise. With the
recommended loop filter calculated, this loop filter is ready to be simulated.
If using integrated components is desired, make adjustments to the integrated components. The effective loop
bandwidth and phase margin with these updates is calculated every time "Update Actual Loop Parameters" is
clicked. The integrated loop filter components are good to use when attempting to eliminate some spurs since
they provide filtering after the bond wires. The recommended procedure is to increase C3/C4 capacitance, then
R3/R4 resistance. Large R3/R4 resistance can result in degraded VCO phase noise performance.
9.2.2.4 Clock Output Assignment
At this time Clock Architect only assign outputs to specific clock outputs numerically; not necessarily by optimum
configuration. The user may wish to make some educated re-assignment of outputs.
During device configuration, some output assignment was discussed since it impacted the part's configuration
relating to loop filter design, such as:
• In this example, OSCout can be used to provide the power on reset (POR) start-up clock to the FPGA at
122.88 MHz since the VCXO frequency is the same as the output frequency.
• Since PLL1 outputs have best in-band noise, CLKout3 is used with CLKout3_OSCin_Sel = 0x01 (OSCin) to
provide a PLL1 based output. LVCMOS (Norm/Inv) is used instead of LVCMOS (Norm/Norm) to reduce
crosstalk. If OSCout was not needed for FPGA start-up clock, OSCout could have been used to provide the
LO reference clocks with lower noise floor, but close-in noise is typically of more concern since noise above
the loop bandwidth of the LO will be dominated by the VCO of the LO. See Figure 39.
Since CLKout3 and CLKout4 have a mux allowing them to be driven by the VCXO and due there is a chance for
some 122.88 MHz crosstalk from the VCXO. The 122.88 MHz SERDES clock will be placed on CLKout4 since it
will not be sensitive to crosstalk as it is operating at the same frequency.
Three converter clocks still need to be assigned. The 245.76 MHz ADC clock and two 983.04 MHz DAC. There
are four remaining clock outputs. To maximize distance of the ADC clock from other clocks which could create
sub-harmonic spurs, CLKout0 is chosen for ADC at 245.76 MHz clock. CLKout1 and CLKout2 are chosen for the
DAC 983.04 MHz clocks. Because the ADC clock is often the most sensitive to sub-harmonic spurs, the goal
was to place the ADC clock as far as possible from other clocks which could result in sub-harmonic spurs.
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Typical Applications (continued)
9.2.2.5 Other Device Specific Configuration
9.2.2.5.1 Digital Lock Detect
Digital lock time for PLL1 will ultimately depend upon the programming of the PLL1_DLD_CNT register as
discussed in Digital Lock Detect Frequency Accuracy. Since the PLL1 phase detector frequency in this example
is 3.84 MHz, the lock time will = 1 / (PLL1_DLD_CNT * 3.84 MHz)
Digital lock time for PLL1 if PLL1_DLD_CNT = 10000 is just over 2.6 ms. When using holdover, it is very
important to program the PLL1_DLD_CNT to a value large enough to prevent false digital lock detect signals.
If PLL1_DLD_CNT is too small, when the device exits holdover and is re-locking, the DLD will go high while the
phase of the reference and feedback are within the specified window size because the programmed
PLL1_DLD_CNT will be satisfied. However, if the loop has not yet settled to without the window size, when the
phases of the reference and feedback once again exceed the window size, the DLD will return low. Provided that
DISABLE_DLD1_DET = 0, the device once again enter holdover. Assuming that the reference clock is valid
because holdover was just exited, the exit criteria will again be met, holdover will exit, and PLL1 will start locking.
Unfortunately, the same sequence of events will repeat resulting in oscillation out-of and back-into holdover.
Setting the PLL1_DLD_CNT to an appropriately large value prevents chattering of the PLL1 DLD signal and
stable holdover operation can be achieved.
Refer to Digital Lock Detect Frequency Accuracy for more detail on calculating exit times and how the
PLL1_DLD_CNT and PLL1_WND_SIZE work together.
9.2.2.5.2 Holdover
For this example, when the recovered clock is lost, the goal is to set the VCXO to Vcc/2 until the recovered clock
returns. Holdover Mode contains detailed information on how to program holdover.
To
•
•
•
•
•
achieve the above goal, fixed holdover will be used. Program:
HOLDOVER_MODE = 2 (Holdover enabled)
EN_TRACK = 0 (Tracking disabled)
EN_MAN_DAC = 1 (Use manual DAC for holdover voltage value)
MAN_DAC = 512 (Approximately Vcc/2)
DISABLE_DLD1_DET = 0 (Use PLL1 DLD = Low to start holdover)
9.2.2.6 Device Programming
The TICS Pro software is used to program the LMK04208 evaluation board using the LMK04208 profile. It also
allows the exporting of a register map which can be used to program the device to the user’s desired
configuration.
Once a configuration has been achieved using the TICS Pro to meet the requested input/output frequencies with
the desired performance, the TICS Pro software is manually updated with this information to meet the required
application. At this time no automatic import exists.
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Typical Applications (continued)
9.2.3 Application Curve
-130
VCO CLKoutX
VCXO CLKout3,4
VCXO OSCout
VCXO Direct
Phase Noise (dBc/Hz)
-135
-140
-145
-150
-155
-160
-165
-170
1k
10k
100k
1M
Frequency Offset (Hz)
10M
D001
Figure 39. LVPECL Phase Noise, 122.88 MHz
Illustration of Different Performance Depending on Signal Path
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9.3 System Examples
9.3.1 System Level Diagram
Figure 40 and Figure 41 show an LMK04208 device with external circuitry for clocking and for power supply to
serve as a guideline for good practices when designing with the LMK04208. Refer to Pin Connection
Recommendations for more details on the pin connections and bypassing recommendations. Also refer to the
evaluation board in LMK0480x Evaluation Board Instructions. PCB design will also play a role in device
performance. As discussed in PLL LO Reference , the LO clocks at 122.88 MHz may be moved to CLKout5 if the
VCXO frequency will support 122.88 MHz output.
Status_CLKin0
240 Ö
Status_CLKin1
To Host
processor
0.1 PF
CLKout0
Status_LD
CLKout0*
Status_HOLDOVER
0.1 PF
SYNC
LVPECL clock
to ADC at
245.76 MHz
240 Ö
LEuWire
CLKuWire
240 Ö
DATAuWire
0.1 PF
CLKout1, 2
Recovered
Reference
Clock
0.1 PF
CLKout1*,2*
CLKin0
0.1 PF
CLKin0*
50 Ö
2x LVPECL
clocks to DAC at
983.04 MHz
240 Ö
0.1 PF
LMK04208
0.1 PF
2x LVCMOS
clocks to LO at
122.88 MHz
CLKout3
CLKout3*
CLKin1
100 Ö
CLKin1*
CLKout4
TCXO
0.1 PF
CLKout4*
0.1 PF
CLKout 3 and 4 active at startup
OSCin*
OSCin
VCXO
Rterm
CLKout5
0.1 PF
CLKout5*
Unused
OSCout
1x LVDS clock
to FPGA at
122.88 MHz
LDObyp1
LDObyp2
OSCout*
LF1_C1
LF2_C2
OSCout on at start-up at OSCin
frequency as LVDS output
CPout2
0.1 PF
CPout1
10 PF
1x LVDS clock to
SERDES at
122.88 MHz
LF1_R3
LF1_C3
LF1_C2
LF1_R2
PLL1 Loop Filter
LF2_C1
LF2_R2
PLL2 External
Loop Filter
Figure 40. Example Application – System Schematic Except for Power
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System Examples (continued)
Figure 40 shows the primary reference clock input is at CLKin0/0*. A secondary reference clock is driving
CLKin1/1*. Both clocks are depicted as AC coupled drivers. The VCXO attached to the OSCin/OSCin* port is
configured as an AC coupled single-ended driver. Any of the input ports (CLKin0/0*, CLKin1/1*, or
OSCin/OSCin*) may be configured as either differential or single-ended. These options are discussed later in the
data sheet.
See Loop Filter for more information on PLL1 and PLL2 loop filters.
In the system shown in Figure 40, LVPECL clocks are AC coupled via 0.1 µF capacitors and LVDS clocks are
DC coupled. Some clock outputs are depicted as LVPECL with 240-Ω emitter resistors and some clock outputs
as LVDS. The appropriate output termination on each output should be implemented according to the output
format to be programmed by the user. Later sections of this data sheet illustrate alternative methods for AC
coupling, DC coupling, and terminating the clock outputs. PCB design will influence crosstalk performance.
Tightly coupled clock traces will have less crosstalk than loosely coupled clock traces. Also proximity to other
clocks traces will influence crosstalk.
PLL Supply Plane
Vcc1
FB
Vcc4
Vcc5
10 µF, 1 µF, 0.1 µF
1 µF, 0.1 µF, 10 nF
Vcc7
Vcc9
LDO
LP3878-ADJ
Vcc6
FB
0.1 µF
0.1 µF
Digital
CLKin
OSCin/OSCout/
PLL2 Circuitry
PLL2 N Divider
PLL1 CP
0.1 µF
PLL2 CP
FB
FB = Ferrite bead
VCO LDO
0.1 µF
Vcc8
LMK04208
Clock Supply Plane
FB
FB
10 µF, 1 µF, 0.1 µF
FB
Do not directly copy schematic for
CLKout Vcc13/2/3/10/11/12. This
is for example frequency plan only.
Vcc13
Example
Frequency 1
Vcc2
Vcc3
FB
Vcc10
Vcc11
Recommendation is to group
supplies by same frequency and
share a ferrite bead among outputs
of the same frequency.
CLKout0
Vcc12
CLKout1
CLKout2
Example
Frequency 2
CLKout3
CLKout4
Example
Frequency 3
CLKout5
Figure 41. Example Application – Power System Schematic
Figure 41 shows an example decoupling and bypassing scheme for the LMK04208, which could apply to
configuration shown in Figure 40. The ferrite beads and capacitors drawn in dotted lines are optional (see Pin
Connection Recommendations). Two power planes are used in these example designs, one for the clock outputs
and one for PLL circuits. It is possible to reduce the number of decoupling components by tying together clock
output Vcc pins for CLKouts that share the same frequency or otherwise can tolerate potential crosstalk between
outputs with different frequencies. In the two examples, Vcc2 and Vcc3 can be tied together since CLKout1 and
CLKout2 will operate at the same frequencies. Vcc10, Vcc11, and Vcc12 can be tied together since potential
crosstalk between the FPGA/SerDes clocks and low-frequency synchronization clocks will not impact the
performance of these digital interfaces, which typically have less stringent jitter requirements. PCB design will
influence impedance to the supply. Vias and traces will increase the impedance to the power supply. Ensure
good direct return current paths.
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9.4 Do's and Don'ts
9.4.1 LVCMOS Complementary vs. Non-Complementary Operation
• TI recommends using a complementary LVCMOS output format such as LVCMOS (Norm/Inv) to reduce
switching noise and crosstalk when using LVCMOS.
• If only a single LVCMOS output is required, the complementary LVCMOS output format can still be used by
leaving the unused LVCMOS output floating.
• A non-complimentary format such as LVCMOS (Norm/Norm) is not recommended as increased switching
noise is present.
9.4.2 LVPECL Outputs
When using an LVPECL output it is not recommended to place a capacitor to ground on the output as might be
done when using a capacitor input LC lowpass filter. The capacitor will appear as a short to the LVPECL output
drivers which are able to supply large amounts of switching current. The effect of the LVPECL sourcing large
switching currents can result in the following:
1. Large switching currents through the Vcc pin of the LVPECL power supply resulting in more Vcc noise and
possible Vcc spikes.
2. Large switching currents injected into the ground plane through the capacitor which could couple onto other
Vcc pins with bypass capacitors to ground resulting in more Vcc noise and possible Vcc spikes.
9.4.3 Sharing MICROWIRE (SPI) Lines
When CLKuWire and DATAuWire toggle and an internal VCO mode is used, there may some spurious content
on the phase noise plot related to the frequency of the CLKuWire and DATAuWire pins.
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10 Power Supply Recommendations
10.1 Pin Connection Recommendations
10.1.1 Vcc Pins and Decoupling
All Vcc pins must always be connected.
Integrated capacitance on the LMK04208 makes external high frequency decoupling capacitors (≤ 1 nF)
unnecessary. The internal capacitance is more effective at filtering high frequency noise than off device bypass
capacitance because there is no bond wire inductance between the LMK04208 circuit and the bypass capacitor.
10.1.1.1 Vcc2, Vcc3, Vcc10, Vcc11, Vcc12, Vcc13 (CLKout Vccs)
Each of these pins has an internal 200 pF of capacitance.
Ferrite beads may be used to reduce crosstalk between different clock output frequencies on the same
LMK04208 device. Ferrite beads placed between the power supply and a clock Vcc pin will reduce noise
between the Vcc pin and the power supply. When several output clocks share the same frequency a single ferrite
bead can be used between the power supply and each same frequency CLKout Vcc pin.
When using ferrite beads on CLKout Vcc pins, consider the following guidelines to ensure the power supply will
source the needed switching current:
• In most cases a ferrite bead may be placed and the internal capacitance is sufficient.
• If a ferrite bead is used with a low frequency output (typically ≤ 30 MHz) and a high current switching clock
output format such as non-complementary LVCMOS or high swing LVPECL is used, then:
– The ferrite bead can be removed to the lower impedance to the main power supply and bypass capacitors,
or
– Localized capacitance can be placed between the ferrite bead and Vcc pin to support the switching
current.
– Note: the decoupling capacitors used between the ferrite bead and a CLKout Vcc pin can permit high
frequency switching noise to couple through the capacitors into the ground plane and onto other
CLKout Vcc pins with decoupling capacitors. This can degrade crosstalk performance.
– TI recommends using a complementary LVCMOS output format such as LVCMOS (Norm/Inv) to reduce
switching noise and crosstalk when using LVCMOS. If only a single LVCMOS output is required, the
complementary LVCMOS output format can still be used by leaving the unused LVCMOS output floating.
10.1.1.2 Vcc1 (VCO), Vcc4 (Digital), and Vcc9 (PLL2)
Each of these pins has internal bypass capacitance.
Ferrite beads should not be used between these pins and the power supply/large bypass capacitors because
these Vcc pins don’t produce much noise and a ferrite bead can cause phase noise disturbances and
resonances.
The typical application diagram in Figure 41 shows all these Vccs connected to together to Vcc without a ferrite
bead.
10.1.1.3 Vcc6 (PLL1 Charge Pump) and Vcc8 (PLL2 Charge Pump)
Each of these pins has an internal bypass capacitor.
Use of a ferrite bead between the power supply/large bypass capacitors and PLL1 is optional. PLL1 charge
pump can be connected directly to Vcc along with Vcc1, Vcc4, and Vcc9. Depending on the application, a 0.1 µF
capacitor may be placed close to PLL1 charge pump Vcc pin.
A ferrite bead should be placed between the power supply/large bypass capacitors and Vcc8. Most applications
have high PLL2 phase detector frequencies and (> 50 MHz) such that the internal bypassing is sufficient and a
ferrite bead can be used to isolate this switching noise from other circuits. For lower phase detector frequencies
a ferrite bead is optional and depending on application a 0.1 µF capacitor may be added on Vcc8.
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Pin Connection Recommendations (continued)
10.1.1.4 Vcc5 (CLKin), Vcc7 (OSCin and OSCout)
Each of these pins has an internal 100 pF of capacitance. No ferrite bead should be placed between the power
supply/large bypass capacitors and Vcc5 or Vcc7.
These pins are unique since they supply an output clock and other circuitry.
Vcc5 supplies CLKin.
Vcc7 supplies OSCin, OSCout, and PLL2 circuitry.
Impacts of excessive noise on PLL2 circuitry may impact PLL2 DLD operation.
TI recommends using a complementary LVCMOS output format such as LVCMOS (Norm/Inv) to reduce
switching noise and crosstalk when using LVCMOS. If only a single LVCMOS output is required, the
complementary LVCMOS output format can still be used by leaving the unused LVCMOS output floating.
10.1.2 LVPECL Outputs
When using an LVPECL output it is not recommended to place a capacitor to ground on the output as might be
done when using a capacitor input LC lowpass filter. The capacitor will appear as a short to the LVPECL output
drivers which are able to supply large amounts of switching current. The effect of the LVPECL sourcing large
switching currents can result in:
1. Large switching currents through the Vcc pin of the LVPECL power supply resulting in more Vcc noise and
possible Vcc spikes.
2. Large switching currents injected into the ground plane through the capacitor which could couple onto other
Vcc pins with bypass capacitors to ground resulting in more Vcc noise and possible Vcc spikes.
10.1.3 Unused Clock Outputs
Leave unused clock outputs floating and powered down.
10.1.4 Unused Clock Inputs
Unused clock inputs can be left floating.
10.1.5 LDO Bypass
The LDObyp1 and LDObyp2 pins should be connected to GND through external capacitors, as shown in
Figure 41.
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10.2 Current Consumption and Power Dissipation Calculations
From Table 118 the current consumption can be calculated for any configuration.
For example, the current for the entire device with 1 LVDS (CLKout0) and 1 LVPECL 1.6 Vpp w/ 240-Ω emitter
resistors (CLKout1) output active with a clock output divide = 1, and no other features enabled can be calculated
by adding up the following blocks: core current, clock buffer, one LVDS output buffer current, and one LVPECL
output buffer current. There will also be one LVPECL output drawing emitter current, which means some of the
power from the current draw of the device is dissipated in the external emitter resistors which doesn't add to the
power dissipation budget for the device but is important for LDO ICC calculations.
For total current consumption of the device, add up the significant functional blocks. In this example, 228.1 mA
equals the sum of the following:
• 140 mA (core current)
• 17.3 mA (base clock distribution)
• 25.5 mA (CLKout0 divider)
• 25.5 mA (CLKout1 divider)
• 14.3 mA (LVDS buffer)
• 31 mA (LVPECL 1.6 Vpp buffer w/ 240-Ω emitter resistors)
Once total current consumption has been calculated, power dissipated by the device can be calculated. The
power dissipation of the device is equation to the total current entering the device multiplied by the voltage at the
device minus the power dissipated in any emitter resistors connected to any of the LVPECL outputs. If no emitter
resistors are connected to the LVPECL outputs, this power will be 0 watts. Continuing the above example which
has 253.6 mA total Icc and one output with 240-Ω emitter resistors. Total IC power = 801.88 mW = 3.3 V * 253.6
mA - 35 mW.
Table 118. Typical Current Consumption for Selected Functional Blocks
(TA = 25 °C, VCC = 3.3 V)
BLOCK
CONDITION
TYPICAL
ICC
(mA)
POWER
POWER
DISSIPATED
DISSIPATED
EXTERNALL
in DEVICE
Y (1) (2) (3)
(mW)
(mW)
CORE and FUNCTIONAL BLOCKS
Core
MODE = 0: Dual Loop, Internal
VCO
PLL1 and PLL2 locked
140
462
-
MODE = 2: Dual Loop, Internal
VCO, 0-Delay
PLL1 and PLL2 locked; Includes
EN_FEEDBACK_MUX = 1
155
512
-
MODE = 3: Dual Loop, External
VCO
PLL1 and PLL2 locked
127
419
-
MODE = 5: Dual PLL, 0-DELAY,
External VCO
PLL1 and PLL2 locked; Includes
EN_FEEDBACK_MUX = 1
142
469
-
MODE = 6: Single Loop (PLL2),
Internal VCO
PLL2 locked
116
383
-
MODE = 11: Single Loop (PLL2),
External VCO
PLL2 locked
103
340
-
PD_OSCin = 0
42
139
-
PD_OSCin = 1
34.5
114
-
2
6.6
-
17.3
57.1
-
2.8
9.2
-
MODE = 16: Clock Distribution
EN_TRACK
Tracking is enabled (EN_TRACK = 1)
Base Clock
Distribution
At least 1 CLKoutX_PD = 0
CLKout Group
Each CLKout group (CLKout0 and 5, CLKout1 and 2, CLKout 3 and 4)
(1)
(2)
(3)
126
Power is dissipated externally in LVPECL emitter resistors. The externally dissipated power is calculated as twice the DC voltage level
of one LVPECL clock output pin squared over the emitter resistance. That is to say power dissipated in emitter resistors = 2 * Vem2 /
Rem.
Assuming R θJA = 15 °C/W, the total power dissipated on chip must be less than (125 °C – 85 °C) / 16 °C/W = 2.5 W to ensure a
junction temperature is less than 125 °C.
Worst case power dissipation can be estimated by multiplying typical power dissipation with a factor of 1.15.
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Current Consumption and Power Dissipation Calculations (continued)
Table 118. Typical Current Consumption for Selected Functional Blocks
(TA = 25 °C, VCC = 3.3 V) (continued)
POWER
POWER
DISSIPATED
DISSIPATED
EXTERNALL
in DEVICE
Y (1) (2) (3)
(mW)
(mW)
CONDITION
TYPICAL
ICC
(mA)
Clock Divider/
Digital Delay
When a clock output is enabled, this contributes the divider/delay block
25.5
84.1
-
Divider / digital delay in extended mode
29.6
97.7
-
VCO Divider
VCO Divider current
7.7
25.4
-
HOLDOVER mode
When in holdover mode
2.2
7.2
-
Feedback Mux
Feedback mux must be enabled for 0-delay modes and digital delay
mode (SYNC_QUAL = 1)
4.9
16.1
-
SYNC Asserted
While SYNC is asserted, this extra current is drawn
1.7
5.6
-
EN_SYNC = 1
Required for SYNC functionality. May be turned off once SYNC is
complete to save power.
6
19.8
-
SYNC_QUAL = 1
Delay enabled, delay > 7 (CLKout_MUX = 2, 3)
BLOCK
Crystal Mode
Enabling the Crystal Oscillator
OSCin Doubler
EN_PLL2_REF_2X = 1
Analog Delay
Analog Delay Value
8.7
28.7
-
XTAL_LVL = 0
1.8
5.9
-
XTAL_LVL = 1
2.7
9
-
XTAL_LVL = 2
3.6
12
-
XTAL_LVL = 3
4.5
15
-
2.8
9.2
-
CLKoutX_ANLG_DLY = 0 to 3
3.4
11.2
-
CLKoutX_ANLG_DLY = 4 to 7
3.8
12.5
-
CLKoutX_ANLG_DLY = 8 to 11
4.2
13.9
-
CLKoutX_ANLG_DLY = 12 to 15
4.7
15.5
-
CLKoutX_ANLG_DLY = 16 to 23
5.2
17.2
-
CLOCK OUTPUT BUFFERS
LVDS
LVPECL
LVCMOS
100-Ω differential termination
14.3
47.2
-
LVPECL 2.0 Vpp, AC coupled using 240-Ω emitter resistors
32
70.6
35
LVPECL 1.6 Vpp, AC coupled using 240-Ω emitter resistors
31
67.3
35
LVPECL 1.6 Vpp, AC coupled using 120-Ω emitter resistors
46
91.8
60
LVPECL 1.2 Vpp, AC coupled using 240-Ω emitter resistors
30
59
40
LVPECL 0.7 Vpp, AC coupled using 240-Ω emitter resistors
29
55.7
40
LVCMOS Pair (CLKoutX_TYPE
= 6 to 9)
CL = 5 pF
3 MHz
24
79.2
-
30 MHz
26.5
87.5
-
150 MHz
36.5
120.5
-
LVCMOS Single (CLKoutX_TYPE
= 10 to 13)
CL = 5 pF
3 MHz
15
49.5
-
30 MHz
16
52.8
-
150 MHz
21.5
71
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11 Layout
11.1 Layout Guidelines
Power consumption of the LMK04208 device can be high enough to require attention to thermal management.
For reliability and performance reasons the die temperature should be limited to a maximum of 125 °C. That is,
as an estimate, TA (ambient temperature) plus device power consumption times RθJA should not exceed 125 °C.
The package of the device has an exposed pad that provides the primary heat removal path as well as excellent
electrical grounding to a printed circuit board. To maximize the removal of heat from the package a thermal land
pattern including multiple vias to a ground plane must be incorporated on the PCB within the footprint of the
package. The exposed pad must be soldered down to ensure adequate heat conduction out of the package.
A recommended land and via pattern is shown at the end of the datasheet, Mechanical, Packaging, and
Orderable Information. More information on soldering WQFN packages can be obtained from
www.ti.com/packaging/.
To minimize junction temperature, TI recommends that a simple heat sink be built into the PCB (if the ground
plane layer is not exposed). This is done by including a copper area on the opposite side of the PCB from the
device. This copper area may be plated or solder coated to prevent corrosion, but should not have conformal
coating (if possible), which could provide thermal insulation.
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11.2 Layout Example
CLKin and OSCin paths ± if differential input (preferred) route trace
tightly coupled like clock outputs. If single ended, have at least 3 trace
width (of CLKin/OSCin trace) separation from other RF traces.
Example shown is hybrid for both differential and single ended ± not
tightly couple to compromise for both configurations. RF Terminations
should be placed as close to IC as possible. When using CLKin1 for
high frequency input for external VCO or distribution, a 3 dB pi pad is
suggested for termination.
)RU &/.RXW 9FF¶V SODFH IHUULWH EHDGV RQ WRS OD\HU FORVH WR SLQV WR FKRNH
high frequency noise from via.
Charge pump output ± shorter traces are better
Place all resistors and caps closer to IC except
a single capacitor next to VCXO. In a 2nd order
filter place C1 close to VCXO Vtune pin. In a 3rd
and 4th order filter place C3 or C4 respectively
close to VCXO.
Clock outputs ± differential signals, should be
routed tightly coupled to minimize PCB crosstal
Trace impedance and terminations should be
designed according to output type being used (i
LVDS, LVPECL...)
Figure 42. LMK04208 Layout Example
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12 Device and Documentation Support
12.1 Device Support
12.1.1 Development Support
For additional support, see the following:
• Clock Architect (simulation): http://www.ti.com/lsds/ti/analog/webench/clock-architect.page
• TICS Pro (EVM programming and register generation tool):
12.2 Documentation Support
12.2.1 Related Documentation
For additional information, see the following:
• AN-912 Common Data Transmission Parameters and their Definitions
• AN-1939 Crystal Based Oscillator Design with the LMK04000 Family
• AN-1865 Frequency Synthesis and Planning for PLL Architectures
12.3 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
12.4 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
12.5 Trademarks
PLLatinum, E2E are trademarks of Texas Instruments.
All other trademarks are the property of their respective owners.
12.6 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
12.7 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
LMK04208NKDR
ACTIVE
WQFN
NKD
64
2000
RoHS & Green
SN
Level-3-260C-168 HR
-40 to 85
K04208NKD
LMK04208NKDT
ACTIVE
WQFN
NKD
64
250
RoHS & Green
SN
Level-3-260C-168 HR
-40 to 85
K04208NKD
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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