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LMK04610
SNAS699B – JANUARY 2017 – REVISED JULY 2019
LMK04610 Ultra-Low Noise and Low Power JESD204B Compliant Clock Jitter Cleaner
With Dual-Loop PLLs
1 Features
•
•
1
•
•
•
•
•
•
•
•
•
•
Dual-loop PLL architecture
Ultra low noise (10 kHz to 20 MHz):
– 48-fs RMS jitter at 1966.08 MHz
– 50-fs RMS jitter at 983.04 MHz
– 61-fs RMS jitter at 122.88 MHz
–165-dBc/Hz noise floor at 122.88 MHz
JESD204B support
– Single shot, pulsed, and continuous SYSREF
10 differential output clocks in 8 frequency groups
– Programmable output swing between 700
mVpp to 1600 mVpp
– Each output pair can be configured to
SYSREF clock output
– 16-bit channel divider
– Minimum SYSREF frequency of 25 kHz
– Maximum output frequency of 2 GHz
– Precision digital delay, dynamically adjustable
– Digital delay (DDLY) of ½ × clock
distribution path frequency (2 GHz
maximum)
– 60-ps step analog delay
– 50% duty cycle output divides, 1 to 65535
(even and odd)
Two reference inputs
– Holdover mode, when inputs are lost
– Automatic and manual switch-over modes
– Loss-of-signal (LOS) detection
0.88-W typical power consumption with 10 outputs
active
Operates typically from a 1.8-V (outputs, inputs)
and 3.3-V supply (digital, PLL1, PLL2_OSC, PLL2
core)
Fully integrated programmable loop filter
PLL2
– PLL2 phase detector rate up to 250 MHz
– OSCin frequency-doubler
– Integrated low-noise VCO
Internal power conditioning: better than –80 dBc
PSRR on VDDO for 122.88-MHz differential
outputs
3- or 4-wire SPI interface (4-wire is default)
•
•
•
–40ºC to +85ºC industrial ambient temperature
Supports 105ºC PCB temperature (measured at
thermal pad)
LMK04610: 8-mm × 8-mm VQFN-56 package with
0.5-mm pitch
2 Applications
•
•
•
•
Wireless infrastructure like LTE-BTS, small cells,
remote radio units (RRU)
Data converter and integrated transceiver clocking
Networking, SONET/SDH, DSLAM
Test and measurement
3 Description
The LMK0461x device family is the industry's highest
performance and lowest power jitter cleaner with
JESD204B support.
Device Information(1)
PART NUMBER
VCO FREQUENCY
LMK04610
5870 MHz to 6175 MHz
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Simplified Schematic
Recovered
³GLUW\´ FORFN RU
clean clock
VCXO
OSCout
LMX2582
PLL+VCO
0XOWLSOH ³FOHDQ´
clocks at different
frequencies
CLKin0
Backup
Reference
Clock
CLKin1
CLKout9
LMK04610
CLKout10
CLKout1 &
CLKout2
CLKout5 &
CLKout6
CLKout3 &
CLKout4
CLKout7 &
CLKout8
ADC
FPGA
DAC
DAC
Copyright © 2017, Texas Instruments Incorporated
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
LMK04610
SNAS699B – JANUARY 2017 – REVISED JULY 2019
www.ti.com
Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Device Comparison Table.....................................
Pin Configuration and Functions .........................
Specifications.........................................................
7.1
7.2
7.3
7.4
7.5
1
1
1
2
4
5
7
Absolute Maximum Ratings ...................................... 7
ESD Ratings.............................................................. 8
Recommended Operating Conditions....................... 8
Thermal Information .................................................. 8
Digital Input and Output Characteristics (CLKin_SEL,
STATUSx, SYNC, RESETN) ..................................... 9
7.6 Clock Input Characteristics (CLKinX)........................ 9
7.7 Clock Input Characteristics (OSCin) ....................... 10
7.8 PLL1 Specification Characteristics ......................... 11
7.9 PLL2 Specification Characteristics ......................... 11
7.10 Clock Output Type Characteristics (CLKoutX)...... 12
7.11 Oscillator Output Characteristics (OSCout) .......... 13
7.12 Jitter and Phase Noise Characteristics for CLKoutX
and OSCout ............................................................. 14
7.13 Clock Output Skew and Isolation Characteristics . 15
7.14 Clock Output Delay Characteristics ...................... 15
7.15 DEFAULT POWER on RESET CLOCK OUTPUT
Characteristics ......................................................... 15
7.16 Power Supply Characteristics ............................... 16
7.17 Typical Power Supply Noise Rejection
Characteristics ......................................................... 16
7.18 SPI Interface Timing ............................................. 17
7.19 Timing Diagram..................................................... 17
7.20 Typical Characteristics .......................................... 18
8
Parameter Measurement Information ................ 20
8.1 Differential Voltage Measurement Terminology ..... 20
8.2 Output Termination Scheme ................................... 20
9
Detailed Description ............................................ 22
9.1
9.2
9.3
9.4
9.5
9.6
Overview .................................................................
Functional Block Diagram .......................................
Feature Description.................................................
Device Functional Modes........................................
Programming...........................................................
Register Maps .........................................................
22
24
25
52
54
56
10 Application and Implementation...................... 116
10.1 Application Information........................................ 116
10.2 Typical Application .............................................. 117
10.3 Do's and Don'ts ................................................... 119
11 Power Supply Recommendations ................... 120
11.1 Recommended Power Supply Connection ......... 120
11.2 Current Consumption / Power Dissipation
Calculations............................................................ 120
12 Layout................................................................. 121
12.1 Layout Guidelines ............................................... 121
12.2 Layout Example .................................................. 122
13 Device and Documentation Support ............... 123
13.1 Device Support ..................................................
13.2 Receiving Notification of Documentation
Updates..................................................................
13.3 Community Resources........................................
13.4 Trademarks .........................................................
13.5 Electrostatic Discharge Caution ..........................
13.6 Glossary ..............................................................
123
123
123
123
123
123
14 Mechanical, Packaging, and Orderable
Information ......................................................... 123
4 Revision History
Changes from Revision A (June 2017) to Revision B
Page
•
Removed bulleted list under the Dual Loop PLL Architecture feature bullet.......................................................................... 1
•
Added Ultra Low Noise feature bullets ................................................................................................................................... 1
•
Changed VCO frequency units from: 5.8 to 6.175 GHz to: 5870 MHz to 6175 MHz............................................................. 1
•
Added LMK04616 device configuration information ............................................................................................................... 4
•
Changed VCO frequency from: 5800 MHz to: 5870 MHz ...................................................................................................... 4
•
Added PACKAGE column to device configuration information table ..................................................................................... 4
•
Added LMK04616 row to device configuration information table ........................................................................................... 4
•
Added Footnote and link to LMK04616 datasheet ................................................................................................................ 4
•
Added OSCout polarity information to the OSCout/OSCout* pin description ........................................................................ 6
•
Changed PLL1 phase detector maximum frequency from 40 MHz to 4 MHz ..................................................................... 11
•
Changed VCO tuning range minimum from: 5800 to: 5870 ................................................................................................. 11
•
Changed VOD symbol to VOD,pp to match mVpp units. .......................................................................................................... 12
•
Changed VOD symbol to VOD,pp to match mVpp units. ......................................................................................................... 13
•
Added content to the HSDS 4/6/8mA section ..................................................................................................................... 20
•
Added content to the HCSL section .................................................................................................................................... 21
•
Changed the VCXO Buffered Output section ...................................................................................................................... 22
2
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Revision History (continued)
•
Changed VCO frequency to 5870 MHz to 6175 MHz and updated max output frequency to 2058 MHz ........................... 23
•
Added content to the Programmable Output Formats section ............................................................................................ 23
•
Changed HSDS to LVPECL With Bias Voltage Vb graphic caption..................................................................................... 31
•
Changed HCSL to LVPECL graphic..................................................................................................................................... 31
•
Changed HSDS to LVPECL With Bias Voltage Vb graphic caption..................................................................................... 32
•
Changed HSDS to LVPECL graphic .................................................................................................................................... 32
•
Added content to the OSCout section ................................................................................................................................. 35
•
Added OSCin to OSCout differential results in clock inversion from OSCin to OSCout. .................................................... 35
•
Added Note to use TICS Pro EVM tool to calculate SDPLL loop filter values. .................................................................... 38
•
Changed PLL1_PROP max from 255 to 127. ..................................................................................................................... 38
•
Added PLL1_PROP_FL to table. ......................................................................................................................................... 38
•
Changed PLL1_FBCLK_INV and CLKinx_PLL1_INV for Low Pulse mode ......................................................................... 38
•
Changed PLL1_FBCLK_INV and CLKinx_PLL1_INV for High Pulse mode ....................................................................... 38
•
Deleted Examples of PLL1 Setting....................................................................................................................................... 38
•
Changed the tuning range of the oscillator from: 5800 MHz to: 5870 MHz ......................................................................... 40
•
Added PLL2 DLD programming information and updated the PLLx DLD flowchart graphic .............................................. 41
•
Changed PLL1_STORAGE_CELL description from 40-bit thermometer code to 6-bit decimal value ................................ 44
•
Clarified CTRL_VCXO represented as PLL1_STORAGE_CELL value .............................................................................. 44
•
Changed section from: Low Skew Mode to: Zero Delay Mode (ZDM) ................................................................................ 49
•
Changed Set Prop/Store-CP from "fast lock" value to "non-fast lock" value at end of flowchart......................................... 51
•
Deleted references to tunable crystal .................................................................................................................................. 52
•
Deleted reference to CLKin2 and CLKin3 ........................................................................................................................... 52
•
Deleted use of external VCO for PLL2. ................................................................................................................................ 52
•
Added register 0x85, 0x86, 0xF6, and 0xAD for PLL2 DLD to recommended programming sequence ............................. 55
•
Changed PLL1_PROP from 8 bit to 7 bit field in register map ............................................................................................ 59
•
Changed PLL1_PROP_FL from 8 bit to 7 bit field in register map ..................................................................................... 59
•
Changed PLL1_STORAGE_CELL 40 bit to 6 bit field. Not a 40 bit thermometer code. Set registers 0x66, 0x67,
0x68, 0x69 to RSRVD in register map ................................................................................................................................ 59
•
Changed PLL2_PROP from 8 bit to 6 bit field in register map ............................................................................................ 60
•
Changed PLL2_INTG from 8 bit to 5 bit field in register map ............................................................................................. 60
•
Added register 0xAC for field PLL1_TSTMODE_REF_FB_EN in register map................................................................... 61
•
Added register 0xAD for fields RESET_PLL2_DLD, PLL2_TSTMODE_REF_FB_EN, and PD_VCO_LDO in register
map....................................................................................................................................................................................... 61
•
Added register 0xF6 for PLL2_DLD_EN in register map ..................................................................................................... 61
•
Deleted unused DEVID values ............................................................................................................................................. 65
•
Changed reset value for CHIPID from 0x1 to 0x3................................................................................................................ 65
•
Changed reset value for CHIPVER from 0x1 to 0x1B ......................................................................................................... 65
•
Changed PLL1_PROP from 8 bit to 7 bit field in register definition .................................................................................... 85
•
Changed PLL1_PROP_FL from 8 bit to 7 bit field in register definition .............................................................................. 85
•
Deleted 'PLL1 Start-up in Holdover.' text from the PLL1_STARTUP_HOLDOVER_EN bit description .............................. 85
•
Changed PLL2_PROP field size from 8 bits to 6 bits in register definition ......................................................................... 90
•
Changed PLL2_INTG field from 8 bit to 5 bit field in register 0x80 definition ...................................................................... 92
•
Added definition and requirement for setting PLL2_LD_WNDW_SIZE = 0 in register 0x85 definition ............................... 93
•
Added definition and requirement for setting PLL2_LD_WNDW_SIZE_INITIAL = 0 in register 0x86 definition.................. 93
•
Added note for using PLL1/2 REF/FB(SYS) status output for STAT0 ................................................................................ 96
•
Added note for using PLL1/2 REF/FB(SYS) status output for STAT1 ................................................................................ 97
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SNAS699B – JANUARY 2017 – REVISED JULY 2019
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Revision History (continued)
•
Added note for using PLL1/2 REF/FB(SYS) status output for SYNC ............................................................................... 100
•
Added register 0xAC to register description. New field PLL1_TSTMODE_REF_FB_EN. ................................................. 101
•
Added register 0xAD to register description. New fields RESET_PLL2_DLD, PLL2_TSTMODE_REF_FB_EN, and
PD_VCO_LDO.................................................................................................................................................................... 101
•
Added register 0xF6 to register description. New field PLL2_DLD_EN ............................................................................. 102
•
Added register 0xF7 to register description. New field PLL2_DUAL_LOOP_EN .............................................................. 102
•
Changed Channel 5 and 6 FBClock Buffers from: Low Skew to: Zero Delay Mode.......................................................... 112
•
Changed registers for WINDOW SIZE and LOCK COUNT. Updated equation to reflect the more general WINDOW
SIZE and LOCK COUNT names and count frequency. Removed reference to holdover. Updated descriptive text ........ 116
•
Updated minimum lock time calculation example to reflect updated register names and count frequency ...................... 116
•
Simplified HSDS format description .................................................................................................................................. 121
Changes from Original (January 2017) to Revision A
Page
•
Removed the 16 differential output clock and 6 frequency group features from the LMK04610 ........................................... 1
•
Removed the 4 reference input feature from the LMK04610 ................................................................................................. 1
•
Changed text from: –70-dBc PSRR to: –80dBc PSRR on VDDO.......................................................................................... 1
•
Changed SPI Interface default from: 3-wire to: 4-wire .......................................................................................................... 1
•
Changed VCO frequency from: 5.8 to 6.2 GHz to: 5.8 to 6.175 GHz .................................................................................... 1
•
Changed VCO frequency from: 6200 MHz to: 6175 MHz ...................................................................................................... 4
•
Updated PLL1_CAP pin description ....................................................................................................................................... 6
•
Removed tablenote from the doubler input frequency parameter ........................................................................................ 11
•
Changed VCO tuning range maximum from: 6200 to: 6175 ................................................................................................ 11
•
Changed tablenote text from: ATE tested at 2949.12 MHz to: ATE tested at 258 MHz ...................................................... 11
•
Removed the CLKin2/CLKin2*, and CLKin3/CLKin3* inputs from the LMK04610............................................................... 22
•
Updated the Functional Block Diagram ................................................................................................................................ 24
•
Added content to the Driving CLKin and OSCin Pins With a Differential Source section.................................................... 28
•
Changed text from: Either AC coupling or DC coupling may be used. to: The clock is internally AC-coupled.................... 29
•
Updated Figure 36 ............................................................................................................................................................... 37
•
Changed the tuning range of the oscillator from: 6200 MHz to: 6175 MHz ......................................................................... 40
•
Updated Figure 49 ............................................................................................................................................................... 50
•
Changed the caption title on Figure 53 ............................................................................................................................... 52
•
Changed the caption title on Figure 54 ............................................................................................................................... 53
•
Changed the caption title on Figure 55 ................................................................................................................................ 53
5 Device Comparison Table
Table 1. Device Configuration Information
PART NUMBER
REFEREN
CE
INPUTS
OSCout (BUFFERED
OSCin OR PLL2 CLOCK)
HCSL/ HSDS/ LVCMOS
PLL2
PROGRAMMABLE
HCSL/HSDS
OUTPUTS
VCO FREQUENCY
PACKAGE
LMK04610
2
1
10
5870 to 6175 MHz
VQFN-56
LMK04616
4
1
16
5870 to 6175 MHz
NFBGA-144 (1)
(1)
4
Refer to LMK04616 datasheet.
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SNAS699B – JANUARY 2017 – REVISED JULY 2019
6 Pin Configuration and Functions
NC
CLKout10
CLKout10*
CLKout9
CLKout9*
VDDO_9/10
CLKout8
CLKout8*
CLKout7
CLKout7*
VDDO_7/8
CLKout6
CLKout6*
VDDO_6
55
54
53
52
51
50
49
48
47
46
45
44
43
NC
1
42
PLL1_CAP
NC
2
41
CTRL_VCXO
NC
3
40
VDD_PLL1
VDD_PLL2OSC
4
39
OSCin
PLL2_VCO_LDO_CAP
5
38
OSCin*
VDD_PLL2CORE
6
37
VDD_OSC
PLL2_LDO_CAP
7
36
OSCout
VDD_CORE
8
35
OSCout*
STATUS0
9
34
CLKin_SEL
STATUS1
10
33
CLKin0
SDIO
11
32
CLKin0*
56 pin QFN
Top down view
DAP = GND
19
20
21
22
23
24
25
26
27
28
CLKout2*
VDDO_1/2
CLKout3
CLKout3*
CLKout4
CLKout4*
VDDO_3/4
CLKout5
CLKout5*
VDDO_5
18
CLKout2
CLKin1*
17
14
CLKout1*
CLKin1
29
16
VDD_IO
30
CLKout1
31
13
15
12
SCL
RESETN
SCS*
SYNC
A.
56
RTQ Package
56-Pin VQFN
Top View
LMK04610
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Pin Functions: LMK04610 (1)
PIN
TYPE
DESCRIPTION
DAP
GND
Die attach pad.
The DAP is an electrical connection and provides a thermal dissipation path. For proper
electrical and thermal performance of the device, the DAP must be connected to the PCB
ground plane.
VDD_CORE
8
P
3.3-V power supply for core
VDD_IO
31
P
1.8-V to 3.3-V power supply for input block
VDD_OSC
37
P
1.8-V to 3.3-V power supply for OSCout
VDD_PLL1
40
P
3.3-V power supply for PLL 1
VDD_PLL2CORE
6
P
3.3-V power supply for PLL 2
VDD_PLL2OSC
4
P
3.3-V power supply for PLL2 VCO
VDDO_1/2
20
P
1.8-V to 3.3-V power supply for CLKout1 and CLKout2
VDDO_3/4
25
P
1.8-V to 3.3-V power supply for CLKout3 and CLKout4
VDDO_5
28
P
1.8-V to 3.3-V power supply for CLKout5
VDDO_6
43
P
1.8-V to 3.3-V power supply for CLKout6
VDDO_7/8
46
P
1.8-V to 3.3-V power supply for CLKout7 and CLKout8
VDDO_9/10
51
P
1.8-V to 3.3-V power supply for CLKout9 and CLKout10
CTRL_VCXO
41
Analog
VCXO control output
PLL1_CAP
42
Analog
PLL1 LDO capacitance - 10-µF external
PLL2_LDO_CAP
7
Analog
PLL2 LDO capacitance - 10-µF external
PLL2_VCO_LDO_
CAP
5
Analog
PLL2 LDO capacitance - 10-µF external
I
CMOS
Manual reference input selection for PLL1 weak pullup resistor.
I
Analog
Reference clock input Port 0 for PLL1.
I
Analog
Reference clock input Port 1 for PLL1.
I
Analog
Feedback to PLL1, reference input to PLL2.
Accepts a differential or single-ended (VCXO)
O
Programmable
Buffered output of OSCin port. When using differential output mode, OSCout polarity is
reversed from OSCin polarity.
O
Programmable
Differential clock output pair 1.
O
Programmable
Differential clock output pair 2.
O
Programmable
Differential clock output pair 3.
O
Programmable
Differential clock output pair 4.
O
Programmable
Differential clock output pair 5.
O
Programmable
Differential clock output pair 6.
O
Programmable
Differential clock output pair 7.
O
Programmable
Differential clock output pair 8.
NAME
NO.
I/O
POWER
DAP
PLL
INPUT BLOCK
CLKin_SEL
34
CLKin0
33
CLKin0*
32
CLKin1
30
CLKin1*
29
OSCin
39
OSCin*
38
OUTPUT BLOCK
OSCout
36
OSCout*
35
CLKout1
16
CLKout1*
17
CLKout2
18
CLKout2*
19
CLKout3
21
CLKout3*
22
CLKout4
23
CLKout4*
24
CLKout5
26
CLKout5*
27
CLKout6
45
CLKout6*
44
CLKout7
48
CLKout7*
47
CLKout8
50
CLKout8*
49
(1)
6
See Pin Connection Recommendations section for recommended connections.
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Pin Functions: LMK04610(1) (continued)
PIN
NAME
NO.
CLKout9
53
CLKout9*
52
CLKout10
55
CLKout10*
54
I/O
TYPE
DESCRIPTION
O
Programmable
Differential clock output pair 9.
O
Programmable
Differential clock output pair 10.
DIGITAL CONTROL / INTERFACES
NC
1, 2, 3, 56
Not connect pin
RESETN
15
I
CMOS
Device reset input
SCL
13
I
CMOS
SPI serial clock.
SCS*
12
I
CMOS
SPI serial chip select (active low).
SDIO
11
I/O
CMOS
SPI serial data input or output
STATUS0
9
I/O
CMOS
Programmable status pin. See STATUS0/1 and SYNC Pin Functions for more details.
STATUS1
10
I/O
CMOS
Programmable status pin. See STATUS0/1 and SYNC Pin Functions for more details.
SYNC
14
I/O
CMOS
Synchronization of output divider, definition of OSCout divider or programmable status
pin. See STATUS0/1 and SYNC Pin Functions for more details.
7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)
VDD_IO
(1) (2)
Supply voltage for input (3)
(3)
MIN
MAX
UNIT
–0.3
3.6
V
VDD_CORE
Supply voltage for digital
–0.3
3.6
V
VDD_PLL1
Supply voltage for PLL1 (3)
–0.3
3.6
V
VDD_PLL2CORE
Supply voltage for PLL2 core
–0.3
3.6
V
(3)
VDD_PLL2OSC
Supply voltage for PLL2 OSC
–0.3
3.6
V
VDD_OSC
Supply voltage for OSCout (3)
–0.3
3.6
V
VDDO_x
Supply voltage for CLKoutX
–0.3
3.6
V
–0.3
(VDD_IO + 0.3)
V
–0.3
2.1
V
°C
(3)
VIN_clk
Input voltage for CLKinX and OSCin
VIN_gpio
Input voltage for digital and status pins (CLKin_SEL, SCK, SDIO,
SCS*, STATUSx, SYNC, RESETN)
TL
Lead temperature (solder 4 s)
+260
TJ
Junction temperature
125
°C
IIN
Input current
20
mA
MSL
Moisture sensitivity level
3
Tstg
Storage temperature
(1)
(2)
(3)
–65
150
°C
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
Stresses in excess of the absolute maximum ratings can cause permanent or latent damage to the device. These are absolute stress
ratings only. Functional operation of the device is only implied at these or any other conditions in excess of those given in the operation
sections of the data sheet. Exposure to absolute maximum ratings for extended periods can adversely affect device reliability.
Never to exceed 3.6 V.
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7.2 ESD Ratings
VALUE
Electrostatic
discharge (1)
V(ESD)
(1)
(2)
(3)
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (2)
±2000
Charged-device model (CDM), per JEDEC specification JESD22-C101 (3)
±250
Machine model
±150
UNIT
V
This device is a high performance RF integrated circuit with an ESD rating up to 2-kV human-body model, up to 150-V machine model,
and up to 250-V charged-device model and is ESD sensitive. Handling and assembly of this device should only be done at ESD-free
workstations.
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
7.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
TJ
Junction temperature
TA
Ambient temperature
TPCB
PCB temperature (measured at thermal pad)
VDD_IO
Supply voltage for input
VDD_CORE
VDD_PLL1
MIN
NOM
–40
25
MAX
UNIT
125
°C
85
°C
105
°C
1.7
1.8
3.465
V
Supply voltage for digital
3.135
3.3
3.465
V
Supply voltage for PLL1
3.135
3.3
3.465
V
VDD_PLL2CORE
Supply voltage for PLL2 Core
3.135
3.3
3.465
V
VDD_PLL2OSC
Supply voltage for PLL2 OSC
3.135
3.3
3.465
V
VDD_OSC
Supply voltage for OSCout
1.7
1.8
3.465
V
VDDO_x
Supply voltage for CLKoutX
1.7
1.8
3.465
V
7.4 Thermal Information
LMK04610
THERMAL METRIC
(1)
RTQ (VQFN)
UNIT
56 PINS
RθJA
Junction-to-ambient thermal resistance (2)
26.2
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance (3)
12.3
°C/W
(4)
RθJB
Junction-to-board thermal resistance
4.6
°C/W
ψJT
Junction-to-top characterization parameter (5)
0.2
°C/W
ψJB
Junction-to-board characterization parameter (6)
4.6
°C/W
(7)
0.8
°C/W
RθJC(bot)
(1)
(2)
(3)
(4)
(5)
(6)
(7)
8
Junction-to-case (bottom) thermal resistance
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report.
The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, High-K board, as
specified in JESD51-7, in an environment described in JESD51-2a.
The junction-to-case(top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific JEDEC-standard
test exists, but a close description can be found in the ANSI SEMI standard G30-88.
The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB
temperature, as described in JESD51-8.
The junction-to-top characterization parameter, ΨJT, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining RθJA, using a procedure described in JESD51-2a (sections 6 and 7).
The junction-to-board characterization parameter, ΨJB estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining RθJA , using a procedure described in JESD51-2a (sections 6 and 7).
The junction-to-case(bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific
JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
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7.5 Digital Input and Output Characteristics (CLKin_SEL, STATUSx, SYNC, RESETN)
3.135 V < VDD_PLL2OSC, VDD_PLL1, VDD_PLL2CORE, VDD_CORE < 3.465 V;
1.7 V < VDD_IO, VDD_OSC, VDDO_x < 3.465 V; –40°C < TA < 85°C and TPCB ≤ 105°C. Typical values at VDD_PLL2OSC,
VDD_PLL1, VDD_PLL2CORE, VDD_CORE = 3.3 V, VDD_IO, VDD_OSC, VDDOx = 1.8 V, TA = 25°C, at the Recommended
Operating Conditions and are not assured.
PARAMETER
TEST CONDITIONS
VOH
High-level output voltage
(STATUSX, SYNC)
IOH = –500 µA
1.8-V mode
VOL
Low-level output voltage
(STATUSX, SYNC)
IOL = 500 µA
1.8-V mode
VOH
High-level output voltage
(SDIO)
IOH = –500 µA during SPI read
1.8-V mode
VOL
Low-level output voltage
(SDIO)
IOL = 500 µA during SPI read
1.8-V mode
VIH
MIN
TYP
MAX
UNIT
1.2
1.9
V
0
0.6
V
1.2
1.9
V
0
0.6
V
High-level input voltage
(CLKin_SEL, STATUSX, SYNC,
RESETN, SCK, SDIO, SCS*)
1.3
1.9
V
VIL
Low-level input voltage
(CLKin_SEL, STATUSX, SYNC,
RESETN, SCK, SDIO, SCS*)
0
0.45
V
VMID
Mid-level input voltage
(CLKin_SEL, SYNC)
0.8
1.0
V
High-level input current
VIH = 1.8 V
(CLKin_SEL, RESETN)
Internal pullup
–10
10
IIH
10
60
Low-level input current
VIL = 0 V
(CLKin_SEL, RESETN)
Internal pullup
–60
–10
IIL
Internal pulldown
–10
10
IIH
High-level input current (SCK, SDIO,
SCS*, SYNC)
VIH = VDD_IO
–10
10
µA
IIL
Low-level input current (SCK, SDIO,
SCS*, SYNC)
VIL = 0
–10
10
µA
Internal pulldown
tLOW
RESETN pin held low for device reset
25
µA
µA
ns
7.6 Clock Input Characteristics (CLKinX)
3.135 V < VDD_PLL2OSC, VDD_PLL1, VDD_PLL2CORE, VDD_CORE < 3.465 V;
1.7 V < VDD_IO, VDD_OSC, VDDO_x < 3.465 V; –40°C < TA < 85°C and TPCB ≤ 105°C. Typical values at VDD_PLL2OSC,
VDD_PLL1, VDD_PLL2CORE, VDD_CORE = 3.3 V, VDD_IO, VDD_OSC, VDDOx = 1.8 V, TA = 25°C, at the Recommended
Operating Conditions and are not assured.
PARAMETER
TEST CONDITIONS
Single-ended, DC-coupled
fCLKin
Clock input frequency
Single-ended, AC-coupled
Differential, AC-coupled
(3)
SLEWDIFF
Differential input slew rate
SLEWSE
Single-ended input slew rate
VCLKin
(1)
(2)
(3)
(3)
Single-ended input voltage
(1)
(1)
(2)
MIN
TYP
MAX
5
500
5
500
5
600
UNIT
MHz
20% to 80%
0.2
6
V/ns
20% to 80%
0.1
3
V/ns
DC-coupled to CLKinX;
CLKinX* AC-coupled to Ground
0.5
3.3
AC-coupled to CLKinX;
CLKinX* AC-coupled to Ground
0.5
3.3
Vpp
See Driving CLKin and OSCin Pins With a Single-Ended Source.
See Driving CLKin and OSCin Pins With a Differential Source.
To meet the jitter performance listed in the subsequent sections of this data sheet, the minimum recommended differential slew rate for
all input clocks is 3 V/ns; this is especially true for single-ended clocks. Phase noise performance begins to degrade as the clock input
slew rate is reduced. However, the device functions at slew rates down to the minimum listed. When compared to single-ended clocks,
differential clocks (LVDS, LVPECL) are less susceptible to degradation in phase noise performance at lower slew rates due to their
common mode noise rejection. However, TI also recommends using the highest possible slew rate for differential clocks to achieve
optimal phase noise performance at the device outputs.
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Clock Input Characteristics (CLKinX) (continued)
3.135 V < VDD_PLL2OSC, VDD_PLL1, VDD_PLL2CORE, VDD_CORE < 3.465 V;
1.7 V < VDD_IO, VDD_OSC, VDDO_x < 3.465 V; –40°C < TA < 85°C and TPCB ≤ 105°C. Typical values at VDD_PLL2OSC,
VDD_PLL1, VDD_PLL2CORE, VDD_CORE = 3.3 V, VDD_IO, VDD_OSC, VDDOx = 1.8 V, TA = 25°C, at the Recommended
Operating Conditions and are not assured.
PARAMETER
TEST CONDITIONS
VID,pp
Peak-to-peak differential input voltage
See Figure 9
IDC
Input duty cycle
(4)
AC-coupled
TYP
0.4
45%
Rejected input voltage noise during LOS
condition
VNoise
MIN
MAX
UNIT
3.3
Vpp
(4)
50%
No LOS state change with singleended, peak-to-peak input voltage
noise injects to either CLKinX or
CLKinX* or to both in phase.
Measured with 1-MHz sinusoidal
signal
55%
40
mV
See Differential Voltage Measurement Terminology for definition of VID and VOD voltages.
7.7 Clock Input Characteristics (OSCin)
3.135 V < VDD_PLL2OSC, VDD_PLL1, VDD_PLL2CORE, VDD_CORE < 3.465 V;
1.7 V < VDD_IO, VDD_OSC, VDDO_x < 3.465 V; –40°C < TA < 85°C and TPCB ≤ 105°C. Typical values at VDD_PLL2OSC,
VDD_PLL1, VDD_PLL2CORE, VDD_CORE = 3.3 V, VDD_IO, VDD_OSC, VDDOx = 1.8 V, TA = 25°C, at the Recommended
Operating Conditions and are not assured.
PARAMETER
TEST CONDITIONS
MIN
(2)
10
300
10
600
Single-ended, AC-coupled
(1)
TYP
MAX
UNIT
fOSCin
PLL2 reference input
SLEWDIFF
Differential input slew rate (4)
20% to 80%
0.2
6
V/ns
SLEWSE
Single-ended input slew rate (4)
20% to 80%
0.1
3
V/ns
Single-ended input voltage
AC-coupled to OSCin;
OSCin* AC-coupled to Ground
0.5
3.3
Vpp
AC-coupled
0.4
3.3
Vpp
VOSCin
VID,pp
Peak-to-peak differential input voltage
See Figure 9
IDC
Input duty cycle
(1)
(2)
(3)
(4)
(5)
10
Differential, AC-coupled
(3)
MHz
(5)
45%
50%
55%
FOSCin maximum frequency assured by characterization. Production tested at 122.88 MHz.
See Driving CLKin and OSCin Pins With a Single-Ended Source.
See Driving CLKin and OSCin Pins With a Differential Source.
To meet the jitter performance listed in the subsequent sections of this data sheet, the minimum recommended differential slew rate for
all input clocks is 3 V/ns; this is especially true for single-ended clocks. Phase noise performance begins to degrade as the clock input
slew rate is reduced. However, the device functions at slew rates down to the minimum listed. When compared to single-ended clocks,
differential clocks (LVDS, LVPECL) are less susceptible to degradation in phase noise performance at lower slew rates due to their
common mode noise rejection. However, TI also recommends using the highest possible slew rate for differential clocks to achieve
optimal phase noise performance at the device outputs.
See Differential Voltage Measurement Terminology for definition of VID and VOD voltages.
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7.8 PLL1 Specification Characteristics
3.135 V < VDD_PLL2OSC, VDD_PLL1, VDD_PLL2CORE, VDD_CORE < 3.465 V;
1.7 V < VDD_IO, VDD_OSC, VDDO_x < 3.465 V; –40°C < TA < 85°C and TPCB ≤ 105°C. Typical values at VDD_PLL2OSC,
VDD_PLL1, VDD_PLL2CORE, VDD_CORE = 3.3 V, VDD_IO, VDD_OSC, VDDOx = 1.8 V, TA = 25°C, at the Recommended
Operating Conditions and are not assured.
PARAMETER
TEST CONDITIONS
fPD1
PLL1 phase detector frequency
VTUNE
CTRL_VCXO tune voltage
PN10kHz
PLL 1/f noise at 10-kHz offset.
Normalized to 1 GHz output
frequency. (1)
BWmin
Minimum PLL1 bandwidth
BWmax
Maximum PLL1 bandwidth
PFDspur
(1)
MIN
TYP
0
PLL1 PFD update spur
UNIT
4
MHz
3.3
10-Hz loop bandwidth
–130
300-Hz loop bandwidth
–131
Measured with PLL1 only. PLL1
Bandwidth set to 50 Hz. PLL1 PFD
update frequency 1 MHz.
MAX
V
dBc/Hz
3
Hz
300
Hz
–150
–100 dBc/Hz
A specification in modeling PLL in-band phase noise is the 1/f flicker noise, LPLL_flicker(f), which is dominant close to the carrier. Flicker
noise has a 10 dB/decade slope. PN10kHz is normalized to a 10-kHz offset and a 1-GHz carrier frequency. PN10kHz = LPLL_flicker(10
kHz) – 20log(Fout / 1 GHz), where LPLL_flicker(f) is the single side band phase noise of only the flicker noise's contribution to total noise,
L(f). To measure LPLL_flicker(f) it is important to be on the 10 dB/decade slope close to the carrier. A high compare frequency and a clean
crystal are important to isolating this noise source from the total phase noise, L(f). LPLL_flicker(f) can be masked by the reference
oscillator performance if a low power or noisy source is used. The total PLL in-band phase noise performance is the sum of LPLL_flicker(f)
and LPLL_flat(f).
7.9 PLL2 Specification Characteristics
3.135 V < VDD_PLL2OSC, VDD_PLL1, VDD_PLL2CORE, VDD_CORE < 3.465 V;
1.7 V < VDD_IO, VDD_OSC, VDDO_x < 3.465 V; –40°C < TA < 85°C and TPCB ≤ 105°C. Typical values at VDD_PLL2OSC,
VDD_PLL1, VDD_PLL2CORE, VDD_CORE = 3.3 V, VDD_IO, VDD_OSC, VDDOx = 1.8 V, TA = 25°C, at the Recommended
Operating Conditions and are not assured.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
125
MHz
250
MHz
(1)
EN_PLL2_REF_2X = 1 ;
OSCin duty cycle 40% to 60%
fdoubler_max
Doubler input frequency
fPD2
Phase detector frequency
PN10kHz
PLL 1/f noise at 10-kHz offset. (3)
Normalized to
1-GHz output frequency
fVCO
VCO tuning range
(2)
400-kHz loop bandwidth
–120
5870
After programming for lock, no changes
to output configuration are permitted to
assure continuous lock
dBc/Hz
6175
MHz
145
°C
|ΔTCL|
Allowable temperature drift for
continuous lock (4)
BWmin
Minimum PLL2 bandwidth
90
kHz
BWmax
Maximum PLL2 bandwidth
1000
kHz
(1)
(2)
(3)
(4)
The EN_PLL2_REF_2X bit enables/disables a frequency doubler mode for the PLL2 OSCin path.
Assured by characterization. ATE tested at 258 MHz.
A specification in modeling PLL in-band phase noise is the 1/f flicker noise, LPLL_flicker(f), which is dominant close to the carrier. Flicker
noise has a 10 dB/decade slope. PN10kHz is normalized to a 10-kHz offset and a 1-GHz carrier frequency. PN10kHz = LPLL_flicker(10
kHz) – 20log(Fout / 1 GHz), where LPLL_flicker(f) is the single side band phase noise of only the flicker noise's contribution to total noise,
L(f). To measure LPLL_flicker(f) it is important to be on the 10 dB/decade slope close to the carrier. A high compare frequency and a clean
crystal are important to isolating this noise source from the total phase noise, L(f). LPLL_flicker(f) can be masked by the reference
oscillator performance if a low power or noisy source is used. The total PLL in-band phase noise performance is the sum of LPLL_flicker(f)
and LPLL_flat(f).
Maximum Allowable Temperature Drift for Continuous Lock is how far the temperature can drift in either direction from the value and still
have the part stay in lock; this implies the part will work over the entire frequency range. However, if the temperature drifts more than
the maximum allowable drift for continuous lock, it will be necessary to reload the appropriate register to ensure it stays in lock.
Regardless of what temperature the part was initially programmed at, the temperature must never drift outside the frequency range of
–40°C to 105°C without violating specifications.
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7.10 Clock Output Type Characteristics (CLKoutX) (1)
3.135 V < VDD_PLL2OSC, VDD_PLL1, VDD_PLL2CORE, VDD_CORE < 3.465 V;
1.7 V < VDD_IO, VDD_OSC, VDDO_x < 3.465 V; –40°C < TA < 85°C and TPCB ≤ 105°C. Typical values at VDD_PLL2OSC,
VDD_PLL1, VDD_PLL2CORE, VDD_CORE = 3.3 V, VDD_IO, VDD_OSC, VDDOx = 1.8 V, TA = 25°C, at the Recommended
Operating Conditions and are not assured.
PARAMETER
fCLKout
Output frequency
TEST CONDITIONS
MIN
TYP
1000
6-mA HSDS
1500
8-mA HSDS
2000
16-mA HCSL
ODC
TR
Output duty cycle
Output rise time
Output fall time
VOH
Output high voltage
VOL
Output low voltage
VOD,pp
ΔVOD
(1)
12
Differential output voltage
Change in VOD for complementary
output states
UNIT
MHz
1500
4-mA HSDS
45%
50%
55%
6-mA HSDS
45%
50%
55%
8-mA HSDS
45%
50%
55%
8-mA HSDS, >1.5 GHz
40%
16-mA HCSL
45%
4-mA HSDS
245.76 MHz, 20% 6-mA HSDS
to 80%,
8-mA HSDS
RL = 100 Ω
16-mA HCSL
60%
50%
55%
148
164
ps
148
73
4-mA HSDS
TF
MAX
4-mA HSDS
149
245.76 MHz, 80% 6-mA HSDS
to 20%,
8-mA HSDS
RL = 100 Ω
16-mA HCSL
163
ps
146
74
4-mA HSDS
0.5
0.75
6-mA HSDS
0.72
1.06
8-mA HSDS
0.75
1.3
16-mA HSCL
0.75
1.04
4-mA HSDS
0.1
0.18
6-mA HSDS
0.15
0.26
8-mA HSDS
0.17
0.31
16-mA HSCL
0.0
0.05
4-mA HSDS
958
6-mA HSDS
1380
8-mA HSDS
1544
16-mA HSCL
1807
V
V
mVpp
4-mA HSDS
–15
6-mA HSDS
–20
15
20
8-mA HSDS
–90
115
16-mA HCSL
–15
15
mVpp
See test load description in Output Termination Scheme.
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7.11 Oscillator Output Characteristics (OSCout)
3.135 V < VDD_PLL2OSC, VDD_PLL1, VDD_PLL2CORE, VDD_CORE < 3.465 V;
1.7 V < VDD_IO, VDD_OSC, VDDO_x < 3.465 V; –40°C < TA < 85°C and TPCB ≤ 105°C. Typical values at VDD_PLL2OSC,
VDD_PLL1, VDD_PLL2CORE, VDD_CORE = 3.3 V, VDD_IO, VDD_OSC, VDDOx = 1.8 V, TA = 25°C, at the Recommended
Operating Conditions and are not assured.
PARAMETER
Output frequency (1)
fCLKout
TEST CONDITIONS
(2)
MIN
TYP
200
4-mA HSDS (3)
800
(3)
1000
8-mA HSDS
16-mA HCSL (3)
ODC
TR / T
VOH
Output duty cycle
F
Output rise/fall time
Output high voltage
Output low voltage
45%
50%
55%
4-mA HSDS
45%
50%
55%
8-mA HSDS
45%
50%
55%
16-mA HCSL
45%
50%
55%
20% to 80%, CL = 2 pF, 1.8 V LVCMOS
156
80% to 20%, CL = 2 pF, 1.8 V LVCMOS
273
< 300 MHz, 20 % to 80 %, RL = 100 Ω,
4-mA HSDS
176
> 300 MHz, 20 % to 80 %, RL = 100
Ω, 4-mA HSDS
152
< 300 MHz, 20% to 80%, RL = 100 Ω, 8mA HSDS
183
> 300 MHz, 20 % to 80 %, RL = 100 Ω,
8-mA HSDS
138
20 % to 80 %, RL = 100 Ω, 16-mA HCSL
135
0.46
0.7
8-mA HSDS
0.82
1.19
16-mA HCSL
0.61
0.89
0.1
0.22
8-mA HSDS
0.11
0.24
0.02
0.06
4-mA HSDS
600
775
950
8-mA HSDS
1240
1548
16-mA HCSL
1000
1360
Output high current (source)
VOUT = 2 pF to GND, 1.8-V LVCMOS
–25
IOL
Output low current (sink)
VOUT = 2 pF to GND, 1.8-V LVCMOS
26
(1)
(2)
(3)
mA
mA
0.1
0.34
0.45
DC-Coupled, 8-mA HSDS
0.3
0.55
0.7
IOUT at VOUT = 0.9 V
V
mVpp
DC-Coupled, 4-mA HSDS
DC-Coupled, 16-mA HCSL
V
0.36
4-mA HSDS
IOH
Output impedance
300
1.44
Differential output voltage
ROUT
ps
4-mA HSDS
VOD,pp
Output common mode
MHz
300
1-mA load, 1.8-V LVCMOS
16-mA HCSL
VOX
UNIT
400
2-pF load, 1.8-V LVCMOS
1-mA load, 1.8-V LVCMOS
VOL
MAX
2-pF load, 1.8-V LVCMOS (3)
V
0.34
67
Ω
Assured by characterization. ATE tested to 122.88 MHz.
OSCout Divider maximum input frequency is 1.5 GHz.
See test load description in Output Termination Scheme.
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7.12 Jitter and Phase Noise Characteristics for CLKoutX and OSCout
3.135 V < VDD_PLL2OSC, VDD_PLL1, VDD_PLL2CORE, VDD_CORE < 3.465 V;
1.7 V < VDD_IO, VDD_OSC, VDDO_x < 3.465 V; –40°C < TA < 85°C and TPCB ≤ 105°C. Typical values at VDD_PLL2OSC,
VDD_PLL1, VDD_PLL2CORE, VDD_CORE = 3.3 V, VDD_IO, VDD_OSC, VDDOx = 1.8 V, TA = 25°C, at the Recommended
Operating Conditions and are not assured.
PARAMETER
L(f)CLKout/OSCoutNF
L(f)CLKoutNF,ADLY
TEST CONDITIONS
Noise floor
20-MHz offset
≤ 100-Hz loop bandwidth for PLL1
400-kHz loop bandwidth for
PLL2 (1)
Noise floor with analog delay
enabled
20-MHz offset
≤ 100-Hz loop bandwidth for PLL1
400-kHz loop bandwidth for
PLL2 (1)
122.88 MHz
122.88 MHz,
maximum analog
delay setting
MIN
–166
HSDS 6 mA
–166
HSDS 8 mA
–166
HCSL 16 mA
–165
OSCout, HSDS 4
mA
–161
OSCout, HSDS 8
mA
–161
OSCout, LVCMOS
–156
HSDS 4 mA
–151
HSDS 6 mA
–151
HSDS 8 mA
–151
HCSL 16 mA
–151
Offset = 100 Hz
L(f)CLKoutPN
SSB phase noise (2)
122.88-MHz output frequency
≤ 100-Hz loop bandwidth for PLL1
400-kHz loop bandwidth for PLL2
(1) (3)
Offset = 10 kHz
–139
Offset = 100 kHz
–147
Offset = 800 kHz
–158
(1) (3)
JCLKout
fCLKout = 122.88 MHz
Integrated RMS jitter
≤ 100-Hz loop bandwidth for PLL1
400-kHz loop bandwidth for PLL2
(1) (4)
(1)
(2)
(3)
(4)
14
dBc/Hz
dBc/Hz
–159
HSDS 8 mA
–166
HCSL 16 mA
–165
Offset = 100 Hz
L(f)OSCoutPN
UNIT
–97
–126
Offset = 10 MHz
MAX
dBc/Hz
Offset = 1 kHz
Offset = 1 MHz
SSB phase noise
122.88-MHz output frequency
≤ 100-Hz loop bandwidth for PLL1
400-kHz loop bandwidth for PLL2
TYP
HSDS 4 mA
–97
Offset = 1 kHz
–136
Offset = 10 kHz
–148
Offset = 100 kHz
–157
Offset = 1 MHz
HSDS 4 mA
–160
Offset = 10 MHz
HSDS 8 mA
–160
HSDS 8 mA, BW = 100 Hz to 20 MHz
dBc/Hz
160
HSDS 8 mA, BW = 10 kHz to 20 MHz
75
HCSL 16 mA, BW = 100 Hz to 20 MHz
160
HCSL 16 mA, BW = 10 kHz to 20 MHz
75
fs rms
VCXO used is a 122.88-MHz Crystek CVHD-950-122.880.
Phase noise is defined in dual-loop mode and in single PLL mode if OSCin is used as the ref input.
The input is configured to either a full swing AC-coupled, single-ended signal or a LVDS like AC-coupled differential signal. The input
frequency is 122.88 MHz. VDD_IN is at 1.8 V.
PLL1 and PLL2 settings optimized to meet multicarrier GSM phase-noise specifications. For RMS jitter optimized settings, see PLL1 and
PLL2.
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7.13 Clock Output Skew and Isolation Characteristics
3.135 V < VDD_PLL2OSC, VDD_PLL1, VDD_PLL2CORE, VDD_CORE < 3.465 V;
1.7 V < VDD_IO, VDD_OSC, VDDO_x < 3.465 V; –40°C < TA < 85°C and TPCB ≤ 105°C. Typical values at VDD_PLL2OSC,
VDD_PLL1, VDD_PLL2CORE, VDD_CORE = 3.3 V, VDD_IO, VDD_OSC, VDDOx = 1.8 V, TA = 25°C, at the Recommended
Operating Conditions and are not assured.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
60
95
UNIT
|TSKEW|
Maximum CLKoutX to
CLKoutY
Same format, after SYNC
FCLK = 245.76 MHz, RL= 100 Ω, AC-coupled
tPDCLKin0_
CLKoutX
Absolute propagation delay
from CLKin0 to CLKout0
Buffer mode
fin=fout=122.88 MHz
CLKout0_TYPE = HSDS 8 mA
isolationSYSrefDeviceCLKtyp
Isolation between a SYSref
signal to a DeviceClk signal (1)
CLKout2 = 7.68 MHz (SYSref, HSDS 8 mA,
aggressor)
CLKout3 = 122.88 MHz (DeviceClk, HSDS 8
mA, victim)
–94
dBc
isolationCLKoutXtyp
Isolation between 2 adjacent
CLKout channels (1)
CLKoutX = 153.6 MHz (HSDS 8 mA,
aggressor)
CLKoutY = 122.88 MHz (HSDS 8 mA, victim)
–70
dBc
isolationOSCoutCLKouttyp
Isolation between OSCout and
CLKoutX channels (1)
OSCout = 30.72 MHz (HSDS 8 mA,
aggressor)
CLKoutY = 122.88 MHz (HSDS 8 mA, victim)
–99
dBc
PLL2 PFD update frequency = 122.88 MHz
(aggressor)
CLKoutX = 491.52 MHz (HSDS 8 mA, victim)
–80
dBc
PLL2 PFD update frequency = 122.88 MHz
(aggressor)
CLKoutX = 1228.8 MHz (HSDS 8 mA, victim)
–80
dBc
isolationPLL2PFDDeviceCLKtyp
(1)
Isolation between PLL2 PFD
update and CLKoutX
channels (1)
3
|ps|
ns
Isolation in the victim channel is measured at aggressor frequency in power spectrum relative to the carrier (victim). Measured with
< 100-Hz resolution bandwidth. Internal LDO must be enabled.
7.14 Clock Output Delay Characteristics
3.135 V < VDD_PLL2OSC, VDD_PLL1, VDD_PLL2CORE, VDD_CORE < 3.465 V;
1.7 V < VDD_IO, VDD_OSC, VDDO_x < 3.465 V; –40°C < TA < 85°C and TPCB ≤ 105°C. Typical values at VDD_PLL2OSC,
VDD_PLL1, VDD_PLL2CORE, VDD_CORE = 3.3 V, VDD_IO, VDD_OSC, VDDOx = 1.8 V, TA = 25°C, at the Recommended
Operating Conditions and are not assured.
PARAMETER
TEST CONDITIONS
fADLYmax
Maximum analog delay frequency
tstepADLY1st
1st Analog delay step size
tstepADLYvariation
Analog delay step size variation
Variation over all steps
tstepDDLY1.47456GHz
Digital delay step size at 1.47456 GHz
Half-step enabled
tstepDDLYvariation
Digital delay step size variation
MIN
TYP
MAX
UNIT
200
MHz
300
ps
66
ps
339
ps
0
ps
7.15 DEFAULT POWER on RESET CLOCK OUTPUT Characteristics
3.135 V < VDD_PLL2OSC, VDD_PLL1, VDD_PLL2CORE, VDD_CORE < 3.465 V;
1.7 V < VDD_IO, VDD_OSC, VDDO_x < 3.465 V; –40 °C < TA < 85°C and TPCB ≤ 105°C. Typical values at VDD_PLL2OSC,
VDD_PLL1, VDD_PLL2CORE, VDD_CORE = 3.3 V, VDD_IO, VDD_OSC, VDDOx = 1.8 V, TA = 25°C, at the Recommended
Operating Conditions and are not assured.
PARAMETER
fCLKout-startup
(1)
(2)
TEST CONDITIONS
Default OSCout clock frequency at device
power on after RESETN = 1 (1) (2)
SYNC pin pulled Low at start up
VCXO used is a 122.88-MHz
Crystek CVHD-950-122.880
MIN
TYP
MAX
122.88
UNIT
MHz
Assured by characterization. ATE tested at 122.88 MHz.
OSCout will oscillate at start-up at the frequency of the VCXO attached to OSCin port. All other outputs are disabled.
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7.16 Power Supply Characteristics
3.135 V < VDD_PLL2OSC, VDD_PLL1, VDD_PLL2CORE, VDD_CORE < 3.465 V;
1.7 V < VDD_IO, VDD_OSC, VDDO_x < 3.465 V; –40°C < TA < 85°C and TPCB ≤ 105°C. Typical values at VDD_PLL2OSC,
VDD_PLL1, VDD_PLL2CORE, VDD_CORE = 3.3 V, VDD_IO, VDD_OSC, VDDOx = 1.8 V, TA = 25°C, at the Recommended
Operating Conditions and are not assured.
PARAMETER
IDD_PD
TEST CONDITIONS
MIN
TYP
MAX
12
20
mA
10 HSDS 8-mA clocks enabled at 122.88
MHz
OSCout disabled, LOS disabled
PLL1 and PLL2 locked.
122.88 MHz at CLKin0 and 122.88-MHz
VCXO
950
1050
mW
10 HSDS 4-mA clocks enabled at 122.88
MHz
OSCout disabled, LOS disabled
PLL1 and PLL2 locked.
122.88 MHz at CLKin0 and 122.88-MHz
VCXO
880
950
mW
41.1
49.1
mA
Power-down supply current
Total power consumption (1)
PTotal
UNIT
IDDO_X
CLKoutX supply current
(VDDO_3/4, VDDO_7/8)
See PTotal Test Condition (HSDS 8-mA)
IDDIO
IO supply current
See PTotal Test Condition (HSDS 8-mA)
5.3
8.4
mA
IDD_PLL1
PLL1 supply current
See PTotal Test Condition (HSDS 8-mA)
14.8
16.1
mA
IDD_PLL2CORE
PLL2 core supply current
See PTotal Test Condition (HSDS 8-mA)
45.5
52.0
mA
IDD_PLL2OSC
PLL2 OSC supply current
See PTotal Test Condition (HSDS 8-mA)
60.7
64.9
mA
IDD_CORE
Core supply current
See PTotal Test Condition (HSDS 8-mA)
22.5
28.6
mA
IDD_OSC
OSC supply current
See PTotal Test Condition (HSDS 8-mA)
3.2
4.1
mA
(1)
See applications section Power Supply Recommendations for Icc for specific part configuration and how to calculate Icc for a specific
design.
7.17 Typical Power Supply Noise Rejection Characteristics
Typical values at VDD_PLL2OSC, VDD_PLL1, VDD_PLL2CORE, VDD_CORE = 3.3 V, VDD_IO, VDD_OSC,
VDDOx = 1.8 V, TA = 25°C, at the Recommended Operating Conditions and are not assured. Sinusoidal noise injected in
either of the following supply nodes: VDD_PLL2OSC, VDD_PLL1, VDD_PLL2CORE, VDD_CORE, VDD_IO, VDD_OSC, or
VDDOx
PARAMETER
TEST
CONDITION
VDD_PLL1
VDD_PLL2
OSC
VDD_PLL2
CORE
VDD_CORE
VDD_OSC/
VDD_IO
VDDOx
–59
–94
n/a
–104
–108
n/a
–71
–87
–101
n/a
n/a
–101
–87
–81
–90
n/a
n/a
–93
PSNR10kHz
10-kHz spur on 122.88MHz output
PSNR100kHz
100-kHz spur on 122.88MHz output
PSNR500kHz
500-kHz spur on 122.88MHz output
PSNR1MHz
1-MHz spur on 122.88MHz output
–100
–80
–83
n/a
n/a
–88
PSNR10kHz
10-kHz spur on 122.88MHz output
–53
–88
–109
–100
–104
–107
PSNR100kHz
100-kHz spur on 122.88MHz output
–65
–81
–98
n/a
n/a
–98
PSNR500kHz
500-kHz spur on 122.88MHz output
–81
–75
–84
–108
n/a
–87
PSNR1MHz
1-MHz spur on 122.88MHz output
–94
–74
–77
–104
n/a
–82
16
25-mV ripple on
supply.
Single HSDS 8mA
output enabled.
50-mV ripple on
supply.
Single HSDS 8mA output
enabled.
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UNIT
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
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7.18 SPI Interface Timing
TEST CONDITIONS
MIN
TYP
MAX
UNIT
tds
Setup time for SDI edge to SCLK rising edge
See Figure 1
10
ns
tdH
Hold time for SDI edge from SCLK rising edge
See Figure 1
10
ns
tSCLK
Period of SCLK
See Figure 1
50
ns
tHIGH
High width of SCLK
See Figure 1
25
ns
tLOW
Low width of SCLK
See Figure 1
25
ns
tcs
Setup time for CS* falling edge to SCLK rising edge
See Figure 1
10
ns
tcH
Hold time for CS* rising edge from SCLK rising edge
See Figure 1
30
tdv
SCLK falling edge to valid read back data
See Figure 1
ns
20
ns
7.19 Timing Diagram
Each serial interface access cycle is exactly (2 + N) bytes long, where N is the number of data bytes. A frame is
initiated by asserting SCS* low. The frame ends when SCS* is de-asserted high. The first bit transferred is the
R/W bit. The next 15 bits are the register address and the remaining bits are data. For all writes, data is
committed in bytes as the 8th data bit of a data field is clocked in on the rising edge of SCL. If the write access is
not an even multiple of 8 clocks, the trailing data bits are not committed. On read access, data is clocked out on
the falling edge of SCL on the SDO pin.
Four-wire mode read back has the same timing as the SDIO pin.
R/W bit = 0 is for SPI write. R/W bit = 1 is for SPI read.
See Programming for more details.
SDIO
(WRITE)
R/W
A14 to A0
tdS
tdH
tcS
tHIGH
D7 to D2
D1
D0
SCL
SDIO
(Read)
tcH
tLOW
tSCLK
D7 to
D2
D1
tdV
D0
Data valid only
during read
SCS*
Figure 1. SPI Timing Diagram
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7.20 Typical Characteristics
7.20.1 Clock Output AC Characteristics
NOTE
These plots show performance at frequencies beyond what the part is ensured to operate
at to give the user an idea of the capabilities of the part, but they do not imply any sort of
ensured specification.
18
Figure 2. LMK0461x CLKout2 Phase Noise
VCO = 5898.24 MHz
CLKout2 Frequency = 122.88 MHz
HSDS 8 mA
Figure 3. LMK0461x CLKout2 Phase Noise
VCO = 5898.24 MHz
CLKout2 Frequency = 122.88 MHz
HSDS 8 mA
With PLL2 3rd Order Pole
Figure 4. LMK0461x CLKout2 Phase Noise
VCO = 5898.24 MHz
CLKout2 Frequency = 245.76 MHz
HSDS 8 mA
Figure 5. LMK0461x CLKout2 Phase Noise
VCO Frequency = 5898.24 MHz
CLKout2 Frequency = 983.04 MHz
HSDS 8 mA
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Clock Output AC Characteristics (continued)
Figure 6. LMK0461x CLKout2 Phase Noise
VCO Frequency = 5898.24 MHz
CLKout2 Frequency = 1474.56 MHz
HSDS 8 mA
Figure 7. LMK0461x CLKout2 Phase Noise
VCO Frequency = 6144 MHz
CLKout2 Frequency = 1228.8 MHz
HSDS 8 mA
Figure 8. LMK0461x CLKout2 Phase Noise
VCO Frequency = 5898.24 MHz
CLKout2 Frequency = 1966.08 MHz
HSDS 8 mA
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8 Parameter Measurement Information
8.1 Differential Voltage Measurement Terminology
The differential voltage of a differential signal can be described by two different definitions, causing confusion
when reading data sheets or communicating with other engineers. This section addresses the measurement and
description of a differential signal so the reader is able to understand and distinguish between the two different
definitions when used.
The first definition used to describe a differential signal is the absolute value of the voltage potential between the
inverting and noninverting signal. The symbol for this first measurement is typically VID or VOD, depending on if
an input or output voltage is being described.
The second definition used to describe a differential signal is to measure the potential of the noninverting signal
with respect to the inverting signal. The symbol for this second measurement is VSS and is a calculated
parameter; this signal does not exist in the IC with respect to ground, it only exists in reference to its differential
pair. VSS can be measured directly by oscilloscopes with floating references, otherwise this value can be
calculated as twice the value of VOD as described in the first description.
Figure 9 illustrates the two different definitions side-by-side for inputs and Figure 10 illustrates the two different
definitions side-by-side for outputs. The VID and VOD definitions show VA and VB DC levels that the noninverting
and inverting signals toggle between with respect to ground. VSS input and output definitions show that if the
inverting signal is considered the voltage potential reference, the noninverting signal voltage potential is now
increasing and decreasing above and below the noninverting reference. Thus the peak-to-peak voltage of the
differential signal can be measured.
VID and VOD are often defined as volts (V) and VSS is often defined as volts peak-to-peak (VPP).
VID Definition
VID Definition for Input
Non-Inverting Clock
VA
VIDpp
VID
VB
Inverting Clock
VID = | VA - VB |
VIDpp = 2· VID
GND
Figure 9. Two Different Definitions for
Differential Input Signals
VOD Definition
VOD Definition for Output
Non-Inverting Clock
VA
VODpp
VOD
VB
Inverting Clock
VOD = | VA - VB |
VODpp = 2· VOD
GND
Figure 10. Two Different Definitions for
Differential Output Signals
Refer to application note AN-912 Common Data Transmission Parameters and their Definitions (SNLA036) for
more information.
8.2 Output Termination Scheme
This section describes the test loads setup during device characterization.
8.2.1 HSDS 4/6/8mA
Available on CLKoutX/CLKoutX* and OSCout/OSCout*. When OSCout is programmed for differential output from
OSCin, the OSCout signal will be inverted from input.
CPARA≤ 3 pF
20
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Output Termination Scheme (continued)
The differential transmission line impedance is 100 Ω.
Receiver
CPARA
50 Ohm
HSDS
VTERM
Diff Microstrip
50 Ohm
CPARA
Figure 11. HSDS Test and Simulation Circuit
8.2.2 HCSL
Available on CLKoutX/CLKoutX* and OSCout/OSCout*. When OSCout is programmed for differential output from
OSCin, the OSCout signal will be inverted from input..
CPARA ≤ 3 pF
The differential transmission line impedance is 100 Ω.
Receiver
Rs (opt.)
50 Ohm
HSCL
CPARA
VTERM
Diff Microstrip ~10cm
50 Ohm
50 Ohm
CPARA
Figure 12. HCSL Test and Simulation Circuit
8.2.3 LVCMOS
Available at STATUS0/1 and OSCout/OSCout*.
CLoad = 10 pF
RS is optional to adjust LVCMOS driver impedance to transmission line.
The transmission line impedance is 50 Ω.
High Impedance Probe
Rs (opt.)
Oscilloscope
LVCMOS
Microstrip ~10cm
CLoad
Figure 13. LVCMOS Test and Simulation Circuit
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9 Detailed Description
9.1 Overview
The LMK04610 device is very flexible in meeting many application requirements. The typical use case for
LMK04610 is a cascaded Dual Loop Jitter Cleaner with optional support for JESD204B.
NOTE
While the Clock outputs (CLKoutX) do not provide LVCMOS outputs, the OSCout may be
used to provide LVCMOS outputs.
In addition to dual-loop operation, by powering down various blocks, the LMK04610 may be configured for singleloop or clock distribution modes also.
9.1.1 Jitter Cleaning
The dual-loop PLL architecture of LMK04610 provides the lowest jitter performance over a wide range of output
frequencies and phase noise integration bandwidths. The first stage PLL (PLL1) is driven by an external
reference clock and uses an external VCXO to provide a frequency accurate, low phase noise reference clock for
the second stage frequency multiplication PLL (PLL2).
PLL1 typically uses a narrow loop bandwidth (typically 10 Hz to 200 Hz) to retain the frequency accuracy of the
reference clock input signal while simultaneously suppressing the higher offset frequency phase noise that the
reference clock may have accumulated along its path or from other circuits. This cleaned reference clock
provides the reference input to PLL2.
The low phase noise reference provided to PLL2 allows PLL2 to operate with a wide loop bandwidth (typically 90
kHz to 500 kHz). The loop bandwidth for PLL2 is chosen to take advantage of the superior high offset frequency
phase noise profile of the internal VCO and the good low offset frequency phase noise of the reference VCXO.
Ultra-low jitter is achieved by allowing the external VCXO phase noise to dominate the final output phase noise
at low offset frequencies and the internal VCO’s phase noise to dominate the final output phase noise at high
offset frequencies. This results in best overall phase noise and jitter performance.
9.1.2 Two Redundant Reference Inputs (CLKin0/CLKin0*, CLKin1/CLKin1*)
The LMK04610 has two reference clock inputs for PLL1. They are CLKin0, CLKin1. The active clock is chosen
based on CLKin_SEL_MODE. Automatic or manual switching can occur between the inputs.
Fast manual switching between CLKin0 and CLKin1 reference clocks is possible with external pin CLKin_SEL.
9.1.3 VCXO Buffered Output
The LMK04610 provides OSCout, which by default is a buffered copy of the PLL1 feedback or PLL2 reference
input. This reference input is typically a low noise VCXO. This output can be used to clock external devices such
as microcontrollers, FPGAs, CPLDs, and so forth, before the LMK04610 is programmed.
The OSCout buffer output types are LVCMOS, HSDS, and HCSL. When using HSDS and HCSL output from
OSCin, the output will be inverted from OSCin input.
OSCout has the option to fan out a copy of PLL2 output.
9.1.4 Frequency Holdover
LMK04610 supports holdover operation for PLL1 to keep the clock outputs on frequency with minimum drift when
the reference is lost until a valid reference clock signal is re-established.
9.1.5 Integrated Programmable PLL1 and PLL2 Loop Filter
LMK04610 features programmable loop filter for PLL1 and PLL2. See PLL1 and PLL2.
22
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Overview (continued)
9.1.6 Internal VCOs
LMK04610 has an internal VCO in PLL2 with 5870 MHz to 6175 MHz tuning range. The output of the VCO is
routed through a mandatory divider (by 3, by 4, by 5, or by 6) to the Clock Distribution Path. This limits the Clock
Distribution Path frequency to 2058 MHz. This same clock is also fed back to the PLL2 phase detector through
the N-divider (feedback divider).
9.1.7 Clock Distribution
The LMK04610 features a total of 10 PLL2 clock outputs driven from one of the internal VCOs.
All PLL2 clock outputs have programmable output types. They can be programmed to HSDS or HCSL.
If OSCout is included in the total number of clock outputs the LMK04610 is able to distribute up to 11 differential
clocks.
The following sections discuss specific features of the clock distribution channels that allow the user to control
various aspects of the output clocks.
9.1.7.1 Output Clock Divider
The output divider supports a divide range of 1 to 65535 (even and odd) with 50% output duty cycle.
9.1.7.2 Output Clock Delay
The clocks include both a analog and digital delay for phase adjustment of the clock outputs.
The analog delay allows a nominal 60-ps step size and range from 0 to 1.2 ns of total delay per output. See
Analog Delay for further information.
The digital delay allows an output channel to be delayed from 1 to 255 VCO cycles. The delay step can be as
small as half the period of the clock distribution path. For example, 1.5-GHz clock distribution path frequency
results in 333-ps coarse tuning steps. The coarse (digital) delay value takes effect on the clock outputs after a
SYNC event. See Digital Delay for further information.
1. Fixed Digital Delay (per output channel) – Allows all the output channels to have a known phase relationship
upon a SYNC event. Typically performed at start-up.
2. Dynamic Digital Delay (per output) – Allows additional coarse adjustment per output.
9.1.7.3 Glitchless Half-Step and Glitchless Analog Delay
The device clocks include a features to ensure glitchless operation of the Half-Step and analog delay operations
when enabled.
9.1.7.4 Programmable Output Formats
All LMK0461x clock outputs (CLKoutX) can be programmed to an HSDS or HCSL output type. The OSCout can
be programmed to an HSDS, HCSL, or LVCMOS output type.
Any HSDS output type can be programmed to typical 800-, 1200-, or 1600-mVpp differential amplitude levels.
When OSCout is programmed for differential output from OSCin, the OSCout signal will be inverted from input.
9.1.7.5 Clock Output SYNChronization
Using the SYNC input causes all active clock outputs to share a rising edge as programmed by fixed digital
delay.
The SYNC event must occur for digital delay values to take effect.
9.1.8 Status Pins
The LMK0461x provides status pins that can be monitored for feedback or in some cases used for input,
depending upon device programming. For example:
• Indication of the loss-of signal (LOS) for CLKinX.
• Indication of the selected active clock input.
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Overview (continued)
•
•
PLL1 and PLL2 lock signal.
Holdover Status.
The status pins can be programmed to a variety of other outputs including PLL divider outputs, combined PLL
lock detect signals, readback, and so forth. See Programming for more information.
A full list of functions can be found in STATUS0/1 and SYNC Pin Functions.
9.2 Functional Block Diagram
Figure 14 illustrates the complete block diagram.
VCXO
VDD_IO
P
(1.8 - 3.3 V)
VDD1v8
M
U
X
Prop
/R
DIV
DIVIDER
DDLY
ADLY
&
DDLY
DRV
CLKout4
LDO
P
VDDO_5
(1.8 - 3.3 V)
CLKout5
DRV
ADLY
&
DDLY
Int. Div
16 bit
DDLY
P
CLKout6
DRV
LDO
VDDO_6
(1.8 - 3.3 V)
VDDO_7/8
(1.8 - 3.3 V)
ADLY
&
DDLY
P
DRV
CLKout7
ADLY
&
DDLY
DDLY
Clock Distribution Path
SYNC & SYSREF_REQ
Generation
Async SYNC
Boot-Up
LDO
SYNC & RST
DRV
CLKout8
(PLL1/PLL2 Status & Test)
SYNC & RST
STATUS0
(LVCMOS)
DDLY
M
U
X
STATUS1
(LVCMOS)
Int. Div
16 bit
M
U
X
Digital
Device Control
and Status
ADLY
&
DDLY
(Digital Status & Debug)
CLKout9
DRV
LDO
ADLY
&
DDLY
Output
Channels
JESD204B
SYNC
DDLY
Holdover
SYNC & RST
SYNC
CLKout3
SYNC & RST
Int. Div
16 bit
RESET
VDDO_3/4
(1.8 - 3.3 V)
DRV
SYNC & RST
Int. Div
16 bit
Input Stage
Clock
Control
CLKOUT1
Control Voltage
Supplies / BGAP / POR
Device
Configuration
Registers
REF
Storage
Storage
Storage
Intgrl
Async SYSREF_REQ
SS
DRV
P
I
/N
DIV
SDIO
DRV
REF
PRE
SCALER
DDLY
x2
Clock Distribution Path
LDO
1v8/1V2
PLL2
BYPASS 1
(Digital
Control)
VDD1v8
PLL2
BYPASS 1
REF
INIT &
RESET
VDD3v3
CLKOUT0
DDLY
Clock
Control
LC-VCO
LDO
3v3/2v5
LDO
SYNC & RST
Digital
Strg-CP
SD-PLL2
CLKout2
DRV
ADLY
&
DDLY
/N
VDDO_1/2
(1.8 - 3.3 V)
ADLY
&
DDLY
I
OSCin
P
Ctrl_VCXO
ADC/
DAC
ADLY
&
DDLY
MUX
controls CLKin0/1
0 V t 3.3 V
Analg
Prop-CP
Int. Div
16 bit
/R
DIV
CLKout1
DRV
LDO
SYNC & RST
LDO
1v8/1V2
Int. Div
16 bit
Ref Clk
M
U
X
CMOS
&
Diff
OSCout
DRV
VDD3v3
Int. Div
16 bit
PLL1
CMOS
&
Diff
Int. Div
8 bit
ADLY
&
DDLY
DDLY
DIGITAL FSM
BIASING
SCL
VDD_OSC
(1.8 - 3.3 V)
Int. Div
16 bit
CLKin1_R_DIV
CLKin0_R_DIV
2
LOS
(Digital Control)
VDD_CORE
(3.3 V)
VDD_PLL2OSC
(3.3 V)
SYNC & RST
DIV
CLKin_SEL
CTRL_VCXO
PLL1_CAP
M
U
X
M
U
X
CLKin1
VDD_PLL2CORE
(1.8 - 3.3 V)
CMOS & Diff
Input Stage
CLKin0
VDD_PLL1
(3.3 V)
OSCin
PLL2_CAP0/1
DRV
P
VDDO_9/10
(1.8 - 3.3 V)
CLKout10
Figure 14. Detailed LMK04610 Block Diagram
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9.3 Feature Description
9.3.1 Reference Inputs (CLKin0/CLKin0*, CLKin1/CLKin1*)
External VCXO
VDD_IO
LOS
Divider implemented
in PLL1
CLKin0
R div
8bit
CLKin1
R div
8bit
PLL1
Digital Logic
- Pin Select
- LOS detection
CLKin_SEL
PLL2
Figure 15. LMK04610 Clock Input Block
9.3.1.1 Input Clock Switching
Manual, pin select, and priority or automatic are three different kinds clock input switching modes can be set with
the CLKIN_SEL_MODE register.
Below is information about how the active input clock is selected and what causes a switching event in the
various clock input selection modes.
9.3.1.1.1 Input Clock Switching – Register Select Mode
When CLKIN_SEL_MODE = 2, then CLKin0 or CLKin1 is selected through register control (SW_REFINSEL[3:0]).
If holdover is entered in this mode, then the device relocks to the selected CLKin upon holdover exit.
Table 2. Active Clock Input – Register Select Mode (SW_REFINSEL[3:0])
SW_REFINSEL[3:0]
ACTIVE CLOCK (LMK04610)
0100b
CLKin0
1000b
CLKin1
9.3.1.1.2 Input Clock Switching – Pin Select Mode (CLKin_SEL)
When CLKIN_SEL_MODE = 1, the pin CLKin_SEL selects which clock input is active.
Configuring Pin Select Mode
The polarity of CLKin_SEL input pin can be inverted with the CLKinSEL1_INV bit.
Table 3 defines which input clock is active depending on CLKin_SEL state.
Table 3. Active Clock Input – Pin Select Mode (CLKin_SEL), CLKinSEL_INV = 0
PIN CLKin_SEL
ACTIVE CLOCK
Low
CLKin0
High
CLKin1
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9.3.1.1.3 Input Clock Switching – Automatic Mode
When CLKINSEL1_MODE = 0, the input clock switching is in automatic mode. The priority of each input clock
can be individually set by programming CLKINx_PRIO[1:0] as shown in Table 4:
Table 4. Clock Input Priority Selection
CLKINx_PRIO[1:0]
CLKINx
00b
Disabled
01b
Priority 1 (Highest)
10b
Priority 2 (Lowest)
SPACER
NOTE
Equal priority setting for two CLKINx inputs are not allowed.
The clock inputs in this mode are monitored by on-chip LOS detection circuits. The device reads the priority bits
at start-up and locks to the input clock with highest priority. In the event of input clock loss, the internal PLL
switches to the next available clock. TI recommends using holdover mode while using the automatic reference
clock switching. See Holdover for programming the holdover mode.
In this case, the outputs clocks see minimum disturbance while switching from one clock to the other. In the
event of reference clock loss, the PLL1 enters the holdover mode. After the internal logic switches the PLL1 input
clock to the next available clock as per priority setting, PLL1 holdover exit is initiated and PLL1 relocks to the
new clock with minimum disturbance. Figure 16 describes the sequence of operations in the automatic reference
clock switching mode while holdover is enabled and programmed.
Lock State
(CLKinX)
CLKinX Priority Loop
IN
NO
NO
Holdover LOS
enabled?
(PLL1_HOLDOVER_
LOS_MASK=0)
Switch to next
highest priority
CLKinZ
LOSz = 0?
Configure CLKinX
PLL1 R divider
YES
OUT
YES
Keep PLL1 R/N divider in Reset
Assert PLL1 reset
Release holdover status
Release PLL1 R/N divider
LOSX = 1?
YES
CLKinY disabled (optional)
LOSY disabled (optional)
Lock State
(CLKinX)
Figure 16. Input Clock Switching – Priority Loop
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9.3.1.2 Loss of Signal Detection – LOS
The loss of signal detection circuit is available for all clock inputs. It has programmable assertion and deassertion cycles. LOS detection circuit reliable operation is ensured with >200-mVpp differential or >200-mV
single-ended CLKin amplitude and input frequencies between 10 MHz to 500 MHz. Maximum input frequency for
the doubler in the LOS block is 250 MHz. The ratio between VCXO frequency and input frequency must be
between 0.25 and 4.
9.3.1.2.1 LOS – Assertion
LOS assertion time is programmable between 1 to 8 VCXO clock cycles. The LOS assertion time is programmed
through
CLKINx_LOS_LAT_SEL[7:0].
LOS_LAT_SEL
is
an
8-Bit
code.
Additionally,
CLKINx_LOS_FRQ_DBL_EN bit controls the frequency doubler for the LOS block. This is especially important
for VCXO frequencies equal or smaller than CLKinX frequency.
For correct operation of LOS, the reference clock must be switched to logic low level (differential or singleended).
Example 1:
LOS_LAT_SEL = 0010 0000
LOS_FRQ_DBL_EN = 0
LOS_LAT_SEL
VCXO = 122.88 MHz
CLKinX = 30.72 MHz
LOS_FRQ_DBL_EN
CNT reset
CNT reset
LOS_LAT_SEL
Example 2:
LOS (internal)
LOS detection 0.5 RefCLK Cycles
LOS_LAT_SEL
LOS_LAT_SEL = 0000 1000
LOS_FRQ_DBL_EN = 1
LOS
(internal)
VCXO
VCXO = 122.88 MHz
CLKinX = 122.88 MHz
x2
CNT reset
CNT reset
CLKinX
LOS (internal)
LOS detection 1 RefCLK Cycles
Example 3:
LOS_LAT_SEL
LOS_LAT_SEL = 0000 0010
LOS_FRQ_DBL_EN = 1
STATUSx
VCXO = 30.72 MHz
CLKinX = 122.88 MHz
LOS (internal)
LOS detection 3 RefCLK Cycles
CNT reset
Figure 17. LOS Detection
Table 5. Recommended LOS Register Configurations
CLKin TO OSCin FREQUENCY
RATIO
LOS_LAT_SEL
LOS_FRQ_DBL_EN
MAX LOS DETECTION
LATENCY IN CLKin CYCLES
0.25
0010 0000b
0
0.5
0.5
0000 1000b
0
1
1
0000 1000b
1
1
1 (OSCin ≥ 250MHz)
0000 0100b
0
2
2
0000 0100b
1
2
4
0000 0010b
1
3
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9.3.1.2.2 LOS – Reference Clock Recovery
LOS de-assertion can be programmed to 15 to 4095 reference clock cycles (CLKINx_LOS_REC_CNT[7:0]).
Number of Cycles
programmable
CLKinX
LOS (internal)
LOS (STATUSx pin)
Figure 18. LOS Deassertion
9.3.1.3 Driving CLKin and OSCin Inputs
9.3.1.3.1 Driving CLKin and OSCin Pins With a Differential Source
The CLKin ports and OSCin can be driven by differential signals. TI recommends setting the input mode to
differential (CLKINX_SE_MODE = 0) when using differential reference clocks. The LMK0461x internally AC
couples the inputs. An optional AC-coupling cap can be connected as shown in input termination sachems. The
recommended circuits for driving the CLKin or OSCin pins with either LVDS or LVPECL are shown in Figure 19
and Figure 20.
100: Trace
(Differential)
LVDS
100:
CLKinX/
OSCin
0.1 PF
LMK046XX
0.1 PF
CLKinX*/
OSCin*
Copyright © 2017, Texas Instruments Incorporated
240:
Figure 19. Termination for an LVDS Reference Clock Source
240:
0.1 PF
0.1 PF
100: Trace
(Differential)
100:
LVPECL
Ref Clk
CLKinX/
OSCin
0.1 PF
0.1 PF
LMK046XX
CLKinX*/
OSCin*
Copyright © 2017, Texas Instruments Incorporated
Figure 20. Termination for an LVPECL Reference Clock Source
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Also, a reference clock source can produce a differential sine wave output can drive the CLKin pins using
Figure 21.
NOTE
The signal level must conform to the requirements for the CLKin pins listed in Clock Input
Characteristics (CLKinX). CLKINX_SE_MODE is recommended to be set to differential
mode (CLKINX_SE_MODE = 0).
CLKinX/
OSCin
0.1 PF
100:
SINE
100: Trace
(Differential)
LMK046XX
0.1 PF
CLKinX*/
OSCin*
Copyright © 2017, Texas Instruments Incorporated
Figure 21. CLKinX/X* Termination for a Differential Sinewave Reference Clock Source
9.3.1.3.2 Driving CLKin and OSCin Pins With a Single-Ended Source
The CLKin pins of the LMK0461x family can be driven using a single-ended reference clock source, like a sine
wave source or an LVCMOS or LVTTL source. The clock is internally AC-coupled.. In the case of the sine wave
source that is expecting a 50-Ω load, TI recommends using AC coupling as shown in Figure 22 with a 50-Ω
termination.
NOTE
The signal level must conform to the requirements for the CLKin pins listed in Clock Input
Characteristics (CLKinX). CLKINX_SE_MODE is recommended to be set to single-ended
mode (CLKINX_SE_MODE = 1).
0.1 PF
50: Trace
Clock Source
CLKinX/
OSCin
50:
0.1 PF
LMK046XX
CLKinX*/
OSCin*
Copyright © 2017, Texas Instruments Incorporated
Figure 22. CLKinX/X* and OSCin AC-Coupled Single-Ended Termination
If the CLKin pins are being driven with a single-ended LVCMOS or LVTTL source, either DC coupling or AC
coupling may be used. If DC coupling is used, the CLKINX_SE_MODE should be set to single-ended buffer
mode (CLKINX_SE_MODE = 1) and the voltage swing of the source must meet the specifications for
DC-coupled, single-ended mode clock inputs given in Clock Input Characteristics (CLKinX). If AC coupling is
used, the CLKINX_SE_MODE should be set to the differential buffer mode (CLKINX_SE_MODE = 0). The
voltage swing at the input pins must meet the specifications for AC-coupled, differential mode clock inputs given
in Clock Input Characteristics (CLKinX). In this case, some attenuation of the clock input level may be required. A
simple resistive divider circuit before the AC-coupling capacitor is sufficient.
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CLKinX
50: Trace
LMK046XX
LVCMOS/LVTTL
Clock Source
0.1 PF
CLKinX*
Copyright © 2017, Texas Instruments Incorporated
Figure 23. DC-Coupled LVCMOS or LVTTL Reference Clock
9.3.2 Clock Outputs (CLKoutX)
This section describes all related features of the clock outputs.
DUAL-CLK OUTPUT CHANNEL
Channel Specific
PRE
SCAL
ER
C
P
DIVID
ER
½
Clock
Distribution Path
CMOS
OUTCHxy_DIV
CYC
DEL
16-bit Divider
RSTB
FB
DIV
CLKoutX
DDLY
ADLY
INV
CLK
SYSREF_control
PLL_WRAPPER
SD-PLL2
PF
D
CLKoutX Specific
HS_EN_CH_xy
CLK
OUTCHxy_
DYN_DDLY_CHx
CHx_ADLY
DIV_INV
CHx_ADLY_EN
DYN_DDLY_EN_CHx
OUTCHx_DRIV_MODE
CLKROOT
CHxy_DDLY
SYNC | RESET
LDO
SYNC TO ALL
CHANNELS
VDDOxy
CLKoutY Specific
SYNC_EN_CHxy
Static Digital Delay
SYNCronize
RSTB
SYSREF_REQ
SYSREF_EN_CHxy
Resampling
SYNC
DDLY
INV
CHx_SYNC
OUTCH_SYSREF_PLSCNT
Resampling
SYSREF Pulse
Counter
SYSREF_control
SYNCronize
OUTCHxy_
DYN_DDLY_CHy
CLKoutY
CHy_ADLY
DIV_INV
CHy_ADLY_EN
DYN_DDLY_EN_CHy
CHx_SYSREF_REQ
ADLY
CLK
OUTCHy_DRIV_MODE
Figure 24. Clock Output Block and SYNC Clocking Path
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9.3.2.1 HCSL
Figure 25 shows a typical implementation for the HCSL output driver mode. HCSL requires external 50-Ω
termination resistors. Optionally, source resistors in the range from 22 Ω to 33 Ω are employed to eliminate
ringing.
For HSCL outputs, set OUTCHxx_DRIV_MODE to 0x3F.
Receiver
Rs (opt.)
CPARA
50 Ohm
HSCL
VTERM
Diff Microstrip ~10cm
50 Ohm
50 Ohm
CPARA
Figure 25. HCSL Output Termination
Figure 26 and Figure 27 show different connection methods to a LVPECL receiver.
Rs (opt.)
HSCL
LVPECL
50 Ohm
50 Ohm
Vb
Figure 26. HCSL to LVPECL With Bias Voltage Vb (Voltage as Required for Receiver Bias)
3.3V
82 Ohm
Rs (opt.)
HSCL
LVPECL
50 Ohm
130 Ohm
Figure 27. HCSL to LVPECL
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9.3.2.2 HSDS
HSDS does not need external output termination (see Figure 28).
For HSDS: 8-mA outputs set OUTCHxx_DRIV_MODE to 0x18.
For HSDS: 6-mA outputs set OUTCHxx_DRIV_MODE to 0x14.
For HSDS: 4-mA outputs set OUTCHxx_DRIV_MODE to 0x10.
Receiver
CPARA
50 Ohm
HSDS
VTERM
Diff Microstrip
50 Ohm
CPARA
Figure 28. HSDS Output Termination
Figure 29 to Figure 31 show different connection methods to a LVPECL and LVDS receiver. In case of LVDS
receivers, use HSDS 4-mA or HSDS 6-mA and for LVPECL use HSDS 8-mA setting.
HSDS
LVPECL
50 Ohm
Vb
Figure 29. HSDS to LVPECL With Bias Voltage Vb (Voltage as Required for Receiver Bias)
3.3V
82 Ohm
HSDS
LVPECL
130 Ohm
Figure 30. HSDS to LVPECL
HSDS
100 Ohm
LVDS
Figure 31. HSDS to LVDS
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9.3.2.3 SYNC
See additional information about the SYNC pin in STATUS0/1 and SYNC Pin Functions.
SYNC aligns all clock outputs to start at a common rising clock distribution path clock edge. Clocks divided by 1
or divider bypass are not gated during the SYNC event.
SYNC is not available in buffer mode.
Clock Distribution
Path (internal)
CLKoutA
(div by 1)
tskew1
CLKoutB
(div by 2)
No CLKout during SYNC
CLKoutC
(div by 5)
CLKoutD
(div by 5 + HS)
Latency 1
SYNC
Latency 2
SYNC asserted
SYNC released
Figure 32. SYNC Example
9.3.2.4 Digital Delay
Digital (coarse) delay allows an output to be delayed by 1 to 255 periods of the clock distribution path frequency.
The delay step can be as small as half the period of the clock distribution path frequency by using the
HS_EN_CHx bit.
The digital delay step size calculates with: 1 / VCO frequency / prescaler
1. Fixed digital delay (per output channel)
2. Dynamic digital delay (per output)
9.3.2.4.1 Fixed Digital Delay
Fixed digital delay value takes effect on the clock outputs after a SYNC event. As such, the outputs are LOW for
a while during the SYNC event. Applications that cannot accept clock breakup when adjusting digital delay
should use dynamic digital delay.
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Clock Distribution
Path
No CLKout during SYNC
CLKoutX
2 Cycles DDLY
CLKoutY
3 Cycles DDLY
1 Clock Distribution Path cycle delay
Fixed Delay
SYNC
SYNC event
Figure 33. Fixed Digital Delay Example
Table 6. Digital Delay Register Controls
REGISTER NAME
DESCRIPTION
HS_EN_CHx
Enables a Half-Step for Channel X: 0.5 / VCO frequency / Prescaler
CHx_DDLY
Sets number of Digital Delay steps for Channel X. The channel delays 0 to 255 Clock
Distribution Path periods compared to other channels.
9.3.2.4.2 Dynamic Digital Delay
Additionally, for the fixed digital delay per output channel, each output can be individually delayed using dynamic
digital delay. Up to 5 periods of the clock distribution path frequency can be shifted.
The setting applies without SYNC to the output.
Table 7. Dynamic Digital Delay Register Controls
REGISTER NAME
DESCRIPTION
DYN_DDLY_CHx_EN
Enable CHx Dynamic Digital Delay.
DYN_DDLY_CHx
Sets number of Dynamic Digital Delay steps for Output X. The Output delays 0 to 5 Clock
Distribution Path periods compared to other channels.
9.3.2.5 Analog Delay
Analog delay is available for all outputs. The typical step size is 60 ps and covers a total range of 1.3 ns.
Table 8. Analog Delay Register Controls
34
REGISTER NAME
DESCRIPTION
CHx_ADLY_EN
Enables Analog Delay for Channel X.
CHx_ADLY
Analog Steps can be programmed from 0 to 15. The resulting delay is shown in Figure 34.
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330
300 306
270
240
210
180
150
120
124
90
72
59
71
59
45
30
49
53
Step 9
70
Step 8
95
60
87
59
64
57
50
Step 15
Step 14
Step 13
Step 12
Step 11
Step 10
Step 7
Step 6
Step 5
Step 4
Step 3
Step 2
Step 1
ADLY Enable
0
Figure 34. Analog Delay
9.3.3 OSCout
The default function for OSCout is providing two buffered LVCMOS copies (in phase or complementary) of the
external VCXO. Additionally, an 8-bit divider is integrated. The multiplexer selects the VCXO input or high-speed
clock distribution tree. The output type can be programmed to HSDS, HCSL, and LVCMOS. See Output
Termination Scheme for test load descriptions. When OSCout is programmed for differential output from OSCin,
the OSCout signal will be inverted from input.
NOTE
External VCXO
VCXO_CTRL
OSCin
CMOS
&
DIFF
Reference
PLL1
Integer Div
8-bit
CMOS
DIFF
OSCout
1.5GHz Channel Clock Tree
M
U
X
PLL2
Figure 35. OSCout Block
9.3.3.1 Pin-Controlled OSCout Divider
During power up (see Power-Up Sequence) after RESET = 1, the state of the SYNC pin is sampled. The input
level determines the OSCout divider setting.
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NOTE
This function is only available after power up and RESET transition from LOW to HIGH.
Table 9. Pin-Controlled OSCout Divider Settings
SYNC PIN INPUT LEVEL AT POWER UP
OR RESET TRANSITION FROM LOW TO HIGH
OSCout DIVIDER SETTING
LOW
1
OPEN
2
HIGH
4
9.3.4 STATUS0/1 and SYNC Pin Functions
Status and SYNC Pins supports 1.8-V logic and it can be configured as:
• Input
• Output
Common STATUS0/1 and SYNC Pin Functions describes the common input and output pin functions.
SYNC and STATUS0 have additional features that are restricted to the pins. See Additional SYNC Pin Functions.
9.3.4.1 Common STATUS0/1 and SYNC Pin Functions
Two status pins are available (STATUS0, STATUS1). STATUSx/SYNC_OUTPUT_HIZ = 1 configures the pins as
input, while STATUSx/SYNC_OUTPUT_HIZ = 0 configures the pins as output. STATUSx/SYNC_INT_MUX
register configures the pin functions in Table 10.
Table 10. Common STATUS0/1 and SYNC Pin Functions
FUNCTION
INPUT/OUTPUT
DESCRIPTION
SDO
Output
Serial Data Output for 4-wire SPI
LD1 and LD2
Output
Digital Lock Detect for PLL1 and PLL2
LD1
Output
Digital Lock Detect for PLL1
LD2
Output
Digital Lock Detect for PLL2
LD1 and LD2 and not Holdover
Output
PLL1 Lock Detect and PLL2 Lock Detect and not PLL1 Holdover
LD1 and not Holdover
Output
PLL1 Lock Detect and not PLL1 Holdover
LOS
Output
Output of LOS Block
Holdover status
Output
Output of Holdover Status. High = Holdover. Low = Normal operation
Holdover Control
Input
Manual Holdover entry through pin. See Holdover.
Copy SYNC pin
Output
Outputs a copy of SYNC pin
Copy CLKIN_SEL pin
Output
Outputs a copy of CLKIN_SEL pin
PLL2 Reference Clock
Output
PLL2 Reference Clock (Copy of OSCin divided by PLL2 R)
PLL1_R
Output
Output PLL1_R Clock Frequency
PLL2_R
Output
Output PLL2_R Clock Frequency
PLL1_N
Output
Output PLL1_N Clock Frequency
PLL2_N
Output
Output PLL2_N Clock Frequency
Logic High
Output
Logic Low
Output
9.3.4.2 Additional STATUS0 Pin Functions
This chapter describes the additional functions that are available on STATUS0 pin only.
Table 11. Additional STATUS0 Pin Functions
36
FUNCTION
INPUT/OUTPUT
DESCRIPTION
CLKIN_SEL0
Input
See for implementation details.
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9.3.4.3 Additional SYNC Pin Functions
This chapter describes the additional functions that are available on SYNC pin only.
Table 12. Additional SYNC Pin Functions
FUNCTION
INPUT/OUTPUT
DESCRIPTION
OSCout Div Control
Input
Sampled Pin Logic state at power up configures default OSCout divider setting.
Low level = divide by 1
Mid level = divide by 2
High level = divide by 4
SYNC
Input
SYNC_PIN_FUNC=0 → SYNC output channels. See SYNC
SYNC_PIN_FUNC=1 → Sysref Request
SYNC_PIN_FUNC=2 → Reset PLL1 N-/R-Dividers
SYNC_PIN_FUNC=3 → Reserved
9.3.5 PLL1 and PLL2
LMK0461x has two programmable PLLs. PLL1 is a very low bandwidth PLL with an external VCXO. The
bandwidth of the PLL1 can be programmed from 3 Hz to 300 Hz. PLL2 is a high bandwidth PLL using an onchip, very low phase noise LC VCO. PLL2 bandwidth can be programmed from 90 kHz to 1 MHz. The detailed
description about the individual PLLs is provided in the following sections.
9.3.5.1 PLL1
PLL1 in LMK0461x is a very low bandwidth PLL. The PLL is a fully programmable, ultra-flexible design and is
intended to be used for jitter cleaning of the noisy input clock. The PLL uses a semi-digital architecture and there
is no need for external loop filter. The loop-filter has separated integral and proportional paths, which can be
programmed individually to define the PLL transfer. There is a possibility to add higher order poles by connecting
a capacitor outside the chip with a fixed on-chip resistor RCTRL. The block diagram of the PLL1 is shown in
Figure 36. The PLL uses an external VCXO as a voltage controlled oscillator. Both positive and negative gain
VCXOs are supported by LMK046xx.
VCTRL
PLL1_PROP
RCTRL
PLL_RDIV
PROP
PROP_MODE
PLL1_RDIV
PFD
INT
PLL1_INTG
PLL_NDIV
PLL1_NDIV
PROP_MODE
Figure 36. PLL1 Block Diagram
To reduce lock time, PLL1 supports two locking modes which can be individually configured by the user. When
configured, PLL1 starts with Fastlock (with very high integral gain) and after lock, it switches to desired integral
gain.
PLL1 Bandwidth depends on the VCXO gain and loop parameters. LMK0461x PLLs are designed with active
damping technique. For a given VCXO gain and divider settings, the bandwidth can be programmed by using the
PLL1_PROP settings. The higher the value, the higher the bandwidth.
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Table 13 shows the internal PLL1 parameter, register and programming ranges. Use the TICS Pro EVM tool to
calculate PLL1_PROP, PLL1_PROP_LF, PLL1_INTG, and PLL1_INTG_LF values.
Table 13. PLL1 Parameter and Register
PARAMETER
REGISTER
DESCRIPTION
MIN
TYP
MAX
CLKINx_PLL1_RDIV
0x1B,0x1C,0X1D,0x1E,
0x1F,0x20,0x21,0x22
Input clock divider for PLL1
1
32771
PLL1_NDIV
0x61,0x62
Feedback clock divider for PLL1
1
32771
127
PLL1_PROP
0x5A
Proportional gain setting
0
PLL1_PROP_FL
0x5B
Proportional gain setting for Fast Lock
0
PLL1_INTG
0x59
Integral gain setting
0
0
15
PLL1_INTG_FL
0x59
Integral gain setting for Fast Lock
0
15
15
RCTRL
UNIT
127
500
Ω
9.3.5.1.1 PLL1 Proportional Modes
PLL1 bandwidth can be increased or decreased even further by using the different PROP modes (see Table 14).
Table 14. PLL1 Proportional Modes
PROP MODE
REGISTER SETTINGS
DUTY CYCLE OF CLOCK
Default
PLL1_RDIV_4CY = 0
PLL1_NDIV_4CY = 0
50%
Low Pulse mode
PLL1_RDIV_4CY = 1
PLL1_NDIV_4CY = 1
PLL1_FBCLK_INV = 1
CLKINx_PLL1_INV = 1
(4/DIV) * 100
High Pulse mode
PLL1_RDIV_4CY = 1
PLL1_NDIV_4CY = 1
PLL1_FBCLK_INV = 0
CLKINx_PLL1_INV = 0
(1-4/DIV) * 100
In the default input mode, the proportional is effective for 50% of the PFD clock period. Using low pulse mode,
the effect of the proportional is reduced which results in a reduced PLL bandwidth. Similarly, using the high pulse
mode, the proportional is effective for more than half of the PFD cycle, which results in higher bandwidth.
PLL1_INTG settings affect the integral gain in the loop. TI recommends using setting 0 in normal mode and
higher settings only for Fast lock using PLL1_INTG_FL.
9.3.5.1.2 PLL1 Higher Order Poles
There are no external resistors and capacitors required for the low bandwidth PLL1. However, to introduce 3rd
order pole in the loop, external capacitor C3 can be attached to the control voltage, which in combination with the
on-chip resistor, creates a pole at the desired frequency. Higher order poles can also be introduced using
external resistors and capacitors like in standard analog PLLs as shown in Figure 37.
PLL1
PLL1
R1
C3
Figure 37. 3rd Order Loop Filter
38
Figure 38. Higher Order Loop Filter
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9.3.5.2 PLL2
The second PLL in LMK046xx is a high bandwidth PLL requiring no external components. The PLL contains a
very low phase noise on chip LC-based Voltage controlled oscillator (VCO). The VCO is very flexible and full
programmable. Similar to PLL1, PLL2 is also a semi-digital PLL designed with an active damping concept. The
bandwidth of the PLL can be programmed between 90 kHz to 1 MHz. PLL2 also has separated integral and
proportional paths to control the VCO. The 3rd order pole can also be introduced by selecting the integrated
resistors and capacitors.
The input clock frequency to the PLL2 can be doubled by using an integrated frequency doubler. Apart from that
there are additional input modes possible to have more flexibility for bandwidth programming.
LC VCO
x2
PRE
SCALER
DIVIDER
Prop
R DIV
I
/N
DIV
Intgrl
Figure 39. PLL2 Block Diagram
9.3.5.2.1 PLL2 Divider
PLL2 contains three dividers. Input clock can be divided down by using reference divider (PLL2_RDIV). Second
divider is the high-frequency prescalar at the output of the VCO. Third divider is in the PLL feedback path which
defines the PLL frequency multiplication ratio in combination with prescalar. Each of the three dividers is
programmable with the registers as described in Table 15.
Table 15. PLL2 Divider
PARAMETER
REGISTER
DESCRIPTION
PLL2_RDIV
0x76
Input clock divider for PLL2
MIN
1
TYP
MAX
31
PLL2_NDIV
0x73, 0x74
Feedback clock divider for
PLL2
1
65535
PLL2_PRESCALER
0x146
The prescaler defines the
Clock Distribution Frequency.
3
6
UNIT
9.3.5.2.2 PLL2 Input Modes
PLL2 has four input modes which can be selected by the user. These modes give more flexibility to adjust the
PLL2 bandwidth. See Table 16.
Table 16. PLL2 Input Modes
INPUT MODE
DESCRIPTION
Doubler Mode
The Input clock gets multiplied by 2. The duty cycle of the clock is 50%.
Pulse mode
The duty cycle of the input clock is adjusted to a fixed value and is >50%.
RDIV mode
The input divider is used to divide down the frequency with the range as shown in Table 15.
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9.3.5.2.3 PLL2 Loop Filter
PLL2 design is based on semi-digital PLL architecture where the proportional and integral parts are separated
from each other. Proportional gain and integral gain can be individually programmed by the user to define the
bandwidth and noise transfer characteristics of the PLL2 in combination with the input modes.
Table 17. PLL2 Parameter and Register
PARAMETER
REGISTER
DESCRIPTION
PLL2_PROP_SET
0x72
Proportional gain setting
MIN
0
63
PLL2_CPROP
0x151
Proportional cap setting
3
5.4
PLL2_INTG
0x80
Integral gain setting
PLL2_RFILT
0x151
3rd order filter resistor selection
PLL2_CFILT
0x153
3rd order filter capacitor selection
TYP
MAX
UNIT
pF
0
31
4.7
9.2
kΩ
124
pF
0
15
The proportional gain can be changed using PLL2_PROP and PLL2_CPROP. The difference between the two
modes is, PLL2_PROP controls the proportional charge pump current to define the gain and PLL2_CPROP
controls the on-chip capacitor used in active damping to define the proportional gain. Higher values of
PLL2_PROP result in higher proportional gain and Higher PLL2_CPROP values result in lower proportional gain.
9.3.5.2.4 PLL2 3rd Order Loop Filter
PLL2 also has programmable on-chip 3rd order loop filter in the proportional path to create additional pole for
better noise cutting, as shown in Figure 39. The resistor and capacitor value can be programmed as shown in
Table 18.
Table 18. 3rd Order Loop Filter
PARAMETER
DESCRIPTION
R3
PLL2_EN_FILTER=1 → Enables resistor
PLL2_RFILT=0 → 9.2 kΩ
PLL2_RFILT=1 → 4.7 kΩ
C3
PLL2_CFILT
00000 → 0 pF
00001 → 4 pF
..
11111 →124 pF
9.3.5.2.5 PLL2 Voltage Controlled Oscillator (VCO)
PLL contains on chip very low phase noise LC oscillator. The tuning range of the oscillator is 5870 MHz to 6175
MHz. The VCO is tuned to the target frequency using the semi-digital control by the PLL loop. Due to the semidigital control, the PLL loops tracks the temperature and input frequency change with its loop bandwidth.
40
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9.3.5.2.6 Examples of PLL2 Setting
This section shows PLL2 setting examples to generate given loop bandwidth.
Table 19. PLL2 Settings
PLL2_PROP
PLL2_INTG
PLL2_
CPROP
R3, C3 (1)
Doubler Invert
20
0
5.4 pF
disabled, 0 pF
Doubler Invert
21
0
5.4 pF
4.7 kΩ, 96 pF
6
Doubler Invert
20
0
5.4 pF
disabled, 0 pF
6
Doubler Invert
7
0
5.4 pF
4.7 kΩ, 96 pF
FIN_PLL2
FVCO
PLL2_RDIV
PLL2_NDIV
122.88 MHz
5898.24 MHz
1
4
6
122.88 MHz
5898.24 MHz
1
4
6
30.72 MHz
5898.24 MHz
1
16
30.72 MHz
5898.24 MHz
1
16
(1)
PRESCALER INPUT MODE
See Table 18 for reference.
9.3.5.3 Digital Lock Detect
Both PLL1 and PLL2 support digital lock detect. Digital lock detect compares the phase between the reference
path (R) and the feedback path (N) of the PLL. When the time error (phase error) between the two signals is less
than a specified window size (ε), a lock detect count increments.
When the PLL1 lock detect count reaches a user specified value, PLL1_LOCKDET_CYC_CNT, lock detect is
asserted true. Once digital lock detect is true, a single phase comparison outside the specified window causes
the digital lock detect to be asserted false (see Figure 40).
NO
START
PLL1
Lock Detected = False
Lock Count = 0
NO
YES
Phase Error < x
Increment
PLL1 Lock Count
PLL1 Lock Count =
YES
PLL1_LOCKDET_CYC_CNT
PLL1
Lock Detected = True
Phase Error < x
YES
NO
Figure 40. PLL1 Digital Lock Detect Flowchart
PLL2 DLD requires register 0xF6 = 0x02, 0x85 = 0x00, and 0x86 = 0x00 set. Then to program register 0xAD for
valid digital lock detect. See Recommended Programming Sequence. When the PLL2 lock detect count reaches
a user specified value, PLL2_LOCKDET_CYC_CNT, lock detect is asserted true. Once digital lock detect is true,
a single phase comparison outside the specified window causes the digital lock detect to be asserted false (see
Figure 41).
START
Set Register 0xAD = 0x30
Wait 20 ms
Set Register 0xAD = 0x00
NO
PLL2
Lock Detected = False
Lock Count = 0
Phase Error < x
NO
YES
Increment
PLL2 Lock Count
PLL2 Lock Count =
YES
PLL2_LOCKDET_CYC_CNT
PLL2
Lock Detected = True
Phase Error < x
YES
NO
Figure 41. PLL2 Digital Lock Detect Flowchart
This incremental lock detect count feature functions as a digital filter to ensure that lock detect isn't asserted for
only a brief time when the phases of R and N are within the specified tolerance for only a brief time during initial
phase lock.
The digital lock detect signal can be monitored on the Status_LD1 or Status_LD2 pin. The pin may be
programmed to output the status of lock detect for PLL1, PLL2, or both PLL1 and PLL2.
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PLL (Analog Domain)
Digital-Block (Digital Domain)
LOCK_CYC_CNT
REF
SYS
Div2
bypass
WNDW
CMP
Div2
bypass
VDD SYNC
CNT
LOCK
WNDW
CMP
Figure 42. Digital Lock Detect Implementation
9.3.5.3.1 Calculating Digital Lock Detect Frequency Accuracy
See Digital Lock Detect Frequency Accuracy for more detailed information on programming the registers to
achieve a specified frequency accuracy in ppm with lock detect.
The digital lock detect feature can also be used with holdover to automatically exit holdover mode. See Exiting
Holdover for more info.
9.3.6 Holdover
Holdover mode causes PLL2 to stay locked on frequency with minimal frequency drift when an input clock
reference to PLL1 becomes invalid. While in holdover mode, the PLL1 charge pump is TRI-STATED and a fixed
tuning voltage is set on CPout1 to operate PLL1 in open-loop.
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9.3.6.1 Holdover Flowchart
Lock State
(CLKinX)
- CLKinY disabled (optional)
- LOSY disabled (optional)
Manual
Holdover
through Pin or
Register?
NO
NO
NO NO
Holdover Rail detect
enabled?
Holdover PLL1 DLD
enabled?
(PLL1_HOLDOVER_
RAILDET_EN=1)
(PLL1_HOLDOVER_
LCKDET_MASK=0)
YES
YES
Holdover LOS
enabled?
(PLL1_HOLDOVER_
LOS_MASK=0)
CLKinX Priority Loop
IN
YES
RAILDET_UPP <
VCTRL <
RAILDET_LOW?
YES
NO
NO
NO
PLL1 LD = 0?
NO
LOSX = 1?
YES
Switch to next
highest Priority
CLKinZ
LOSz = 0?
- configure CLKinX
PLL1 R Divider
YES
YES
OUT
YES
NO
- enable Holdover
- enable Holdover status
- hold last Vctrl value
- enable Holdover
- enable Holdover status
- hold last Vctrl value
CLKINSEL1_MODE =
AUTO?
YES
- enable Holdover
- enable Holdover status
- hold last Vctrl value
Start
Holdover
Counter
YES
Holdover
Counter enabled?
Holdover Counter Loop
(PLL1_HOLDOVER_MAX
_CNT_EN=1)
NO
NO
Deassert Pin or
register?
Wait for SPI command to exit
Holdover
(Rail detect: PLL1_HOLDOVER_DLD_SWRST
or
PLL1 Loss of Lock:
PLL1_HOLDOVER_LOCKDET_SWRST)
NO
NO
LOSX = 0?
YES
LOSX = 0?
NO
Holdover
counter
elapsed?
CLKinX Priority
Loop
YES
YES
- configure CLKinX
PLL1 R Divider
YES
CLKinX Priority
Loop
- keep PLL1 R/N Divider in Reset
- assert PLL1 reset
- release Holdover Status
- release PLL1 R/N Divider
- CLKinY disabled (optional)
- LOSY disabled (optional)
Register Setting
Lock State
(CLKinX)
Figure 43. Holdover Flowchart Using LOS
9.3.6.2 Enable Holdover
Program HOLDOVER_EN = 1 to enable holdover mode for PLL1.
9.3.6.2.1 Automatic Tracked CTRL_VCXO Holdover Mode
In holdover mode, PLL1 retains the last used control voltage.
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9.3.6.3 Enter Holdover
Holdover can be entered through different events.
• LOS_x detects reference loss.
• PLL1 DLD detects PLL1 unlock.
• CTRL_VCXO rail detect.
• Manual through register control
• Manual through pin
• Start-up into holdover
9.3.6.3.1 LOS_x Detect
Enter holdover if reference is lost.
9.3.6.3.2 PLL1 DLD Detect
Enter holdover if PLL1 is unlocked.
9.3.6.3.3 CTRL_VCXO Rail Detect
Rail detection allows to set upper and lower boundaries for the tuning voltage.
Once the boundaries are touched, the device enters holdover mode if this feature is enabled. The boundaries get
compared against the current 6-bit value of the PLL1 storage cells array, PLL1_STORAGE_CELL. It can be
determined whether the boundaries are absolute or relative boundaries.
Enter holdover if CTRL_VCXO represented as PLL1_STORAGE_CELL crosses a programmable high or low limit
of CTRL_VCXO.
• If PLL1_STORAGE_CELL ≤ RAILDET_LOW, then go to holdover or into normal operation.
• If PLL1_STORAGE_CELL ≥ RAILDET_UPP, then go to holdover or into normal operation.
CTRL_VCXO_HIGH/LOW_RAIL granularity is 82.5 mV.
9.3.6.3.3.1 Absolute Limits
RAILDET_LOW and RAILDET_UPP values are considered as absolute numbers, being compared against
current storage value.
9.3.6.3.3.2 Relative Limits
RAILDET_LOW and RAILDET_UPP values are considered as relative numbers. After PLL1 has locked the
current storage value is added to the relative numbers to form the absolute boundary.
9.3.6.3.4 Manual Holdover Enable – Register Control
When PLL1_HOLDOVER_FORCE is 1 PLL1 enters holdover mode regardless of other conditions.
9.3.6.3.5 Manual Holdover Enable – Pin Control
The SYNC control pin can be programmed to control the entry and exit of holdover.
9.3.6.3.6 Start-Up into Holdover
During the initial programming, the LMK0461x can be configured to start-up into holdover. It presets the VCXO
Control voltage to approximately 1.2 V. This allows PLL2 to lock to the VCXO reference. PLL1 locks as soon a
valid reference input clock is detected. The holdover status can be optionally displayed at the status pins.
9.3.6.4 During Holdover
PLL1 is run in open-loop mode:
• PLL1 charge pump is set to TRI-STATE.
• PLL1 DLD is unasserted.
• The HOLDOVER status is asserted.
• During holdover, if the PLL2 was locked prior to entry of holdover mode, PLL2 DLD continues to be asserted.
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LOS engine searches for active input clock.
PLL1 attempts to lock with the active clock input.
The HOLDOVER status signal can be monitored on the Status_LD1 or Status_LD2 pin by programming the
PLL1_DLD_MUX or PLL2_DLD_MUX register to Holdover Status.
9.3.6.5 Exiting Holdover
Holdover mode can be exited in one of four ways.
• Manually by programming the device from the host.
• Manual through pin.
• Automatically by a clock operating within a specified ppm of the current PLL1 frequency on the active clock
input.
• Automatically by LOS deassertion.
• Automatically by switching to next clock input after holdover counter overflow. The order of switching is set in
a priority list.
9.3.6.6 Holdover Frequency Accuracy
The holdover frequency accuracy depends on the PLL1 loop bandwidth. A low loop bandwidth of ≤10 Hz results
in less then 0.6-ppm accuracy typical.
9.3.6.7 Holdover Mode – Automatic Exit by LOS Deassertion
As soon as the reference clock is valid again and the LOS signal is deasserted, the PLL1_N and PLL1_R divider
reset and PLL1 exits holdover.
9.3.6.8 Holdover Mode – Automatic Exit of Holdover With Holdover Counter
A programmable holdover counter can be set between 0 and 17 seconds count time. The counter starts counting
as soon the device is in holdover.
If the reference clock is valid again within the specified time, the device exits holdover.
If the counter overflows, the device switches to the next clock input. The order of clock inputs is set in a priority
list.
• Minimum Holdover counter configuration step size: 4.069 ns
• Holdover counter range: 0 – 17 s
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9.3.7 JEDEC JESD204B
Table 20 illustrates the some possible SYNC and SYSREF modes.
Table 20. Possible SYNC/SYSREF_REQ Configurations
NAME
DESCRIPTION
SYNC Disabled
No SYNC occurs.
Pin or SPI SYNC
Basic SYNC functionality, SYNC pin polarity is selected by SYNC_POL.
To achieve SYNC through SPI, toggle the SYNC_POL bit.
JESD204B Pulser on pin transition.
Produce SYSREF_PULSE_CNT programmed number of pulses on pin transition. SYNC_POL can be
used to cause SYNC through SPI.
JESD204B Pulser on SPI
programming.
Programming SYSREF_PULSE_CNT register starts sending the number of pulses.
External SYSREF request
When SYNC pin is asserted, continuous SYSERF pulses occur. Turning on and off of the pulses is
SYNChronized to prevent runt pulses from occurring on SYSREF.
Continuous SYSREF
Continuous SYSREF signal.
LMK0461x family provides support for JEDEC JESD204B. High-frequency device clock and low frequency
SYSREF clocks can be generated with programmable analog and digital delays and SYNC functionality. The
device provides possibility to control the SYNC and SYSREF functions by SYNC pin (pin mode) or SPI
programming. Each clock output can be used either as a device clock or SYSREF clock. Steps to use the SYNC
and SYSREF modes are described in Figure 44.
SYNC output divider
Program SYNC mode
(Pin/SPI)
&
Enable the SYNC for the
channels to be synced
Setup SYSREF mode (and pulser)
Issue a SYNC request
(PIN/SPI)
Program SYSREF mode
(Pulser /Continuous) &
Enable SYSREF channels
Program SYSREF
Pin/SPI mode
Issue a SYSREF request
(PIN/SPI)
Figure 44. Manual SYSREF Setup
The programming of the SYNC and SYSREF modes can be already done at the device setup. One time SYNC
for the output channels is issued automatically at the device start-up irrespective of the SYNC programming.
Detail description on setting up the SYNC and SYSREF modes are described in the following sections.
9.3.7.1 SYNC Pins
The SYNC pin in LMK0461x family has multiple functions which can be configured by the user using SPI
interface. Following table lists the possible function:
Table 21. SYNC Pins
BIT NAME
FUNCTION
EN_SYNC_PIN_FUNC
Enables the different functions at the SYNC pin when 1
SYNC_INV
SYNC_PIN_FUNC[1:0]
Inverts SYNC Input when 1
00
SYNC output channels
01
SYSREF Request
10
Reset PLL1 N-divider and R-divider
11
46
Reserved
SYNC_ANALOGDLY_EN
Enables the Analog delay at the SYNC input pin
SYNC_ANALOGDLY[4:0]
Analog delay can be programed from 0-15. See Analog Delay for details
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9.3.7.2 SYNC modes
SYNC can be requested by either PIN or using the SPI interface. Following table lists the register values that
must be programmed to use the SYNC functionality:
Table 22. Additional SYNC Bits
BIT NAME
FUNCTION
GLOBAL_SYNC
Global SW SYNC. Writing 1 puts the Device into SYNC mode. Writing 0 exits SYNC mode.
SYNC_EN_CH1
SYNC_EN_CH2
SYNC_EN_CH3_4
SYNC_EN_CH5
SYNC_EN_CH6
SYNC_EN_CH7_8
SYNC_EN_CH9
SYNC_EN_CH10
Enables the corresponding channel for SYNC functionality
Steps to configure each mode are described below.
•
•
SYNC pin mode:
1. EN_SYNC_PIN_FUNC should be set to 1. This enables the different functions supported by the SYNC
pin.
2. SYNC_PIN_FUNC[1:0] should be programmed to 00b (default). This sets the SYNC pin for SYNC
function.
3. SYNC_INV, when 0, SYNC is rising edge triggered. When set to 1, the SYNC pin is internaly inverted and
is falling edge triggered.
4. SYNC_EN_CHx should be set 1 for the channels which needs to SYNCed.
5. Depending on the SYNC_INV value, the output channels are SYNChronized by either rising edge or the
falling edge on the SYNC pin.
SYNC SPI mode:
1. EN_SYNC_PIN_FUNC should be set to 0. This disables the pin mode for SYNC function.
2. SYNC_EN_CHx should be set 1 for the channels which must SYNCed.
3. Writing 1 to the GLOBAL_SYNC puts the device into SYNC mode.
9.3.7.3 SYSREF Modes
Any channel can be programmed to generate SYSREF clock. There are different SYSREF modes supported by
LMK0461x. SYSREF can be either fixed number of pulses or a continuous clock. There is a 5-bit register
provided to program the number of pulses to be generated at each SYSREF request. Also, there is a possibility
to control the number of pulses with the SYNC pin. Each SYSREF clock can be individually delayed. There are
different options to introduce the delay in the SYSREF path. See Digital Delay and Analog Delay for
programming the delays. Following bits needs to be programed to use the SYSREF feature:
Table 23. SYSREF Registers
BIT NAME
FUNCTION
EN_SYNC_PIN_FUNC
Enable SYNC_SYSREF features at SYNC pin
GLOBAL_CONT_SYSREF
Enable continuous SYSREF
GLOBAL_SYSREF
Trigger SYSREF, Self-clearing
OUTCH_SYSREF_PLSCNT
Set number of desired SYSREF pulses from 1 to 32. 0 Enables continuous SYSREF
SYSREF_EN_CH10
SYSREF_EN_CH9
SYSREF_EN_CH7_8
SYSREF_EN_CH6
SYSREF_EN_CH5
SYSREF_EN_CH3_4
SYSREF_EN_CH2
SYSREF_EN_CH1
Enable SYSREF feature at channel CHx
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9.3.7.3.1 SYSREF Pulser
This mode allows for the output of 1 to 32 SYSREF pulses for every SYNC pin event or SPI programming. This
implements the gapped periodic functionality of the JEDEC JESD204B specification.
programmable
SYSREF_PULSE_CNT
SYSREF Output
SPI Programming
Or
SYNC pin
Figure 45. SYSREF Pulser
9.3.7.3.1.1 SPI Pulser Mode
OUTCH_SYSREF_PLSCNT is a 5-bit register that can be programmed to the required number of pulses.
When GLOBAL_SYSREF is programmed to 1, fixed number of pulses are defined by
OUTCH_SYSREF_PLSCNT are generated at the output channels which are enabled for SYSREF. The
GLOBAL_SYSREF bit is cleared automatically after fulfilling the SYSREF request.
9.3.7.3.1.2 Pin Pulser Mode
By programming EN_SYNC_PIN_FUNC= 1, SYNC_PIN_FUNC=01 and OUTCH_SYSREF_PLSCNT to the
desired number of pulses, The SYSREF output is in pin control Pulser mode. The SYSREF clock can be initiated
by a pulse at the SYNC pin. Fixed number of pulses as per the OUTCH_SYSREF_PLSCNT value are generated
after a fixed latency.
9.3.7.3.1.3 Multiple SYSREF Frequencies
In case of multiple SYSREF frequencies the latencies until SYSREF pulses start are different. As shown in
Figure 46, the different SYSREF signals are rising edge aligned with the device clock. The different SYSREF
signals might not be rising edge aligned if different SYSREF frequencies are used.
DeviceCLK
SYSREF_A
SYSREF_B
Latency A
SYSREF Request
Latency B
asserted
released
Figure 46. SYSREF Timing in Pulsor Mode With Different SYSREF Frequencies
9.3.7.3.2 Continuous SYSREF
This mode allows for continuous output of the SYSREF clock.
Setting GLOBAL_CONT_SYSREF to 1 allows for continuous output of the SYSREF clock.
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Continuous operation of SYSREF is not recommended due to crosstalk from the SYSREF clock to device clock.
JESD204B is designed to operate with a single burst of pulses to initialize the system at start-up, after which it is
theoretically not required to send another SYSREF because the system continues to operate with deterministic
phases.
If continuous operation of SYSREF is required, consider using a SYSREF output from a non-adjacent output or
SYSREF from the OSCout pin to minimize crosstalk.
SYSREF Output
Figure 47. Continuous SYSREF
9.3.7.3.3 SYSREF Request
This mode allows an external source to SYNChronously turn on or off a continuous stream of SYSREF pulses
using the SYNC pin.
When programming EN_SYNC_PIN_FUNC= 1, SYNC_PIN_FUNC=01 and OUTCH_SYSREF_PLSCNT=0, the
SYSREF output is in pin mode. The SYSREF pulses can be controlled by the pulse width at the SYNC pin.
When the SYNC pin is asserted, the channel is SYNChronously set to continuous mode providing continuous
pulses at the SYSREF frequency until the SYNC pin is unasserted. SYSREF stops after completing the final
pulse SYNChronously.
SYSREF Output
SYSREF_REQ
Or
SPI
Figure 48. SYSREF Request
9.3.7.4 How to Enable SYSREF
Enabling JESD204B operation involves SYNChronizing all the clock dividers and programming of the delays,
then configuring the actual SYSREF functionality.
9.3.7.4.1 Setup Example 1: Pulser Mode, Pin Controlled
1. Program EN_SYNC_PIN_FUNC=1, SYNC pin is enabled for SYSREF requests.
2. Program SYNC_PIN_FUNC=01, SYNC pin is programmed to accept the SYSREF requests.
3. Program OUTCH_SYSREF_PLSCNT= xx (max 32), programs the number of SYSREF pulses to be
generated.
4. Program SYSREF_EN_CHxx=1, enables corresponding output channels to generate SYSREF clock pulses.
5. Apply rising Edge at SYNC pin generates xx number of at the enabled at the enabled channel.
9.3.7.4.2 Setup Example 2: Pulser Mode, Spi Controlled
1. Program EN_SYNC_PIN_FUNC=0, the SYSREF function on the SYNC pin is not enabled.
2. Program OUTCH_SYSREF_PLSCNT= xx (max 32), programs the number of SYSREF pulses to be
generated.
3. Program SYSREF_EN_CHxx=1, enables corresponding output channels to generate SYSREF clock pulses.
4. Programming GLOBAL_SYSREF=1 generates the defined number of pulses on the SYSREF enabled
channels.
9.3.8 Zero Delay Mode (ZDM)
The LMK0461x zero delay mode (ZDM) is an internal feedback loop that minimizes the phase error between
output and reference input. The feedback can be selected from CLKout5 or CLKout6.
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OSCin
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PLL2
R
Phase
Detector
PLL2
Integrated
Loop Filter
CLKoutX*
CLKoutX
- Divider
- Digital Delay
- Analog Delay
Pre
Div
N
CLKoutY*
CLKoutY
CLKoutX*
CLKoutX
- Divider
- Digital Delay
- Analog Delay
CLKoutY*
CLKoutY
Figure 49. Zero Delay Mode (ZDM)
9.3.9 Power-Up Sequence
Figure 50 shows the steps to power up the device.
All Supplies
powered up
Power Supplies
all off
DEVICE
NOT READY
Ramp-up Power Supplies
DEVICE IDLE
In
Power-Down
State
Release RESETn
DEVICE IDLE
READY FOR SPI
PROGRAMMING
RESETn = 0
(Power-down)
RESETn = X
(Power-down)
RESETn = 1
Program device configuration settings
DEVICE IDLE
DEVICE
CONFIG
PROGRAMMING
DONE
Trigger Startup
Sequence through SPI
DEV_STARTUP = 1
(self clearing bit)
RESETn = 1
DEVICE
BOOTING
UP
DEVICE
RUNNING
RESETn = 1
RESETn = 1
STAT0/1
indicates
PLL Lock
Figure 50. Simplified Power-Up Sequence
The first step is to apply all the supplies needed for device to be functional. The RESETn should be kept at logic
0 when power supplies start ramping. LMK046xx devices do not need any specific power up sequencing for the
external power supplies. The on-chip POR logic makes sure that the device stays in power-down state until all
the supplies are available.
After all the device power supplies are stable, RESETn can be released to logic 1. The device enters idle state
and is now ready for the SPI programming.
After programming the device configuration, the DEV_start-up should be triggered using SPI, which initiates the
device bootup sequence. The loading of the configurations to the corresponding functional blocks and enable
sequencing is cared for by the on-chip state machines. One-time SYNC is also issued to the output channels
during device booting. The lock signals for the PLLs can be observed at the STAT0/1.
50
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Figure 51 shows the LMK0461x booting sequence of operations in details. Branch A, B, and C run in parallel.
RESETN = 0
SET OSCout
divider = 1
Low level
Enable OSCout
buffer:
LVCMOS
All Supplies
powered up
Sample SYNC pin
voltage level
RESETN = 1
SET OSCout
divider = 2
Mid level
SPI interface
ready
SET OSCout
divider = 4
High level
Branch A
(PLL1)
Program
device and
boot up
Branch B
(PLL2)
PLL1 Enabled?
YES
Internal LDO
settling time
PLL2 Enabled?
Branch C
(Outputs)
NO
PLL2 in power down
mode.
PLL2 REF clock
available.
Internal LDO
settling time
YES
Set Prop/
Store-CP to
^( •š o} l_
value
YES
^( •š o} l_
enabled?
YES
Internal LDO
settling time
PLL2
Amplitude
Calibration
NO
Force Holdover
Mode with
CRTL_VCXO =
VDD/2
Assert internal
SYNC signal
PLL1_STARTUP_I
N_HOLDOVER
Set?
Waiting for
PLL2 lock
NO
Release reset
of channels
Release reset
of channels
NO
NO
PLL1_N,
PLL1_R divider
reset is
released
CLKinX
available?
Wait for PLL2
lock
Release
internal SYNC
signal
Wait for PLL1
Lock
Set Prop/
Store-CP to
^v}v-( •š o} l_
value
MUTE enabled?
YES
YES
^( •š o} l_
enabled?
NO
Release
internal SYNC
signal
PLL2 locks
STATUS0/1 will
indicate PLL lock
Switch digital-block
clock to PLL2 Ref
clock source
Figure 51. Detailed Power-Up Sequence
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9.4 Device Functional Modes
The following section describes the settings to enable various modes of operation for the LMK0461x device
family.
The LMK0461x device is a flexible device that can be configured for many different use cases. The following
simplified block diagrams help show the user the different use cases of the device.
9.4.1 Dual PLL
Figure 60 illustrates the typical use case of the LMK0461x device family in dual-loop mode. In dual-loop mode
the reference to PLL1 from CLKin0 or CLKin1. An external VCXO is used to provide feedback for the first PLL
and a reference to the second PLL. This first PLL cleans the jitter with the VCXO by using a narrow loop
bandwidth. The VCXO output may be buffered through the OSCout port. The VCXO is used as the reference to
PLL2 and may be doubled using the frequency doubler. The internal VCO drives up to 8 divide or delay blocks
which drive up to 10 clock outputs.
Holdover functionality is optionally available when the input reference clock is lost. Holdover works by fixing the
tuning voltage of PLL1 to the VCXO.
PLL1
R
2 inputs
N
Phase
Detector
PLL1
Integrated
Loop Filter
Divider
OSCin
External
VCXO
Device/SYSref
Clock
Divider
Digital Delay
Analog Delay
Internal VCO
CTRL_VCXO
CLKinX
CLKinX*
PLL2
R
Phase
Detector
PLL2
Pre
Div
Integrated
Loop Filter
2 blocks
Device/SYSref
Clock
Divider
Digital Delay
Analog Delay
N
LMK04610
OSCout
OSCout*
CLKoutX*
CLKoutX
10 Device/Sysref
Clocks
CLKoutX*
CLKoutX
CLKoutX*
CLKoutX
4 blocks
Copyright © 2017, Texas Instruments Incorporated
Figure 52. Simplified Functional Block Diagram for Dual-Loop Mode
9.4.2 Single PLL
No LOS detection and automatic reference switching available in this mode.
PLL1
R
2 inputs
N
Phase
Detector
PLL1
Integrated
Loop Filter
Divider
OSCin
External
VCXO
CTRL_VCXO
CLKinX
CLKinX*
PLL2
Device/SYSref
Clock
Divider
Digital Delay
Analog Delay
Internal VCO
R
Phase
Detector
PLL2
Integrated
Loop Filter
N
LMK04610
Pre
Div
2 blocks
Device/SYSref
Clock
Divider
Digital Delay
Analog Delay
OSCout
OSCout*
CLKoutX*
CLKoutX
10 Device/Sysref
Clocks
CLKoutX*
CLKoutX
CLKoutX*
CLKoutX
4 blocks
Copyright © 2017, Texas Instruments Incorporated
Figure 53. Simplified Functional Block Diagram for PLL2 Only or Clock Generator Mode
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Device Functional Modes (continued)
9.4.3 PLL2 Bypass
PLL1
R
2 inputs
N
Phase
Detector
PLL1
Integrated
Loop Filter
Divider
OSCin
External
VCXO
Device/SYSref
Clock
Divider
Digital Delay
Analog Delay
Internal VCO
CTRL_VCXO
CLKinX
CLKinX*
PLL2
R
Phase
Detector
PLL2
Pre
Div
Integrated
Loop Filter
LMK04610
CLKoutX*
CLKoutX
10 Device/Sysref
Clocks
2 blocks
Device/SYSref
Clock
Divider
Digital Delay
Analog Delay
N
OSCout
OSCout*
CLKoutX*
CLKoutX
CLKoutX*
CLKoutX
4 blocks
Copyright © 2017, Texas Instruments Incorporated
Figure 54. Simplified Functional Block Diagram for PLL1 Only or PLL2 Bypass Mode
9.4.4 Clock Distribution
No LOS detection and automatic Reference Switching available in this mode.
PLL1
R
2 inputs
N
Phase
Detector
PLL1
Integrated
Loop Filter
Divider
OSCin
External
VCXO
CTRL_VCXO
CLKinX
CLKinX*
PLL2
Device/SYSref
Clock
Divider
Digital Delay
Analog Delay
Internal VCO
R
Phase
Detector
PLL2
Integrated
Loop Filter
N
LMK04610
Pre
Div
2 blocks
Device/SYSref
Clock
Divider
Digital Delay
Analog Delay
OSCout
OSCout*
CLKoutX*
CLKoutX
10 Device/Sysref
Clocks
CLKoutX*
CLKoutX
CLKoutX*
CLKoutX
4 blocks
Copyright © 2017, Texas Instruments Incorporated
Figure 55. Simplified Functional Block Diagram for Clock Distribution Mode
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9.5 Programming
LMK0461x device is programmed using 24-bit registers. Each register consists of a 1-bit command field (R/W), a
15-bit address field (A14 to A0) and a 8-bit data field (D7 to D0). The contents of each register is clocked in MSB
first (R/W), and the LSB (D0) last. During programming, the CS* signal is held low. The serial data is clocked in
on the rising edge of the SCK signal. After the LSB is clocked in, the CS* signal goes high to latch the contents
into the shift register. TI recommends programming registers in numeric order -- for example, 0x000 to 0x1FFF -to achieve proper device operation. Each register consists of one or more fields that control the device
functionality. See the electrical characteristics and Figure 1 for timing details.
R/W bit = 0 is for SPI write. R/W bit = 1 is for SPI read.
3 Wire Mode
4 Wire Mode
SCS*
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
D7
D6
D5
D4
D3
D2
D1
D0
SCL
SDIO
R/W A14 A13 A12 A11 A10
SDO
(STATUS1)
Figure 56. SPI Write
3 Wire Mode
4 Wire Mode
SCS*
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
D7
D6
D5
D4
D3
D2
D1
D0
D7
D6
D5
D4
D3
D2
D1
D0
SCL
SDIO
R/W A14 A13 A12 A11 A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
SDIO
R/W A14 A13 A12 A11 A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
SDO
(STATUS1)
Figure 57. SPI Read
3 Wire Mode
4 Wire Mode
SCS*
1
2
3
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
SCL
Addr N
SDIO
R/W A14 A13
A2
A1
A0
D7
D6
D5
D4
D3
Addr N+1 (ascending), Addr N-1 (descending)
D2
D1
D0
D7
D6
D5
D4
D3
D2
D1
D0
SDO
(STATUS1)
Figure 58. SPI Write – Streaming Mode
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Programming (continued)
3 Wire Mode
4 Wire Mode
SCS*
1
2
3
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
SCL
Addr N
SDIO
R/W A14 A13
A2
A1
A0
SDIO
R/W A14 A13
A2
A1
A0
SDO
(STATUS1)
Addr N+1 (ascending), Addr N-1 (descending)
D7
D6
D5
D4
D3
D2
D1
D0
D7
D6
D5
D4
D3
D2
D1
D0
D7
D6
D5
D4
D3
D2
D1
D0
D7
D6
D5
D4
D3
D2
D1
D0
Figure 59. SPI Read – Streaming Mode
9.5.1 Recommended Programming Sequence
The default programming sequence from POR involves:
1. Toggle RESETn pin High-Low-High
2. Program all registers with Register 0x0011 bit 0 = 0
– Register 0x85 = 0x00
– Register 0x86 = 0x00
– Register 0xF6 = 0x02
3. Program Register 0x0011 bit 0 = 1 to start the device
4. Enable PLL2 digital lock detect
– 0xAD = 0x30
– Delay 20 ms
– 0xAD = 0x00
Also refer to Power-Up Sequence.
9.5.1.1 Readback
Readback of the complete register content is possible.
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9.6 Register Maps
9.6.1
Register Map for Device Programming
Table 24 provides the register map for device programming. Any register can be read from the same data address it is written to.
Table 24. Register Map
ADDRESS
[15:0]
0x00
DATA
D7
D6
SWRST
LSB_FIRST
D5
D4
ADDR_ASCEND
SDO_ACTIVE
0x01
D1
D0
SDO_ACTIVE_CPY
LSB_FIRST_CPY
SWRST_CPY
RSRVD1
RSRVD
DEVID[1:0]
RSRVD2[1:0]
RSRVD
CHIPTYPE[3:0]
0x04
CHIPID[15:8]
0x05
CHIPID[7:0]
0x06
CHIPVER[7:0]
0x07
RSRVD
RSRVD3
0x08
RSRVD
RSRVD4
0x09
RSRVD
RSRVD5
0x0A
RSRVD
RSRVD6
0x0B
RSRVD
RSRVD7
0x0C
VENDORID[15:8]
0x0D
VENDORID[7:0]
0x0E
RSRVD
RSRVD8
0x0F
RSRVD
RSRVD9
0x10
RSRVD
OUTCH_MUTE
0x11
CH1TO5EN
PLL2EN
PLL1EN
PLL2_DIG_CLK_EN
PORCLKAFTERLO
CK
DEV_STARTUP
DIG_CLK_EN
RSRVD
EN_SYNC_PIN_F
UNC
RSRVD
0x15
0x16
CH6TO10EN
RSRVD
0x13
0x14
CLKINBLK_LOSLD
O_EN
RSRVD
0x12
56
D2
ADDR_ASCEND_C
PY
RSRVD
0x02
0x03
D3
PLL2_REF_DIGCLK_DIV[4:0]
GLOBAL_CONT_SY
SREF
GLOBAL_SYSREF
RSRVD
CLKINBLK_ALL_E
N
CLKINSEL1_MODE[1:0]
CLKINBLK_EN_BU
F_CLK_PLL
INV_SYNC_INPUT_
SYNC_CLK
SYNC_PIN_FUNC[1:0]
GLOBAL_SYNC
CLKIN_STAGGER_
EN
CLKIN_SWRST
RSRVD
CLKINSEL1_INV
CLKINBLK_EN_BU
F_BYP_PLL
RSRVD
RSRVD
RSRVD
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Register Maps (continued)
Table 24. Register Map (continued)
ADDRESS
DATA
0x19
RSRVD
CLKIN0_PLL1_INV
CLKIN0_LOS_FRQ_
DBL_EN
CLKIN0_EN
CLKIN0_SE_MODE
CLKIN0_PRIO[2:0]
0x1A
RSRVD
CLKIN1_PLL1_INV
CLKIN1_LOS_FRQ_
DBL_EN
CLKIN1_EN
CLKIN1_SE_MODE
CLKIN1_PRIO[2:0]
0x1F
CLKIN0_PLL1_RDIV[15:8]
0x20
CLKIN0_PLL1_RDIV[7:0]
0x21
CLKIN1_PLL1_RDIV[15:8]
0x22
CLKIN1_PLL1_RDIV[7:0]
0x27
CLKIN0_LOS_REC_CNT[7:0]
0x28
CLKIN0_LOS_LAT_SEL[7:0]
0x29
CLKIN1_LOS_REC_CNT[7:0]
0x2A
CLKIN1_LOS_LAT_SEL[7:0]
0x2B
RSRVD
0x2C
SW_CLKLOS_TMR[4:0]
SW_REFINSEL[3:0]
0x2D
SW_LOS_CH_SEL[3:0]
RSRVD
0x2E
RSRVD
0x2F
OSCOUT_LVCMO OSCOUT_DIV_REG
S_WEAK_DRIVE
CONTROL
SW_ALLREFSON_TMR[4:0]
OSCIN_PD_LDO
OSCIN_SE_MODE
OSCOUT_PINSEL_DIV[1:0]
0x30
0x31
CH10_SWRST
CH9_SWRST
0x33
OUTCH1_LDO_B
YP_MODE
OUTCH1_LDO_MA
SK
0x34
OUTCH2_LDO_B
YP_MODE
OSCIN_BUF_LOS_
EN
OSCOUT_SEL_VB
G
OSCOUT_DIV_CLK
EN
OSCOUT_SWRST
OSCOUT_SEL_SR
C
CH2_SWRST
CH1_SWRST
DIV_DCC_EN_CH1
OUTCH1_DIV_CLK
EN
DIV_DCC_EN_CH2
OUTCH2_DIV_CLK
EN
DIV_DCC_EN_CH3
_4
OUTCH34_DIV_CL
KEN
OSCOUT_DRV_MODE[5:0]
CH78_SWRST
CH6_SWRST
CH5_SWRST
CH34_SWRST
RESERVED[5:0]
OUTCH2_LDO_MA
SK
OUTCH2_DRIV_MODE[5:0]
RESERVED[5:0]
OUTCH34_LDO_
BYP_MODE
OUTCH34_LDO_M
ASK
0x38
0x39
OSCIN_BUF_REF_
EN
OUTCH1_DRIV_MODE[5:0]
0x36
0x37
OSCIN_OSCINSTA
GE_EN
OSCOUT_DIV[7:0]
OSCOUT_DRV_MUTE[1:0]
0x32
0x35
OSCIN_BUF_TO_O
SCOUT_EN
OUTCH3_DRIV_MODE[5:0]
OUTCH4_DRIV_MODE[5:0]
OUTCH5_LDO_B
YP_MODE
OUTCH5_LDO_MA
SK
OUTCH5_DRIV_MODE[5:0]
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Register Maps (continued)
Table 24. Register Map (continued)
ADDRESS
DATA
0x3A
DIV_DCC_EN_CH
5
OUTCH5_DIV_CLK
EN
RESERVED[5:0]
0x3B
OUTCH6_LDO_B
YP_MODE
OUTCH6_LDO_MA
SK
RESERVED[5:0]
0x3C
0x3D
OUTCH6_DRIV_MODE[5:0]
OUTCH78_LDO_
BYP_MODE
OUTCH78_LDO_M
ASK
0x3E
0x3F
OUTCH9_LDO_MA
SK
0x40
0x41
OUTCH10_LDO_M
ASK
0x42
0x43
58
DIV_DCC_EN_CH7
_8
OUTCH78_DIV_CL
KEN
DIV_DCC_EN_CH9
OUTCH9_DIV_CLK
EN
DIV_DCC_EN_CH1
0
OUTCH10_DIV_CL
KEN
RESERVED[5:0]
OUTCH9_DRIV_MODE[5:0]
OUTCH10_LDO_
BYP_MODE
OUTCH6_DIV_CLK
EN
OUTCH7_DRIV_MODE[5:0]
OUTCH8_DRIV_MODE[5:0]
OUTCH9_LDO_B
YP_MODE
DIV_DCC_EN_CH6
OUTCH10_DRIV_MODE[5:0]
RESERVED[5:0]
OUTCH1_DIV[15:8]
0x44
OUTCH1_DIV[7:0]
0x45
OUTCH2_DIV[15:8]
0x46
OUTCH2_DIV[7:0]
0x47
OUTCH34_DIV[15:8]
0x48
OUTCH34_DIV[7:0]
0x49
OUTCH5_DIV[15:8]
0x4A
OUTCH5_DIV[7:0]
0x4B
OUTCH6_DIV[15:8]
0x4C
OUTCH6_DIV[7:0]
0x4D
OUTCH78_DIV[15:8]
0x4E
OUTCH78_DIV[7:0]
0x4F
OUTCH9_DIV[15:8]
0x50
OUTCH9_DIV[7:0]
0x51
OUTCH10_DIV[15:8]
0x52
OUTCH10_DIV[7:0]
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Register Maps (continued)
Table 24. Register Map (continued)
ADDRESS
DATA
0x53
OUTCH10_DIV_IN
V
OUTCH9_DIV_INV
OUTCH78_DIV_INV
OUTCH6_DIV_INV
0x54
PLL1_F_30
PLL1_EN_REGULA
TION
PLL1_PD_LD
PLL1_DIR_POS_GA
IN
0x55
PLL1_LCKDET_B
Y_32
PLL1_FAST_LOCK
PLL1_LCKDET_LO
S_MASK
PLL1_FBCLK_INV
RSRVD
PLL1_BYP_LOS
PLL1_PFD_UP_HO
LDOVER
PLL1_PFD_DOWN_
HOLDOVER
PLL1_LOL_NORES
ET
PLL1_RDIV_CLKEN
PLL1_RDIV_4CY
PLL1_NDIV_CLKEN
PLL1_NDIV_4CY
PLL1_RDIV_SWRS
T
PLL1_NDIV_SWRS
T
0x56
RSRVD
0x57
PLL1_HOLDOVER_
DLD_SWRST
RSRVD
0x58
OUTCH2_DIV_INV
OUTCH1_DIV_INV
PLL1_LDO_WAIT_TMR[3:0]
PLL1_INTG_FL [3:0]
PLL1_HOLDOVERC PLL1_HOLDOVER_
NT_SWRST
LOCKDET_SWRST
PLL1_SWRST
PLL1_INTG [3:0]
RSRVD
PLL1_PROP[6:0]
0x5B
RSRVD
0x5C0x5C
PLL1_HOLDOVE
R_EN
PLL1_PROP_FL[6:0]
PLL1_STARTUP_H
OLDOVER_EN
PLL1_HOLDOVER_
FORCE
PLL1_HOLDOVER_
RAIL_MODE
PLL1_HOLDOVER_ PLL1_HOLDOVER_
MAX_CNT_EN
LOS_MASK
0x5D
PLL1_HOLDOVER_MAX_CNT[31:24]
0x5E
PLL1_HOLDOVER_MAX_CNT[23:16]
0x5F
PLL1_HOLDOVER_MAX_CNT[15:8]
0x60
PLL1_HOLDOVER_MAX_CNT[7:0]
0x61
PLL1_NDIV[15:8]
0x62
PLL1_NDIV[7:0]
0x63
PLL1_LOCKDET_CYC_CNT[23:16]
0x64
PLL1_LOCKDET_CYC_CNT[15:8]
0x65
PLL1_LOCKDET_CYC_CNT[7:0]
0x66
RSRVD
0x67
RSRVD
0x68
RSRVD
0x69
0x6A
OUTCH34_DIV_INV
PLL1_LD_WNDW_SIZE[7:0]
0x59
0x5A
OUTCH5_DIV_INV
PLL1_HOLDOVER_
LCKDET_MASK
PLL1_HOLDOVER_
RAILDET_EN
RSRVD
RSRVD
PLL1_STORAGE_CELL[5:0]
0x6B
RSRVD
PLL1_RC_CLK_EN
RSRVD
0x6C
RSRVD
PLL2_VCO_PRESC
_LOW_POWER
PLL2_BYP_OSC
PLL2_BYP_TOP
PLL2_BYP_BOT
PLL2_GLOBAL_BY
P
PLL2_SMART_TRI
M
PLL2_LCKDET_LO
S_MASK
PLL2_RDIV_DBL_E
N
PLL2_PD_LD
0x6D
PLL2_EN_PULSE
_GEN
PLL2_RDIV_BYP
PLL2_DBL_EN_INV PLL2_PD_VARBIAS
PLL1_RC_CLK_DIV[2:0]
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Register Maps (continued)
Table 24. Register Map (continued)
ADDRESS
0x6E
DATA
PLL2_BYP_SYNC
_TOP
PLL2_BYP_SYNC_
BOTTOM
PLL2_EN_BYP_BU
F
0x6F
PLL2_C4_LF_SEL[3:0]
0x71
PLL2_C3_LF_SEL[3:0]
PLL2_EN_BUF_OS
COUT
PLL2_EN_BUF_CL
K_TOP
PLL2_EN_BUF_CL
K_BOTTOM
PLL2_RDIV_SWRS
T
PLL2_NDIV_SWRS
T
PLL2_SWRST
PLL2_R4_LF_SEL[3:0]
PLL2_R3_LF_SEL[3:0]
RSRVD
PLL2_PROP[5:0]
0x73
PLL2_NDIV[15:8]
0x74
PLL2_NDIV[7:0]
0x75
PLL2_RDIV[15:8]
0x76
PLL2_RDIV[7:0]
0x77
PLL2_STRG_INITVAL[15:8]
0x78
PLL2_STRG_INITVAL[7:0]
0x7D
RSRVD
0x7E
RSRVD
0x7F
RSRVD
RAILDET_UPP[5:0]
RAILDET_LOW[5:0]
PLL2_AC_CAL_EN
PLL2_PD_AC
PLL2_IDACSET_RECAL[1:0]
PLL2_AC_REQ
0x80
RSRVD
0x81
RSRVD
PLL2_AC_THRESHOLD[4:0]
0x82
RSRVD
PLL2_AC_STRT_THRESHOLD[4:0]
0x83
PLL2_AC_CMP_WAIT[3:0]
PLL2_AC_INIT_WAIT[3:0]
0x84
RSRVD
PLL2_AC_JUMP_STEP[3:0]
0x85
PLL2_LD_WNDW_SIZE[7:0]
0x86
PLL2_LD_WNDW_SIZE_INITIAL[7:0]
0x87
PLL2_LOCKDET_CYC_CNT[23:16]
0x88
PLL2_LOCKDET_CYC_CNT[15:8]
0x89
PLL2_LOCKDET_CYC_CNT[7:0]
0x8A
PLL2_LOCKDET_CYC_CNT_INITIAL[23:16]
0x8B
PLL2_LOCKDET_CYC_CNT_INITIAL[15:8]
0x8D
PLL2_FAST_ACAL
PLL2_INTG[4:0]
0x8C
PLL2_LOCKDET_CYC_CNT_INITIAL[7:0]
SPI_EN_THREE_
WIRE_IF
0x8E
60
PLL2_EN_BUF_SY
NC_BOTTOM
RSRVD
0x70
0x72
PLL2_EN_BUF_SY
NC_TOP
RSRVD
RSRVD
SPI_SDIO_OUTPUT SPI_SDIO_OUTPUT SPI_SDIO_OUTPUT SPI_SDIO_EN_PUL
_MUTE
_INV
_WEAK_DRIVE
LUP
SPI_SDIO_EN_PUL
LDOWN
SPI_SCL_EN_PULL SPI_SCL_EN_PULL SPI_SCS_EN_PULL SPI_SCS_EN_PULL
UP
DOWN
UP
DOWN
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Register Maps (continued)
Table 24. Register Map (continued)
ADDRESS
0x8F
DATA
SPI_SDIO_OUTPUT
_HIZ
RSRVD
SPI_SDIO_ENB_IN
STAGE
SPI_SDIO_EN_ML_
INSTAGE
SPI_SDIO_OUTPUT
_DATA
RSRVD
SPI_SDIO_INPUT_
Y12
SPI_SDIO_INPUT_
M12
SPI_SCL_INPUT_M
12
0x90
RSRVD
SPI_SCL_ENB_INS
TAGE
SPI_SCL_EN_ML_I
NSTAGE
RSRVD
SPI_SCL_INPUT_Y
12
0x91
RSRVD
SPI_SCS_ENB_INS
TAGE
SPI_SCS_EN_ML_I
NSTAGE
RSRVD
SPI_SCS_INPUT_Y SPI_SCS_INPUT_M
12
12
0x92
STATUS0_MUX_SEL[2:0]
STATUS0_OUTPUT STATUS0_OUTPUT STATUS0_OUTPUT
_MUTE
_INV
_WEAK_DRIVE
STATUS0_EN_PUL
LUP
STATUS0_EN_PUL
LDOWN
0x93
STATUS1_MUX_SEL[2:0]
STATUS1_OUTPUT STATUS1_OUTPUT STATUS1_OUTPUT
_MUTE
_INV
_WEAK_DRIVE
STATUS1_EN_PUL
LUP
STATUS1_EN_PUL
LDOWN
0x94
STATUS1_INT_MUX[7:0]
0x95
STATUS0_INT_MUX[7:0]
0x96
RSRVD
PLL2_REF_CLK_E
N
RSRVD
PLL2_REF_STATCLK_DIV[2:0]
0x97
RSRVD
STATUS0_OUTPUT
_HIZ
STATUS0_ENB_IN
STAGE
STATUS0_EN_ML_I
NSTAGE
RSRVD
STATUS0_OUTPUT STATUS0_INPUT_Y
_DATA
12
STATUS0_INPUT_
M12
0x98
RSRVD
STATUS1_OUTPUT
_HIZ
STATUS1_ENB_IN
STAGE
STATUS1_EN_ML_I
NSTAGE
RSRVD
STATUS1_OUTPUT STATUS1_INPUT_Y
_DATA
12
STATUS1_INPUT_
M12
SYNC_OUTPUT_M
UTE
SYNC_OUTPUT_IN
V
0x99
SYNC_MUX_SEL[2:0]
0x9A
0xAC
SYNC_EN_PULLUP
RSRVD
0x9B
0x9C
SYNC_OUTPUT_W
EAK_DRIVE
RSRVD
CLKINSEL1_EN_PU CLKINSEL1_EN_PU
LLUP
LLDOWN
RSRVD
RSRVD
CLKINSEL1_ENB_I
NSTAGE
CLKINSEL1_EN_ML
_INSTAGE
PLL1_TSTMODE_
REF_FB_EN
0xAD
RSRVD
0xBE
RSRVD
0xF6
SYNC_EN_PULLDO
WN
RSRVD
CLKINSEL1_INPUT
_Y12
CLKINSEL1_INPUT
_M12
RSRVD
RESET_PLL2_DLD[1:0]
LOS
HOLDOVER_DLD
RSRVD
PLL2_TSTMODE_R
EF_FB_EN
HOLDOVER_LOL
HOLDOVER_LOS
RSRVD
0xFD
OUTCH1_DDLY[7:0]
0xFF
OUTCH2_DDLY[7:0]
0x101
OUTCH34_DDLY[7:0]
0x103
OUTCH5_DDLY[7:0]
0x105
OUTCH6_DDLY[7:0]
PD_VCO_LDO[1:0]
PLL2_LCK_DET
PLL1_LCK_DET
PLL2_DLD_EN
RSRVD
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Register Maps (continued)
Table 24. Register Map (continued)
ADDRESS
DATA
0x107
OUTCH78_DDLY[7:0]
0x109
OUTCH9_DDLY[7:0]
0x10B
OUTCH10_DDLY[7:0]
0x10D
RSRVD
CH1_ADLY[4:0]
CH1_ADLY_EN
RSRVD
0x10E
RSRVD
CH2_ADLY[4:0]
CH2_ADLY_EN
RSRVD
0x110
RSRVD
CH3_ADLY[4:0]
CH3_ADLY_EN
RSRVD
0x111
RSRVD
CH4_ADLY[4:0]
CH4_ADLY_EN
RSRVD
0x112
RSRVD
CH5_ADLY[4:0]
CH5_ADLY_EN
RSRVD
0x115
RSRVD
CH6_ADLY[4:0]
CH6_ADLY_EN
RSRVD
0x116
RSRVD
CH7_ADLY[4:0]
CH7_ADLY_EN
RSRVD
0x117
RSRVD
CH8_ADLY[4:0]
CH8_ADLY_EN
RSRVD
0x119
RSRVD
CH9_ADLY[4:0]
CH9_ADLY_EN
RSRVD
0x11A
RSRVD
CH10_ADLY[4:0]
CH10_ADLY_EN
RSRVD
0x124
62
RSRVD
CLKMUX[3:0]
0x127
SYSREF_BYP_D
YNDIGDLY_GATI
NG_CH1
SYSREF_BYP_ANA
LOGDLY_GATING_
CH1
SYNC_EN_CH1
HS_EN_CH1
DRIV_1_SLEW[1:0]
RSRVD
0x128
SYSREF_BYP_D
YNDIGDLY_GATI
NG_CH2
SYSREF_BYP_ANA
LOGDLY_GATING_
CH2
SYNC_EN_CH2
HS_EN_CH2
RSRVD
DRIV_2_SLEW[1:0]
0x129
SYSREF_BYP_D
YNDIGDLY_GATI
NG_CH3_4
SYSREF_BYP_ANA
LOGDLY_GATING_
CH3_4
SYNC_EN_CH3_4
HS_EN_CH3_4
DRIV_4_SLEW[1:0]
DRIV_3_SLEW[1:0]
0x12A
SYSREF_BYP_D
YNDIGDLY_GATI
NG_CH5
SYSREF_BYP_ANA
LOGDLY_GATING_
CH5
SYNC_EN_CH5
HS_EN_CH5
RSRVD
DRIV_5_SLEW[1:0]
0x12B
SYSREF_BYP_D
YNDIGDLY_GATI
NG_CH6
SYSREF_BYP_ANA
LOGDLY_GATING_
CH6
SYNC_EN_CH6
HS_EN_CH6
DRIV_6_SLEW[1:0]
RSRVD
0x12C
SYSREF_BYP_D
YNDIGDLY_GATI
NG_CH7_8
SYSREF_BYP_ANA
LOGDLY_GATING_
CH7_8
SYNC_EN_CH7_8
HS_EN_CH7_8
DRIV_8_SLEW[1:0]
DRIV_7_SLEW[1:0]
0x12D
SYSREF_BYP_D
YNDIGDLY_GATI
NG_CH9
SYSREF_BYP_ANA
LOGDLY_GATING_
CH9
SYNC_EN_CH9
HS_EN_CH9
DRIV_9_SLEW[1:0]
RSRVD
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Register Maps (continued)
Table 24. Register Map (continued)
ADDRESS
0x12E
DATA
SYSREF_BYP_D
YNDIGDLY_GATI
NG_CH10
SYSREF_BYP_ANA
LOGDLY_GATING_
CH10
SYNC_EN_CH10
HS_EN_CH10
RSRVD
DRIV_10_SLEW[1:0]
0x130
RSRVD
DYN_DDLY_CH1[2:0]
0x131
RSRVD
DYN_DDLY_CH2[2:0]
0x133
RSRVD
DYN_DDLY_CH3[2:0]
0x134
RSRVD
DYN_DDLY_CH4[2:0]
0x135
RSRVD
DYN_DDLY_CH5[2:0]
0x138
RSRVD
DYN_DDLY_CH6[2:0]
0x139
RSRVD
DYN_DDLY_CH7[2:0]
0x13A
RSRVD
DYN_DDLY_CH8[2:0]
0x13C
RSRVD
DYN_DDLY_CH9[2:0]
0x13D
RSRVD
DYN_DDLY_CH10[2:0]
0x140
RSRVD
OUTCH_SYSREF_PLSCNT[5:0]
0x141
0x142
SYNC_INT_MUX[7:0]
RSRVD
0x143
0x146
SYNC_OUTPUT_HI
Z
SYNC_ENB_INSTA
GE
RSRVD
RSRVD
RSRVD
0x14B
RESERVED
SYNC_OUTPUT_D
ATA
SYNC_INPUT_Y12
RSRVD
PLL1_CLKINSEL1_
ML_HOLDOVER
SYNC_INPUT_M12
FBBUF_CH6_EN
PLL2_PRESCALER[3:0]
RSRVD
0x14A
RSRVD
FBBUF_CH5_EN
PLL2_NBYPASS_DI
V2_FB
0x149
SYNC_EN_ML_INS
TAGE
PLL2_FBDIV_MUXSEL[1:0]
PLL1_SYNC_HOLD
OVER
SYNC_ANALOGDLY[4:0]
PLL1_STATUS1_H
OLDOVER
PLL1_STATUS0_H
OLDOVER
SYNC_ANALOGDL
Y_EN
SYNC_INV
DYN_DDLY_CH10_ DYN_DDLY_CH9_E
EN
N
RESERVED
DYN_DDLY_CH8_E DYN_DDLY_CH7_E DYN_DDLY_CH6_E
N
N
N
RESERVED
0x14C
DYN_DDLY_CH5_ DYN_DDLY_CH4_E DYN_DDLY_CH3_E
EN
N
N
RESERVED
DYN_DDLY_CH2_E DYN_DDLY_CH1_E
N
N
RESERVED
RESERVED
0x14E
SYSREF_EN_CH
10
SYSREF_EN_CH2
SYSREF_EN_CH1
SYSREF_EN_CH9
0x150
0x151
SYSREF_EN_CH6
RSRVD
PLL2_RFILT
RSRVD
SYSREF_EN_CH5
SYSREF_EN_CH3_
4
PLL2_PFD_DIS_SA
MPLE
RSRVD
0x152
0x153
SYSREF_EN_CH7_
8
RSRVD
PLL2_PROG_PFD_RESET[2:0]
PLL2_CP_EN_SAM
PLE_BYP
PLL2_EN_FILTER
RSRVD
PLL2_CPROP[1:0]
PLL2_CSAMPLE[2:0]
PLL2_CFILT
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9.6.2 Device Register Descriptions
The following section details the fields of each register, the Power-On-Reset Defaults, and specific descriptions
of each bit.
In some cases similar fields are located in multiple registers. In this case specific outputs may be designated as
X or Y. In these cases, the X represents even numbers from 0 to 12 and the Y represents odd numbers from 1 to
13. In the case where X and Y are both used in a bit name, then Y = X + 1.
9.6.2.1 CONFIGA
The CONFIGA Register provides control of the SPI operation. The data written to this register must always be
symmetrical otherwise the write will not take place, that is, Bit0=Bit7, Bit1=Bit6, Bit2=Bit5, Bit3=Bit4. Return to
Register Map.
Table 25. Register – 0x00
BIT NO.
FIELD
TYPE
RESET
DESCRIPTION
[7]
SWRST
RWSC
0
Software Reset. Writing a 1 to SWRST resets the device
apart from the SPI programmable registers. SWRST is
automatically cleared to 0.
[6]
LSB_FIRST
RW
0
Least Significant Bit First. This feature is not support, register
data is always transmitted MSB first.
[5]
ADDR_ASCEND
RW
0
Address Increment Ascending. When set to 1 the address in
streaming transactions is incremented by 1 after each data
byte. When set to 0 the address is decremented by 1 in
streaming transactions.
[4]
SDO_ACTIVE
RW
0
SDO Active. SDO is always active. This bit always reads 1.
[3]
SDO_ACTIVE_CPY
RW
0
SDO Active. Must be programmed equal to bit 4.
[2]
ADDR_ASCEND_CPY
RW
0
Address Increment Ascending. Must be programmed equal
to bit 5.
[1]
LSB_FIRST_CPY
RW
0
Least Significant Bit First. Must be programmed equal to bit
6.
[0]
SWRST_CPY
RWSC
0
Software Reset. Must be programmed equal to bit 7.
9.6.2.2 RESERVED1
Reserved Register space. Return to Register Map.
Table 26. Register – 0x01
BIT NO.
FIELD
TYPE
RESET
[7:1]
RSRVD
-
-
DESCRIPTION
Reserved.
[0]
RSRVD1
R
0
Reserved for compatibility.
9.6.2.3 RESERVED2
Reserved Register space. Return to Register Map.
Table 27. Register – 0x02
BIT NO.
64
FIELD
TYPE
RESET
DESCRIPTION
[7:2]
RSRVD
-
-
Reserved.
[1:0]
RSRVD2[1:0]
R
0x0
Reserved for compatibility.
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9.6.2.4 CHIP_TYPE
The CHIP_TYPE Register defines the nature of this device. Return to Register Map.
Table 28. Register – 0x03
BIT NO.
FIELD
[7:6]
DEVID[1:0]
TYPE
R
RESET
DESCRIPTION
0x0
Device Identification. Indicates the device partname
DEVID - Device
0 - LMK04616
1 - LMK04610
[5:4]
RSRVD
-
-
Reserved.
[3:0]
CHIPTYPE[3:0]
R
0x6
Chip Type. Indicates that this is a PLL Device.
9.6.2.5 CHIP_ID_BY1
The CHIP_ID is a vendor specific field recorded in registers CHIP_ID_BY1 and CHIP_ID_BY0. Return to
Register Map.
Table 29. Register – 0x04
BIT NO.
FIELD
TYPE
RESET
DESCRIPTION
[7:0]
CHIPID[15:8]
R
0x38
CHIP Identification.
9.6.2.6 CHIP_ID_BY0
The CHIP_ID lower byte is recorded in CHIP_ID_BY1. Return to Register Map.
Table 30. Register – 0x05
BIT NO.
FIELD
TYPE
RESET
DESCRIPTION
[7:0]
CHIPID[7:0]
R
0x3
CHIP Identification.
9.6.2.7 CHIP_VER
The CHIP_VER Register records the mask set revision. Return to Register Map.
Table 31. Register – 0x06
BIT NO.
FIELD
TYPE
RESET
DESCRIPTION
[7:0]
CHIPVER[7:0]
R
0x1B
CHIP Version.
9.6.2.8 RESERVED3
Reserved Register space. Return to Register Map.
Table 32. Register – 0x07
BIT NO.
FIELD
TYPE
RESET
[7:1]
RSRVD
-
-
DESCRIPTION
Reserved.
[0]
RSRVD3
R
0
Reserved for compatibility.
9.6.2.9 RESERVED4
Reserved Register space. Return to Register Map.
Table 33. Register – 0x08
BIT NO.
FIELD
TYPE
RESET
DESCRIPTION
[7:1]
RSRVD
-
-
Reserved.
[0]
RSRVD4
R
0
Reserved for compatibility.
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9.6.2.10 RESERVED5
Reserved Register space. Return to Register Map.
Table 34. Register – 0x09
BIT NO.
FIELD
TYPE
RESET
[7:1]
RSRVD
-
-
DESCRIPTION
Reserved.
[0]
RSRVD5
R
0
Reserved for compatibility.
9.6.2.11 RESERVED6
Reserved Register space. Return to Register Map.
Table 35. Register – 0x0A
BIT NO.
FIELD
TYPE
RESET
DESCRIPTION
[7:1]
RSRVD
-
-
Reserved.
[0]
RSRVD6
R
0
Reserved for compatibility.
9.6.2.12 RESERVED7
Reserved Register space. Return to Register Map.
Table 36. Register – 0x0B
BIT NO.
FIELD
TYPE
RESET
[7:1]
RSRVD
-
-
DESCRIPTION
Reserved.
[0]
RSRVD7
R
0
Reserved for compatibility.
9.6.2.13 VENDOR_ID_BY1
The VENDOR_ID field is recorded in registers VENDOR_ID_BY1 and VENDOR_ID_BY0. Return to Register
Map.
Table 37. Register – 0x0C
BIT NO.
FIELD
TYPE
RESET
DESCRIPTION
[7:0]
VENDORID[15:8]
R
0x51
Vendor Identification.
9.6.2.14 VENDOR_ID_BY0
VENDOR_ID Lower Byte. Return to Register Map.
Table 38. Register – 0x0D
BIT NO.
FIELD
TYPE
RESET
DESCRIPTION
[7:0]
VENDORID[7:0]
R
0x8
Vendor Identification.
9.6.2.15 RESERVED8
Reserved Register space. Return to Register Map.
Table 39. Register – 0x0E
66
BIT NO.
FIELD
TYPE
RESET
[7:1]
RSRVD
-
-
Reserved.
[0]
RSRVD8
R
0
Reserved for compatibility.
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9.6.2.16 RESERVED9
Reserved Register space. Return to Register Map.
Table 40. Register – 0x0F
BIT NO.
FIELD
TYPE
RESET
[7:1]
RSRVD
-
-
DESCRIPTION
Reserved.
[0]
RSRVD9
R
0
Reserved for compatibility.
9.6.2.17 STARTUP_CFG
The STARTUP_CFG Register provides control of the device operation at start-up. Return to Register Map.
Table 41. Register – 0x10
BIT NO.
FIELD
TYPE
RESET
DESCRIPTION
[7:6]
RSRVD
-
-
Reserved.
[5]
OUTCH_MUTE
RW
0
Output Channel Mute. When OUTCH_MUTE is 1 the output
drivers are disabled until the PLL's have locked.
[4]
CLKINBLK_LOSLDO_EN
RW
1
Enable LOS LDO during the start-up sequence.
[3]
CH6TO10EN
RW
1
Enable Channels 6 to 10 during the start-up sequence.
[2]
CH1TO5EN
RW
1
Enable Channels 1 to 5 during the start-up sequence.
[1]
PLL2EN
RW
1
Activate PLL2 during the start-up sequence.
[0]
PLL1EN
RW
1
Activate PLL1 during the start-up sequence.
9.6.2.18 STARTUP
The STARTUP Register allows device activation to be triggered. Return to Register Map.
Table 42. Register – 0x11
BIT NO.
FIELD
TYPE
RESET
[7:1]
RSRVD
-
-
Reserved.
0
Device Start-up. When DEV_STARTUP is 1 the device
activation sequence is triggered. The device modules that
are automatically enabled during the sequence is determined
by the STARTUP_CFG register. If DEV_STARTUP is 1 on
exit from software reset then the start-up sequence is also
triggered.
[0]
DEV_STARTUP
RW
DESCRIPTION
9.6.2.19 DIGCLKCTRL
The DIGCLKCTRL Register allows control of the digital system clock. Return to Register Map.
Table 43. Register – 0x12
BIT NO.
FIELD
TYPE
RESET
DESCRIPTION
[7:3]
RSRVD
-
-
Reserved.
Digital Clock Enable. When DIG_CLK_EN is 1 the digital
system clock is active. When DIG_CLK_EN is 0 the digital
system clock is disabled.
[2]
DIG_CLK_EN
RW
1
[1]
PLL2_DIG_CLK_EN
RW
1
Enable PLL2 Digital Clock Buffer.
0
POR Clock behavior after Lock. If PORCLKAFTERLOCK is 0
then the system clock is switched from the POR Clock to the
PLL2 Digital Clock after lock and the POR Clock oscillator is
disabled. If PORCLKAFTERLOCK is 1, the POR Clock
remains as the digital system clock regardless of the PLL
Lock state.
[0]
PORCLKAFTERLOCK
RW
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9.6.2.20 PLL2REFCLKDIV
The PLL2REFCLKDIV Register controls the PLL2 Reference Clock Divider value. Return to Register Map.
Table 44. Register – 0x13
BIT NO.
FIELD
TYPE
RESET
[7:5]
RSRVD
-
-
Reserved.
0x0
PLL2 Ref Clock Divider for Digital Clock. Defines the divider
ratio for the PLL2 Reference Clock that can be used as the
digital system clock.
PLL2_REF_DIGCLK_DIV– Divider Value
b00000– 32
b00001– 16
b00010– 8
b00100– 4
b01000– 2
b10000– 1
[4:0]
PLL2_REF_DIGCLK_DIV[4:0
]
RW
DESCRIPTION
9.6.2.21 GLBL_SYNC_SYSREF
The GLBL_SYNC_SYSREF Register provides software control of the SYSREF and SYNC features. Return to
Register Map.
Table 45. Register – 0x14
BIT NO.
FIELD
TYPE
RESET
DESCRIPTION
[7]
EN_SYNC_PIN_FUNC
RW
0
Enable SYNC_SYSREF features at SYNC pin.
[6]
RSRVD
-
-
Reserved.
[5]
GLOBAL_CONT_SYSREF
RW
0
Enable continuous SYSREF.
[4]
GLOBAL_SYSREF
RWSC
0
Trigger SYSREF. Self-clearing.
[3]
INV_SYNC_INPUT_SYNC_C
LK
RW
0
Invert the internal synchronization clock for SYNC input sync
(For PLL1 N- and R-Divider Reset)
[2:1]
SYNC_PIN_FUNC[1:0]
RW
0x0
SYNC input pin function.
SYNC_PIN_FUNC– Function
00– SYNC output channels
01– Sysref Request
10– Reset PLL1 N- and R-Divider
11– Reserved
[0]
GLOBAL_SYNC
RW
0
Global SW SYNC. Writing 1 puts the Device into SYNC
mode. Writing 0 exits SYNC mode.
9.6.2.22 CLKIN_CTRL0
The CLKIN_CTRL0 Register provides control of CLK Input features. Return to Register Map.
Table 46. Register – 0x15
BIT NO.
FIELD
TYPE
RESET
[7:4]
RSRVD
-
-
Reserved.
[3]
CLKIN_STAGGER_EN
RW
1
CLKINBLK Staggered Activation/Deactivation. When
CLKIN_STAGGER_EN is 1, the input clock stages are
activated and deactivated one at a time.
[2]
CLKIN_SWRST
RWSC
0
CLKINBLK Software Reset. Writing a 1 to CLKIN_SWRST
resets the CLKIN Block. The CLKIN_SWRST is cleared
automatically to 0.
[1]
RSRVD
-
-
Reserved.
0
CLKIN_SEL Invert.
CLKINSEL1_INV– Polarity
0– Non-Inverted
1– Inverted
[0]
68
DESCRIPTION
CLKINSEL1_INV
RW
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9.6.2.23 CLKIN_CTRL1
The CLKIN_CTRL1 Register provides control of CLK Input features. Return to Register Map.
Table 47. Register – 0x16
BIT NO.
[7]
FIELD
CLKINBLK_ALL_EN
TYPE
RW
RESET
DESCRIPTION
0
CLK Inputs All Enabled after Clock Switch. If
CLKINBLK_ALL_EN is 1 then all clock input paths remain
enabled after a valid clock has been selected. If
CLKINBLK_ALL_EN is 0 then the clock paths are disabled
apart from the selected clock.
[6:5]
CLKINSEL1_MODE[1:0]
RW
0x0
CLK Input Select Mode.
CLKINSEL1_MODE– CLOCK Selection Mode
0– Auto
1– Pin
2– Register
[4]
CLKINBLK_EN_BUF_CLK_P
LL
RW
0
Clock Buffer for PLL1 Enable.
[3]
CLKINBLK_EN_BUF_BYP_P
LL
RW
0
Clock Buffer for PLL2 Enable (PLL1 By-Passed).
[2]
RSRVD
RW
0
Reserved.
[1]
RSRVD
RW
0
Reserved.
[0]
RSRVD
RW
0
Reserved.
9.6.2.24 CLKIN0CTRL
The CLKIN0CTRL Register provides control of the CLK0 input path. Return to Register Map.
Table 48. Register – 0x19
BIT NO.
FIELD
TYPE
RESET
DESCRIPTION
[7]
RSRVD
-
-
Reserved.
[6]
CLKIN0_PLL1_INV
RW
1
Inverts CLKIN0_PLL1_RDIV.
0=Noninverted
1=Inverted
[5]
CLKIN0_LOS_FRQ_DBL_EN
RW
0
CLKIN0 Loss of Source Frequency Doubler Enable.
[4]
CLKIN0_EN
RW
0
CLKIN0 Input Stage Enable. (not clk buffer).
1
CLKIN0 Signal Mode.
CLKIN0_SE_MODE– Signal Mode Selection
0– Differential
1– Single-ended
0x3
CLKIN0 Priority.
CLKIN0_PRIO– Clock Priority
0– Clock Disabled
1– Priority 1– Highest
2– Priority 2
3– Priority 3
4– Priority 4– Lowest
[3]
[2:0]
CLKIN0_SE_MODE
CLKIN0_PRIO[2:0]
RW
RW
9.6.2.25 CLKIN1CTRL
The CLKIN1CTRL Register provides control of the CLK1 input path. Return to Register Map.
Table 49. Register – 0x1A
BIT NO.
FIELD
TYPE
RESET
[7]
RSRVD
-
-
Reserved.
1
Inverts CLKIN1_PLL1_RDIV.
0=Non-Inverted
1=Inverted
[6]
CLKIN1_PLL1_INV
RW
DESCRIPTION
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Table 49. Register – 0x1A (continued)
BIT NO.
FIELD
TYPE
RESET
DESCRIPTION
[5]
CLKIN1_LOS_FRQ_DBL_EN
RW
0
CLKIN1 Loss of Source Frequency Doubler Enable.
[4]
CLKIN1_EN
RW
0
CLKIN1 Input Stage Enable. (not CLK buffer).
1
CLKIN1 Signal Mode.
CLKIN1_SE_MODE– Signal Mode Selection
0– Differential
1– Single-ended
0x4
CLKIN1 Priority.
CLKIN1_PRIO– Clock Priority
0– Clock Disabled
1– Priority 1– Highest
2– Priority 2
3– Priority 3
4– Priority 4– Lowest
[3]
[2:0]
CLKIN1_SE_MODE
CLKIN1_PRIO[2:0]
RW
RW
9.6.2.26 CLKIN0RDIV_BY1
The CLKIN0 RDIV Values is determined by CLKIN0RDIV_BY1 and CLKIN0RDIV_BY0. Return to Register Map.
Table 50. Register – 0x1F
BIT NO.
[7:0]
FIELD
CLKIN0_PLL1_RDIV[15:8]
TYPE
RW
RESET
DESCRIPTION
0x0
CLKIN0 PLL1 Reference Divider Value.
CLKIN0_PLL1_RDIV– Reference Divider
0– Reserved
1– 1
..– ..
65535– 65535
9.6.2.27 CLKIN0RDIV_BY0
The CLKIN0RDIV_BY0 Register controls the lower 8-bits of the CLKIN0 Reference Divider. Return to Register
Map.
Table 51. Register – 0x20
BIT NO.
FIELD
TYPE
RESET
DESCRIPTION
[7:0]
CLKIN0_PLL1_RDIV[7:0]
RW
0x78
CLKIN0 PLL1 Reference Divider Value.
9.6.2.28 CLKIN1RDIV_BY1
The CLKIN1 RDIV Values is determined by CLKIN1RDIV_BY1 and CLKIN1RDIV_BY0. Return to Register Map.
Table 52. Register – 0x21
BIT NO.
[7:0]
70
FIELD
CLKIN1_PLL1_RDIV[15:8]
TYPE
RW
RESET
DESCRIPTION
0x0
CLKIN1 PLL1 Reference Divider Value.
CLKIN1_PLL1_RDIV– Reference Divider
0– Reserved
1– 1
..– ..
65535– 65535
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9.6.2.29 CLKIN1RDIV_BY0
The CLKIN1RDIV_BY0 Register controls the lower 8-bits of the CLKIN1 Reference Divider. Return to Register
Map.
Table 53. Register – 0x22
BIT NO.
FIELD
TYPE
RESET
DESCRIPTION
[7:0]
CLKIN1_PLL1_RDIV[7:0]
RW
0x78
CLKIN1 PLL1 Reference Divider Value.
9.6.2.30 CLKIN0LOS_REC_CNT
The CLKIN0LOS_REC_CNT Register sets the CLKIN0 Loss of Source recovery counter value. Return to
Register Map.
Table 54. Register – 0x27
BIT NO.
[7:0]
FIELD
CLKIN0_LOS_REC_CNT[7:0
]
TYPE
RW
RESET
DESCRIPTION
0x14
CLKIN0 LOS Recovery Counter Value.
CLKIN0_LOS_REC_CNT– Counter Value
0– 15+0*16
1– 15+1*16
2– 15+2*16
3– 15+3*16
..– ..
255– 15+255*16
9.6.2.31 CLKIN0LOS_LAT_SEL
The CLKIN0LOS_LAT_SEL Register sets the CLKIN0 Loss of Source latency. Return to Register Map.
Table 55. Register – 0x28
BIT NO.
FIELD
TYPE
RESET
DESCRIPTION
[7:0]
CLKIN0_LOS_LAT_SEL[7:0]
RW
0x80
CLKIN0 LOS Max Latency for LOS Detection.
9.6.2.32 CLKIN1LOS_REC_CNT
The CLKIN1LOS_REC_CNT Register sets the CLKIN1 Loss of Source recovery counter value. Return to
Register Map.
Table 56. Register – 0x29
BIT NO.
[7:0]
FIELD
CLKIN1_LOS_REC_CNT[7:0
]
TYPE
RW
RESET
DESCRIPTION
0x14
CLKIN1 LOS Recovery Counter Value.
CLKIN1_LOS_REC_CNT– Counter Value
0– 15+0*16
1– 15+1*16
2– 15+2*16
3– 15+3*16
..– ..
255– 15+255*16
9.6.2.33 CLKIN1LOS_LAT_SEL
The CLKIN1LOS_LAT_SEL Register sets the CLKIN1 Loss of Source latency. Return to Register Map.
Table 57. Register – 0x2A
BIT NO.
FIELD
TYPE
RESET
DESCRIPTION
[7:0]
CLKIN1_LOS_LAT_SEL[7:0]
RW
0x80
CLKIN1 LOS Max Latency for LOS Detection.
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9.6.2.34 CLKIN_SWCTRL0
The CLKIN_SWCTRL0 Register provides control of the input settling time after switching to another Ref channel
for Loss-Of-Signal Inspection. Return to Register Map.
Table 58. Register – 0x2B
BIT NO.
FIELD
TYPE
RESET
[7:5]
RSRVD
-
-
Reserved.
0x0
Wait Time for a Valid LOS Detection. Used during Priority
Switching in Auto CLKin selection mode.
[4:0]
SW_CLKLOS_TMR[4:0]
RW
DESCRIPTION
9.6.2.35 CLKIN_SWCTRL1
The CLKIN_SWCTRL1 Register provides control of the Loss-Of-Signal Channel select. Return to Register Map.
Table 59. Register – 0x2C
BIT NO.
[7:4]
[3:0]
FIELD
SW_REFINSEL[3:0]
SW_LOS_CH_SEL[3:0]
TYPE
RW
RW
RESET
DESCRIPTION
0x0
Software Mode Reference Input Select.
SW_REFINSEL– Input Selected
0001– RESERVED
0010– RESERVED
0100– CLKIN0
1000– CLKIN1
0x0
Loss of Source Channel Select.
SW_LOS_CH_SEL– Input Selected
0001– RESERVED
0010– RESERVED
0100– CLKIN0
1000– CLKIN1
9.6.2.36 CLKIN_SWCTRL2
The CLKIN_SWCTRL2 Register provides control of the input stage settling time when switching on all inputs in
case of Loss-Of-Signal. Return to Register Map.
Table 60. Register – 0x2D
BIT NO.
FIELD
TYPE
RESET
[7:5]
RSRVD
-
-
DESCRIPTION
Reserved.
[4:0]
SW_ALLREFSON_TMR[4:0]
RW
0x0
Wait Time to allow Clock Inputs to Settle.
9.6.2.37 OSCIN_CTRL
The OSCIN_CTRL Register provides control of the OSCIN signal path. Return to Register Map.
Table 61. Register – 0x2E
BIT NO.
FIELD
TYPE
RESET
[7:6]
RSRVD
-
-
Reserved.
0
OSCIN LDO Power Down.
OSCIN_PD_LDO– LDO State
0– LDO On
1– LDO Off
[5]
72
OSCIN_PD_LDO
RW
DESCRIPTION
[4]
OSCIN_SE_MODE
RW
1
OSCin Signal Mode.
OSCIN_SE_MODE– Signal Mode Selection
0– Differential
1– Single-ended
[3]
OSCIN_BUF_TO_OSCOUT_
EN
RW
1
OSCin to OSCout Buffer Enable.
[2]
OSCIN_OSCINSTAGE_EN
RW
1
OSCin Clock Input Stage Enable.
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Table 61. Register – 0x2E (continued)
BIT NO.
FIELD
TYPE
RESET
DESCRIPTION
[1]
OSCIN_BUF_REF_EN
RW
0
OSCin to PLL1 and PLL2 Ref Clock Buffer Enable.
[0]
OSCIN_BUF_LOS_EN
RW
0
OSCin to LOS Clock Buffer Enable.
9.6.2.38 OSCOUT_CTRL
The OSCOUT_CTRL Register controls the OSCOUT Function. Return to Register Map.
Table 62. Register – 0x2F
BIT NO.
FIELD
TYPE
RESET
DESCRIPTION
[7]
OSCOUT_LVCMOS_WEAK_
DRIVE
RW
0
Enable OSCOUT LVCMOS weak drive.
[6]
OSCOUT_DIV_REGCONTR
OL
RW
0
Enable OSCOUT Divider setting through configuration
register rather than SYNC pin control.
[5:4]
OSCOUT_PINSEL_DIV[1:0]
R
0x0
OSCOUT pin-selected Divider.
OSCOUT_PINSEL_DIV– Pin-Selected Oscout Divider ratio
00– 1
01– 2
10– 2
11– 4
[3]
OSCOUT_SEL_VBG
RW
0
OSCOUT Bandgap Source Select. When
OSCOUT_SEL_VBG is 0 the PLL1 Bandgap is used for
OSCOUT. If OSCOUT_SEL_VBG is 1 the Output Channel
Bandgap is used.
[2]
OSCOUT_DIV_CLKEN
RW
1
OSCout Divider Clock Enable. (RESERVED for PG1p0)
0
OSCOUT Software Reset. Writing a 1 to OSCOUT_SWRST
resets the OSCOUT Block. The OSCOUT_SWRST is
cleared automatically to 0.
1
OSCout Clock source select.
OSCOUT_SEL_SRC– Clock Source
0– PLL2 Output
1– OSCin
[1]
[0]
OSCOUT_SWRST
OSCOUT_SEL_SRC
RWSC
RW
9.6.2.39 OSCOUT_DIV
The OSCOUT_DIV Register controls the OSCOUT Divider. Return to Register Map.
Table 63. Register – 0x30
BIT NO.
FIELD
TYPE
RESET
DESCRIPTION
[7:0]
OSCOUT_DIV[7:0]
RW
0x0
OSCOUT Divider. Set value of OSCOUT channel divider.
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9.6.2.40 OSCOUT_DRV
The OSCOUT_DRV Register controls the OSCOUT Driver. Return to Register Map.
Table 64. Register – 0x31
BIT NO.
[7:6]
[5:0]
74
FIELD
OSCOUT_DRV_MUTE[1:0]
OSCOUT_DRV_MODE[5:0]
TYPE
RW
RW
RESET
DESCRIPTION
0x0
OSCOUT Driver Mute Control. OSCOUT_DRV_MUTE sets
the OSCOUT driver mute input after the internal reset has
been de-asserted. During the reset sequence the mute input
is set to 11. It is configured together with
OSCOUT_DRV_MODE.
OSCOUT_DRV_MUTE,OSCOUT_DRV_MODE– Output
State
00,XXXXXX– OSCOUT Driver is Active
01,11XXXX– OSCOUT_P operating normal, OSCOUT_N
Low
01,01XXXX– OSCOUT_P operating normal, OSCOUT_N
Operating normal
01,10XX00– OSCOUT_P High, OSCOUT_N High
01,10XX01– OSCOUT_P operating normal, OSCOUT_N
operating normal
01,10XX10– OSCOUT_P operating normal, OSCOUT_N
operating normal
01,10XX11– OSCOUT_P operating normal, OSCOUT_N
operating normal
10,11XXXX– OSCOUT_P Low, OSCOUT_N operating
normal
10,01XXXX– OSCOUT_P Low, OSCOUT_N High
10,10XX00– OSCOUT_P High, OSCOUT_N High
10,10XX01– OSCOUT_P Low, OSCOUT_N High
10,10XX10– OSCOUT_P Low, OSCOUT_N High
10,10XX11– OSCOUT_P Low, OSCOUT_N High
11,11XXXX– OSCOUT_P Low, OSCOUT_N Low
11,01XXXX– OSCOUT_P Low, OSCOUT_N High
11,10XX00– OSCOUT_P High, OSCOUT_N High
11,10XX01– OSCOUT_P Low, OSCOUT_N High
11,10XX10– OSCOUT_P Low, OSCOUT_N High
11,10XX11– OSCOUT_P Low, OSCOUT_N High
0x3F
OSCOUT Driver Mode.
OSCOUT_DRV_MODE– Output stage configuration
00XXXX– Power Down
01XXXX– HSDS Mode
10XXXX– HSCL Mode
11XXXX– LVCMOS Mode
XX00XX– HSDS, HSCL: ITail: 4mA, LVCMOS: OSCOUT_P
tristate
XX01XX– HSDS, HSCL: ITail: 6mA, LVCMOS: OSCOUT_P
Weak Drive
XX10XX– HSDS, HSCL: ITail: 8mA, LVCMOS: OSCOUT_P
Normal Drive Inverted
XX11XX– ITail HSDS: 8mA, HSCL: 16mA, LVCMOS:
OSCOUT_P Normal Drive Non-Inverted
XXXX00– Rload HSDS: open, HSCL: open, LVCMOS:
OSCOUT_N tristate
XXXX01– Rload HSDS: open, HSCL: 50Ohm, LVCMOS:
OSCOUT_N Weak Drive
XXXX10– Rload HSDS: open, HSCL: 100Ohm for Itail=4mA,
6mA, 8mA, LVCMOS: OSCOUT_N Normal Drive Inverted
XXXX11– Rload HSDS: open, HSCL: 200Ohm for Itail=4mA,
LVCMOS: OSCOUT_N Normal Drive Non-Inverted
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9.6.2.41 OUTCH_SWRST
The OUTCH_SWRST Register allows software reset to applied independently to each output channel. Return to
Register Map.
Table 65. Register – 0x32
BIT NO.
FIELD
TYPE
RESET
DESCRIPTION
[7]
CH10_SWRST
RWSC
0
CH10 Software Reset. Writing a 1 to CH10_SWRST resets
CH10. CH10_SWRST is cleared automatically to 0.
[6]
CH9_SWRST
RWSC
0
CH9 Software Reset. Writing a 1 to CH9_SWRST resets
CH9. CH9_SWRST is cleared automatically to 0.
[5]
CH78_SWRST
RWSC
0
CH78 Software Reset. Writing a 1 to CH78_SWRST resets
CH78. CH78_SWRST is cleared automatically to 0.
[4]
CH6_SWRST
RWSC
0
CH6 Software Reset. Writing a 1 to CH6_SWRST resets
CH6. CH6_SWRST is cleared automatically to 0.
[3]
CH5_SWRST
RWSC
0
CH5 Software Reset. Writing a 1 to CH5_SWRST resets
CH5. CH5_SWRST is cleared automatically to 0.
[2]
CH34_SWRST
RWSC
0
CH34 Software Reset. Writing a 1 to CH34_SWRST resets
CH34. CH34_SWRST is cleared automatically to 0.
[1]
CH2_SWRST
RWSC
0
CH2 Software Reset. Writing a 1 to CH2_SWRST resets
CH2. CH2_SWRST is cleared automatically to 0.
[0]
CH1_SWRST
RWSC
0
CH1 Software Reset. Writing a 1 to CH1_SWRST resets
CH1. CH1_SWRST is cleared automatically to 0.
9.6.2.42 OUTCH1CNTL0
The OUTCH1CNTRL0 Register controls Output CH1. Return to Register Map.
Table 66. Register – 0x33
BIT NO.
FIELD
TYPE
RESET
DESCRIPTION
[7]
OUTCH1_LDO_BYP_MODE
RW
0
OUTCH1 LDO Bypass.
OUTCH1_LDO_BYP_MODE– LDO State
0– Enabled
1– Bypassed
[6]
OUTCH1_LDO_MASK
RW
0
OUTCH1 LDO Mask. If OUTCH1_LDO_MASK is 1 then CH1
LDO is masked from the Power Up Sequence and enabled
directly.
[5:0]
RSRVD[5:0]
RW
0
RESERVED
9.6.2.43 OUTCH1CNTL1
The OUTCH1CNTRL1 Register controls Output CH1. Return to Register Map.
Table 67. Register – 0x34
BIT NO.
FIELD
TYPE
RESET
DESCRIPTION
OUTCH1 Clock Driver Mode Setting.
0 - Power down
16 - HSDS 4 mA
20 - HSDS 6 mA
24 - HSDS 8 mA
59 - HCSL 8 mA
63 - HCSL 16 mA
[7:2]
OUTCH1_DRIV_MODE[5:0]
RW
0x18
[1]
DIV_DCC_EN_CH1
RW
1
Output CH1 Divier Duty Cycle Correction Enable
1
OUTCH1 Channel Divider Clock Enable. Enables output
channel PLL Clock Buffer.
[0]
OUTCH1_DIV_CLKEN
RW
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9.6.2.44 OUTCH2CNTL0
The OUTCH2CNTL0 Register controls Output CH2. Return to Register Map.
Table 68. Register – 0x35
BIT NO.
FIELD
TYPE
RESET
DESCRIPTION
[7]
OUTCH2_LDO_BYP_MODE
RW
0
OUTCH2 LDO Bypass.
OUTCH2_LDO_BYP_MODE– LDO State
0– Enabled
1– Bypassed
[6]
OUTCH2_LDO_MASK
RW
0
OUTCH2 LDO Mask. If OUTCH2_LDO_MASK is 1 then CH2
LDO is masked from the Power Sequence.
0x18
OUTCH2 Clock Driver Mode Setting.
0 - Power down
16 - HSDS 4 mA
20 - HSDS 6 mA
24 - HSDS 8 mA
59 - HCSL 8 mA
63 - HCSL 16 mA
[5:0]
OUTCH2_DRIV_MODE[5:0]
RW
9.6.2.45 OUTCH2CNTL1
The OUTCH2CNTRL1 Register controls Output CH2. Return to Register Map.
Table 69. Register – 0x36
BIT NO.
FIELD
TYPE
RESET
[7:2]
RESERVED[5:0]
RW
0
DESCRIPTION
RESERVED
[1]
DIV_DCC_EN_CH2
RW
1
Output CH2 Divider Duty Cycle Correction Enable
[0]
OUTCH2_DIV_CLKEN
RW
1
OUTCH2 Channel Divider Clock Enable. Enables output
channel PLL Clock Buffer.
9.6.2.46 OUTCH34CNTL0
The OUTCH34CNTRL0 Register controls Output CH3_4. Return to Register Map.
Table 70. Register – 0x37
BIT NO.
TYPE
RESET
DESCRIPTION
[7]
OUTCH34_LDO_BYP_MOD
E
RW
0
OUTCH34 LDO Bypass.
OUTCH34_LDO_BYP_MODE– LDO State
0– Enabled
1– Bypassed
[6]
OUTCH34_LDO_MASK
RW
0
OUTCH34 LDO Mask. If OUTCH34_LDO_MASK is 1 then
CH34 LDO is masked from the Power Sequence.
0x18
OUTCH3 Clock Driver Mode Setting.
0 - Power down
16 - HSDS 4 mA
20 - HSDS 6 mA
24 - HSDS 8 mA
59 - HCSL 8 mA
63 - HCSL 16 mA
[5:0]
76
FIELD
OUTCH3_DRIV_MODE[5:0]
RW
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9.6.2.47 OUTCH34CNTL1
The OUTCH34CNTRL1 Register controls Output CH3_4. Return to Register Map.
Table 71. Register – 0x38
BIT NO.
FIELD
TYPE
RESET
DESCRIPTION
OUTCH4 Clock Driver Mode Setting.
0 - Power down
16 - HSDS 4 mA
20 - HSDS 6 mA
24 - HSDS 8 mA
59 - HCSL 8 mA
63 - HCSL 16 mA
[7:2]
OUTCH4_DRIV_MODE[5:0]
RW
0x18
[1]
DIV_DCC_EN_CH3_4
RW
1
Output CH3_4 Divider Duty Cycle Correction Enable
1
OUTCH34 Channel Divider Clock Enable. Enables output
channel PLL Clock Buffer.
[0]
OUTCH34_DIV_CLKEN
RW
9.6.2.48 OUTCH5CNTL0
The OUTCH5CNTRL0 Register controls Output CH5. Return to Register Map.
Table 72. Register – 0x39
BIT NO.
FIELD
TYPE
RESET
DESCRIPTION
[7]
OUTCH5_LDO_BYP_MODE
RW
0
OUTCH5 LDO Bypass.
OUTCH5_LDO_BYP_MODE– LDO State
0– Enabled
1– Bypassed
[6]
OUTCH5_LDO_MASK
RW
0
OUTCH5 LDO Mask. If OUTCH5_LDO_MASK is 1 then CH5
LDO is masked from the Power Sequence.
0x18
OUTCH5 Clock Driver Mode Setting.
0 - Power down
16 - HSDS 4 mA
20 - HSDS 6 mA
24 - HSDS 8 mA
59 - HCSL 8 mA
63 - HCSL 16 mA
[5:0]
OUTCH5_DRIV_MODE[5:0]
RW
9.6.2.49 OUTCH5CNTL1
The OUTCH5CNTRL1 Register controls Output CH5. Return to Register Map.
Table 73. Register – 0x3A
BIT NO.
FIELD
TYPE
RESET
DESCRIPTION
[7:2]
RSRVD[5:0]
RW
0
RESERVED
[1]
DIV_DCC_EN_CH5
RW
0
Output CH5 Divider Duty Cycle Correction Enable
[0]
OUTCH5_DIV_CLKEN
RW
1
OUTCH5 Channel Divider Clock Enable. Enables output
channel PLL Clock Buffer.
9.6.2.50 OUTCH6CNTL0
The OUTCH6CNTRL0 Register controls Output CH6. Return to Register Map.
Table 74. Register – 0x3B
BIT NO.
FIELD
TYPE
RESET
DESCRIPTION
[7]
OUTCH6_LDO_BYP_MODE
RW
0
OUTCH6 LDO Bypass.
OUTCH6_LDO_BYP_MODE– LDO State
0– Enabled
1– Bypassed
[6]
OUTCH6_LDO_MASK
RW
0
OUTCH6 LDO Mask. If OUTCH6_LDO_MASK is 1 then CH6
LDO is masked from the Power Sequence.
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Table 74. Register – 0x3B (continued)
BIT NO.
FIELD
TYPE
RESET
DESCRIPTION
[5:0]
RSRVD[5:0]
RW
0
RESERVED
9.6.2.51 OUTCH6CNTL1
The OUTCH6CNTRL1 Register controls Output CH6. Return to Register Map.
Table 75. Register – 0x3C
BIT NO.
FIELD
TYPE
RESET
DESCRIPTION
OUTCH6 Clock Driver Mode Setting.
0 - Power down
16 - HSDS 4 mA
20 - HSDS 6 mA
24 - HSDS 8 mA
59 - HCSL 8 mA
63 - HCSL 16 mA
[7:2]
OUTCH6_DRIV_MODE[5:0]
RW
0x18
[1]
DIV_DCC_EN_CH6
RW
0
Output CH6 Divider Duty Cycle Correction Enable
1
OUTCH6 Channel Divider Clock Enable. Enables output
channel PLL Clock Buffer.
[0]
OUTCH6_DIV_CLKEN
RW
9.6.2.52 OUTCH78CNTL0
The OUTCH78CNTRL0 Register controls Output CH7_8. Return to Register Map.
Table 76. Register – 0x3D
BIT NO.
FIELD
TYPE
RESET
DESCRIPTION
[7]
OUTCH78_LDO_BYP_MOD
E
RW
0
OUTCH78 LDO Bypass.
OUTCH78_LDO_BYP_MODE– LDO State
0– Enabled
1– Bypassed
[6]
OUTCH78_LDO_MASK
RW
0
OUTCH78 LDO Mask. If OUTCH78_LDO_MASK is 1 then
CH78 LDO is masked from the Power Sequence.
0x18
OUTCH7 Clock Driver Mode Setting.
0 - Power down
16 - HSDS 4 mA
20 - HSDS 6 mA
24 - HSDS 8 mA
59 - HCSL 8 mA
63 - HCSL 16 mA
[5:0]
OUTCH7_DRIV_MODE[5:0]
RW
9.6.2.53 OUTCH78CNTL1
The OUTCH78CNTRL1 Register controls Output CH7_8. Return to Register Map.
Table 77. Register – 0x3E
BIT NO.
78
FIELD
TYPE
RESET
DESCRIPTION
[7:2]
OUTCH8_DRIV_MODE[5:0]
RW
0x18
OUTCH8 Clock Driver Mode Setting.
0 - Power down
16 - HSDS 4 mA
20 - HSDS 6 mA
24 - HSDS 8 mA
59 - HCSL 8 mA
63 - HCSL 16 mA
[1]
DIV_DCC_EN_CH7_8
RW
0
Output CH7_8 Divider Duty Cycle Correction Enable
[0]
OUTCH78_DIV_CLKEN
RW
1
OUTCH78 Channel Divider Clock Enable. Enables output
channel PLL Clock Buffer.
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9.6.2.54 OUTCH9CNTL0
The OUTCH9CNTRL0 Register controls Output CH9. Return to Register Map.
Table 78. Register – 0x3F
BIT NO.
FIELD
TYPE
RESET
DESCRIPTION
[7]
OUTCH9_LDO_BYP_MODE
RW
0
OUTCH9 LDO Bypass.
OUTCH9_LDO_BYP_MODE– LDO State
0– Enabled
1– Bypassed
[6]
OUTCH9_LDO_MASK
RW
0
OUTCH9 LDO Mask. If OUTCH9_LDO_MASK is 1 then CH9
LDO is masked from the Power Sequence.
[5:0]
RSRVD[5:0]
RW
0
RESERVED
9.6.2.55 OUTCH9CNTL1
The OUTCH9CNTRL1 Register controls Output CH9. Return to Register Map.
Table 79. Register – 0x40
BIT NO.
FIELD
TYPE
RESET
DESCRIPTION
[7:2]
OUTCH9_DRIV_MODE[5:0]
RW
0x18
OUTCH9 Clock Driver Mode Setting.
0 - Power down
16 - HSDS 4 mA
20 - HSDS 6 mA
24 - HSDS 8 mA
59 - HCSL 8 mA
63 - HCSL 16 mA
[1]
DIV_DCC_EN_CH9
RW
0
Output CH9 Divider Duty Cycle Correction Enable
[0]
OUTCH9_DIV_CLKEN
RW
1
OUTCH9 Channel Divider Clock Enable. Enables output
channel PLL Clock Buffer.
9.6.2.56 OUTCH10CNTL0
The OUTCH10CNTRL0 Register controls Output CH10. Return to Register Map.
Table 80. Register – 0x41
BIT NO.
FIELD
TYPE
RESET
DESCRIPTION
[7]
OUTCH10_LDO_BYP_MOD
E
RW
0
OUTCH10 LDO Bypass.
OUTCH10_LDO_BYP_MODE– LDO State
0– Enabled
1– Bypassed
[6]
OUTCH10_LDO_MASK
RW
0
OUTCH10 LDO Mask. If OUTCH10_LDO_MASK is 1 then
CH10 LDO is masked from the Power Sequence.
0x18
OUTCH10 Clock Driver Mode Setting.
0 - Power down
16 - HSDS 4 mA
20 - HSDS 6 mA
24 - HSDS 8 mA
59 - HCSL 8 mA
63 - HCSL 16 mA
[5:0]
OUTCH10_DRIV_MODE[5:0]
RW
9.6.2.57 OUTCH10CNTL1
The OUTCH10CNTRL1 Register controls Output CH10. Return to Register Map.
Table 81. Register – 0x42
BIT NO.
FIELD
TYPE
RESET
DESCRIPTION
[7:2]
RESERVED[5:0]
RW
0
RESERVED
[1]
DIV_DCC_EN_CH10
RW
0
Output CH10 Divider Duty Cycle Correction Enable
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Table 81. Register – 0x42 (continued)
BIT NO.
[0]
FIELD
OUTCH10_DIV_CLKEN
TYPE
RW
RESET
DESCRIPTION
1
OUTCH10 Channel Divider Clock Enable. Enables output
channel PLL Clock Buffer.
9.6.2.58 OUTCH1DIV_BY1
The OUTCH1DIV_BY1,BY0 Registers set the OUTCH1 Divider Value. Return to Register Map.
Table 82. Register – 0x43
BIT NO.
[7:0]
FIELD
OUTCH1_DIV[15:8]
TYPE
RW
RESET
DESCRIPTION
0x0
OUTCH1 Divider Value. Sets the divider value for output
channel 1. An automatic reset is issued whenever the divider
value is changed.
9.6.2.59 OUTCH1DIV_BY0
The OUTCH1DIV_BY0 Register sets the lower 7 bits of the OUTCH1 Divider Value. Return to Register Map.
Table 83. Register – 0x44
BIT NO.
FIELD
TYPE
RESET
DESCRIPTION
[7:0]
OUTCH1_DIV[7:0]
RW
0x1
OUTCH1 Divider Value.
9.6.2.60 OUTCH2DIV_BY1
The OUTCH2DIV_BY1,BY0 Registers set the OUTCH2 Divider Value. Return to Register Map.
Table 84. Register – 0x45
BIT NO.
[7:0]
FIELD
OUTCH2_DIV[15:8]
TYPE
RW
RESET
DESCRIPTION
0x0
OUTCH2 Divider Value. Sets the divider value for output
channel 2. An automatic reset is issued whenever the divider
value is changed.
9.6.2.61 OUTCH2DIV_BY0
The OUTCH2DIV_BY0 Register sets the lower 7 bits of the OUTCH2 Divider Value. Return to Register Map.
Table 85. Register – 0x46
BIT NO.
FIELD
TYPE
RESET
DESCRIPTION
[7:0]
OUTCH2_DIV[7:0]
RW
0x2
OUTCH2 Divider Value.
9.6.2.62 OUTCH34DIV_BY1
The OUTCH34DIV_BY1,BY0 Registers set the OUTCH34 Divider Value. Return to Register Map.
Table 86. Register – 0x47
BIT NO.
[7:0]
80
FIELD
OUTCH34_DIV[15:8]
TYPE
RW
RESET
DESCRIPTION
0x0
OUTCH34 Divider Value. Sets the divider value for output
channels 3 and 4. An automatic reset is issued whenever the
divider value is changed.
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9.6.2.63 OUTCH34DIV_BY0
The OUTCH34DIV_BY0 Register sets the lower 7 bits of the OUTCH34 Divider Value. Return to Register Map.
Table 87. Register – 0x48
BIT NO.
FIELD
TYPE
RESET
DESCRIPTION
[7:0]
OUTCH34_DIV[7:0]
RW
0x8
OUTCH34 Divider Value.
9.6.2.64 OUTCH5DIV_BY1
The OUTCH5DIV_BY1,BY0 Registers set the OUTCH5 Divider Value. Return to Register Map.
Table 88. Register – 0x49
BIT NO.
[7:0]
FIELD
OUTCH5_DIV[15:8]
TYPE
RW
RESET
DESCRIPTION
0x0
OUTCH5 Divider Value. Sets the divider value for output
channel 5. An automatic reset is issued whenever the divider
value is changed.
9.6.2.65 OUTCH5DIV_BY0
The OUTCH5DIV_BY0 Register sets the lower 7 bits of the OUTCH5 Divider Value. Return to Register Map.
Table 89. Register – 0x4A
BIT NO.
FIELD
TYPE
RESET
DESCRIPTION
[7:0]
OUTCH5_DIV[7:0]
RW
0x20
OUTCH5 Divider Value.
9.6.2.66 OUTCH6DIV_BY1
The OUTCH6DIV_BY1,BY0 Registers set the OUTCH6 Divider Value. Return to Register Map.
Table 90. Register – 0x4B
BIT NO.
[7:0]
FIELD
OUTCH6_DIV[15:8]
TYPE
RW
RESET
DESCRIPTION
0x0
OUTCH6 Divider Value. Sets the divider value for output
channel 6. An automatic reset is issued whenever the divider
value is changed.
9.6.2.67 OUTCH6DIV_BY0
The OUTCH6DIV_BY0 Register sets the lower 7 bits of the OUTCH6 Divider Value. Return to Register Map.
Table 91. Register – 0x4C
BIT NO.
FIELD
TYPE
RESET
DESCRIPTION
[7:0]
OUTCH6_DIV[7:0]
RW
0x3
OUTCH6 Divider Value.
9.6.2.68 OUTCH78DIV_BY1
The OUTCH78DIV_BY1,BY0 Registers set the OUTCH78 Divider Value. Return to Register Map.
Table 92. Register – 0x4D
BIT NO.
[7:0]
FIELD
OUTCH78_DIV[15:8]
TYPE
RW
RESET
DESCRIPTION
0x0
OUTCH78 Divider Value. Sets the divider value for output
channels 7 and 8. An automatic reset is issued whenever the
divider value is changed.
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9.6.2.69 OUTCH78DIV_BY0
The OUTCH78DIV_BY0 Register sets the lower 7 bits of the OUTCH78 Divider Value. Return to Register Map.
Table 93. Register – 0x4E
BIT NO.
FIELD
TYPE
RESET
DESCRIPTION
[7:0]
OUTCH78_DIV[7:0]
RW
0x5
OUTCH78 Divider Value.
9.6.2.70 OUTCH9DIV_BY1
The OUTCH9DIV_BY1,BY0 Registers set the OUTCH9 Divider Value. Return to Register Map.
Table 94. Register – 0x4F
BIT NO.
[7:0]
FIELD
OUTCH9_DIV[15:8]
TYPE
RW
RESET
DESCRIPTION
0x0
OUTCH9 Divider Value. Sets the divider value for output
channel 9. An automatic reset is issued whenever the divider
value is changed.
9.6.2.71 OUTCH9DIV_BY0
The OUTCH9DIV_BY0 Register sets the lower 7 bits of the OUTCH9 Divider Value. Return to Register Map.
Table 95. Register – 0x50
BIT NO.
FIELD
TYPE
RESET
DESCRIPTION
[7:0]
OUTCH9_DIV[7:0]
RW
0x9
OUTCH9 Divider Value.
9.6.2.72 OUTCH10DIV_BY1
The OUTCH10DIV_BY1,BY0 Registers set the OUTCH10 Divider Value. Return to Register Map.
Table 96. Register – 0x51
BIT NO.
[7:0]
FIELD
OUTCH10_DIV[15:8]
TYPE
RW
RESET
DESCRIPTION
0x0
OUTCH10 Divider Value. Sets the divider value for output
channel 10. An automatic reset is issued whenever the
divider value is changed.
9.6.2.73 OUTCH10DIV_BY0
The OUTCH10DIV_BY0 Register sets the lower 7 bits of the OUTCH10 Divider Value. Return to Register Map.
Table 97. Register – 0x52
BIT NO.
FIELD
TYPE
RESET
DESCRIPTION
[7:0]
OUTCH10_DIV[7:0]
RW
0x1F
OUTCH10 Divider Value.
9.6.2.74 OUTCH_DIV_INV
The OUTCH_DIV_INV Register controls inversion of the dividier output clock. Return to Register Map.
Table 98. Register – 0x53
BIT NO.
82
FIELD
TYPE
RESET
DESCRIPTION
[7]
OUTCH10_DIV_INV
RW
0
OUTCH10 Divider Output Invert. When OUTCH10_DIV_INV
is 1 the divider output for channel 10 is inverted.
[6]
OUTCH9_DIV_INV
RW
0
OUTCH9 Divider Output Invert. When OUTCH9_DIV_INV is
1 the divider output for channel 9 is inverted.
[5]
OUTCH78_DIV_INV
RW
0
OUTCH78 Divider Output Invert. When OUTCH78_DIV_INV
is 1 the divider output for channels 7 and 8 is inverted.
[4]
OUTCH6_DIV_INV
RW
0
OUTCH6 Divider Output Invert. When OUTCH6_DIV_INV is
1 the divider output for channel 6 is inverted.
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Table 98. Register – 0x53 (continued)
BIT NO.
FIELD
TYPE
RESET
DESCRIPTION
[3]
OUTCH5_DIV_INV
RW
0
OUTCH5 Divider Output Invert. When OUTCH5_DIV_INV is
1 the divider output for channel 5 is inverted.
[2]
OUTCH34_DIV_INV
RW
0
OUTCH34 Divider Output Invert. When OUTCH34_DIV_INV
is 1 the divider output for channels 3 and 4 is inverted.
[1]
OUTCH2_DIV_INV
RW
0
OUTCH2 Divider Output Invert. When OUTCH2_DIV_INV is
1 the divider output for channel 2 is inverted.
[0]
OUTCH1_DIV_INV
RW
0
OUTCH1 Divider Output Invert. When OUTCH1_DIV_INV is
1 the divider output for channel 1 is inverted.
9.6.2.75 PLL1CTRL0
The PLL1CTRL0 Register provides control of the following PLL1 related features. Return to Register Map.
Table 99. Register – 0x54
BIT NO.
FIELD
TYPE
RESET
DESCRIPTION
[7]
PLL1_F_30
RW
0
PLL1 RC Freq 0=122MHz 1=32MHz.
PLL1_F_30– PLL1 RC Frequency
0– 122MHz
1– 32MHz
[6]
PLL1_EN_REGULATION
RW
0
PLL1 Prop-CP Enable Regulation
[5]
PLL1_PD_LD
RW
1
PLL1 Window Comparator Power Down.
PLL1_PD_LD– PLL1 Window Comparator
0– Enabled
1– Off
[4]
PLL1_DIR_POS_GAIN
RW
1
PLL1 VCXO pos/neg Gain.
PLL1_DIR_POS_GAIN– Polarity
0– Positive
1– Negative
[3:0]
PLL1_LDO_WAIT_TMR[3:0]
RW
0x0
PLL1 LDO Wait Timer. The PLL1 LDO Wait Timer counts a
number of clock cycles equal to
32*(PLL1_LDO_WAIT_TMR+31) before releasing the PLL1
NDIV and RDIV resets.
9.6.2.76 PLL1CTRL1
The PLL1CTRL1 Register provides control over PLL1 related features. Return to Register Map.
Table 100. Register – 0x55
BIT NO.
FIELD
TYPE
RESET
DESCRIPTION
[7]
PLL1_LCKDET_BY_32
RW
0
PLL1 Lock Detect counter multiply with 32.
[6]
PLL1_FAST_LOCK
RW
1
PLL1 Fast Lock Enable.
[5]
PLL1_LCKDET_LOS_MASK
RW
0
PLL1 Lock Detect LOS Mask. When
PLL1_LCKDET_LOS_MASK is 1 then Loss of Source has no
effect on the PLL1 Lock Detect circuit.
[4]
PLL1_FBCLK_INV
RW
1
PLL1 Feedback Clock Inversion. When PLL1_FBCLK_INV is
1 then the Feedback Clock divider output is inverted.
[3]
RSRVD
-
-
Reserved.
[2]
PLL1_BYP_LOS
RW
0
PLL1 Bypass Loss of Source indication. When
PLL1_BYP_LOS is 1 the PLL1 controller ignores the LOS
indicator.
[1]
PLL1_PFD_UP_HOLDOVER
RW
0
PLL1 PFD UP-Input value during Holdover.
[0]
PLL1_PFD_DOWN_HOLDO
VER
RW
0
PLL1 PFD DN-Input value during Holdover.
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9.6.2.77 PLL1CTRL2
The PLL1CTRL2 Register provides control over PLL1 related features. Return to Register Map.
Table 101. Register – 0x56
BIT NO.
FIELD
TYPE
RESET
[7:5]
RSRVD
-
-
DESCRIPTION
Reserved.
[4]
PLL1_LOL_NORESET
RW
0
If set to 1, PLL1 will not reset on a Loss-of-Lock event.
[3]
PLL1_RDIV_CLKEN
RW
1
PLL1 RDIV Clock Enable.
[2]
PLL1_RDIV_4CY
RW
1
PLL1 RDIV Enable tied clock low phase to 4cycs.
Independent from divider setting.
[1]
PLL1_NDIV_CLKEN
RW
1
PLL1 NDIV Clock Enable
[0]
PLL1_NDIV_4CY
RW
1
PLL1 NDIV Enable tied clock low phase to 4cycs.
Independent from divider setting.
9.6.2.78 PLL1_SWRST
The PLL1_SWRST Register provides control of the PLL1 software resets. Return to Register Map.
Table 102. Register – 0x57
BIT NO.
FIELD
TYPE
RESET
[7:6]
RSRVD
-
-
DESCRIPTION
Reserved.
[5]
PLL1_HOLDOVER_DLD_SW
RST
RWSC
0
PLL1 Holdover DLD Software Reset. Writing a 1 to
PLL1_HOLDOVER_DLD_SWRST activates the reset.
PLL1_HOLDOVER_DLD_SWRST is cleared automatically to
0.
[4]
PLL1_RDIV_SWRST
RWSC
0
PLL1 R-Divider Software Reset. Writing a 1 to
PLL1_RDIV_SWRST resets the R-Divider.
PLL1_RDIV_SWRST is cleared automatically to 0.
[3]
PLL1_NDIV_SWRST
RWSC
0
PLL1 N-Divider Software Reset. Writing a 1 to
PLL1_NDIV_SWRST resets the N-Divider.
PLL1_NDIV_SWRST is cleared automatically to 0.
[2]
PLL1_HOLDOVERCNT_SW
RST
0
PLL1 Holdover Counter Software Reset. Writing a 1 to
PLL1_HOLDOVERCNT_SWRST activates the reset.
PLL1_HOLDOVERCNT_SWRST is cleared automatically to
0.
[1]
PLL1_HOLDOVER_LOCKDE
T_SWRST
RWSC
0
PLL1 Holdover Lock Detect Software Reset. Writing a 1 to
PLL1_HOLDOVER_LOCKDET_SWRST activates the reset.
PLL1_HOLDOVER_LOCKDET_SWRST is cleared
automatically to 0.
[0]
PLL1_SWRST
RWSC
0
PLL1 Software Reset. Writing a 1 to PLL1_SWRST resets
PLL1 PLL1_SWRST is cleared automatically to 0.
RWSC
9.6.2.79 PLL1WNDWSIZE
The PLL1WNDWSIZE Register sets the PLL1 Window Comparator Size. Return to Register Map.
Table 103. Register – 0x58
BIT NO.
FIELD
TYPE
RESET
DESCRIPTION
[7:0]
PLL1_LD_WNDW_SIZE[7:0]
RW
0x3F
PLL1 Window Comparator Size.
9.6.2.80 PLL1STRCELL
The PLL1STRCELL Register provides control of the Storage Cell settings. Return to Register Map.
Table 104. Register – 0x59
84
BIT NO.
FIELD
TYPE
RESET
DESCRIPTION
[7:4]
PLL1_INTG_FL[3:0]
RW
0x1
PLL1 Integral Gain setting during Fast Lock.
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Table 104. Register – 0x59 (continued)
BIT NO.
FIELD
TYPE
RESET
DESCRIPTION
[3:0]
PLL1_INTG[3:0]
RW
0x1
PLL1 Integral Gain setting.
9.6.2.81 PLL1CPSETTING
The PLL1CPSETTING Register provides control of the Chargepump Current/Bandwidth Setting. Return to
Register Map.
Table 105. Register – 0x5A
BIT NO.
FIELD
TYPE
RESET
DESCRIPTION
[7]
RSRVD
RW
0x0
Reserved.
[6:0]
PLL1_PROP[6:0]
RW
0x8
Prop-CP Current/Bandwidth Setting.
9.6.2.82 PLL1CPSETTING_FL
The PLL1CPSETTING_FL Register provides control of the Chargepump Current/Bandwidth Setting during Fast
Lock. Return to Register Map.
Table 106. Register – 0x5B
BIT NO.
FIELD
TYPE
RESET
[7]
RSRVD
RW
0x1
DESCRIPTION
Reserved
[6:0]
PLL1_PROP_FL[6:0]
RW
0x7F
Prop-CP Current/Bandwidth Setting for Fast Lock.
9.6.2.83 PLL1_HOLDOVER_CTRL1
The PLL1_HOLDOVER_CTRL1 Register provides control of the PLL1 holdover operation. Return to Register
Map.
Table 107. Register – 0x5C
BIT NO.
FIELD
TYPE
RESET
DESCRIPTION
[7]
PLL1_HOLDOVER_EN
RW
1
Enable PLL1 Holdover function. When
PLL1_HOLDOVER_EN is 1 the holdover circuit is enabled.
When PLL1_HOLDOVER_EN is 0 the holdover circuit is
disabled.
[6]
PLL1_STARTUP_HOLDOVE
R_EN
RW
1
When PLL1_HOLDOVER_FORCE is 1, PLL1 enters
holdover mode immediately on start-up.
[5]
PLL1_HOLDOVER_FORCE
RW
0
PLL1 Force Holdover Operation. When
PLL1_HOLDOVER_FORCE is 1 PLL1 enters holdover mode
regardless of other conditions.
[4]
PLL1_HOLDOVER_RAIL_M
ODE
RW
0
PLL1 Rail Detection Level Relative or absolute.
PLL1_HOLDOVER_RAIL_MODE– Level Mode
0– Absolute-Level
1– Relative to Level set at Lock
[3]
PLL1_HOLDOVER_MAX_CN
T_EN
RW
1
PLL1 Holdover Max Counter enable. Wait for
PLL1_HOLDOVER_MAXCNT cycles before starting AutoCLKin-Switch procedure.
[2]
PLL1_HOLDOVER_LOS_MA
SK
RW
0
PLL1 Holdover LOS Mask. When
PLL1_HOLDOVER_LOS_MASK is 1 then Loss of Source
has no effect in the activation of holdover.
[1]
PLL1_HOLDOVER_LCKDET
_MASK
RW
1
PLL1 Holdover Lock Detect Mask. When
PLL1_HOLDOVER_LCKDET_MASK is 1 then Lock Detect
has no effect in the activation of holdover.
[0]
PLL1_HOLDOVER_RAILDE
T_EN
RW
0
PLL1 Holdover Rail Detection Enable. When
PLL1_HOLDOVER_RAILDET_EN is 1 the rail detection
circuit is enabled. When PLL1_HOLDOVER_RAILDET EN is
0 the rail detection circuit is disabled.
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9.6.2.84 PLL1_HOLDOVER_MAXCNT_BY3
The PLL1_HOLDOVER_MAXCNT field is set by PLL1_HOLDOVER_MAXCNT_BY3,BY2,BY1 and BY0. Return
to Register Map.
Table 108. Register – 0x5D
BIT NO.
FIELD
TYPE
RESET
DESCRIPTION
[7:0]
PLL1_HOLDOVER_MAX_CN
T[31:24]
RW
0x0
PLL1 Maximum Holdover Count. When the value specified
by PLL1_HOLDOVER_MAX_CNT is reached then the
device attempts to switch to any available reference clocks.
9.6.2.85 PLL1_HOLDOVER_MAXCNT_BY2
The PLL1_HOLDOVER_MAXCNT1 Register sets bits [23:16]. Return to Register Map.
Table 109. Register – 0x5E
BIT NO.
FIELD
TYPE
RESET
DESCRIPTION
[7:0]
PLL1_HOLDOVER_MAX_CN
T[23:16]
RW
0x1
PLL1 Maximum Holdover Count.
9.6.2.86 PLL1_HOLDOVER_MAXCNT_BY1
The PLL1_HOLDOVER_MAXCNT0 Register sets bits [15:8]. Return to Register Map.
Table 110. Register – 0x5F
BIT NO.
FIELD
TYPE
RESET
DESCRIPTION
[7:0]
PLL1_HOLDOVER_MAX_CN
T[15:8]
RW
0x84
PLL1 Maximum Holdover Count.
9.6.2.87 PLL1_HOLDOVER_MAXCNT_BY0
The PLL1_HOLDOVER_MAXCNT0 Register sets bits [7:0]. Return to Register Map.
Table 111. Register – 0x60
BIT NO.
FIELD
TYPE
RESET
DESCRIPTION
[7:0]
PLL1_HOLDOVER_MAX_CN
T[7:0]
RW
0x80
PLL1 Maximum Holdover Count.
9.6.2.88 PLL1_NDIV_BY1
The PLL1_NDIV value is set by Register's PLL1_NDIV_BY1 and PLL1_NDIV_BY0. Return to Register Map.
Table 112. Register – 0x61
BIT NO.
[7:0]
FIELD
PLL1_NDIV[15:8]
TYPE
RW
RESET
DESCRIPTION
0x0
PLL1 N-Feedback Divider Value.
PLL1_NDIV– N-Feedback Divider
0– Reserved
1– 1
..– ..
65535– 65535
9.6.2.89 PLL1_NDIV_BY0
The PLL1_NDIV_BY0 Register sets bits [7:0]. Return to Register Map.
Table 113. Register – 0x62
86
BIT NO.
FIELD
TYPE
RESET
DESCRIPTION
[7:0]
PLL1_NDIV[7:0]
RW
0x78
PLL1 N-Feedback Divider Value.
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9.6.2.90 PLL1_LOCKDET_CYC_CNT_BY2
The
PLL1_LOCKDET_CYC_CNT
is
set
by
registers
PLL1_LOCKDET_CYC_CNT_BY2,
PLL1_LOCKDET_CYC_CNT_BY1 and PLL1_LOCKDET_CYC_CNT_BY0. Return to Register Map.
Table 114. Register – 0x63
BIT NO.
FIELD
TYPE
RESET
DESCRIPTION
[7:0]
PLL1_LOCKDET_CYC_CNT[
23:16]
RW
0x0
PLL1 Lock Detect Cycle Counter.
9.6.2.91 PLL1_LOCKDET_CYC_CNT_BY1
The PLL1_LOCKDET_CYC_CNT_BY1 Register sets bits [15:8]. Return to Register Map.
Table 115. Register – 0x64
BIT NO.
FIELD
TYPE
RESET
DESCRIPTION
[7:0]
PLL1_LOCKDET_CYC_CNT[
15:8]
RW
0x40
PLL1 Lock Detect Cycle Counter.
9.6.2.92 PLL1_LOCKDET_CYC_CNT_BY0
The PLL1_LOCKDET_CYC_CNT_BY0 Register sets bits [7:0]. Return to Register Map.
Table 116. Register – 0x65
BIT NO.
FIELD
TYPE
RESET
DESCRIPTION
[7:0]
PLL1_LOCKDET_CYC_CNT[
7:0]
RW
0x0
PLL1 Lock Detect Cycle Counter.
9.6.2.93 PLL1_STRG_BY4
Readback of the PLL1 Storage cell's is provided by PLL1_STRG_BY4/BY3/BY2/BY1/BY0 Registers. Return to
Register Map.
Table 117. Register – 0x66
BIT NO.
FIELD
TYPE
RESET
DESCRIPTION
[7:0]
PLL1_STORAGE_CELL[39:3
2]
R
0x0
PLL1 Storage Cell Value.
9.6.2.94 PLL1_STRG_BY3
The PLL1_STRG_BY3 reads bits[31:24]. Return to Register Map.
Table 118. Register – 0x67
BIT NO.
FIELD
TYPE
RESET
DESCRIPTION
[7:0]
PLL1_STORAGE_CELL[31:2
4]
R
0x0
PLL1 Storage Cell Value.
9.6.2.95 PLL1_STRG_BY2
The PLL1_STRG_BY3 reads bits [23:16]. Return to Register Map.
Table 119. Register – 0x68
BIT NO.
FIELD
TYPE
RESET
DESCRIPTION
[7:0]
PLL1_STORAGE_CELL[23:1
6]
R
0x0
PLL1 Storage Cell Value.
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9.6.2.96 PLL1_STRG_BY1
The PLL1_STRG_BY3 reads bits [15:8]. Return to Register Map.
Table 120. Register – 0x69
BIT NO.
FIELD
TYPE
RESET
DESCRIPTION
[7:0]
PLL1_STORAGE_CELL[15:8
]
R
0x0
PLL1 Storage Cell Value.
9.6.2.97 PLL1_STRG_BY0
The PLL1_STRG_BY3 reads bits [7:0]. Return to Register Map.
Table 121. Register – 0x6A
BIT NO.
FIELD
TYPE
RESET
DESCRIPTION
[7:0]
PLL1_STORAGE_CELL[7:0]
R
0x0
PLL1 Storage Cell Value.
9.6.2.98 PLL1RCCLKDIV
The PLL1RCCLKDIV Register controls the PLL1 RC Clock Divider. Return to Register Map.
Table 122. Register – 0x6B
BIT NO.
FIELD
TYPE
RESET
DESCRIPTION
[7:5]
RSRVD
-
-
Reserved.
[4]
PLL1_RC_CLK_EN
RW
1
PLL1 RC Clock Enable.
[3]
RSRVD
-
-
Reserved.
0x7
PLL1 RC Clk Divider value. Sets the divider value for the
PLL1 RC clock that is derived from the PLL2 VCO Clock.
PLL1_RC_CLK_DIV– Divider Value
0– 1
1– 2
..– ..
7– 8
[2:0]
PLL1_RC_CLK_DIV[2:0]
RW
9.6.2.99 PLL2_CTRL0
The PLL2_CTRL0 Register provides control of PLL2 features. Return to Register Map.
Table 123. Register – 0x6C
BIT NO.
FIELD
TYPE
RESET
DESCRIPTION
[7:5]
RSRVD
-
-
Reserved.
[4]
PLL2_VCO_PRESC_LOW_P
OWER
RW
0
PLL2 Prescaler Low Power Mode.
[3]
PLL2_BYP_OSC
RW
0
Clock Source for Oscout Buffer.
PLL2_BYP_OSC– Oscout Clock Source
0– PLL2 Output
1– PLL2 Input
0
Clock Source for Top Outputs.
PLL2_BYP_TOP– Top Outputs Clock Source
0– PLL2 Output
1– PLL2 Input
0
Clock Source for Bottom Outputs.
PLL2_BYP_BOT– Bottom Outputs Clock Source
0– PLL2 Output
1– PLL2 Input
[2]
[1]
88
PLL2_BYP_TOP
PLL2_BYP_BOT
RW
RW
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Table 123. Register – 0x6C (continued)
BIT NO.
[0]
FIELD
PLL2_GLOBAL_BYP
TYPE
RW
RESET
DESCRIPTION
0
PLL2 Global Bypass Enable.
PLL2_GLOBAL_BYP– PLL2 Input Clock Source
0– OSCin
1– CLKIN0..1
9.6.2.100 PLL2_CTRL1
The PLL2_CTRL1 Register provides control of PLL2 features. Return to Register Map.
Table 124. Register – 0x6D
BIT NO.
FIELD
TYPE
RESET
DESCRIPTION
[7]
PLL2_EN_PULSE_GEN
RW
0
Enable Pulse Generator in PLL2 R input block.
[6]
PLL2_RDIV_BYP
RW
0
PLL2 R-Divider Bypass. When PLL2_RDIV_BYP is 1 the RDivider is by-passed.
[5]
PLL2_DBL_EN_INV
RW
0
PLL2 Doubler Enable Invert. When PLL2_DBL_EN_INV is 1
the output of the PLL2 Doubler is inverted.
[4]
PLL2_PD_VARBIAS
RW
0
VCO Varactor Biasing PD.
[3]
PLL2_SMART_TRIM
RW
1
PLL2 Smart trim enable. If PLL2_SMART_TRIM is set to 1
then the initial calibration threshold is set by
PLL2_AC_STRT_THRESHOLD and the final threshold is set
by PLL2_AC_THRESHOLD. If PLL2_SMART_TRIM is 0 the
threshold is set by PLL2_AC_THRESHOLD at all times.
[2]
PLL2_LCKDET_LOS_MASK
RW
1
PLL2 Lock Detect LOS Mask. When
PLL2_LCKDET_LOS_MASK is 1 then Loss of Source has no
effect on the PLL2 Lock Detect circuit.
[1]
PLL2_RDIV_DBL_EN
RW
0
PLL2 R-Divider Doubler Enable.
[0]
PLL2_PD_LD
RW
1
PLL2 Window Comparator Powerdown.
9.6.2.101 PLL2_CTRL2
The PLL2_CTRL2 Register provides control of PLL2 features. Return to Register Map.
Table 125. Register – 0x6E
BIT NO.
FIELD
TYPE
RESET
DESCRIPTION
[7]
PLL2_BYP_SYNC_TOP
RW
0
RESERVED
[6]
PLL2_BYP_SYNC_BOTTOM
RW
0
RESERVED
[5]
PLL2_EN_BYP_BUF
RW
0
PLL2 Enable Bypass Clock Buffer.
[4]
PLL2_EN_BUF_SYNC_TOP
RW
1
PLL2 Enable Clock Buffer for Re-clocked SYNC signal to
TOP Output-CHs.
[3]
PLL2_EN_BUF_SYNC_BOT
TOM
RW
1
PLL2 Enable Clock Buffer for Re-clocked SYNC signal to
Bottom Output-CHs.
[2]
PLL2_EN_BUF_OSCOUT
RW
0
PLL2 Enable Clock Buffer for OSCOut.
[1]
PLL2_EN_BUF_CLK_TOP
RW
1
PLL2 Enable Clock Buffer for Top Output-CHs.
[0]
PLL2_EN_BUF_CLK_BOTT
OM
RW
1
PLL2 Enable Clock Buffer for Bottom Output-CHs.
9.6.2.102 PLL2_SWRST
The PLL2_SWRST Register allows activation of the following PLL2 related software resets. Return to Register
Map.
Table 126. Register – 0x6F
BIT NO.
FIELD
TYPE
RESET
DESCRIPTION
[7:3]
RSRVD
-
-
Reserved.
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Table 126. Register – 0x6F (continued)
BIT NO.
FIELD
TYPE
RESET
DESCRIPTION
[2]
PLL2_RDIV_SWRST
RWSC
0
PLL2 R-Divider Software Reset. Writing a 1 to
PLL2_RDIV_SWRST resets the R-Divider.
PLL2_RDIV_SWRST is cleared automatically to 0.
[1]
PLL2_NDIV_SWRST
RWSC
0
PLL2 N-Divider Software Reset. Writing a 1 to
PLL2_NDIV_SWRST resets the N-Divider.
PLL2_NDIV_SWRST is cleared automatically to 0.
[0]
PLL2_SWRST
RWSC
0
PLL2 Software Reset. Writing a 1 to PLL2_SWRST resets
PLL2. PLL2_SWRST is cleared automatically to 0.
9.6.2.103 PLL2_LF_C4R4
The PLL2_LF_C4R4 Register sets the values for C4 and R4. Return to Register Map.
Table 127. Register – 0x70
BIT NO.
FIELD
TYPE
RESET
DESCRIPTION
[7:4]
PLL2_C4_LF_SEL[3:0]
RW
0x0
PLL2 Loop Filter C4 Value.
[3:0]
PLL2_R4_LF_SEL[3:0]
RW
0x0
PLL2 Loop Filter R4 Value.
9.6.2.104 PLL2_LF_C3R3
The PLL2_LF_C3R3 Register sets the values for C3 and R3. Return to Register Map.
Table 128. Register – 0x71
BIT NO.
FIELD
TYPE
RESET
DESCRIPTION
[7:4]
PLL2_C3_LF_SEL[3:0]
RW
0x0
PLL2 Loop Filter C3 Value.
[3:0]
PLL2_R3_LF_SEL[3:0]
RW
0x0
PLL2 Loop Filter R3 Value.
9.6.2.105 PLL2_CP_SETTING
The PLL2_CP_SETTING Register provides control of the PLL2 Chargepump. Return to Register Map.
Table 129. Register – 0x72
BIT NO.
FIELD
TYPE
RESET
DESCRIPTION
[7:6]
RSRVD
RW
0x0
Reserved.
[5:0]
PLL2_PROP[5:0]
RW
0x3
PLL2 Charge pump Setting.
9.6.2.106 PLL2_NDIV_BY1
The PLL2 N-Divider Value is set by Register's PLL2_NDIV_BY1 and PLL2_NDIV_BY0. Return to Register Map.
Table 130. Register – 0x73
BIT NO.
FIELD
TYPE
RESET
DESCRIPTION
[7:0]
PLL2_NDIV[15:8]
RW
0x0
PLL2 N-Divider Value.
9.6.2.107 PLL2_NDIV_BY0
The PLL2_NDIV_BY0 Register sets bits [7:0]. Return to Register Map.
Table 131. Register – 0x74
90
BIT NO.
FIELD
TYPE
RESET
DESCRIPTION
[7:0]
PLL2_NDIV[7:0]
RW
0x20
PLL2 N-Divider Value.
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9.6.2.108 PLL2_RDIV_BY1
RESERVED. Return to Register Map.
Table 132. Register – 0x75
BIT NO.
[7:0]
FIELD
PLL2_RDIV[15:8]
TYPE
RW
RESET
DESCRIPTION
0x0
PLL2 R-Divider Value. PLL2 R-Divider configuration limited
to bits [5..0].
9.6.2.109 PLL2_RDIV_BY0
The PLL2_RDIV Register sets the PLL2 R-Divider bits [5:0]. Return to Register Map.
Table 133. Register – 0x76
BIT NO.
[7:0]
FIELD
PLL2_RDIV[7:0]
TYPE
RW
RESET
DESCRIPTION
0x0
PLL2 R-Divider Value. PLL2 R-Divider configuration limited
to bits [5..0].
9.6.2.110 PLL2_STRG_INIT_BY1
The PLL2_STRG_INIT_BY1 Register. Return to Register Map.
Table 134. Register – 0x77
BIT NO.
FIELD
TYPE
RESET
DESCRIPTION
[7:0]
PLL2_STRG_INITVAL[15:8]
RW
0x0
PLL2 Storage-CP Init Value.
9.6.2.111 PLL2_STRG_INIT_BY0
The PLL2_STRG_INIT_BY0 Register. Return to Register Map.
Table 135. Register – 0x78
BIT NO.
FIELD
TYPE
RESET
DESCRIPTION
[7:0]
PLL2_STRG_INITVAL[7:0]
RW
0xFF
PLL2 Storage-CP Init Value.
9.6.2.112 RAILDET_UP
The Rail Detect Upper Limit. Return to Register Map.
Table 136. Register – 0x7D
BIT NO.
FIELD
TYPE
RESET
DESCRIPTION
[7:6]
RSRVD
-
-
Reserved.
[5:0]
RAILDET_UPP[5:0]
RW
0x0
Upper Rail Detection Limit.
9.6.2.113 RAILDET_LOW
The Rail Detect Lower Limit. Return to Register Map.
Table 137. Register – 0x7E
BIT NO.
FIELD
TYPE
RESET
[7:6]
RSRVD
-
-
DESCRIPTION
Reserved.
[5:0]
RAILDET_LOW[5:0]
RW
0x0
Lower Rail Detection Limit.
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9.6.2.114 PLL2_AC_CTRL
The PLL2_AC_CTRL Register provides control of PLL2 Amplitude Calibration features. Return to Register Map.
Table 138. Register – 0x7F
BIT NO.
FIELD
TYPE
RESET
[7:6]
RSRVD
-
-
Reserved.
[5]
PLL2_AC_CAL_EN
RW
1
PLL2 Amplitude Calibration Enable.
[4]
PLL2_PD_AC
RW
1
VCO Peak detector Power down. 1=off, 0=enabled.
PLL2 IDAC Re-Calibration Setting. When the difference
between consecutive IDACSET values is greater than
PLL2_IDACSET_RECAL the amplitude calibration is
restarted.
[3:2]
DESCRIPTION
PLL2_IDACSET_RECAL[1:0]
RW
0x1
[1]
PLL2_AC_REQ
RWSC
0
PLL2 Amplitude Calibration Request.
[0]
PLL2_FAST_ACAL
RW
0
PLL2 Fast Amplitude Calibration Enable.
9.6.2.115 PLL2_CURR_STOR_CELL
The PLL2_CURR_STOR_CELL Register is described below. Return to Register Map.
Table 139. Register – 0x80
BIT NO.
FIELD
TYPE
RESET
DESCRIPTION
[7:5]
RSRVD
RW
0x0
Reserved.
[4:0]
PLL2_INTG[4:0]
RW
0x3
PLL2 Integral gain setting.
9.6.2.116 PLL2_AC_THRESHOLD
The PLL2_AC_THRESHOLD Register sets the Amplitude Calibration Threshold. Return to Register Map.
Table 140. Register – 0x81
BIT NO.
FIELD
TYPE
RESET
[7:5]
RSRVD
-
-
DESCRIPTION
Reserved.
[4:0]
PLL2_AC_THRESHOLD[4:0]
RW
0x0
PLL2 VCO Amplitude Calibration Threshold.
9.6.2.117 PLL2_AC_STRT_THRESHOLD
The PLL2_AC_THRESHOLD Register sets the Amplitude Calibration Starting Threshold. Return to Register
Map.
Table 141. Register – 0x82
BIT NO.
FIELD
TYPE
RESET
DESCRIPTION
[7:5]
RSRVD
-
-
Reserved.
[4:0]
PLL2_AC_STRT_THRESHO
LD[4:0]
RW
0x0
PLL2 VCO Amplitude Calibration Starting Threshold.
9.6.2.118 PLL2_AC_WAIT_CTRL
The PLL2_AC_WAIT_CTRL Register sets the Amplitude Calibration Wait Periods. Return to Register Map.
Table 142. Register – 0x83
BIT NO.
92
FIELD
TYPE
RESET
DESCRIPTION
[7:4]
PLL2_AC_CMP_WAIT[3:0]
RW
0x0
PLL2 VCO Amplitude Calibration Delay between IDAC Code
Changes. Delay is equal to PLL2_AC_CMP_WAIT*4*Clock
Period (Clock Period 100 ns).
[3:0]
PLL2_AC_INIT_WAIT[3:0]
RW
0x0
PLL2 VCO Amplitude Calibration Initial Comparator Delay.
Delay is equal to PLL2_AC_INIT_WAIT*4*Clock Period.
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9.6.2.119 PLL2_AC_JUMPSTEP
The PLL2_AC_JUMPSTEP Register provides control of the PLL2 Amplitude Calibration step size. Return to
Register Map.
Table 143. Register – 0x84
BIT NO.
FIELD
TYPE
RESET
[7:4]
RSRVD
-
-
Reserved.
0xF
PLL2 IDAC Code Jump Step. When PLL2_FAST_ACAL is 1
then the IDACSET step value is set by
PLL2_AC_JUMP_STEP.
[3:0]
PLL2_AC_JUMP_STEP[3:0]
RW
DESCRIPTION
9.6.2.120 PLL2_LD_WNDW_SIZE
The PLL2_LD_WNDW_SIZE Register sets the PLL2 Window Comparator Setting. Return to Register Map.
Table 144. Register – 0x85
BIT NO.
[7:0]
FIELD
PLL2_LD_WNDW_SIZE[7:0]
TYPE
RW
RESET
DESCRIPTION
0x1
PLL2 Window Comparator Size Setting. PLL2 Window
comparator size after PLL2 AC Calibration and initial lock.
Always set to 0.
0: 1 ns.
1 to 255: Reserved
9.6.2.121 PLL2_LD_WNDW_SIZE_INITIAL
The PLL2_LD_WNDW_SIZE_INITIAL Register sets the PLL2 Window Comparator Initial Setting. Return to
Register Map.
Table 145. Register – 0x86
BIT NO.
FIELD
[7:0]
PLL2_LD_WNDW_SIZE_INI
TIAL[7:0]
TYPE
RW
RESET
DESCRIPTION
0x7F
PLL2 Window Comparator Size Initial Setting. Window
comparator size prior to PLL2 AC Calibration and initial lock.
Always set to 0.
0: 1 ns.
1 to 255: Reserved
9.6.2.122 PLL2_LOCKDET_CYC_CNT_BY2
The
PLL2
Lock
Detection
Cycle
Count
is
set
by
PLL2_LOCKDET_CYC_CNT_BY2,
PLL2_LOCKDET_CYC_CNT_BY1 and PLL2_LOCKDET_CYC_CNT_BY0. Return to Register Map.
Table 146. Register – 0x87
BIT NO.
FIELD
TYPE
RESET
DESCRIPTION
[7:0]
PLL2_LOCKDET_CYC_CNT[
23:16]
RW
0x0
PLL2 Lock detection cycle counter.
9.6.2.123 PLL2_LOCKDET_CYC_CNT_BY1
The PLL2_LOCKDET_CYC_CNT_BY1 Register sets bits [15:8]. Return to Register Map.
Table 147. Register – 0x88
BIT NO.
FIELD
TYPE
RESET
DESCRIPTION
[7:0]
PLL2_LOCKDET_CYC_CNT[
15:8]
RW
0x40
PLL2 Lock detection cycle counter.
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9.6.2.124 PLL2_LOCKDET_CYC_CNT_BY0
The PLL2_LOCKDET_CYC_CNT_BY0 Register sets bits [7:0]. Return to Register Map.
Table 148. Register – 0x89
BIT NO.
FIELD
TYPE
RESET
DESCRIPTION
[7:0]
PLL2_LOCKDET_CYC_CNT[
7:0]
RW
0x0
PLL2 Lock detection cycle counter.
9.6.2.125 PLL2_LOCKDET_CYC_CNT_INITIAL_BY2
The PLL2 Lock Detection Initial Cycle Count is set by PLL2_LOCKDET_CYC_CNT_INITIAL_BY2,
PLL2_LOCKDET_CYC_CNT_INITIAL_BY1 and PLL2_LOCKDET_CYC_CNT_INITIAL_BY0. This counter is
used for initial PLL2 Lock before final Amplitude Calibration has finished. Return to Register Map.
Table 149. Register – 0x8A
BIT NO.
FIELD
TYPE
RESET
DESCRIPTION
[7:0]
PLL2_LOCKDET_CYC_CNT
_INITIAL[23:16]
RW
0x0
PLL2 Lock detection initial cycle counter.
9.6.2.126 PLL2_LOCKDET_CYC_CNT_INITIAL_BY1
The PLL2_LOCKDET_CYC_CNT_INITIAL_BY1 Register sets bits [15:8]. Return to Register Map.
Table 150. Register – 0x8B
BIT NO.
FIELD
TYPE
RESET
DESCRIPTION
[7:0]
PLL2_LOCKDET_CYC_CNT
_INITIAL[15:8]
RW
0x40
PLL2 Lock detection initial cycle counter.
9.6.2.127 PLL2_LOCKDET_CYC_CNT_INITIAL_BY0
The PLL2_LOCKDET_CYC_CNT_INITIAL_BY0 Register sets bits [7:0]. Return to Register Map.
Table 151. Register – 0x8C
BIT NO.
FIELD
TYPE
RESET
DESCRIPTION
[7:0]
PLL2_LOCKDET_CYC_CNT
_INITIAL[7:0]
RW
0x0
PLL2 Lock detection initial cycle counter.
9.6.2.128 IOCTRL_SPI0
The IOCTRL_SPI0 Register provides control of the SDIO Input/Output Driver. Return to Register Map.
Table 152. Register – 0x8D
94
BIT NO.
FIELD
TYPE
RESET
DESCRIPTION
[7]
SPI_EN_THREE_WIRE_IF
RW
0
SPI 3-Wire Selection. 1=3-Wire, 0=4-Wire. When configured
for 4-wire operation the SDO output is connected to the
STATUS1 output pad.
[6:5]
RSRVD
-
-
Reserved.
[4]
SPI_SDIO_OUTPUT_MUTE
RW
0
SDIO Output Mute. When SPI_SDIO_OUTPUT_MUTE is 1
the SDIO output driver is forced to 0 if it is enabled.
[3]
SPI_SDIO_OUTPUT_INV
RW
0
SDIO Output Invert. When SPI_SDIO_OUTPUT_INV is 1 the
SDIO output is inverted.
[2]
SPI_SDIO_OUTPUT_WEAK
_DRIVE
RW
0
SDIO Output Weak Drive Strength. When
SPI_SDIO_OUTPUT_WEAK DRIVE is 1 the SDIO output is
configured with a low slew rate.
[1]
SPI_SDIO_EN_PULLUP
RW
0
SPI SDIO Pullup Enable. When SPI_SDIO_PULLUP_EN is 1
a pullup resistor is activated.
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Table 152. Register – 0x8D (continued)
BIT NO.
[0]
FIELD
SPI_SDIO_EN_PULLDOWN
TYPE
RW
RESET
DESCRIPTION
0
SPI SDIO Pulldown Enable. When
SPI_SDIO_PULLDWN_EN is 1 a pulldown resistor is
activated.
9.6.2.129 IOCTRL_SPI1
The IOCTRL_SPI1 Register provides control of the SCL and SCS input drivers. Return to Register Map.
Table 153. Register – 0x8E
BIT NO.
FIELD
TYPE
RESET
DESCRIPTION
[7:4]
RSRVD
-
-
Reserved.
[3]
SPI_SCL_EN_PULLUP
RW
0
SPI SCL Pullup Enable. When SPI_SCL_PULLUP_EN is 1 a
pullup resistor is activated.
[2]
SPI_SCL_EN_PULLDOWN
RW
0
SPI SCL Pulldown Enable. When SPI_SCL_PULLDWN_EN
is 1 a pulldown resistor is activated.
[1]
SPI_SCS_EN_PULLUP
RW
0
SPI SCS Pullup Enable. When SPI_SCS_PULLUP_EN is 1
a pullup resistor is activated.
[0]
SPI_SCS_EN_PULLDOWN
RW
0
SPI SCS Pulldown Enable. When
SPI_SCS_PULLDWNEN_EN is 1 a pulldown resistor is
activated.
9.6.2.130 IOTEST_SDIO
The IOTEST_SDIO Register provides control of the SDIO driver and test features. Return to Register Map.
Table 154. Register – 0x8F
BIT NO.
FIELD
TYPE
RESET
[7]
RSRVD
RW
0
Reserved.
1
SPI SDIO Output Driver High Impedance. When
SPI_SDIO_OUTPUT_HIZ is set to 1 the SDIO output driver
stage is disabled. Only when SPI_SDIO_IOTESTEN is 1.
[6]
SPI_SDIO_OUTPUT_HIZ
RW
DESCRIPTION
[5]
SPI_SDIO_ENB_INSTAGE
RW
0
SPI SDIO Input Stage Enable BAR. When
SPI_SDIO_INPUT_ENB is 0 the SDIO Input stage is
enabled. Whenever SPI_SDIO_INPUT_ENB is set to 1 the
SPI interface is rendered inoperable and can only be
recovered by a hardware reset.
[4]
SPI_SDIO_EN_ML_INSTAG
E
RW
0
SPI SDIO Input Stage Enable Multi-level. When
SPI_SDIO_INPUT_ENML is 1 the input stage is configured
for multi-level mode.
[3]
RSRVD
RW
0
Reserved.
[2]
SPI_SDIO_OUTPUT_DATA
RW
0
SPI SDIO Output Data. Controls the SDIO output data value
when SPI_SDIO_IOTESTEN is set to 1.
[1]
SPI_SDIO_INPUT_Y12
R
0
SPI SDIO Input Y12 Value. Indicates the logic level present
on the SDIO Y12 pin. This feature is currently not supported.
[0]
SPI_SDIO_INPUT_M12
R
0
SPI SDIO Input M12 Value. Indicates the logic level present
on the SDIO M12 pin. This feature is currently not supported.
9.6.2.131 IOTEST_SCL
The IOTEST_SCL Register provides control of the SCL driver and test features. Return to Register Map.
Table 155. Register – 0x90
BIT NO.
FIELD
TYPE
RESET
DESCRIPTION
[7:6]
RSRVD
-
-
Reserved.
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Table 155. Register – 0x90 (continued)
BIT NO.
FIELD
TYPE
RESET
DESCRIPTION
[5]
SPI_SCL_ENB_INSTAGE
RW
0
SPI SCL Input Stage Enable BAR. When
SPI_SCL_INPUT_ENB is 0 the SCL Input stage is enabled.
Whenever SPI_SCL_INPUT_ENB is set to 1 the SPI
interface is rendered inoperable and can only be recovered
by a hardware reset.
[4]
SPI_SCL_EN_ML_INSTAGE
RW
0
SPI SCL Input Stage Enable Multi-level. When
SPI_SCL_INPUT_ENML is 1 the input stage is configured for
multi-level mode.
[3:2]
RSRVD
-
-
Reserved.
[1]
SPI_SCL_INPUT_Y12
R
0
SPI SCL Input Y12 Value. Indicates the logic level present
on the SCL Y12 pin. This feature is currently not supported.
[0]
SPI_SCL_INPUT_M12
R
0
SPI SCL Input M12 Value. Indicates the logic level present
on the SCL M12 pin. This feature is currently not supported.
9.6.2.132 IOTEST_SCS
The IOTEST_SCS Register provides control of the SCS driver and test features. Return to Register Map.
Table 156. Register – 0x91
BIT NO.
FIELD
TYPE
RESET
[7:6]
RSRVD
-
-
DESCRIPTION
Reserved.
[5]
SPI_SCS_ENB_INSTAGE
RW
0
SPI SCS Input Stage Enable BAR. When
SPI_SCS_INPUT_ENB is 0 the SCS Input stage is enabled.
Whenever SPI_SCS_INPUT_ENB is set to 1 the SPI
interface is rendered inoperable and can only be recovered
by a hardware reset.
[4]
SPI_SCS_EN_ML_INSTAGE
RW
0
SPI SCS Input Stage Enable Multi-level. When
SPI_SCS_INPUT_ENML is 1 the input stage is configured
for multi-level mode.
[3:2]
RSRVD
-
-
Reserved.
[1]
SPI_SCS_INPUT_Y12
R
0
SPI SCS Input Y12 Value. Indicates the logic level present
on the SCS Y12 pin. This feature is currently not supported.
[0]
SPI_SCS_INPUT_M12
R
0
SPI SCS Input M12 Value. Indicates the logic level present
on the SCS M12 pin. This feature is currently not supported.
9.6.2.133 IOCTRL_STAT0
The IOCTRL_STAT0 Register provides control of the STATUS0 Input/Output Driver. Return to Register Map.
Table 157. Register – 0x92
BIT NO.
96
FIELD
TYPE
RESET
DESCRIPTION
[7:5]
STATUS0_MUX_SEL[2:0]
RW
0x4
STAT0 Output Mux Select. When selecting PLL1 or 2
REF/FB clock, also set corresponding
PLLx_TSTMODE_REF_FB_EN bit.
STATUS0_MUX_SEL - STATUS0 Output
000 - PLL1 REF CLK
001 - PLL2 REF CLK
010 - PLL1 FB (SYS) CLK
011 - PLL2 FB (SYS) CLK
1XX - Signal selected by STATUS0_INT_MUX (digital)
[4]
STATUS0_OUTPUT_MUTE
RW
0
STATUS0 Output Mute. When STATUS0_OUTPUT_MUTE
is 1 the STATUS0 output driver is forced to 0 if it is enabled.
[3]
STATUS0_OUTPUT_INV
RW
0
STATUS0 Output Invert. When STATUS0_OUTPUT_INV is
1 the STATUS0 output is inverted.
[2]
STATUS0_OUTPUT_WEAK_
DRIVE
RW
0
STATUS0 Output Weak drivestrength. When
STATUS0_OUTPUT_WEAK DRIVE is 1 the STATUS0
output is configured with a lower slew rate.
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Table 157. Register – 0x92 (continued)
BIT NO.
FIELD
TYPE
RESET
DESCRIPTION
[1]
STATUS0_EN_PULLUP
RW
0
STATUS0 Pullup Enable. When STATUS0_PULLUPEN_EN
is 1 a pullup resistor is activated.
[0]
STATUS0_EN_PULLDOWN
RW
0
STATUS0 Pulldown Enable. When
STATUS0_PULLDWN_EN is 1 a pulldown resistor is
activated.
9.6.2.134 IOCTRL_STAT1
The IOCTRL_STAT1 Register provides control of the STATUS1 Input/Output Driver. Return to Register Map.
Table 158. Register – 0x93
BIT NO.
FIELD
TYPE
RESET
DESCRIPTION
[7:5]
STATUS1_MUX_SEL[2:0]
RW
0x4
STAT1 Output Mux Select. When selecting PLL1 or 2
REF/FB clock, also set corresponding
PLLx_TSTMODE_REF_FB_EN bit.
STATUS1_MUX_SEL - STATUS1 Output
000 - PLL1 REF CLK
001 - PLL2 REF CLK
010 - PLL1 FB (SYS) CLK
011 - PLL2 FB (SYS) CLK
1XX - Signal selected by STATUS1_INT_MUX (digital)
[4]
STATUS1_OUTPUT_MUTE
RW
0
STATUS1 Output Mute. When STATUS1_OUTPUT_MUTE
is 1 the STATUS1 output driver is forced to 0 if it is enabled.
[3]
STATUS1_OUTPUT_INV
RW
0
STATUS1 Output Invert. When STATUS1_OUTPUT_INV is
1 the STATUS1 output is inverted.
[2]
STATUS1_OUTPUT_WEAK_
DRIVE
RW
0
STATUS1 Output weak drive. When
STATUS1_OUTPUT_WEAK_DRIVE is 1 the STATUS1
output is configured with a lower slew rate.
[1]
STATUS1_EN_PULLUP
RW
0
STATUS1 Pullup Enable. When STATUS1_PULLUP_EN is
1 a pullup resistor is activated.
[0]
STATUS1_EN_PULLDOWN
RW
0
STATUS1 Pulldown Enable. When
STATUS1_PULLDWN_EN is 1 a pulldown resistor is
activated.
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9.6.2.135 STAT1MUX
The STAT1MUX Register controls the status signal that is routed to the STATUS0 output. Return to Register
Map.
Table 159. Register – 0x94
BIT NO.
[7:0]
FIELD
STATUS1_INT_MUX[7:0]
TYPE
RW
RESET
DESCRIPTION
0x4
STAT1 Integrated Mux Select.
STAT1_INT_MUX– STATUS1 Output
0– PLL1 Lock Detect and PLL2 Lock Detect
1– PLL1 Lock Detect
2– PLL2 Lock Detect
3– CLKINBLK LOS
4– SPI Output Data
5– Reserved
6– Reserved
7– Reserved
8– HOLDOVER_EN
9– Mirror of SYNC_INPUT
10– Mirror of CLKINSEL1 INPUT
11– Reserved
12– Reserved
13– PLL2 Reference Clock
14– Reserved
15– PLL1 Lock Detect and PLL2 Lock Detect and not PLL1
Holdover
16– PLL1 Lock Detect and not PLL1 Holdover
17– Logic 1
18– Logic 0
9.6.2.136 STAT0MUX
The STAT0MUX Register controls the status signal that is routed to the STATUS1 output. Return to Register
Map.
Table 160. Register – 0x95
BIT NO.
[7:0]
98
FIELD
STATUS0_INT_MUX[7:0]
TYPE
RW
RESET
DESCRIPTION
0x0
STAT0 Integrated Mux Select.
STAT0_INT_MUX– STATUS0 Output
0– PLL1 Lock Detect and PLL2 Lock Detect
1– PLL1 Lock Detect
2– PLL2 Lock Detect
3– CLKINBLK LOS
4– SPI Output Data
5– Reserved
6– Reserved
7– Reserved
8– HOLDOVER_EN
9– Mirror of SYNC_INPUT
10– Mirror of CLKINSEL1 INPUT
11– Reserved
12– Reserved
13– PLL2 Reference Clock
14– Reserved
15– PLL1 Lock Detect and PLL2 Lock Detect and not PLL1
Holdover
16– PLL1 Lock Detect and not PLL1 Holdover
17– Logic 1
18– Logic 0
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9.6.2.137 STATPLL2CLKDIV
The STATPLL2CLKDIV Register controls the PLL2 Status Output Clock Divider. Return to Register Map.
Table 161. Register – 0x96
BIT NO.
FIELD
TYPE
RESET
[7:5]
RSRVD
-
-
Reserved.
[4]
PLL2_REF_CLK_EN
RW
1
PLL2 Ref Clock Enable.
[3]
RSRVD
-
-
Reserved.
0x0
PLL2 Ref Clock Divider for Status Outputs. Sets the divider
value for the PLL2 VCO clock that can be routed to the
STAT0/1 outputs.
PLL2_REF_STATCLK_DIV– Divider Value
0– 1
1– 2
..– ..
7– 8
[2:0]
PLL2_REF_STATCLK_DIV[2
:0]
RW
DESCRIPTION
9.6.2.138 IOTEST_STAT0
The IOTEST_STAT0 Register provides control of the STATUS0 driver and test features. Return to Register Map.
Table 162. Register – 0x97
BIT NO.
FIELD
TYPE
RESET
DESCRIPTION
[7]
RSRVD
RW
0
Reserved.
[6]
STATUS0_OUTPUT_HIZ
RW
0
STATUS0 Output Driver High Impedance. When
STATUS0_OUTPUT_HIZ is set to 1 the STATUS0 output
driver stage is disabled.
[5]
STATUS0_ENB_INSTAGE
RW
1
STATUS0 Input Stage Enable BAR. When
STATUS0_INPUT_ENB is 0 the STATUS0 Input stage is
enabled. When STATUS0_INPUT_ENB is set to 1 the
STATUS0 input stage is disabled.
[4]
STATUS0_EN_ML_INSTAG
E
RW
0
STATUS0 Input Stage Enable Multi-level. When
STATUS0_INPUT_ENML is 1 the input stage is configured
for multi-level mode.
[3]
RSRVD
RW
0
Reserved.
[2]
STATUS0_OUTPUT_DATA
RW
0
STATUS0 Output Data. Set the STATUS0 output data value
when STATUS0_IOTESTEN is 1.
[1]
STATUS0_INPUT_Y12
R
0
STATUS0 Input Y12 Value. Indicates the logic level present
on the STATUS0 Y12 pin.
[0]
STATUS0_INPUT_M12
R
0
STATUS0 Input M12 Value. Indicates the logic level present
on the STATUS0 M12 pin.
9.6.2.139 IOTEST_STAT1
The IOTEST_STAT1 Register provides control of the STATUS1 driver and test features. Return to Register Map.
Table 163. Register – 0x98
BIT NO.
FIELD
TYPE
RESET
[7]
RSRVD
RW
0
Reserved.
0
STATUS1 Output Driver High Impedance. When
STATUS1_OUTPUT_HIZ is set to 1 the STATUS1 output
driver stage is disabled.
1
STATUS1 Input Stage Enable BAR. When
STATUS1_INPUT_ENB is 0 the STATUS1 Input stage is
enabled. When STATUS1_INPUT_ENB is set to 1 the
STATUS1 input stage is disabled.
[6]
[5]
STATUS1_OUTPUT_HIZ
STATUS1_ENB_INSTAGE
RW
RW
DESCRIPTION
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Table 163. Register – 0x98 (continued)
BIT NO.
FIELD
TYPE
RESET
DESCRIPTION
[4]
STATUS1_EN_ML_INSTAG
E
RW
0
STATUS1 Input Stage Enable Multi-level. When
STATUS1_INPUT_ENML is 1 the input stage is configured
for multi-level mode.
[3]
RSRVD
RW
0
Reserved.
[2]
STATUS1_OUTPUT_DATA
RW
0
STATUS1 Output Data. Set the STATUS1 output data value
when STATUS1_IOTESTEN is 1.
[1]
STATUS1_INPUT_Y12
R
0
STATUS1 Input Y12 Value. Indicates the logic level present
on the STATUS1 Y12 (high-level) pin.
[0]
STATUS1_INPUT_M12
R
0
STATUS1 Input M12 Value. Indicates the logic level present
on the STATUS1 M12 (mid-level) pin.
9.6.2.140 IOCTRL_SYNC
The IOCTRL_SYNC Register provides control of the SYNC Input. Return to Register Map.
Table 164. Register – 0x99
BIT NO.
FIELD
TYPE
RESET
DESCRIPTION
[7:5]
SYNC_MUX_SEL[2:0]
RW
0x4
SYNC Output Mux Select. When selecting PLL1 or 2
REF/FB clock, also set corresponding
PLLx_TSTMODE_REF_FB_EN bit.
SYNC_MUX_SEL - SYNC Output
000 - PLL1 REF CLK
001 - PLL2 REF CLK
010 - PLL1 FB (SYS) CLK
011 - PLL2 FB (SYS) CLK
1XX - Signal selected by SYNC_INT_MUX (digital)
[4]
SYNC_OUTPUT_MUTE
RW
0
SYNC Output Mute. When SYNC_OUTPUT_MUTE is 1 the
SYNC output driver is forced to 0 if it is enabled.
[3]
SYNC_OUTPUT_INV
RW
0
SYNC Output Invert. When SYNC_OUTPUT_INV is 1 the
SYNC output is inverted.
[2]
SYNC_OUTPUT_WEAK_DRI
VE
RW
0
SYNC Output weak drive. When
SYNC_OUTPUT_WEAK_DRIVE is 1 the SYNC output is
configured with a lower slew rate.
[1]
SYNC_EN_PULLUP
RW
0
SYNC Pullup Enable. When SYNC_PULLUPEN_EN is 1 a
pullup resistor is activated.
[0]
SYNC_EN_PULLDOWN
RW
0
SYNC Pulldown Enable. When SYNC_PULLDWN_EN is 1 a
pulldown resistor is activated.
9.6.2.141 DUMMY_REGISTER_1
Placeholder 1. Return to Register Map.
Table 165. Register – 0x9A
BIT NO.
FIELD
TYPE
RESET
DESCRIPTION
[7:1]
RSRVD
-
-
Reserved.
[0]
RSRVD
-
-
Reserved.
9.6.2.142 IOCTRL_CLKINSEL1
The IOCTRL_CLKINSEL1 Register provides control of the CLKINSEL1 Input. Return to Register Map.
Table 166. Register – 0x9B
BIT NO.
FIELD
TYPE
RESET
[7:2]
RSRVD
-
-
Reserved.
0
CLKIN_SEL1 Pullup Enable. When
CLKINSEL1_PULLUP_EN is 1 a pullup resistor is activated.
[1]
100
CLKINSEL1_EN_PULLUP
RW
DESCRIPTION
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Table 166. Register – 0x9B (continued)
BIT NO.
[0]
FIELD
CLKINSEL1_EN_PULLDOW
N
TYPE
RW
RESET
DESCRIPTION
0
CLKIN_SEL1 Pulldown Enable. When
CLKINSEL1_PULLDWN_EN is 1 a pulldown resistor is
activated.
9.6.2.143 IOTEST_CLKINSEL1
The IOTEST_CLKINSEL1 Register provides control of the CLKINSEL1 driver test features. Return to Register
Map.
Table 167. Register – 0x9C
BIT NO.
FIELD
TYPE
RESET
[7:6]
RSRVD
-
-
DESCRIPTION
Reserved.
[5]
CLKINSEL1_ENB_INSTAGE
RW
0
CLKINSEL1 Input Stage Enable BAR. When
CLKINSEL1_INPUT_ENB is 0 the CLKINSEL1 Input stage is
enabled.
[4]
CLKINSEL1_EN_ML_INSTA
GE
RW
0
CLKINSEL1 Input Stage Enable Multi-level. When
CLKINSEL1_INPUT_ENML is 1 the input stage is configured
for multi-level mode.
[3:2]
RSRVD
-
-
Reserved.
[1]
CLKINSEL1_INPUT_Y12
R
0
CLKINSEL1 Input Y12 Value. Indicates the logic level
present on the CLKINSEL1 Y12 (high-level) pin.
[0]
CLKINSEL1_INPUT_M12
R
0
CLKINSEL1 Input M12 Value. Indicates the logic level
present on the CLKINSEL1 M12 (mid-level) pin.
9.6.2.144 PLL1_TSTMODE
The PLL1_TSTMODE Register supports PLL1 Test by enabling output of PLL1 phase detector inputs.Back to
Register Map.
Table 168. Register - 0xAC
BIT NO.
FIELD
TYPE
RESET
DESCRIPTION
[7]
PLL1_TSTMODE_REF_FB_
EN
RW
0
Set this bit when STATUS0_MUX_SEL,
STATUS1_MUX_SEL, or SYNC_MUX_SEL selects a PLL1
REF clock or FB (SYS) clock output.
0: PLL1 REF or PLL1 FB (SYS) clock not selected by any
mux
1: PLL1 REF or PLL1 FB (SYS) clock selected by at least
one mux
[6:0]
RSRVD
RW
0
Reserved.
9.6.2.145 PLL2_CTRL
The PLL2_CTRL Register supports other PLL2 features. Back to Register Map.
Table 169. Register - 0xAD
BIT NO.
FIELD
TYPE
RESET
[7:6]
RSRVD
-
-
DESCRIPTION
Reserved.
[5:4]
RESET_PLL2_DLD
RW
0
Before using PLL2 DLD signal, set this field to 0x3, wait 20
ms, set to 0x0. Refer to PLL2 DLD flow chart in Figure 41.
0x0: Clear reset state
0x1: Reserved
0x2: Reserved
0x3: Reset set
[3]
RSRVD
-
-
Reserved.
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Table 169. Register - 0xAD (continued)
BIT NO.
[2]
[1:0]
FIELD
PLL2_TSTMODE_REF_FB_
EN
PD_VCO_LDO
TYPE
RW
RW
RESET
DESCRIPTION
0
Set this bit when STATUS0_MUX_SEL,
STATUS1_MUX_SEL, or SYNC_MUX_SEL selects a PLL1
REF clock or FB (SYS) clock output.
0: PLL1 REF or PLL1 FB (SYS) clock not selected by any
mux
1: PLL1 REF or PLL1 FB (SYS) clock selected by at least
one mux
0
Set for modes not using PLL2 VCO.
0x0: VCO LDO active
0x1: Reserved
0x2: Reserved
0x3: VCO LDO disabled
9.6.2.146 STATUS
The STATUS Register provides access to the following status signals. Return to Register Map.
Table 170. Register – 0xBE
BIT NO.
FIELD
TYPE
RESET
DESCRIPTION
[7:6]
RSRVD
-
-
Reserved.
[5]
LOS
R
0
Loss of Source
[4]
HOLDOVER_DLD
R
0
Holdover – Digital Lock Detect
[3]
HOLDOVER_LOL
R
0
Holdover – Loss of Lock
[2]
HOLDOVER_LOS
R
0
Holdover – Loss of Source
[1]
PLL2_LCK_DET
R
0
PLL2 Lock Detect
[0]
PLL1_LCK_DET
R
0
PLL1 Lock Detect
9.6.2.147 PLL2_DLD_EN
The PLL2_DLD_EN Register supports PLL2 DLD EN Feature Back to Register Map.
Table 171. Register – 0xF6
BIT NO.
FIELD
TYPE
RESET
DESCRIPTION
[7:2]
RSRVD
RW
0
Reserved
[1]
PLL2_DLD_EN
RW
0
Enable for PLL2 DLD
0: Non PLL2 modes
1: PLL2 DLD enabled
[0]
RSRVD
RW
0
Reserved
9.6.2.148 PLL2_DUAL_LOOP
The PLL2_DUAL_LOOP Register supports Dual Loop Feature Back to Register Map.
Table 172. Register – 0xF7
BIT NO.
FIELD
TYPE
RESET
[7]
RSRVD
R
0
Reserved.
102
DESCRIPTION
[6:5]
PLL2_DUAL_LOOP_EN
RW
0
Dual Loop enable
0: Non-Dual Loop mode
1: Dual Loop mode
[4:0]
RSRVD
RW
0
Reserved.
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9.6.2.149 RESERVED10
RESERVED. Return to Register Map.
Table 173. Register – 0xFB
BIT NO.
FIELD
TYPE
RESET
DESCRIPTION
[7:1]
RSRVD
-
-
Reserved.
[0]
RSRVD
-
-
Reserved.
9.6.2.150 CH1_DDLY_BY0
Register CH1_DDLY_BY0 provides control of the following JESD204B control signals. Return to Register Map.
Table 174. Register – 0xFD
BIT NO.
[7:0]
FIELD
CH1_DDLY[7:0]
TYPE
RW
RESET
DESCRIPTION
0x0
Sets number of Digital Delay steps for Channel X. The
channel delays 0 to 255 Clock Distribution Path periods
compared to other channels.
9.6.2.151 CH2_DDLY_BY0
Register CH2_DDLY_BY0 provides control of the following JESD204B control signals. Return to Register Map.
Table 175. Register – 0xFF
BIT NO.
[7:0]
FIELD
CH2_DDLY[7:0]
TYPE
RW
RESET
DESCRIPTION
0x0
Sets number of Digital Delay steps for Channel X. The
channel delays 0 to 255 Clock Distribution Path periods
compared to other channels.
9.6.2.152 CH34_DDLY_BY0
Register CH34_DDLY_BY0 provides control of the following JESD204B control signals. Return to Register Map.
Table 176. Register – 0x101
BIT NO.
[7:0]
FIELD
CH34_DDLY[7:0]
TYPE
RW
RESET
DESCRIPTION
0x0
Sets number of Digital Delay steps for Channel X. The
channel delays 0 to 255 Clock Distribution Path periods
compared to other channels.
9.6.2.153 CH5_DDLY_BY0
Register CH5_DDLY_BY0 provides control of the following JESD204B control signals. Return to Register Map.
Table 177. Register – 0x103
BIT NO.
[7:0]
FIELD
CH5_DDLY[7:0]
TYPE
RW
RESET
DESCRIPTION
0x0
Sets number of Digital Delay steps for Channel X. The
channel delays 0 to 255 Clock Distribution Path periods
compared to other channels.
9.6.2.154 CH6_DDLY_BY0
Register CH6_DDLY_BY0 provides control of the following JESD204B control signals. Return to Register Map.
Table 178. Register – 0x105
BIT NO.
FIELD
TYPE
RESET
DESCRIPTION
[7:0]
CH6_DDLY[7:0]
RW
0x0
Sets number of Digital Delay steps for Channel X. The
channel delays 0 to 255 Clock Distribution Path periods
compared to other channels.
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9.6.2.155 CH78_DDLY_BY0
Register CH78_DDLY_BY0 provides control of the following JESD204B control signals. Return to Register Map.
Table 179. Register – 0x107
BIT NO.
[7:0]
FIELD
CH78_DDLY[7:0]
TYPE
RW
RESET
DESCRIPTION
0x0
Sets number of Digital Delay steps for Channel X. The
channel delays 0 to 255 Clock Distribution Path periods
compared to other channels.
9.6.2.156 CH9_DDLY_BY0
Register CH9_DDLY_BY0 provides control of the following JESD204B control signals. Return to Register Map.
Table 180. Register – 0x109
BIT NO.
FIELD
TYPE
RESET
DESCRIPTION
[7:0]
CH9_DDLY[7:0]
RW
0x0
Sets number of Digital Delay steps for Channel X. The
channel delays 0 to 255 Clock Distribution Path periods
compared to other channels.
9.6.2.157 CH10_DDLY_BY0
Register CH10_DDLY_BY0 provides control of the following JESD204B control signals. Return to Register Map.
Table 181. Register – 0x10B
BIT NO.
[7:0]
FIELD
CH10_DDLY[7:0]
TYPE
RW
RESET
DESCRIPTION
0x0
Sets number of Digital Delay steps for Channel X. The
channel delays 0 to 255 Clock Distribution Path periods
compared to other channels.
9.6.2.158 OUTCH1_JESD_CTRL
Register OUTCH1_JESD_CTRL provides control of the following JESD204B control signals. Return to Register
Map.
Table 182. Register – 0x10D
BIT NO.
FIELD
TYPE
RESET
[7]
RSRVD
-
-
DESCRIPTION
Reserved.
[6:2]
CH1_ADLY[4:0]
RW
0x0
Analog Steps can be programmed from 0 to 15. The
resulting delay is shown in Figure 34.
[1]
CH1_ADLY_EN
RW
0
Enables Analog Delay for Channel 1.
[0]
RSRVD
-
-
Reserved.
9.6.2.159 OUTCH2_JESD_CTRL
Register OUTCH2_JESD_CTRL provides control of the following JESD204B control signals. Return to Register
Map.
Table 183. Register – 0x10E
BIT NO.
FIELD
TYPE
RESET
[7]
RSRVD
-
-
Reserved.
104
DESCRIPTION
[6:2]
CH2_ADLY[4:0]
RW
0x0
Analog Steps can be programmed from 0 to 15. The
resulting delay is shown in Figure 34.
[1]
CH2_ADLY_EN
RW
0
Enables Analog Delay for Channel 2.
[0]
RSRVD
-
-
Reserved.
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9.6.2.160 OUTCH3_JESD_CTRL
Register OUTCH3_JESD_CTRL provides control of the following JESD204B control signals. Return to Register
Map.
Table 184. Register – 0x110
BIT NO.
FIELD
TYPE
RESET
DESCRIPTION
[7]
RSRVD
-
-
Reserved.
[6:2]
CH3_ADLY[4:0]
RW
0x0
Analog Steps can be programmed from 0 to 15. The
resulting delay is shown in Figure 34.
[1]
CH3_ADLY_EN
RW
0
Enables Analog Delay for Channel 3.
[0]
RSRVD
-
-
Reserved.
9.6.2.161 OUTCH4_JESD_CTRL
Register OUTCH4_JESD_CTRL provides control of the following JESD204B control signals. Return to Register
Map.
Table 185. Register – 0x111
BIT NO.
FIELD
TYPE
RESET
[7]
RSRVD
-
-
DESCRIPTION
Reserved.
[6:2]
CH4_ADLY[4:0]
RW
0x0
Analog Steps can be programmed from 0 to 15. The
resulting delay is shown in Figure 34.
[1]
CH4_ADLY_EN
RW
0
Enables Analog Delay for Channel 4.
[0]
RSRVD
-
-
Reserved.
9.6.2.162 OUTCH5_JESD_CTRL
Register OUTCH5_JESD_CTRL provides control of the following JESD204B control signals. Return to Register
Map.
Table 186. Register – 0x112
BIT NO.
FIELD
TYPE
RESET
[7]
RSRVD
-
-
DESCRIPTION
Reserved.
[6:2]
CH5_ADLY[4:0]
RW
0x0
Analog Steps can be programmed from 0 to 15. The
resulting delay is shown in Figure 34.
[1]
CH5_ADLY_EN
RW
0
Enables Analog Delay for Channel 5.
[0]
RSRVD
-
-
Reserved.
9.6.2.163 OUTCH6_JESD_CTRL
Register OUTCH6_JESD_CTRL provides control of the following JESD204B control signals. Return to Register
Map.
Table 187. Register – 0x115
BIT NO.
FIELD
TYPE
RESET
[7]
RSRVD
-
-
DESCRIPTION
Reserved.
[6:2]
CH6_ADLY[4:0]
RW
0x0
Analog Steps can be programmed from 0 to 15. The
resulting delay is shown in Figure 34.
[1]
CH6_ADLY_EN
RW
0
Enables Analog Delay for Channel 6.
[0]
RSRVD
-
-
Reserved.
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9.6.2.164 OUTCH7_JESD_CTRL
Register OUTCH7_JESD_CTRL provides control of the following JESD204B control signals. Return to Register
Map.
Table 188. Register – 0x116
BIT NO.
FIELD
TYPE
RESET
DESCRIPTION
[7]
RSRVD
-
-
Reserved.
[6:2]
CH7_ADLY[4:0]
RW
0x0
Analog Steps can be programmed from 0 to 15. The
resulting delay is shown in Figure 34.
[1]
CH7_ADLY_EN
RW
0
Enables Analog Delay for Channel 7.
[0]
RSRVD
-
-
Reserved.
9.6.2.165 OUTCH8_JESD_CTRL
Register OUTCH8_JESD_CTRL provides control of the following JESD204B control signals. Return to Register
Map.
Table 189. Register – 0x117
BIT NO.
FIELD
TYPE
RESET
[7]
RSRVD
-
-
DESCRIPTION
Reserved.
[6:2]
CH8_ADLY[4:0]
RW
0x0
Analog Steps can be programmed from 0 to 15. The
resulting delay is shown in Figure 34.
[1]
CH8_ADLY_EN
RW
0
Enables Analog Delay for Channel 8.
[0]
RSRVD
-
-
Reserved.
9.6.2.166 OUTCH9_JESD_CTRL
Register OUTCH9_JESD_CTRL provides control of the following JESD204B control signals. Return to Register
Map.
Table 190. Register – 0x119
BIT NO.
FIELD
TYPE
RESET
[7]
RSRVD
-
-
DESCRIPTION
Reserved.
[6:2]
CH9_ADLY[4:0]
RW
0x0
Analog Steps can be programmed from 0 to 15. The
resulting delay is shown in Figure 34.
[1]
CH9_ADLY_EN
RW
0
Enables Analog Delay for Channel 9.
[0]
RSRVD
-
-
Reserved.
9.6.2.167 OUTCH10_JESD_CTRL
Register OUTCH10_JESD_CTRL provides control of the following JESD204B control signals. Return to Register
Map.
Table 191. Register – 0x11A
BIT NO.
FIELD
TYPE
RESET
[7]
RSRVD
-
-
Reserved.
106
DESCRIPTION
[6:2]
CH10_ADLY[4:0]
RW
0x0
Analog Steps can be programmed from 0 to 15. The
resulting delay is shown in Figure 34.
[1]
CH10_ADLY_EN
RW
0
Enables Analog Delay for Channel 10.
[0]
RSRVD
-
-
Reserved.
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9.6.2.168 CLKMUXVECTOR
The CLKMUXVECTOR Register reflects the current status of the RefClk Mux. Return to Register Map.
Table 192. Register – 0x124
BIT NO.
FIELD
TYPE
RESET
[7:4]
RSRVD
-
-
DESCRIPTION
Reserved.
[3:0]
CLKMUX[3:0]
R
0x0
CLKmux status.
9.6.2.169 OUTCH1CNTL2
The OUTCH1CNTRL2 Register controls Output CH1. Return to Register Map.
Table 193. Register – 0x127
BIT NO.
FIELD
TYPE
RESET
DESCRIPTION
[7]
SYSREF_BYP_DYNDIGDLY
_GATING_CH1
RW
0
Bypass CH1 Dynamic Digital Delay Gating
[6]
SYSREF_BYP_ANALOGDLY
_GATING_CH1
RW
0
Bypass CH1 Analog Delay Gating
[5]
SYNC_EN_CH1
RW
0
Output CH1 SYNC Enable
[4]
HS_EN_CH1
RW
0
Output CH1 Enable Half-cycle delay
[3:2]
DRIV_1_SLEW[1:0]
RW
0x0
Slew Rate Setting OUTCH1.
[1:0]
RSRVD
-
-
Reserved.
9.6.2.170 OUTCH2CNTL2
The OUTCH2CNTRL2 Register controls Output CH2. Return to Register Map.
Table 194. Register – 0x128
BIT NO.
FIELD
TYPE
RESET
DESCRIPTION
[7]
SYSREF_BYP_DYNDIGDLY
_GATING_CH2
RW
0
Bypass CH2 Dynamic Digital Delay Gating
[6]
SYSREF_BYP_ANALOGDLY
_GATING_CH2
RW
0
Bypass CH2 Analog Delay Gating
[5]
SYNC_EN_CH2
RW
0
Output CH2 SYNC Enable
[4]
HS_EN_CH2
RW
0
Output CH2 Enable Half-cycle delay
[3:2]
RSRVD
-
-
Reserved.
[1:0]
DRIV_2_SLEW[1:0]
RW
0x0
Slew Rate Setting OUTCH2.
9.6.2.171 OUTCH34CNTL2
The OUTCH34CNTRL2 Register controls Output CH3_4. Return to Register Map.
Table 195. Register – 0x129
BIT NO.
FIELD
TYPE
RESET
DESCRIPTION
[7]
SYSREF_BYP_DYNDIGDLY
_GATING_CH3_4
RW
0
Bypass CH3_4 Dynamic Digital Delay Gating
[6]
SYSREF_BYP_ANALOGDLY
_GATING_CH3_4
RW
0
Bypass CH3_4 Analog Delay Gating
[5]
SYNC_EN_CH3_4
RW
0
Output CH3_4 SYNC Enable
[4]
HS_EN_CH3_4
RW
0
Output CH3_4 Enable Half-cycle delay
[3:2]
DRIV_4_SLEW[1:0]
RW
0x0
Slew Rate Setting OUTCH4.
[1:0]
DRIV_3_SLEW[1:0]
RW
0x0
Slew Rate Setting OUTCH3.
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9.6.2.172 OUTCH5CNTL2
The OUTCH5CNTRL2 Register controls Output CH5. Return to Register Map.
Table 196. Register – 0x12A
BIT NO.
FIELD
TYPE
RESET
DESCRIPTION
[7]
SYSREF_BYP_DYNDIGDLY
_GATING_CH5
RW
0
Bypass CH5 Dynamic Digital Delay Gating
[6]
SYSREF_BYP_ANALOGDLY
_GATING_CH5
RW
0
Bypass CH5 Analog Delay Gating
[5]
SYNC_EN_CH5
RW
0
Output CH5 SYNC Enable
[4]
HS_EN_CH5
RW
0
Output CH5 Enable Half-cycle delay
[3:2]
RSRVD
-
-
Reserved.
[1:0]
DRIV_5_SLEW[1:0]
RW
0x0
Slew Rate Setting OUTCH5.
9.6.2.173 OUTCH6CNTL2
The OUTCH6CNTRL2 Register controls Output CH6. Return to Register Map.
Table 197. Register – 0x12B
BIT NO.
FIELD
TYPE
RESET
DESCRIPTION
[7]
SYSREF_BYP_DYNDIGDLY
_GATING_CH6
RW
0
Bypass CH6 Dynamic Digital Delay Gating
[6]
SYSREF_BYP_ANALOGDLY
_GATING_CH6
RW
0
Bypass CH6 Analog Delay Gating
[5]
SYNC_EN_CH6
RW
0
Output CH6 SYNC Enable
[4]
HS_EN_CH6
RW
0
Output CH6 Enable Half-cycle delay
[3:2]
DRIV_6_SLEW[1:0]
RW
0x0
Slew Rate Setting OUTCH6.
[1:0]
RSRVD
-
-
Reserved.
9.6.2.174 OUTCH78CNTL2
The OUTCH78CNTRL2 Register controls Output CH7_8. Return to Register Map.
Table 198. Register – 0x12C
BIT NO.
FIELD
TYPE
RESET
DESCRIPTION
[7]
SYSREF_BYP_DYNDIGDLY
_GATING_CH7_8
RW
0
Bypass CH7_8 Dynamic Digital Delay Gating
[6]
SYSREF_BYP_ANALOGDLY
_GATING_CH7_8
RW
0
Bypass CH7_8 Analog Delay Gating
[5]
SYNC_EN_CH7_8
RW
0
Output CH7_8 SYNC Enable
[4]
HS_EN_CH7_8
RW
0
Output CH7_8 Enable Half-cycle delay
[3:2]
DRIV_8_SLEW[1:0]
RW
0x0
Slew Rate Setting OUTCH8.
[1:0]
DRIV_7_SLEW[1:0]
RW
0x0
Slew Rate Setting OUTCH7.
9.6.2.175 OUTCH9CNTL2
The OUTCH9CNTRL2 Register controls Output CH9. Return to Register Map.
Table 199. Register – 0x12D
BIT NO.
FIELD
TYPE
RESET
DESCRIPTION
[7]
SYSREF_BYP_DYNDIGDLY
_GATING_CH9
RW
0
Bypass CH9 Dynamic Digital Delay Gating
[6]
SYSREF_BYP_ANALOGDLY
_GATING_CH9
RW
0
Bypass CH9 Analog Delay Gating
[5]
SYNC_EN_CH9
RW
0
Output CH9 SYNC Enable
108
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Table 199. Register – 0x12D (continued)
BIT NO.
FIELD
TYPE
RESET
DESCRIPTION
[4]
HS_EN_CH9
RW
0
Output CH9 Enable Half-cycle delay
[3:2]
DRIV_9_SLEW[1:0]
RW
0x0
Slew Rate Setting OUTCH9.
[1:0]
RSRVD
-
-
Reserved.
9.6.2.176 OUTCH10CNTL2
The OUTCH10CNTRL2 Register controls Output CH10. Return to Register Map.
Table 200. Register – 0x12E
BIT NO.
FIELD
TYPE
RESET
DESCRIPTION
[7]
SYSREF_BYP_DYNDIGDLY
_GATING_CH10
RW
0
Bypass CH10 Dynamic Digital Delay Gating
[6]
SYSREF_BYP_ANALOGDLY
_GATING_CH10
RW
0
Bypass CH10 Analog Delay Gating
[5]
SYNC_EN_CH10
RW
0
Output CH10 SYNC Enable
Output CH10 Enable Half-cycle delay
[4]
HS_EN_CH10
RW
0
[3:2]
RSRVD
-
-
Reserved.
[1:0]
DRIV_10_SLEW[1:0]
RW
0x0
Slew Rate Setting OUTCH10.
9.6.2.177 OUTCH1_JESD_CTRL1
The OUTCH1_JESD_CTRL1 Register controls Output CH1. Return to Register Map.
Table 201. Register – 0x130
BIT NO.
FIELD
TYPE
RESET
[7:3]
RSRVD
-
-
Reserved.
0x0
Sets number of Dynamic Digital Delay steps for Output X.
The Output delays 0 to 5 Clock Distribution Path periods
compared to other channels.
[2:0]
DYN_DDLY_CH1[2:0]
RW
DESCRIPTION
9.6.2.178 OUTCH2_JESD_CTRL1
The OUTCH2_JESD_CTRL1 Register controls Output CH2. Return to Register Map.
Table 202. Register – 0x131
BIT NO.
FIELD
TYPE
RESET
[7:3]
RSRVD
-
-
Reserved.
0x0
Sets number of Dynamic Digital Delay steps for Output X.
The Output delays 0 to 5 Clock Distribution Path periods
compared to other channels.
[2:0]
DYN_DDLY_CH2[2:0]
RW
DESCRIPTION
9.6.2.179 OUTCH3_JESD_CTRL1
The OUTCH3_JESD_CTRL1 Register controls Output CH3. Return to Register Map.
Table 203. Register – 0x133
BIT NO.
FIELD
TYPE
RESET
[7:3]
RSRVD
-
-
Reserved.
0x0
Sets number of Dynamic Digital Delay steps for Output X.
The Output delays 0 to 5 Clock Distribution Path periods
compared to other channels.
[2:0]
DYN_DDLY_CH3[2:0]
RW
DESCRIPTION
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9.6.2.180 OUTCH4_JESD_CTRL1
The OUTCH4_JESD_CTRL1 Register controls Output CH4. Return to Register Map.
Table 204. Register – 0x134
BIT NO.
FIELD
TYPE
RESET
[7:3]
RSRVD
-
-
Reserved.
0x0
Sets number of Dynamic Digital Delay steps for Output X.
The Output delays 0 to 5 Clock Distribution Path periods
compared to other channels.
[2:0]
DYN_DDLY_CH4[2:0]
RW
DESCRIPTION
9.6.2.181 OUTCH5_JESD_CTRL1
The OUTCH5_JESD_CTRL1 Register controls Output CH5. Return to Register Map.
Table 205. Register – 0x135
BIT NO.
FIELD
TYPE
RESET
[7:3]
RSRVD
-
-
Reserved.
0x0
Sets number of Dynamic Digital Delay steps for Output X.
The Output delays 0 to 5 Clock Distribution Path periods
compared to other channels.
[2:0]
DYN_DDLY_CH5[2:0]
RW
DESCRIPTION
9.6.2.182 OUTCH6_JESD_CTRL1
The OUTCH6_JESD_CTRL1 Register controls Output CH6. Return to Register Map.
Table 206. Register – 0x138
BIT NO.
FIELD
TYPE
RESET
[7:3]
RSRVD
-
-
Reserved.
0x0
Sets number of Dynamic Digital Delay steps for Output X.
The Output delays 0 to 5 Clock Distribution Path periods
compared to other channels.
[2:0]
DYN_DDLY_CH6[2:0]
RW
DESCRIPTION
9.6.2.183 OUTCH7_JESD_CTRL1
The OUTCH7_JESD_CTRL1 Register controls Output CH7. Return to Register Map.
Table 207. Register – 0x139
BIT NO.
FIELD
TYPE
RESET
[7:3]
RSRVD
-
-
Reserved.
0x0
Sets number of Dynamic Digital Delay steps for Output X.
The Output delays 0 to 5 Clock Distribution Path periods
compared to other channels.
[2:0]
DYN_DDLY_CH7[2:0]
RW
DESCRIPTION
9.6.2.184 OUTCH8_JESD_CTRL1
The OUTCH8_JESD_CTRL1 Register controls Output CH8. Return to Register Map.
Table 208. Register – 0x13A
BIT NO.
FIELD
TYPE
RESET
DESCRIPTION
[7:3]
RSRVD
-
-
Reserved.
[2:0]
DYN_DDLY_CH8[2:0]
RW
0x0
Sets number of Dynamic Digital Delay steps for Output X.
The Output delays 0 to 5 Clock Distribution Path periods
compared to other channels.
110
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9.6.2.185 OUTCH9_JESD_CTRL1
The OUTCH9_JESD_CTRL1 Register controls Output CH9. Return to Register Map.
Table 209. Register – 0x13C
BIT NO.
FIELD
TYPE
RESET
[7:3]
RSRVD
-
-
Reserved.
0x0
Sets number of Dynamic Digital Delay steps for Output X.
The Output delays 0 to 5 Clock Distribution Path periods
compared to other channels.
[2:0]
DYN_DDLY_CH9[2:0]
RW
DESCRIPTION
9.6.2.186 OUTCH10_JESD_CTRL1
The OUTCH10_JESD_CTRL1 Register controls Output CH10. Return to Register Map.
Table 210. Register – 0x13D
BIT NO.
FIELD
TYPE
RESET
[7:3]
RSRVD
-
-
DESCRIPTION
Reserved.
[2:0]
DYN_DDLY_CH10[2:0]
RW
0x0
Output CH10 Dynamic/Individual Digital Delay.
9.6.2.187 SYSREF_PLS_CNT
Sysref Pulse Count Configuration. Return to Register Map.
Table 211. Register – 0x140
BIT NO.
FIELD
TYPE
RESET
[7:6]
RSRVD
-
-
Reserved.
[5:0]
OUTCH_SYSREF_PLSCNT[
5:0]
0x0
Set number of desired sysref pulses. 0 Enables continuous
sysref.
RW
DESCRIPTION
9.6.2.188 SYNCMUX
The SYNCMUX Register controls the status signal that is routed to the SYNC output. Return to Register Map.
Table 212. Register – 0x141
BIT NO.
[7:0]
FIELD
SYNC_INT_MUX[7:0]
TYPE
RW
RESET
DESCRIPTION
0x4
SYNC Integrated Mux Select.
SYNC_INT_MUX– SYNC Output
0– PLL1 Lock Detect and PLL2 Lock Detect
1– PLL1 Lock Detect
2– PLL2 Lock Detect
3– CLKINBLK LOS
4– SPI Output Data
5– Reserved
6– Reserved
7– Reserved
8– HOLDOVER_EN
9– Mirror of SYNC_INPUT
10– Mirror of CLKINSEL1 INPUT
11– Reserved
12– Reserved
13– PLL2 Reference Clock
14– Reserved
15– PLL1 Lock Detect and PLL2 Lock Detect and not PLL1
Holdover
16– PLL1 Lock Detect and not PLL1 Holdover
17– Logic 1
18– Logic 0
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9.6.2.189 IOTEST_SYNC
The IOTEST_SYNC Register provides control of the SYNC driver and test features. Return to Register Map.
Table 213. Register – 0x142
BIT NO.
FIELD
TYPE
RESET
[7]
RSRVD
RW
0
DESCRIPTION
Reserved.
[6]
SYNC_OUTPUT_HIZ
RW
1
SYNC Output Driver High Impedance. When
SYNC_OUTPUT_HIZ is set to 1 the SYNC output driver
stage is disabled.
[5]
SYNC_ENB_INSTAGE
RW
1
SYNC Input Stage Enable BAR. When SYNC_INPUT_ENB
is 0 the SYNC Input stage is enabled. When
SYNC_INPUT_ENB is set to 1 the SYNC input stage is
disabled.
[4]
SYNC_EN_ML_INSTAGE
RW
1
SYNC Input Stage Enable Multi-level. When
SYNC_INPUT_ENML is 1 the input stage is configured for
multi-level mode.
[3]
RSRVD
RW
0
Reserved.
[2]
SYNC_OUTPUT_DATA
RW
0
SYNC Output Data. Set the SYNC output data value when
SYNC_IOTESTEN is 1.
[1]
SYNC_INPUT_Y12
R
0
SYNC Input Y12 Value. Indicates the logic level present on
the SYNC Y12 pin.
[0]
SYNC_INPUT_M12
R
0
SYNC Input M12 Value. Indicates the logic level present on
the SYNC M12 pin.
9.6.2.190 OUTCH_ZDM
Low Skew Feedback Buffer Settings Back to Register Map.
Table 214. Register – 0x143
BIT NO.
FIELD
TYPE
RESET
DESCRIPTION
[7:5]
RSRVD
-
-
Reserved.
[4]
FBBUF_CH5_EN
RW
0
Enable Channel 5 Zero Delay Mode FBClock Buffer
[3:1]
RSRVD
-
-
Reserved.
[0]
FBBUF_CH6_EN
RW
0
Enable Channel 6 Zero Delay Mode FBClock Buffer
9.6.2.191 PLL2_CTRL3
The PLL2_CTRL3 Register provides control of PLL2 features. Return to Register Map.
Table 215. Register – 0x146
BIT NO.
FIELD
TYPE
RESET
[7]
RSRVD
-
-
Reserved.
0
Enable By-2 Divider in PLL2 Feedback.
nbypass_div2_fb– PLL2 Feedback by-2 Divider
0– Divider Off
1– Divider On
0x0
PLL2 VCO Prescaler Configuration.
PLL2_PRESCALEr – Effect
00XX– PLL2 VCO Prescaler DIV3
01XX– PLL2 VCO Prescaler DIV4
10XX– PLL2 VCO Prescaler DIV5
11XX– PLL2 VCO Prescaler DIV6
0x0
PLL2 Feedback MUX control.
PLL2_FBDIV_MUXSEL– Effect
00– Feedback Prescaler Output
01– Feedback OUTCH6 Output (Zero Delay Mode)
10– Feedback OUTCH5 Output (Zero Delay Mode)
[6]
[5:2]
[1:0]
112
PLL2_NBYPASS_DIV2_FB
PLL2_PRESCALER[3:0]
PLL2_FBDIV_MUXSEL[1:0]
RW
RW
RW
DESCRIPTION
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9.6.2.192 PLL1_HOLDOVER_CTRL0
The PLL1_HOLDOVER_CTRL0 Register selects the GPIO pin to use to force Holdover mode. Return to Register
Map.
Table 216. Register – 0x149
BIT NO.
FIELD
TYPE
RESET
DESCRIPTION
[7:4]
RSRVD
-
-
Reserved.
[3]
PLL1_CLKINSEL1_ML_HOL
DOVER
RW
0
Force holdover by applying mid-level at CLKINSEL1.
[2]
PLL1_SYNC_HOLDOVER
RW
0
Force holdover by applying high-level at SYNC.
[1]
PLL1_STATUS1_HOLDOVE
R
RW
0
Force holdover by applying high-level at STATUS1.
[0]
PLL1_STATUS0_HOLDOVE
R
RW
0
Force holdover by applying high-level at STATUS0.
9.6.2.193 IOCTRL_SYNC_1
The IOCTRL_SYNC_1 Register provides control of SYNC Input features. Return to Register Map.
Table 217. Register – 0x14A
BIT NO.
FIELD
TYPE
RESET
[7]
RSRVD
-
-
Reserved.
[6:2]
SYNC_ANALOGDLY[4:0]
RW
0x0
SYNC input Analog Delay.
[1]
SYNC_ANALOGDLY_EN
RW
0
Enable Analog Delay at SYNC input.
0
SYNC_IN Invert.
SYNC_INV– Polarity
0– Not inverted
1– Inverted
[0]
SYNC_INV
RW
DESCRIPTION
9.6.2.194 OUTCH_TOP_JESD_CTRL
OUTCH_TOP_JESD_CTRL controls JESD functions for TOP output channels. Return to Register Map.
Table 218. Register – 0x14B
BIT NO.
FIELD
TYPE
RESET
DESCRIPTION
[7]
RESERVED
RW
0
RESERVED
[6]
DYN_DDLY_CH10_EN
RW
0
Enable CH10 Dynamic Digital Delay.
[5]
DYN_DDLY_CH9_EN
RW
0
Enable CH9 Dynamic Digital Delay.
[4]
RESERVED
RW
0
RESERVED
[3]
DYN_DDLY_CH8_EN
RW
0
Enable CH8 Dynamic Digital Delay.
[2]
DYN_DDLY_CH7_EN
RW
0
Enable CH7 Dynamic Digital Delay.
[1]
DYN_DDLY_CH6_EN
RW
0
Enable CH6 Dynamic Digital Delay.
[0]
RESERVED
RW
0
RESERVED
9.6.2.195 OUTCH_BOT_JESD_CTRL
OUTCH_BOT_JESD_CTRL controls JESD functions for BOTTOM output channels. Return to Register Map.
Table 219. Register – 0x14C
BIT NO.
FIELD
TYPE
[7]
RW
0
RESET
DESCRIPTION
[6]
DYN_DDLY_CH5_EN
RW
0
Enable CH5 Dynamic Digital Delay.
[5]
[4]
DYN_DDLY_CH4_EN
RW
0
Enable CH4 Dynamic Digital Delay.
DYN_DDLY_CH3_EN
RW
0
Enable CH3 Dynamic Digital Delay.
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Table 219. Register – 0x14C (continued)
BIT NO.
FIELD
TYPE
RESET
DESCRIPTION
[3]
RESERVED
RW
0
RESERVED
[2]
DYN_DDLY_CH2_EN
RW
0
Enable CH2 Dynamic Digital Delay.
[1]
DYN_DDLY_CH1_EN
RW
0
Enable CH1 Dynamic Digital Delay.
[0]
RESERVED
RW
0
RESERVED
9.6.2.196 OUTCH_JESD_CTRL1
OUTCH_TOP_JESD_CTRL controls JESD functions for TOP output channels. Return to Register Map.
Table 220. Register – 0x14E
BIT NO.
FIELD
TYPE
RESET
DESCRIPTION
[7]
SYSREF_EN_CH10
RW
0
Enable CH10 Sysref feature.
[6]
SYSREF_EN_CH9
RW
0
Enable CH9 Sysref feature.
[5]
SYSREF_EN_CH7_8
RW
0
Enable CH7_8 Sysref feature.
[4]
SYSREF_EN_CH6
RW
0
Enable CH6 Sysref feature.
[3]
SYSREF_EN_CH5
RW
0
Enable CH5 Sysref feature.
[2]
SYSREF_EN_CH3_4
RW
0
Enable CH3_4 Sysref feature.
[1]
SYSREF_EN_CH2
RW
0
Enable CH2 Sysref feature.
[0]
SYSREF_EN_CH1
RW
0
Enable CH1 Sysref feature.
9.6.2.197 PLL2_CTRL4
PLL2 CTRL4 Register sets PLL2 configuration. Return to Register Map.
Table 221. Register – 0x150
BIT NO.
FIELD
TYPE
RESET
[7:4]
RSRVD
-
-
DESCRIPTION
Reserved.
[3]
PLL2_PFD_DIS_SAMPLE
RW
0
Disable PFD Sampling.
[2:0]
PLL2_PROG_PFD_RESET[2
:0]
RW
0x0
Programmable PFD reset.
9.6.2.198 PLL2_CTRL5
PLL2 CTRL5 Register sets PLL2 configuration. Return to Register Map.
Table 222. Register – 0x151
BIT NO.
FIELD
TYPE
RESET
[7:5]
RSRVD
-
-
DESCRIPTION
Reserved.
PLL2_RFILT
RW
0
0-> 9.2 kΩ
1->4.7 kΩ
[3]
RSRVD
-
-
Reserved.
[2]
PLL2_CP_EN_SAMPLE_BY
P
RW
0
Bypass PLL2 Chargepump sampling.
[1:0]
PLL2_CPROP[1:0]
RW
0x0
Set Cap prior Sampling.
[4]
9.6.2.199 PLL2_CTRL6
PLL2 CTRL6 Register sets PLL2 configuration. Return to Register Map.
Table 223. Register – 0x152
BIT NO.
FIELD
TYPE
RESET
DESCRIPTION
[7:4]
RSRVD
-
-
Reserved.
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Table 223. Register – 0x152 (continued)
BIT NO.
FIELD
TYPE
RESET
DESCRIPTION
[3]
PLL2_EN_FILTER
RW
0
Enable PLL2 Chargepump Filter.
[2:0]
PLL2_CSAMPLE[2:0]
RW
0x0
PLL2 Set Cap After sampling.
9.6.2.200 PLL2_CTRL7
PLL2 CTRL7 Register sets PLL2 configuration. Return to Register Map.
Table 224. Register – 0x153
BIT NO.
FIELD
TYPE
RESET
[7:5]
RSRVD
-
-
DESCRIPTION
Reserved.
[4:0]
PLL2_CFILT
RW
0
0 to 124 pF in 4-pF steps
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10 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
10.1 Application Information
To assist customers in frequency planning and design of loop filters Texas Instrument's provides the Clock
Design Tool and Clock Architect.
10.1.1 Digital Lock Detect Frequency Accuracy
The digital lock detect circuit is used to determine PLL1 locked and PLL2 locked. A window size and lock count
register are programmed to set a ppm frequency accuracy of reference to feedback signals of the PLL for each
event to occur. When a PLL digital lock event occurs the PLL's digital lock detect is asserted true.
EVENT
PLL
WINDOW SIZE
LOCK COUNT
PLL1 Lock
PLL1
PLL1_LD_WNDW_SIZE
PLL1_LOCKDET_CYC_CNT * (1 + (31 * PLL1_LCKDET_BY_32))
PLL2 Lock
(Initial)
PLL2
PLL2_LD_WNDW_SIZE_INITIAL =
1 ns
PLL2_LOCKDET_CYC_CNT_INITIAL
PLL2 Lock
PLL2
PLL2_LD_WNDW_SIZE = 1 ns
PLL2_LOCKDET_CYC_CNT
For a digital lock detect event to occur there must be a lock count number of a count frequency during which the
time/phase error of the PLLX_R reference and PLLX_N feedback signal edges are within the user programmable
window size. Because there must be at least lock count number of count frequency cycles, a minimum digital
lock detect assert time can be calculated as lock count / count frequency where count frequency = PLL2 phase
detector frequency. PLL2 lock time is the sum of the PLL2 Lock (Initial) + PLL2 Lock time.
By using Equation 1, values for a lock count and window size can be chosen to set the frequency accuracy
required by the system in ppm before the digital lock detect event occurs:
ppm =
1e6 × WINDOW SIZE × COUNT FREQUENCY
LOCK COUNT
(1)
The effect of the lock count value is that it shortens the effective lock window size by dividing the window size by
lock count.
If at any time the PLLX_R reference and PLLX_N feedback signals are outside the time window set by window
size, then the lock count value is reset to 0.
10.1.1.1 Minimum Lock Time Calculation Example
To calculate the minimum PLL2 digital lock time given a PLL2 phase detector frequency of 245.76 MHz,
PLL2_LOCK_DET_CYC_CNT_INITAL = 32768, and PLL2_LOCK_DET_CYC_CNT = 16384. Then the minimum
digital lock time assert time of PLL2 is PLL2 Lock time (Initial) + PLL2 Lock time = (32768 / 245.76 MHz) +
(16384 / 245.76 MHz) = 200 µs.
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10.2 Typical Application
Normal use case of the LMK04610 device is as a dual loop jitter cleaner. This section will discuss a design
example to illustrate the various functional aspects of the LMK04610 device.
PLL1
R
2 inputs
N
Phase
Detector
PLL1
Integrated
Loop Filter
Divider
OSCin
External
VCXO
CTRL_VCXO
CLKinX
CLKinX*
PLL2
Device/SYSref
Clock
Divider
Digital Delay
Analog Delay
Internal VCO
R
Phase
Detector
PLL2
Integrated
Loop Filter
N
LMK04610
Pre
Div
OSCout
OSCout*
CLKoutX*
CLKoutX
10 Device/Sysref
Clocks
2 blocks
Device/SYSref
Clock
Divider
Digital Delay
Analog Delay
CLKoutX*
CLKoutX
CLKoutX*
CLKoutX
4 blocks
Copyright © 2017, Texas Instruments Incorporated
Figure 60. Simplified Functional Block Diagram for Dual-Loop Mode
10.2.1 Design Requirements
Given a remote radio head (RRU) type application which needs to clock some ADCs, DACs, FPGA, SERDES,
and an LO. The input clock is a recovered clock which needs jitter cleaning. The FPGA clock should have a
clock output on power up. A summary of clock input and output requirements are as follows:
Clock Input:
• 122.88-MHz recovered clock.
Clock Outputs:
• 1x 245.76-MHz clock
• 2x 983.04-MHz clock
• 2x 122.88-MHz clock
• 1x 122.88-MHz clock
for ADC
for DAC
for FPGA
for SERDES
It is also desirable to have the holdover feature engage if the recovered clock reference is ever lost. The
following information reviews the steps to produce this design.
If JESD204B support is also required for the clock outputs, see JEDEC JESD204B for more details.
10.2.2 Detailed Design Procedure
Design of all aspects of the LMK04610 are quite involved and software has been written to assist in part
selection and part programming. Contact TI for optimized loop filter settings based on the system requirement.
This design procedure gives a quick outline of the process.
NOTE
This information is current as of the date of the release of this data sheet. Design tools
receive continuous improvements to add features and improve model accuracy. Refer to
software instructions or training for latest features.
1. Device Selection
– The key to device selection is required VCO frequency given required output frequencies. The device
must be able to produce the VCO frequency that can be divided down to required output frequencies.
– The software design tools take the VCO frequency range into account for specific devices based on the
application's required output frequencies.
– To understand the process better, see the Detailed Description which provides more insight into the
functional blocks and programming options.
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Typical Application (continued)
2. Device Configuration
There are many possible permutations of dividers and other registers to get same input and output
frequencies from a device. However, consider that there are some optimizations and trade-offs. It is possible,
although not assured, that some crosstalk and mixing could be created when using some divides.
– The optimum setting attempts to maximize phase detector frequency and uses the smallest dividers
settings.
– For lowest possible in-band PLL noise, maximize phase detector frequency to minimize N divide value.
– As rule of thumb, keeping the phase detector frequency approximately between 10 × PLL loop bandwidth
and 100 × PLL loop bandwidth. A phase detector frequency less than 5 × PLL bandwidth may be
unstable and a phase detector frequency > 100 × loop bandwidth may experience increased lock time
due to cycle slipping. However, for clock generation and jitter cleaning applications, lock time is typically
not critical and large phase detector frequencies typically result in reduced PLL noise, so cycle-slipping
during lock is acceptable.
10.2.2.1 PLL Loop Filter Design
Contact TI with the application requirements to get the optimized loop filter settings.
10.2.2.2 Clock Output Assignment
It is best to consider proximity of each clock output to each other and other PLL circuitry when choosing final
clock output locations. Here are some guidelines to help achieve best performance when assigning outputs to
specific CLKout/OSCout pins.
• Group common frequencies together.
• Some clock targets require low close-in phase noise. If possible, use a VCXO based PLL1 output from
OSCout/OSCout* for such a clock target.
• Some clock targets require excellent noise floor performance. Outputs driven by the internal LC-VCO have
the best noise floor performance. An example is an ADC or DAC.
Other device specific configuration. For LMK04610, consider the following:
• Holdover Configuration
LMK04610 provides the option to have two clock inputs. The clock priority, clock loss detection, holdover, and
loss recovery can be programmed. See Holdover for more details.
• JESD204B support
To generate JESD204B compliant clocks, see JEDEC JESD204B for more details.
• Digital delay: phase alignment of the output clocks.
• Analog delay: another method to shift phases of clocks with finer resolution with the penalty of increase noise
floor.
10.2.2.3
Calculation Using LCM
In this example, the LCM (245.76 MHz, 983.04 MHz, 122.88 MHz) = 983.04 MHz. A valid VCO frequency for
LMK04610 is 5898.24 MHz = 6 × 983.04 MHz. Therefore, the LMK04610 may be used to produce these output
frequencies.
10.2.2.4 Device Programming
The software tool TICS Pro for EVM programming can be used to set up the device in the desired configuration,
then export a hex register map suitable for use in applications.
10.2.2.5
Device Selection
Use the WEBENCH Clock Architect Tool and enter the required frequencies and formats into the tool. To use
this device, find a solution using the LMK04610.
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Typical Application (continued)
10.2.2.6 Clock Architect
When viewing resulting solutions, it is possible to narrow the parts used in the solution by setting a filter. Filtering
of a specific device can be done by selecting the device from the filter combo box. Also, regular expressions can
be typed into filter combo box. LMK04610 will only filter for the LMK04610 device.
10.2.3 Application Curves
Table 225 lists the application curves for this device.
Table 225. Table of Graphs
FIGURE
LMK04610 CLKout2 Phase Noise
VCO = 5898.24 MHz
CLKout2 Frequency = 122.88 MHz
HSDS 8 mA
Figure 2
LMK04610 CLKout2 Phase Noise
VCO = 5898.24 MHz
CLKout2 Frequency = 245.76 MHz
HSDS 8 mA
Figure 4
LMK04610 CLKout2 Phase Noise
VCO Frequency = 5898.24 MHz
CLKout2 Frequency = 983.04 MHz
HSDS 8 mA
Figure 5
10.3 Do's and Don'ts
10.3.1 Pin Connection Recommendations
• VCC Pins and Decoupling: all VCC pins must always be connected.
• Unused Clock Outputs: leave unused clock outputs floating and powered down.
• Unused Clock Inputs: unused clock inputs can be left floating.
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11 Power Supply Recommendations
11.1 Recommended Power Supply Connection
Figure 61 shows the recommended power supply connection using a low-noise LDO and a DC-DC converter.
Clean 3.3V
LDO
LMK0461x
VDD_PLL2OSC
3.3V
VDD_PLL1
3.3V
VDD_CORE
3.3V
VDD_PLL2CORE
3.3V
DC-DC
1.8V
VDD_OSC
1.8V - 3.3V
VDD_IO
1.8V - 3.3V
VDDO_0..7
1.8V - 3.3V
Copyright © 2017, Texas Instruments Incorporated
Figure 61. Recommended Power Supply Connection
11.2 Current Consumption / Power Dissipation Calculations
From Table 226 the current consumption can be calculated for any configuration. Data below is typical and not
assured.
Table 226. Typical Current Consumption for Selected Functional Blocks
(TA = 25°C, VCC = 3.3 V)
BLOCK
TEST CONDITIONS
TYPICAL ICC
(mA)
POWER
DISSIPATED
IN DEVICE
(mW)
POWER
DISSIPATED
EXTERNALLY
(mW)
-
CORE AND FUNCTIONAL BLOCKS
PLL1
PLL1 locked
14.5
47.85
PLL2
PLL2 locked
44
145.2
VCO (with VCO divider)
VCO
60
198
LOS
LOS enabled
1.8
3.24
0.1
0.33
PLL1 Regulation
-
OSCin Doubler
Doubler is enabled
EN_PLL2_REF_2X = 1
1.5
3.24
-
CLKinX
Any one of the CLKinX
is enabled
Single-Ended Mode
1.2
2.16
-
Differential Mode
1.5
2.7
Holdover
Holdover is enabled
HOLDOVER_EN = 1
0
0
-
SYNC_EN = 1
Required for SYNC and SYSREF functionality
0
0
-
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Current Consumption / Power Dissipation Calculations (continued)
Table 226. Typical Current Consumption for Selected Functional Blocks
(TA = 25°C, VCC = 3.3 V) (continued)
BLOCK
TEST CONDITIONS
TYPICAL ICC
(mA)
POWER
DISSIPATED
IN DEVICE
(mW)
POWER
DISSIPATED
EXTERNALLY
(mW)
0
0
-
Enabled
SYSREF_PD = 0
Dynamic Digital Delay
enabled
SYSREF_DDLY_PD = 0
3.5
6.3
Pulser is enabled
SYSREF_PLSR_PD = 0
0
0
SYSREF Pulses mode
SYSREF_MUX = 2
0
0
SYSREF Continuous
mode
SYSREF_MUX = 3
0
0
Static Digital Delay
0
0
Static Digital Delay + Half step
0
0
Dynamic Digital Delay
3.5
6.3
Analog Delay
2.5
4.8
Analog Delay per Step
0.2
0.36
50 Ω to Ground termination
19
34.2
-
HSDS 4 mA
5
9
-
HSDS 6 mA
7
12.6
-
HSDS 8 mA
9
16.2
-
HCSL
50 Ω to Ground termination
19
34.2
-
HSDS
HSDS 8 mA
9
16.2
SYSREF
Output channel
CLOCK OUTPUT BUFFERS
HCSL
HSDS
OSCout BUFFERS
LVCMOS
LVCMOS Pair
150 MHz
5
9
-
LVCMOS Single
150 MHz
2.5
4.5
-
12 Layout
12.1 Layout Guidelines
Power consumption of the LMK0461x family of devices can be high enough to require attention to thermal
management. For reliability and performance reasons the die temperature should be limited to a maximum of
125°C.
The device package has an exposed pad that provides the primary heat removal path to the printed-circuit board
(PCB). To maximize the heat dissipation from the package, a thermal landing pattern including multiple vias to a
ground plane must be incorporated into the PCB within the footprint of the package. The exposed pad must be
soldered down to ensure adequate heat conduction out of the package. Figure 62 shows a recommended land
and via pattern.
12.1.1 CLKin and OSCin
If differential input (preferred) is used route traces tightly coupled. If single-ended, have at least 3 trace width (of
CLKin or OSCin trace) separation from other RF traces. Place terminations close to IC.
12.1.2 CLKout
Normally differential signals must be routed tightly coupled to minimize PCB crosstalk. Trace impedance and
terminations must be designed accord to output type being used. Unused outputs must be left open and
programmed to power-down state.
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12.2 Layout Example
5.6 mm (typ)
0.5 mm (typ)
1.22 mm (typ)
Figure 62. Recommended PCB Layout
1. CLKin and OSCin path:
– If differential input (preferred), route traces tightly coupled. If single ended, have at least 3 trace width (of
CLKin/OSCin trace) separation from other RF traces.
2. CLKouts/OSCout:
– Normally differential signals should be routed tightly coupled to minimize PCB crosstalk. Trace impedance
must be designed according to 100-Ω differential. For optimal isolation place different clock group signals
on different layers.
3. VCXO connection
– Shorter traces are better. Place a resistors and capacitors closer to IC except for a single capacitor and
associated resistor, if any, next to VCXO. If any, place loop filter components close to VCXO Vtune pin.
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13 Device and Documentation Support
13.1 Device Support
13.1.1 Development Support
13.1.1.1 Clock Design Tool
For the Clock Design Tool, go to www.ti.com/tool/clockdesigntool
13.1.1.2 Clock Architect
Part selection, loop filter design, simulation.
For the Clock Architect, go to www.ti.com/clockarchitect.
13.1.1.3 TICS Pro
EVM programming software. Can also be used to generate register map for programming for a specific
application.
For TICS Pro, go to www.ti.com/tool/TICSPRO-SW
13.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
13.3 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
13.4 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
13.5 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
13.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
14 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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Product Folder Links: LMK04610
123
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
LMK04610RTQR
ACTIVE
QFN
RTQ
56
2000
RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 85
LMK04610
LMK04610RTQT
ACTIVE
QFN
RTQ
56
250
RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 85
LMK04610
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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