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LMK04816
SNAS597C – JULY 2012 – REVISED JANUARY 2016
LMK04816 Three Input Low-Noise Clock Jitter Cleaner With Dual Loop PLLs
1 Features
2 Applications
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•
1
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•
•
•
•
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Ultralow RMS Jitter Performance
– 100-fs RMS Jitter (12 kHz to 20 MHz)
– 123-fs RMS Jitter (100 Hz to 20 MHz)
Dual-Loop PLLATINUM™ PLL Architecture
– PLL1
– Integrated Low-Noise Crystal Oscillator
Circuit
– Holdover Mode When Input Clocks are Lost
– Automatic or Manual Triggering and
Recovery
– PLL2
– Normalized 1-Hz PLL Noise Floor of
–227 dBc/Hz
– Phase Detector Rate Up to 155 MHz
– OSCin Frequency-Doubler
– Integrated Low-Noise VCO
– VCO Frequency Ranges From 2370 MHz
to 2600 MHz
Three Redundant Input Clocks With LOS
– Automatic and Manual Switch-Over Modes
50% Duty Cycle Output Divides, 1 to 1045 (Even
and Odd)
LVPECL, LVDS, or LVCMOS Programmable
Outputs
Precision Digital Delay, Fixed or DynamicallyAdjustable
25-ps Step Analog Delay Control, Up to 575 ps
1/2 Clock Distribution Period Step Digital Delay,
up to 522 Steps
13 Differential Outputs; up to 26 Single-Ended
– Up to 5 VCXO and Crystal-Buffered Outputs
Clock Rates of Up to 2600 MHz
0-Delay Mode
Three Default Clock Outputs at Power Up
Multi-Mode: Dual PLL, Single PLL, and Clock
Distribution
Industrial Temperature Range: –40°C to +85°C
3.15-V to 3.45-V Operation
Package: 64-Pin WQFN (9.0 × 9.0 × 0.8 mm)
Data Converter Clocking and Wireless
Infrastructure
Networking, SONET or SDH, DSLAM
Medical, Video, Military, and Aerospace
Test and Measurement
•
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•
3 Description
The LMK04816 device is the industry's highest
performance clock conditioner with superior clock
jitter cleaning, generation, and distribution with
advanced features to meet next generation system
requirements. The dual-loop PLLATINUM architecture
enables
111-fs
RMS
jitter
(12
kHz
to
20 MHz) using a low-noise VCXO module or sub200-fs RMS jitter (12 kHz to 20 MHz) using a lowcost external crystal and varactor diode.
The dual-loop architecture consists of two highperformance phase-locked loops (PLL), a low-noise
crystal oscillator circuit, and a high-performance
voltage controlled oscillator (VCO). The first PLL
(PLL1) provides a low-noise jitter cleaner function
while the second PLL (PLL2) performs the clock
generation. PLL1 can be configured to either work
with an external VCXO module or the integrated
crystal oscillator with an external tunable crystal and
varactor diode. When used with a very narrow loop
bandwidth, PLL1 uses the superior close-in phase
noise (offsets below 50 kHz) of the VCXO module or
the tunable crystal to clean the input clock. The
output of PLL1 is used as the clean input reference to
PLL2 where it locks the integrated VCO. The loop
bandwidth of PLL2 can be optimized to clean the farout phase noise (offsets above 50 kHz) where the
integrated VCO outperforms the VCXO module or
tunable crystal used in PLL1.
Device Information(1)
PART NUMBER
LMK04816
PACKAGE
WQFN (64)
BODY SIZE (NOM)
9.00 mm × 9.00 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Simplified Schematic
Recovered
³GLUW\´ FORFN RU
clean clock
Backup
Reference Clock
Crystal or
VCXO
OSCout0
PLL+VCO
CLKin0
CLKin1
CLKin2
0XOWLSOH ³FOHDQ´
clocks at different
frequencies
CLKout0, 1
LMK04816
CLKout2
CLKout3
Precision Clock
Conditioner
FPGA
FPGA
Serializer/
Deserializer
CLKout4, 5, 6, 7
I
CLKout11
LMX2541
CLKout8A
IF
CLKout9
Q
CPLD
ADC
DAC
DAC
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
LMK04816
SNAS597C – JULY 2012 – REVISED JANUARY 2016
www.ti.com
Table of Contents
1
2
3
4
5
6
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
6.1
6.2
6.3
6.4
6.5
6.6
6.7
7
1
1
1
2
3
5
Absolute Maximum Ratings ...................................... 5
ESD Ratings.............................................................. 5
Recommended Operating Conditions....................... 5
Thermal Information .................................................. 6
Electrical Characteristics........................................... 6
Timing Requirements .............................................. 12
Typical Characteristics: Clock Output AC
Charcteristics ........................................................... 13
Parameter Measurement Information ................ 14
7.1 Charge Pump Current Specification Definitions...... 14
7.2 Differential Voltage Measurement Terminology ..... 15
8
Detailed Description ............................................ 16
8.1
8.2
8.3
8.4
Overview .................................................................
Functional Block Diagram .......................................
Feature Description.................................................
Device Functional Modes........................................
16
20
21
41
8.5 Programming........................................................... 45
8.6 Register Maps ......................................................... 49
9
Application and Implementation ........................ 90
9.1 Application Information............................................ 90
9.2 Typical Application ................................................ 105
9.3 System Examples ................................................. 112
10 Power Supply Recommendations ................... 115
10.1 Pin Connection Recommendations..................... 115
10.2 Current Consumption and Power Dissipation
Calculations............................................................ 116
11 Layout................................................................. 119
11.1 Layout Guidelines ............................................... 119
11.2 Layout Example .................................................. 120
12 Device and Documentation Support ............... 121
12.1
12.2
12.3
12.4
12.5
12.6
Device Support ..................................................
Documentation Support .....................................
Community Resources........................................
Trademarks .........................................................
Electrostatic Discharge Caution ..........................
Glossary ..............................................................
121
121
121
121
121
121
13 Mechanical, Packaging, and Orderable
Information ......................................................... 121
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision B (April 2013) to Revision C
Page
•
Added Pin Configuration and Functions section, ESD Ratings table, Thermal Information table, Feature Description
section, Device Functional Modes, Application and Implementation section, Power Supply Recommendations
section, Layout section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable
Information section ................................................................................................................................................................ 1
•
Changed organization of Detailed Description section for improved readability. ................................................................ 16
•
Added Typical Application section for expanded example of device use........................................................................... 105
Changes from Revision A (April 2013) to Revision B
•
2
Page
Changed layout of National Data Sheet to TI format ............................................................................................................ 1
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SNAS597C – JULY 2012 – REVISED JANUARY 2016
5 Pin Configuration and Functions
Vcc13
Status_CLKin1
Status_CLKin0
CLKout11
CLKout11*
CLKout10*
CLKout10
Vcc12
CLKout9
CLKout9*
CLKout8*
CLKout8
Vcc11
CLKout7
CLKout7*
CLKout6*
NKD Package
64-Pin WQFN
Top View
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
CLKout0
1
48
CLKout6
CLKout0*
2
47
Vcc10
CLKout1*
3
46
DATAuWire
CLKout1
4
45
CLKuWire
NC
5
44
LEuWire
SYNC/Status_CLKin2
6
43
Vcc9
NC
7
42
CPout2
NC
8
41
Vcc8
NC
9
40
OSCout0*
Vcc1
10
39
OSCout0
LDObyp1
11
38
Vcc7
LDObyp2
12
37
OSCin*
CLKout2
13
36
OSCin
CLKout2*
14
35
Vcc6
CLKout3*
15
34
CPout1
CLKout3
16
33
Status_LD
Top Down View
24
25
26
27
28
29
30
31
32
Status_Holdover
CLKin0
CLKin0*
Vcc5
CLKin2
CLKin2*
CLKout4*
23
FBCLKin*/Fin*/CLKin1*
CLKout4
22
FBCLKin/Fin/CLKin1
Vcc3
21
Vcc4
20
GND
19
CLKout5
18
CLKout5*
17
Vcc2
DAP
Pin Functions
PIN
I/O
TYPE
CLKout0, CLKout0*
O
Programmable
Clock output 0 (clock group 0)
CLKout1*, CLKout1
O
Programmable
Clock output 1 (clock group 0)
SYNC
I/O
NO.
NAME
1, 2
3, 4
6
DESCRIPTION
CLKout Synchronization input or programmable status pin
Programmable
Input for pin control of PLL1 reference clock selection. CLKin2
LOS status and other options available by programming.
Status_CLKin2
I/O
NC
—
10
Vcc1
—
PWR
Power supply for VCO LDO
11
LDObyp1
—
ANLG
LDO Bypass, bypassed to ground with 10-µF capacitor
12
LDObyp2
—
ANLG
LDO Bypass, bypassed to ground with a 0.1-µF capacitor
13, 14
CLKout2, CLKout2*
O
Programmable
Clock output 2 (clock group 1)
15, 16
Clock output 3 (clock group 1)
5, 7, 8, 9
—
No Connection. These pins must be left floating.
CLKout3*, CLKout3
O
Programmable
17
Vcc2
—
PWR
Power supply for clock group 1: CLKout2 and CLKout3
18
Vcc3
—
PWR
Power supply for clock group 2: CLKout4 and CLKout5
19, 20
CLKout4, CLKout4*
O
Programmable
Clock output 4 (clock group 2)
21, 22
CLKout5*, CLKout5
O
Programmable
Clock output 5 (clock group 2)
23
GND
—
PWR
Ground
24
Vcc4
—
PWR
Power supply for digital
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Pin Functions (continued)
PIN
NO.
NAME
I/O
TYPE
CLKin1, CLKin1*
25, 26
FBCLKin, FBCLKin*
DESCRIPTION
Reference Clock Input Port 1 for PLL1. AC- or DC-Coupled
I
ANLG
Fin, Fin*
Feedback input for external clock feedback input (0-delay
mode). AC- or DC-Coupled
External VCO input (External VCO mode). AC- or DC-Coupled
Programmable status pin, default readback output.
Programmable to holdover mode indicator. Other options
available by programming.
27
Status_Holdover
I/O
Programmable
28, 29
CLKin0, CLKin0*
I
ANLG
Reference Clock Input Port 0 for PLL1,
AC- or DC-Coupled
Vcc5
—
PWR
Power supply for clock inputs
CLKin2, CLKin2*
I
ANLG
Reference Clock Input Port 2 for PLL1,
AC- or DC-Coupled
33
Status_LD
I/O
Programmable
34
CPout1
O
ANLG
Charge pump 1 output
35
Vcc6
—
PWR
Power supply for PLL1, charge pump 1
OSCin, OSCin*
I
ANLG
Feedback to PLL1, Reference input to PLL2,
AC-Coupled
Power supply for OSCin port
30
31, 32
36, 37
38
Programmable status pin, default lock detect for PLL1 and
PLL2. Other options available by programming.
Vcc7
—
PWR
OSCout0, OSCout0*
O
Programmable
41
Vcc8
—
PWR
Power supply for PLL2, charge pump 2
42
CPout2
O
ANLG
Charge pump 2 output
43
Vcc9
—
PWR
Power supply for PLL2
44
LEuWire
I
CMOS
MICROWIRE Latch Enable Input
45
CLKuWire
I
CMOS
MICROWIRE Clock Input
46
DATAuWire
I
CMOS
MICROWIRE Data Input
47
Vcc10
—
PWR
48, 49
CLKout6, CLKout6*
O
Programmable
Clock output 6 (clock group 3)
50, 51
CLKout7*, CLKout7
O
Programmable
Clock output 7 (clock group 3)
Vcc11
—
PWR
53, 54
CLKout8, CLKout8*
O
Programmable
Clock output 8 (clock group 4)
55, 56
CLKout9*, CLKout9
O
Programmable
Clock output 9 (clock group 4)
Vcc12
—
PWR
58, 59
CLKout10,
CLKout10*
O
Programmable
Clock output 10 (clock group 5)
60, 61
CLKout11*,
CLKout11
O
Programmable
Clock output 11 (clock group 5)
62
Status_CLKin0
I/O
Programmable
Programmable status pin. Default is input for pin control of
PLL1 reference clock selection. CLKin0 LOS status and other
options available by programming.
63
Status_CLKin1
I/O
Programmable
Programmable status pin. Default is input for pin control of
PLL1 reference clock selection. CLKin1 LOS status and other
options available by programming.
64
Vcc13
—
PWR
Power supply for clock group 0: CLKout0 and CLKout1
DAP
—
GND
DIE ATTACH PAD, connect to GND
39, 40
52
57
DAP
4
Buffered output 0 of OSCin port
Power supply for clock group 3: CLKout6 and CLKout7
Power supply for clock group 4: CLKout8 and CLKout9
Power supply for clock group 5: CLKout10 and CLKout11
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6 Specifications
6.1 Absolute Maximum Ratings
See
(1) (2) (3)
.
MIN
MAX
UNIT
–0.3
3.6
V
–0.3
(VCC + 0.3)
V
260
°C
Junction temperature
150
°C
IIN
Differential input current (CLKinX/X*,
OSCin/OSCin*, FBCLKin/FBCLKin*, Fin/Fin*)
±5
mA
MSL
Moisture sensitivity level
3
Tstg
Storage temperature
(4)
VCC
Supply voltage
VIN
Input voltage
TL
Lead temperature (solder 4 seconds)
TJ
(1)
(2)
(3)
(4)
–65
150
°C
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
This device is a high performance RF integrated circuit with an ESD rating up to 2-kV Human Body Model, up to 150-V Machine Model,
and up to 750-V Charged Device Model and is ESD sensitive. Handling and assembly of this device must only be done at ESD-free
workstations.
If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/Distributors for availability and
specifications.
Never to exceed 3.6 V.
6.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1)
±2000
Charged-device model (CDM), per JEDEC specification JESD22C101 (2)
±750
Machine model (MM)
±150
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Manufacturing with
less than 500-V HBM is possible with the necessary precautions. Pins listed as ±2000 V may actually have higher performance.
Manufacturing with less than 500-V HBM is possible with the necessary precautions. Pins listed as ±2000 V may actually have higher
performance.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Manufacturing with
less than 250-V CDM is possible with the necessary recautions. Pins listed as ±750 V may actually have higher performance.
Manufacturing with less than 250-V CDM is possible with the necessary precautions. Pins listed as ±750 V may actually have higher
performance.
6.3 Recommended Operating Conditions
MIN
TJ
Junction temperature
TA
Ambient temperature
VCC
Supply voltage
VCC = 3.3 V
NOM
MAX
UNIT
125
°C
–40
25
85
°C
3.15
3.3
3.45
V
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6.4 Thermal Information
LMK04816
THERMAL METRIC (1)
NKD (WQFN)
UNIT
64 PINS
RθJA
Junction-to-ambient thermal resistance
(2)
(3)
RθJC(top)
Junction-to-case (top) thermal resistance
RθJB
Junction-to-board thermal resistance
ψJT
Junction-to-top characterization parameter
(4)
(5)
ψJB
Junction-to-board characterization parameter
(6)
RθJC(bot)
Junction-to-case (bottom) thermal resistance
(7)
(1)
(2)
(3)
(4)
(5)
(6)
(7)
24.3
°C/W
6.1
°C/W
3.5
°C/W
0.1
°C/W
3.5
°C/W
0.7
°C/W
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, High-K board, as
specified in JESD51-7, in an environment described in JESD51-2a.
The junction-to-case(top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific JEDEC-standard
test exists, but a close description can be found in the ANSI SEMI standard G30-88.
The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB
temperature, as described in JESD51-8.
The junction-to-top characterization parameter, ΨJT, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining RθJA, using a procedure described in JESD51-2a (sections 6 and 7).
The junction-to-board characterization parameter, ΨJB estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining RθJA , using a procedure described in JESD51-2a (sections 6 and 7).
The junction-to-case(bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific
JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
6.5 Electrical Characteristics
3.15 V ≤ VCC ≤ 3.45 V, –40°C ≤ TA ≤ 85°C. Typical values represent most likely parametric norms at VCC = 3.3 V, TA = 25°C,
at the Recommended Operating Conditions at the time of product characterization and are not ensured.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
1
3
mA
505
590
mA
500
MHz
CURRENT CONSUMPTION
ICC_PD
Power-down supply
current
ICC_CLKS
Supply current with all
clocks enabled (1)
All clock delays disabled,
CLKoutX_Y_DIV = 1045,
CLKoutX_TYPE = 1 (LVDS),
PLL1 and PLL2 locked.
CLKin0/0*, CLKin1/1*, AND CLKin2/2* INPUT CLOCK SPECIFICATIONS
fCLKin
Clock input frequency
SLEWCLKin
(2)
Clock input slew rate
(3) (4)
VIDCLKin
VSSCLKin
VIDCLKin
Clock input
Differential input voltage
(5)
Figure 5
VSSCLKin
(1)
(2)
(3)
(4)
(5)
6
0.001
20% to 80%
0.15
0.5
V/ns
AC-coupled
CLKinX_BUF_TYPE = 0 (bipolar)
0.25
1.55
|V|
0.5
3.1
Vpp
AC-coupled
CLKinX_BUF_TYPE = 1 (MOS)
0.25
1.55
|V|
0.5
3.1
Vpp
Load conditions for output clocks: LVDS: 100 Ω differential. See applications section Current Consumption and Power Dissipation
Calculations for Icc for specific part configuration and how to calculate Icc for a specific design.
CLKin0, CLKin1, and CLKin2 maximum is ensured by characterization, production tested at 200 MHz.
Ensured by characterization.
In order to meet the jitter performance listed in the subsequent sections of this data sheet, the minimum recommended slew rate for all
input clocks is 0.5 V/ns. This is especially true for single-ended clocks. Phase noise performance begins to degrade as the clock input
slew rate is reduced. However, the device functions at slew rates down to the minimum listed. When compared to single-ended clocks,
differential clocks (LVDS, LVPECL) are less susceptible to degradation in phase noise performance at lower slew rates due to their
common mode noise rejection. However, it is also recommended to use the highest possible slew rate for differential clocks to achieve
optimal phase noise performance at the device outputs.
See Differential Voltage Measurement Terminology for definition of VID and VOD voltages.
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Electrical Characteristics (continued)
3.15 V ≤ VCC ≤ 3.45 V, –40°C ≤ TA ≤ 85°C. Typical values represent most likely parametric norms at VCC = 3.3 V, TA = 25°C,
at the Recommended Operating Conditions at the time of product characterization and are not ensured.
PARAMETER
VCLKin
TEST CONDITIONS
Clock input
Single-ended input
voltage (3)
AC-coupled to CLKinX; CLKinX* AC-coupled to
ground
CLKinX_BUF_TYPE = 0 (bipolar)
AC-coupled to CLKinX; CLKinX* AC-coupled to
ground
CLKinX_BUF_TYPE = 1 (MOS)
VCLKin0-offset
DC offset voltage
between CLKin0/CLKin0*
CLKin0* – CLKin0
VCLKin1-offset
DC offset voltage
Each pin AC-coupled
between CLKin1/CLKin1*
CLKin0_BUF_TYPE = 0 (Bipolar)
CLKin1* – CLKin1
VCLKin2-offset
DC offset voltage
between CLKin2/CLKin2*
CLKin2* – CLKin2
VCLKinX-offset
DC offset voltage
between
CLKinX/CLKinX*
CLKinX* – CLKinX
VCLKin- VIH
High input voltage
VCLKin- VIL
Low input voltage
MIN
MAX
UNIT
0.25
2.4
Vpp
0.25
2.4
Vpp
Each pin AC-coupled
CLKinX_BUF_TYPE = 1 (MOS)
DC-coupled to CLKinX; CLKinX* AC-coupled to
ground
CLKinX_BUF_TYPE = 1 (MOS)
TYP
20
mV
0
mV
20
mV
55
mV
2.0
VCC
V
0
0.4
V
FBCLKin/FBCLKin* AND Fin/Fin* INPUT SPECIFICATIONS
fFBCLKin
Clock input frequency
(3)
AC-coupled
(CLKinX_BUF_TYPE = 0)
MODE = 2 or 8; FEEDBACK_MUX = 6
0.001
1000
MHz
fFin
Clock input frequency
(3)
AC-coupled
(CLKinX_BUF_TYPE = 0)
MODE = 3 or 11
0.001
3100
MHz
VFBCLKin/Fin
Single-ended clock input
voltage (3)
AC-coupled;
(CLKinX_BUF_TYPE = 0)
0.25
2
Vpp
SLEWFBCLKin/Fin
Slew rate on CLKin
AC-coupled; 20% to 80%;
(CLKinX_BUF_TYPE = 0)
0.15
(3)
0.5
V/ns
PLL1 SPECIFICATIONS
PLL1 phase detector
frequency
fPD1
ICPout1SOURCE
PLL1 charge
Pump source current
40
(6)
VCPout1 = VCC / 2, PLL1_CP_GAIN = 0
100
VCPout1 = VCC / 2, PLL1_CP_GAIN = 1
200
VCPout1 = VCC / 2, PLL1_CP_GAIN = 2
400
VCPout1 = VCC / 2, PLL1_CP_GAIN = 3
1600
VCPout1 = VCC / 2, PLL1_CP_GAIN = 0
–100
VCPout1 = VCC / 2, PLL1_CP_GAIN = 1
–200
VCPout1 = VCC / 2, PLL1_CP_GAIN = 2
–400
VCPout1 = VCC / 2, PLL1_CP_GAIN = 3
–1600
ICPout1SINK
PLL1 charge
Pump sink current
ICPout1%MIS
Charge pump
Sink / source mismatch
VCPout1 = VCC / 2, T = 25°C
3%
ICPout1VTUNE
Magnitude of charge
pump current variation
vs. charge pump voltage
0.5 V < VCPout1 < VCC – 0.5 V
TA = 25°C
4%
ICPout1%TEMP
Charge pump current vs.
temperature variation
ICPout1 TRI
Charge pump tri-state
leakage current
(6)
(6)
MHz
µA
µA
10%
4%
0.5 V < VCPout < VCC – 0.5 V
5
nA
This parameter is programmable
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Electrical Characteristics (continued)
3.15 V ≤ VCC ≤ 3.45 V, –40°C ≤ TA ≤ 85°C. Typical values represent most likely parametric norms at VCC = 3.3 V, TA = 25°C,
at the Recommended Operating Conditions at the time of product characterization and are not ensured.
PARAMETER
TEST CONDITIONS
MIN
TYP
PLL1_CP_GAIN = 400 µA
–117
PN10kHz
PLL 1/f noise at 10-kHz
offset. Normalized to 1GHz output frequency
PLL1_CP_GAIN = 1600 µA
–118
PN1Hz
Normalized phase noise
contribution
PLL1_CP_GAIN = 400 µA
MAX
dBc/Hz
–221.5
PLL1_CP_GAIN = 1600 µA
UNIT
dBc/Hz
–223
PLL2 REFERENCE INPUT (OSCIN) SPECIFICATIONS
(7)
fOSCin
PLL2 reference input
SLEWOSCin
PLL2 Reference Clock
minimum slew rate on
OSCin (3)
20% to 80%
VOSCin
Input voltage for OSCin
or OSCin* (3)
AC-coupled; single-ended (Unused pin AC-coupled
to GND)
VIDOSCin
VSSOSCin
VOSCin-offset
fdoubler_max
500
0.15
Differential voltage swing
AC-coupled
Figure 5
DC offset voltage
between OSCin/OSCin*
OSCinX* – OSCinX
Each pin AC-coupled
Doubler input frequency
EN_PLL2_REF_2X = 1; (8)
OSCin Duty Cycle 40% to 60%
(3)
0.5
MHz
V/ns
0.2
2.4
0.2
1.55
|V|
0.4
3.1
Vpp
20
Vpp
mV
155
MHz
20.5
MHz
CRYSTAL OSCILLATOR MODE SPECIFICATIONS
Crystal frequency range
fXTAL
(3)
RESR < 40 Ω
6
PXTAL
Crystal power dissipation Vectron VXB1 crystal, 20.48 MHz, RESR < 40 Ω
(9)
XTAL_LVL = 0
CIN
Input capacitance of
LMK04816 OSCin port
-40 to +85°C
100
µW
6
pF
PLL2 PHASE DETECTOR AND CHARGE-PUMP SPECIFICATIONS
Phase detector
frequency
fPD2
155
VCPout2=VCC / 2, PLL2_CP_GAIN = 0
ICPoutSOURCE
PLL2 charge pump
source current (6)
100
VCPout2=VCC / 2, PLL2_CP_GAIN = 1
400
VCPout2=VCC / 2, PLL2_CP_GAIN = 2
1600
VCPout2=VCC / 2, PLL2_CP_GAIN = 3
3200
VCPout2=VCC / 2, PLL2_CP_GAIN = 0
–100
VCPout2=VCC / 2, PLL2_CP_GAIN = 1
–400
VCPout2=VCC / 2, PLL2_CP_GAIN = 2
–1600
VCPout2=VCC / 2, PLL2_CP_GAIN = 3
–3200
ICPoutSINK
PLL2 charge pump sink
current (6)
ICPout2%MIS
Charge pump sink and
source mismatch
VCPout2=VCC / 2, TA = 25 °C
3%
ICPout2VTUNE
Magnitude of charge
pump current vs. charge
pump voltage variation
0.5 V < VCPout2 < VCC – 0.5 V
TA = 25°C
4%
ICPout2%TEMP
Charge pump current vs.
temperature variation
ICPout2TRI
Charge pump leakage
(7)
(8)
(9)
8
MHz
µA
µA
10%
4%
0.5 V < VCPout2 < VCC – 0.5 V
10
nA
FOSCin maximum frequency ensured by characterization. Production tested at 200 MHz.
The EN_PLL2_REF_2X bit (Register 13) enables/disables a frequency doubler mode for the PLL2 OSCin path.
See Application Section discussion of Optional Crystal Oscillator Implementation (OSCin and OSCin*).
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Electrical Characteristics (continued)
3.15 V ≤ VCC ≤ 3.45 V, –40°C ≤ TA ≤ 85°C. Typical values represent most likely parametric norms at VCC = 3.3 V, TA = 25°C,
at the Recommended Operating Conditions at the time of product characterization and are not ensured.
PARAMETER
TEST CONDITIONS
MIN
TYP
PLL2_CP_GAIN = 400 µA
–118
PN10kHz
PLL 1/f noise at 10-kHz
offset (10)
Normalized to 1-GHz
output frequency
PLL2_CP_GAIN = 3200 µA
–121
PN1Hz
Normalized phase noise
contribution (11)
PLL2_CP_GAIN = 400 µA
MAX
dBc/Hz
–222.5
PLL2_CP_GAIN = 3200 µA
UNIT
dBc/Hz
–227
INTERNAL VCO SPECIFICATIONS
fVCO
VCO tuning range
LMK04816
2370
16
higher end of the tuning range
21
KVCO
Fine tuning sensitivity
LMK04816
|ΔTCL|
Allowable temperature
drift for continuous lock
After programming R30 for lock, no changes to
output configuration are permitted to ensure
continuous lock
(12) (3)
2600
lower end of the tuning range
MHz
MHz/V
125
°C
CLKOUT CLOSED-LOOP JITTER SPECIFICATIONS USING A COMMERCIAL QUALITY VCXO (13)
L(f)CLKout
JCLKout
LVDS/LVPECL/L
VCMOS
LMK04816
fCLKout = 245.76 MHz
SSB phase noise
Measured at clock
outputs
Value is average for all
output types (14)
(14)
LMK04816
fCLKout = 245.76 MHz
Integrated RMS jitter
Offset = 1 kHz
–122.5
Offset = 10 kHz
–132.9
Offset = 100 kHz
–135.2
Offset = 800 kHz
–143.9
Offset = 10 MHz; LVDS
dBc/Hz
–156
Offset = 10 MHz; LVPECL 1600 mVpp
–157.5
Offset = 10 MHz; LVCMOS
–157.1
BW = 12 kHz to 20 MHz
115
BW = 100 Hz to 20 MHz
123
fs rms
CLKOUT CLOSED-LOOP JITTER SPECIFICATIONS USING THE INTEGRATED LOW-NOISE CRYSTAL OSCILLATOR CIRCUIT (15)
LMK04816
fCLKout = 245.76 MHz
Integrated RMS jitter
BW = 12 kHz to 20 MHz
XTAL_LVL = 3
192
BW = 100 Hz to 20 MHz
XTAL_LVL = 3
450
fs rms
DEFAULT POWER ON RESET CLOCK OUTPUT FREQUENCY
fCLKout-startup
Default output clock
frequency at device
power-on (16)
CLKout8, LVDS, LMK04816
90
98
110
MHz
(10) A specification in modeling PLL in-band phase noise is the 1/f flicker noise, LPLL_flicker(f), which is dominant close to the carrier. Flicker
noise has a 10 dB/decade slope. PN10kHz is normalized to a 10 kHz offset and a 1 GHz carrier frequency. PN10kHz = LPLL_flicker(10
kHz) - 20log(Fout / 1 GHz), where LPLL_flicker(f) is the single side band phase noise of only the flicker noise's contribution to total noise,
L(f). To measure LPLL_flicker(f) it is important to be on the 10-dB/decade slope close to the carrier. A high compare frequency and a clean
crystal are important to isolating this noise source from the total phase noise, L(f). LPLL_flicker(f) can be masked by the reference
oscillator performance if a low power or noisy source is used. The total PLL in-band phase noise performance is the sum of LPLL_flicker(f)
and LPLL_flat(f).
(11) A specification modeling PLL in-band phase noise. The normalized phase noise contribution of the PLL, LPLL_flat(f), is defined as:
PN1HZ=LPLL_flat(f) - 20log(N) - 10log(fPDX). LPLL_flat(f) is the single side band phase noise measured at an offset frequency, f, in a 1 Hz
bandwidth and fPDX is the phase detector frequency of the synthesizer. LPLL_flat(f) contributes to the total noise, L(f).
(12) Maximum Allowable Temperature Drift for Continuous Lock is how far the temperature can drift in either direction from the value it was
at the time that the R30 register was last programmed, and still have the part stay in lock. The action of programming the R30 register,
even to the same value, activates a frequency calibration routine. This implies the part works over the entire frequency range, but if the
temperature drifts more than the maximum allowable drift for continuous lock, then it is necessary to reload the R30 register to ensure it
stays in lock. Regardless of what temperature the part was initially programmed at, the temperature can never drift outside the
frequency range of –40°C to 85°C without violating specifications.
(13) VCXO used is a 122.88 MHz Crystek CVHD-950-122.880.
(14) fVCO = 2457.6 MHz, PLL1 parameters: EN_PLL2_REF_2X = 1, PLL2_R = 2, FPD1 = 1.024 MHz, ICP1 = 100 μA, loop bandwidth = 10 Hz.
A 122.88 MHz Crystek CVHD-950–122.880. PLL2 parameters: PLL2_R = 1, FPD2 = 122.88 MHz, ICP2 = 3200 μA, C1 = 47 pF, C2 = 3.9
nF, R2 = 620 Ω, PLL2_C3_LF = 0, PLL2_R3_LF = 0, PLL2_C4_LF = 0, PLL2_R4_LF = 0, CLKoutX_Y_DIV = 10, and
CLKoutX_ADLY_SEL = 0.
(15) Crystal used is a 20.48 MHz Vectron VXB1-1150-20M480 and Skyworks varactor diode, SMV-1249-074LF.
(16) CLKout6 and OSCout0 also oscillate at start-up at the frequency of the VCXO attached to OSCin port.
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Electrical Characteristics (continued)
3.15 V ≤ VCC ≤ 3.45 V, –40°C ≤ TA ≤ 85°C. Typical values represent most likely parametric norms at VCC = 3.3 V, TA = 25°C,
at the Recommended Operating Conditions at the time of product characterization and are not ensured.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
CLOCK SKEW AND DELAY
Maximum CLKoutX to
CLKoutY (17) (3)
|TSKEW|
MixedTSKEW
td0-DELAY
LVDS-to-LVDS, T = 25°C,
FCLK = 800 MHz, RL= 100 Ω
AC coupled
30
LVPECL-to-LVPECL,
T = 25°C,
FCLK = 800 MHz, RL= 100 Ω
emitter resistors =
240 Ω to GND
AC coupled
30
Maximum skew between
RL = 50 Ω, CL = 5 pF,
any two LVCMOS
T = 25°C, FCLK = 100 MHz.
outputs, same CLKout or (17)
(17) (3)
different CLKout
100
LVDS or LVPECL to
LVCMOS
750
Same device, T = 25 °C,
250 MHz
CLKin to CLKoutX delay
(17)
MODE = 2
PLL1_R_DLY = 0; PLL1_N_DLY = 0
1850
MODE = 2
PLL1_R_DLY = 0; PLL1_N_DLY = 0;
VCO Frequency = 2457.6 MHz
Analog delay select = 0;
Feedback clock digital delay = 11;
Feedback clock half step = 1;
Output clock digital delay = 5;
Output clock half step = 0;
0
ps
ps
ps
LVDS CLOCK OUTPUTS (CLKoutX), CLKoutX_TYPE = 1
fCLKout
VOD
VSS
Maximum frequency
(3)
RL = 100 Ω
(18)
1536
Differential output
voltage Figure 6
ΔVOD
Change in magnitude of
VOD for complementary
output states
VOS
Output offset voltage
ΔVOS
Change in VOS for
complementary output
states
T = 25°C, DC measurement
AC-coupled to receiver input
R = 100-Ω differential termination
MHz
250
400
450
|mV|
500
800
900
mVpp
50
mV
–50
1.125
1.25
1.375
35
V
|mV|
Output rise time
20% to 80%, RL = 100 Ω
Output fall time
80% to 20%, RL = 100 Ω
ISA
ISB
Output short-circuit
current - single-ended
Single-ended output shorted to GND, T = 25°C
–24
24
mA
ISAB
Output short-circuit
current - differential
Complimentary outputs tied together
–12
12
mA
TR / TF
200
ps
LVPECL CLOCK OUTPUTS (CLKoutX)
fCLKout
Maximum frequency
(3)
20% to 80% output rise
TR / TF
1536
(18)
80% to 20% output fall
time
RL = 100-Ω, emitter resistors = 240 Ω to GND
CLKoutX_TYPE = 4 or 5
(1600 or 2000 mVpp)
MHz
150
ps
(17) Equal loading and identical clock output configuration on each clock output is required for specification to be valid. Specification not valid
for delay mode.
(18) Refer to typical performance charts for output operation performance at higher frequencies than the minimum maximum output
frequency.
10
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Electrical Characteristics (continued)
3.15 V ≤ VCC ≤ 3.45 V, –40°C ≤ TA ≤ 85°C. Typical values represent most likely parametric norms at VCC = 3.3 V, TA = 25°C,
at the Recommended Operating Conditions at the time of product characterization and are not ensured.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
700-mVpp LVPECL CLOCK OUTPUTS (CLKoutX), CLKoutX_TYPE = 2
VOH
Output high voltage
VOL
Output low voltage
VOD
VSS
T = 25°C, DC measurement
Termination = 50 Ω to
VCC - 1.4 V
Output voltage Figure 6
VCC –
1.03
V
VCC –
1.41
V
305
380
440
[mV]
610
760
880
mVpp
1200-mVpp LVPECL CLOCK OUTPUTS (CLKoutX), CLKoutX_TYPE = 3
VOH
Output high voltage
VOL
Output low voltage
VOD
VSS
T = 25°C, DC measurement
Termination = 50 Ω to
VCC - 1.7 V
Output voltage Figure 6
VCC –
1.07
V
VCC –
1.69
V
545
625
705
|mV|
1090
1250
1410
mVpp
1600-mVpp LVPECL CLOCK OUTPUTS (CLKoutX), CLKoutX_TYPE = 4
VOH
Output high voltage
VOL
Output low voltage
VOD
VSS
T = 25°C, DC Measurement
Termination = 50 Ω to
VCC - 2.0 V
Output voltage Figure 6
VCC –
1.1
V
VCC –
1.97
V
660
870
965
|mV|
1320
1740
1930
mVpp
2000-mVpp LVPECL (2VPECL) CLOCK OUTPUTS (CLKoutX), CLKoutX_TYPE = 5
VOH
Output high voltage
VOL
Output low voltage
VOD
VSS
T = 25°C, DC Measurement
Termination = 50 Ω to
VCC – 2.3 V
Output voltage Figure 6
VCC –
1.13
V
VCC –
2.2
V
800
1070
1200
|mV|
1600
2140
2400
mVpp
LVCMOS CLOCK OUTPUTS (CLKoutX)
fCLKout
Maximum frequency
(3)
(18)
5-pF Load
VOH
Output high voltage
1-mA Load
VOL
Output low voltage
1-mA Load
IOH
Output high current
(source)
VCC = 3.3 V, VO = 1.65 V
IOL
Output low current (sink)
VCC = 3.3 V, VO = 1.65 V
DUTYCLK
Output duty cycle
TR
Output rise time
20% to 80%, RL = 50 Ω,
CL = 5 pF
400
ps
TF
Output fall time
80% to 20%, RL = 50 Ω,
CL = 5 pF
400
ps
(3)
VCC / 2 to VCC / 2, FCLK = 100 MHz, T = 25°C
250
MHz
VCC –
0.1
V
0.1
28
mA
28
45%
50%
V
mA
55%
DIGITAL OUTPUTS (Status_CLKinX, Status_LD, Status_Holdover, SYNC)
VOH
High-level output voltage
IOH = –500 µA
VOL
Low-level output voltage
IOL = 500 µA
VCC –
0.4
V
0.4
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Electrical Characteristics (continued)
3.15 V ≤ VCC ≤ 3.45 V, –40°C ≤ TA ≤ 85°C. Typical values represent most likely parametric norms at VCC = 3.3 V, TA = 25°C,
at the Recommended Operating Conditions at the time of product characterization and are not ensured.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VCC
V
0.4
V
DIGITAL INPUTS (Status_CLKinX, SYNC)
VIH
High-level input voltage
VIL
Low-level input voltage
High-level input current
VIH = VCC
IIH
Low-level input current
VIL = 0 V
IIL
1.6
Status_CLKinX_TYPE = 0
(High impedance)
–5
5
Status_CLKinX_TYPE = 1
(Pullup)
–5
5
Status_CLKinX_TYPE = 2
(Pulldown)
10
80
Status_CLKinX_TYPE = 0
(High impedance)
–5
5
Status_CLKinX_TYPE = 1
(Pullup)
–40
-5
Status_CLKinX_TYPE = 2
(Pulldown)
–5
5
1.6
VCC
µA
µA
DIGITAL INPUTS (CLKuWire, DATAuWire, LEuWire)
VIH
High-level input voltage
VIL
Low-level input voltage
IIH
High-level input current
VIH = VCC
IIL
Low-level input current
VIL = 0
V
0.4
V
5
25
µA
–5
5
µA
6.6 Timing Requirements
See Figure 8
MIN
NOM
MAX
UNIT
TECS
LE-to-clock setup time
25
ns
TDCS
Data-to-clock setup time
25
ns
TCDH
Clock-to-data hold time
8
ns
TCWH
Clock pulse width high
25
ns
TCWL
Clock pulse width low
25
ns
TCES
Clock-to-LE setup time
25
ns
TEWH
LE pulse width
25
ns
TCR
Falling clock to readback time
25
ns
12
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6.7 Typical Characteristics: Clock Output AC Charcteristics
500
1200
2000 mVpp
1600 mVpp
1200 mVpp
700 mVpp
450
1000
400
VOD (mV)
VOD (mV)
350
300
250
200
800
600
400
150
100
200
50
0
0
0
500
1000 1500 2000 2500 3000
FREQUENCY (MHz)
0
Figure 1. LVDS VOD vs Frequency
500 1000 1500 2000 2500 3000
FREQUENCY (MHz)
Figure 2. LVPECL With 240-Ω Emitter Resistors VOD vs
Frequency
1200
VOD (mV)
1000
2000 mVpp
800
600
1600 mVpp
400
200
0
0
500 1000 1500 2000 2500 3000
FREQUENCY (MHz)
Figure 3. LVPECL With 120-Ω Emitter Resistors VOD vs Frequency
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7 Parameter Measurement Information
7.1 Charge Pump Current Specification Definitions
Figure 4. Charge-Pump Current
I1 = Charge-Pump Sink Current at VCPout = VCC – ΔV
I2 = Charge-Pump Sink Current at VCPout = VCC / 2
I3 = Charge-Pump Sink Current at VCPout = ΔV
I4 = Charge-Pump Source Current at VCPout = VCC – ΔV
I5 = Charge-Pump Source Current at VCPout = VCC / 2
I6 = Charge-Pump Source Current at VCPout = ΔV
ΔV = Voltage offset from the positive and negative supply rails. Defined to be 0.5 V for this device.
7.1.1 Charge-Pump Output Current Magnitude Variation vs Charge-Pump Output Voltage
Use Equation 1 to calculate the charge-pump output current variation versus the charge-pump output voltage.
(1)
7.1.2 Charge-Pump Sink Current vs Charge-Pump Output Source Current Mismatch
Use Equation 2 to calculate the charge-pump sink current versus the source current mismatch.
(2)
14
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Charge Pump Current Specification Definitions (continued)
7.1.3 Charge-Pump Output Current Magnitude Variation vs Temperature
Use Equation 3 to calculate the charge-pump output current magnitude variation versus the temperature.
(3)
7.2 Differential Voltage Measurement Terminology
The differential voltage of a differential signal can be described by two different definitions causing confusion
when reading data sheets or communicating with other engineers. This section addresses the measurement and
description of a differential signal so that the reader can understand and discern between the two different
definitions when used.
The first definition used to describe a differential signal is the absolute value of the voltage potential between the
inverting and noninverting signal. The symbol for this first measurement is typically VID or VOD depending on if an
input or output voltage is being described.
The second definition used to describe a differential signal is to measure the potential of the noninverting signal
with respect to the inverting signal. The symbol for this second measurement is VSS and is a calculated
parameter. Nowhere in the IC does this signal exist with respect to ground, it only exists in reference to its
differential pair. VSS can be measured directly by oscilloscopes with floating references, otherwise this value can
be calculated as twice the value of VOD as described in the first description.
Figure 5 shows the two different definitions side-by-side for inputs and Figure 6 shows the two different
definitions side-by-side for outputs. The VID and VOD definitions show VA and VB DC levels that the noninverting
and inverting signals toggle between with respect to ground. VSS input and output definitions show that if the
inverting signal is considered the voltage potential reference, the noninverting signal voltage potential is now
increasing and decreasing above and below the noninverting reference. Thus the peak-to-peak voltage of the
differential signal can be measured.
VID and VOD are often defined as volts (V) and VSS is often defined as volts peak-to-peak (VPP).
VID Definition
VSS Definition for Input
Non-Inverting Clock
VA
2· VID
VID
VB
Inverting Clock
VSS = 2· VID
VID = | VA - VB |
GND
Figure 5. Two Different Definitions for Differential Input Signals
VOD Definition
VSS Definition for Output
Non-Inverting Clock
VA
2· VOD
VOD
VB
Inverting Clock
VOD = | VA - VB |
VSS = 2· VOD
GND
Figure 6. Two Different Definitions for Differential Output Signals
Refer to AN-912 Common Data Transmission Parameters and their Definitions (SNLA036) for more information.
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8 Detailed Description
8.1 Overview
In default mode of operation, dual PLL mode with internal VCO, the phase frequency detector in PLL1 compares
the active CLKinX reference divided by CLKinX_PreR_DIV and PLL1 R divider with the external VCXO or crystal
attached to the PLL2 OSCin port divided by PLL1 N divider. The external loop filter for PLL1 must be narrow to
provide an ultra clean reference clock from the external VCXO or crystal to the OSCin/OSCin* pins for PLL2.
The phase frequency detector in PLL2 compares the external VCXO or crystal attached to the OCSin port
divided by the PLL2 R divider with the output of the internal VCO divided by the PLL2 N divider and N2 prescaler and optionally the VCO divider. The bandwidth of the external loop filter for PLL2 must be designed to be
wide enough to take advantage of the low in-band phase noise of PLL2 and the low high offset phase noise of
the internal VCO. The VCO output is also placed on the distribution path for the Clock Distribution section. The
clock distribution consists of 6 groups of dividers and delays which drive 12 outputs. Each clock group allows the
user to select a divide value, a digital delay value, and an analog delay. The 6 groups drive programmable output
buffers. Two groups allow their input signal to be from the OSCin port directly.
When a 0-delay mode is used, a clock output is passed through the feedback mux to the PLL1 N Divider for
synchronization and 0-delay.
When an external VCO mode is used, the Fin port is used to input an external VCO signal. PLL2 Phase
comparison is now with this signal divided by the PLL2 N divider and N2 pre-scaler. The VCO divider may not be
used. One less clock input is available when using an external VCO mode.
When a single PLL mode is used, PLL1 is powered down. OSCin is used as a reference to PLL2.
8.1.1 System Architecture
The dual-loop PLL architecture of the LMK04816 provides the lowest jitter performance over the widest range of
output frequencies and phase noise integration bandwidths. The first stage PLL (PLL1) is driven by an external
reference clock and uses an external VCXO or tunable crystal to provide a frequency accurate, low phase noise
reference clock for the second stage frequency multiplication PLL (PLL2). PLL1 typically uses a narrow loop
bandwidth (10 Hz to 200 Hz) to retain the frequency accuracy of the reference clock input signal while at the
same time suppressing the higher offset frequency phase noise that the reference clock may have accumulated
along its path or from other circuits. This cleaned reference clock provides the reference input to PLL2.
The low phase noise reference provided to PLL2 allows PLL2 to operate with a wide loop bandwidth (50 kHz to
200 kHz). The loop bandwidth for PLL2 is chosen to take advantage of the superior high offset frequency phase
noise profile of the internal VCO and the good low offset frequency phase noise of the reference VCXO or
tunable crystal.
Ultralow jitter is achieved by allowing the phase noise of the external VCXO or Crystal to dominate the final
output phase noise at low offset frequencies and phase noise of the internal VCO to dominate the final output
phase noise at high offset frequencies. This results in best overall phase noise and jitter performance.
The LMK04816 allows subsets of the device to be used to increase the flexibility of device. These different
modes are selected using MODE: Device Mode. For instance:
• Dual-Loop Mode - Typical use case of LMK04816. CLKinX used as reference input to PLL1, OSCin port is
connected to VCXO or tunable crystal.
• Single-Loop Mode - Powers down PLL1. OSCin port is used as reference input.
• Clock Distribution Mode - Allows input of CLKin1 to be distributed to output with division, digital delay, and
analog delay.
See Device Functional Modes for more information on these modes.
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Overview (continued)
8.1.2 PLL1 Redundant Reference Inputs (CLKin0/CLKin0*, CLKin1/CLKin1*, and CLKin2/CLKin2*)
The LMK04816 has three reference clock inputs for PLL1, CLKin0, CLKin1, and CLKin2. Ref Mux selects
CLKin0, CLKin1, or CLKin2. Automatic or manual switching occurs between the inputs.
CLKin0, CLKin1, and CLKin2 each have input dividers. The input divider allows different clock input frequencies
to be normalized so that the frequency input to the PLL1 R divider remains constant during automatic switching.
By programming these dividers such that the frequency presented to the input of the PLL1_R divider is the same
prevents the user from needing to reprogram the PLL1 R divider when the input reference is changed to another
CLKin port with a different frequency.
CLKin1 is shared for use as an external 0-delay feedback (FBCLKin), or for use with an external VCO (Fin).
Fast manual switching between reference clocks is possible with a external pins Status_CLKin0, Status_CLKin1,
Status_CLKin2.
8.1.3 PLL1 Tunable Crystal Support
The LMK04816 integrates a crystal oscillator on PLL1 for use with an external crystal and varactor diode to
perform jitter cleaning.
The LMK04816 must be programmed to enable Crystal mode.
8.1.4 VCXO and CRYSTAL-Buffered Outputs
The LMK04816 provides a dedicated output which is a buffered copy of the PLL2 reference input. This reference
input is typically a low-noise VCXO or Crystal. When using a VCXO, this output can be used to clock external
devices such as microcontrollers, FPGAs, CPLDs, and so forth. before the LMK04816 is programmed.
The OSCout0 buffer output type is programmable to LVDS, LVPECL, or LVCMOS.
The dedicated output buffer OSCout0 can output frequency lower than the VCXO or Crystal frequency by
programming the OSC Divider. The OSC Divider value range is 1 to 8. Each OSCoutX can individually choose to
use the OSC Divider output or to bypass the OSC divider.
Two clock output groups can also be programmed to be driven by OSCin. This allows a total of 4 additional
differential outputs to be buffered outputs of OSCin. When programmed in this way, a total of 6 differential
outputs can be driven by a buffered copy of OSCin.
VCXO and Crystal-buffered outputs cannot be synchronized to the VCO clock distribution outputs. The assertion
of SYNC still causes these outputs to become low. Because these outputs turn off and on asynchronously with
respect to the VCO sourced clock outputs during a SYNC, it is possible for glitches to occur on the buffered clock
outputs when SYNC is asserted and unasserted. If the NO_SYNC_CLKoutX_Y bits are set these outputs are not
affected by the SYNC event except that the phase relationship changes with the other synchronized clocks
unless a buffered clock output is used as a qualification clock during SYNC.
8.1.5 Frequency Holdover
The LMK04816 supports holdover operation to keep the clock outputs on frequency with minimum drift when the
reference is lost until a valid reference clock signal is re-established.
8.1.6 Integrated Loop Filter Poles
The LMK04816 features programmable 3rd and 4th order loop filter poles for PLL2. These internal resistors and
capacitor values may be selected from a fixed range of values to achieve either a 3rd or 4th order loop filter
response. The integrated programmable resistors and capacitors compliment external components mounted near
the chip.
These integrated components can be effectively disabled by programming the integrated resistors and capacitors
to their minimum values.
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Overview (continued)
8.1.7 Internal VCO
The output of the internal VCO is routed to a mux which allows the user to select either the direct VCO output or
a divided version of the VCO for the clock distribution path. This same selection is also fed back to the PLL2
phase detector through a prescaler and N-divider.
The mux selectable VCO divider has a divide range of 2 to 8 with 50% output duty cycle for both even and odd
divide values.
The primary use of the VCO divider is to achieve divides greater than the clock output divider supports alone.
8.1.8 External VCO Mode
The Fin/Fin* input allows an external VCO to be used with PLL2 of the LMK04816.
Using an external VCO reduces the number of available clock inputs by one.
8.1.9 Clock Distribution
The LMK04816 features a total of 12 outputs driven from the internal or external VCO.
All VCO driven outputs have programmable output types. They can be programmed to LVPECL, LVDS, or
LVCMOS. When all distribution outputs are configured for LVCMOS or single ended LVPECL a total of 24
outputs are available.
If the buffered OSCin output OSCout0 is included in the total number of clock outputs the LMK04816 is able to
distribute, then up to 13 differential clocks or up to 26 single-ended clocks may be generated with the LMK04816.
The following sections discuss specific features of the clock distribution channels that allow the user to control
various aspects of the output clocks.
8.1.9.1 CLKout Divider
Each clock group, which is a pair of outputs such as CLKout0 and CLKout1, has a single clock output divider.
The divider supports a divide range of 1 to 1045 (even and odd) with 50% output duty cycle. When divides of 26
or greater are used, the divider an delay block uses extended mode.
The VCO Divider may be used to reduce the divide needed by the clock group divider so that it may operate in
normal mode instead of extended mode. This can result in a small current saving if enabling the VCO divider
allows 3 or more clock output divides to change from extended to normal mode.
8.1.9.2 CLKout Delay
The clock distribution section includes both a fine (analog) and coarse (digital) delay for phase adjustment of the
clock outputs.
The fine (analog) delay allows a nominal 25-ps step size and range from 0 to 475 ps of total delay. Enabling the
analog delay adds a nominal 500 ps of delay in addition to the programmed value. When adjusting analog delay,
glitches may occur on the clock outputs being adjusted. Analog delay may not operate at frequencies above the
minimum-ensured maximum output frequency of 1536 MHz.
The coarse (digital) delay allows a group of outputs to be delayed by 4.5 to 12 clock distribution path cycles in
normal mode, or from 12.5 to 522 VCO cycles in extended mode. The delay step can be as small as half the
period of the clock distribution path by using the CLKoutX_Y_HS bit provided the output divide value is greater
than 1. For example, 2-GHz VCO frequency without using the VCO divider results in 250-ps coarse tuning steps.
The coarse (digital) delay value takes effect on the clock outputs after a SYNC event.
There are 3 different ways to use the digital (coarse) delay.
1. Fixed Digital Delay
2. Absolute Dynamic Digital Delay
3. Relative Dynamic Digital Delay
These are further discussed in the Device Functional Modes.
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Overview (continued)
8.1.9.3 Programmable Output Type
For increased flexibility all LMK04816 clock outputs (CLKoutX) and OSCout0 can be programmed to an LVDS,
LVPECL, or LVCMOS output type.
Any LVPECL output type can be programmed to 700, 1200, 1600, or 2000-mVpp amplitude levels. The 2000mVpp LVPECL output type is a Texas Instruments proprietary configuration that produces a 2000-mVpp
differential swing for compatibility with many data converters and is also known as 2VPECL.
8.1.9.4 Clock Output Synchronization
Using the SYNC input causes all active clock outputs to share a rising edge. See Clock Output Synchronization
(SYNC) for more information.
The SYNC event also causes the digital delay values to take effect.
8.1.10 0-Delay
The 0-delay mode synchronizes the input clock phase to the output clock phase. The 0-delay feedback may
performed with an internal feedback loop from any of the clock groups or with an external feedback loop into the
FBCLKin port as selected by the FEEDBACK_MUX.
Without using 0-delay mode, there are n possible fixed phase relationships from clock input to clock output
depending on the clock output divide value.
Using an external 0-delay feedback reduces the number of available clock inputs by one.
8.1.11 Default Start-Up Clocks
Before the LMK04816 is programmed, CLKout8 is enabled and operating at a nominal frequency and CLKout6
and OSCout0 are enabled and operating at the OSCin frequency. These clocks can be used to clock external
devices such as microcontrollers, FPGAs, CPLDs, and so forth, before the LMK04816 is programmed.
For CLKout6 and OSCout0 to work before the LMK04816 is programmed the device must not be using Crystal
mode.
8.1.12 Status Pins
The LMK04816 provides status pins which can be monitored for feedback or in some cases used for input
depending upon device programming. For example:
• The Status_Holdover pin may indicate if the device is in holdover mode.
• The Status_CLKin0 pin may indicate the LOS (loss-of-signal) for CLKin0.
• The Status_CLKin0 pin may be an input for selecting the active clock input.
• The Status_LD pin may indicate if the device is locked.
The status pins can be programmed to a variety of other outputs including analog lock detect, PLL divider
outputs, combined PLL lock detect signals, PLL1 Vtune railing, readback, etc. Refer to the MICROWIRE
programming section of this datasheet for more information. Default pin programming is captured in Table 17.
8.1.13 Register Readback
Programmed registers may be read back using the MICROWIRE interface. For readback one of the status pins
must be programmed for readback mode.
At no time may registers be programed to values other than the valid states defined in the datasheet.
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8.2 Functional Block Diagram
CLKin2 Divider
(1, 2, 4, or 8)
CLKin0*
CLKin0
CLKin0 Divider
(1, 2, 4, or 8)
CLKin1*/Fin*
FBCLKin*
CLKin1/
Fin/FBCLKin
CLKin1 Divider
(1, 2, 4, or 8)
Fin/Fin*
CLKout0
CLKout2
CLKout4
CLKout6
CLKout8
CLKout10
OSCout0
OSCout0*
Ref
Mux
OSCout0
_MUX
R Delay
Phase
Detector
PLL1
N1 Divider
(1 to 16,383)
N Delay
Mode
Mux2
2X
Mux
OSC Divider
(2 to 8)
R2 Divider
(1 to 4,095)
N2 Divider
(1 to 262,143)
Mode
Mux3
OSCin*
OSCin
Mux
Delay
CLKout1
CLKout1*
Mux
CLKout2
CLKout2*
Mux
Divider
(1 to 1045)
PWire
Port
DATAuWire
2X
Clock Group 0
Clock Group 1
Delay
Mux
CLKout4
CLKout4*
Mux
Digital
Delay
Phase
Detector
PLL2
Clock Distribution Path
Osc
Mux1
Mode
Mux1
Partially
Integrated
Loop Filter
VCO
Mux
Internal VCO
VCO Divider
(2 to 8)
Mux
Digital
Delay
Divider
(1 to 1045)
Divider
(1 to 1045)
Digital
Delay
Osc
Mux2
Digital
Delay
Divider
(1 to 1045)
Delay
Divider
(1 to 1045)
Digital
Delay
Digital
Delay
Divider
(1 to 1045)
Mux
Mux
CLKout7
CLKout7*
Mux
CLKout8
CLKout8*
Clock Group 4
Delay
Mux
CLKout9
CLKout9*
Mux
CLKout10
CLKout10*
Clock Group 5
Delay
Mux
Clock Buffer 2
Clock Buffer 1
Fin/Fin*
CLKout6
CLKout6*
Clock Group 3
Delay
Clock Buffer 3
Clock Group 2
Status_CLKin0
Control
Registers
Clock Buffer 1
CLKout3
CLKout3*
Status_Holdover
LEuWire
N2 Prescaler
(2 to 8)
CLKout0
CLKout0*
Device
Control
CLKuWire
Holdover
FB
Mux
Status_LD
SYNC/
Status_
CLKin2
Status_CLKin1
FBMux
FBMux
CLKout5
CLKout5*
R1 Divider
(1 to 16,383)
CPout2
CLKin2*
CLKin2
CPout1
Figure 7 shows the complete LMK04816 block diagram for the LMK04816.
CLKout11
CLKout11*
Figure 7. Detailed LMK04816 Block Diagram
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8.3 Feature Description
8.3.1 Serial MICROWIRE Timing Diagram
For timing specifications, see Timing Requirements. Register programming information on the DATAuWire pin is
clocked into a shift register on each rising edge of the CLKuWire signal. On the rising edge of the LEuWire
signal, the register is sent from the shift register to the register addressed. A slew rate of at least 30 V/µs is
recommended for these signals. After programming is complete the CLKuWire, DATAuWire, and LEuWire
signals must be returned to a low state. If the CLKuWire or DATAuWire lines are toggled while the VCO is in
lock, as is sometimes the case when these lines are shared with other parts, the phase noise may be degraded
during this programming.
MSB
DATAuWire
LSB
D26
D25
D24
D23
D22
D0
A4
A1
A0
CLKuWire
tECS
tCES
tDCS
tCDH
tCWH
tECS
tCWL
LEuWire
tEWH
Figure 8. MICROWIRE Input Timing Diagram
8.3.2 Advanced MICROWIRE Timing Diagrams
8.3.2.1 Three Extra Clocks or Double Program
For timing specifications, see Timing Requirements. Figure 9 shows the timing for the programming sequence for
loading CLKoutX_Y_DIV > 25 or CLKoutX_Y_DDLY > 12 as described in Special Programming Case for R0 to
R5 for CLKoutX_Y_DIV and CLKoutX_Y_DDLY.
DATAuWire
MSB
LSB
D26
A0
CLKuWire
tCES
tECS
tCWL
LEuWire
tCWH
tEWH
Figure 9. MICROWIRE Timing Diagram: Extra CLKuWire Pulses for R0 to R5
8.3.2.2 Three Extra Clocks with LEuWire High
For timing specifications, see Timing Requirements. Figure 10 shows the timing for the programming sequence
which allows SYNC_EN_AUTO = 1 when loading CLKoutX_Y_DIV > 25 or CLKoutX_Y_DDLY > 12. When
SYNC_EN_AUTO = 1, a SYNC event is automatically generated on the falling edge of LEuWire. See Special
Programming Case for R0 to R5 for CLKoutX_Y_DIV and CLKoutX_Y_DDLY.
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Feature Description (continued)
DATAuWire
MSB
LSB
D26
A0
CLKuWire
tECS
tCES
tCES
LEuWire
Figure 10. MICROWIRE Timing Diagram: Extra CLKuWire Pulses for R0 to R5 with LEuWire Asserted
8.3.2.3 Readback
For timing specifications, see Timing Requirements. See Readback for more information on performing a
readback operation. Figure 11 shows timing for LEuWire for both READBACK_LE = 1 and 0.
The rising edges of CLKuWire during MICROWIRE readback continue to clock data on DATAuWire into the
device during readback. If after the readback, LEuWire transitions from low to high, this clock data is latched to
the decoded register. The decoded register address consists of the last 5 bits clocked on DATAuWire as shown
in the MICROWIRE Timing Diagrams.
DATAuWire
MSB
LSB
D26
A0
CLKuWire
tCR
tECS
tCWH
tCR
tCWL
LEuWire
READBACK_LE = 0
tCES
tEWH
tECS
LEuWire
READBACK_LE = 1
Readback Pin
RD26
Register Write
RD25
RD24
RD23
RD0
Register Read
Figure 11. MICROWIRE Readback Timing Diagram
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Feature Description (continued)
8.3.3 Inputs and Outputs
8.3.3.1 PLL1 Reference Inputs (CLKin0, CLKin1, and CLKin2)
The reference clock inputs for PLL1 may be selected from either CLKin0, CLKin1, or CLKin2. The user has the
capability to manually select one of the inputs or to configure an automatic switching mode of operation. See
Input Clock Switching for more info.
CLKin0, CLKin1, and CLKin2 have dividers which allow the device to switch between reference inputs of different
frequencies automatically without needing to reprogram the PLL1 R divider. The CLKin pre-divider values are 1,
2, 4, and 8.
CLKin1 input can alternatively be used for external feedback in 0-delay mode (FBCLKin) or for an external VCO
input port (Fin).
8.3.3.2 PLL2 OSCin and OSCin* Port
The feedback from the external oscillator being locked with PLL1 drives the OSCin and OSCin* pins. Internally
this signal is routed to the PLL1 N Divider and to the reference input for PLL2.
This input may be driven with either a single-ended or differential signal and must be AC-coupled. If operated in
single-ended mode, the unused input must be connected to GND with a 0.1-µF capacitor.
8.3.3.3 Crystal Oscillator
The internal circuitry of the OSCin port also supports the optional implementation of a crystal based oscillator
circuit. A crystal, a varactor diode, and a small number of other external components may be used to implement
the oscillator. The internal oscillator circuit is enabled by setting the EN_PLL2_XTAL bit. See EN_PLL2_XTAL.
8.3.4 Input Clock Switching
Manual, pin select, and automatic are three different kinds clock input switching modes can be set with the
CLKin_SELECT_MODE register.
Below is information about how the active input clock is selected and what causes a switching event in the
various clock input selection modes.
8.3.4.1 Input Clock Switching - Manual Mode
When CLKin_SELECT_MODE is 0, 1, or 2 then CLKin0, CLKin1, or CLKin2 respectively is always selected as
the active input clock. Manual mode also overrides the EN_CLKinX bits such that the CLKinX buffer operates
even if CLKinX is is disabled with EN_CLKinX = 0.
• Entering Holdover: If holdover mode is enabled then holdover mode is entered if: Digital lock detect of PLL1
goes low and DISABLE_DLD1_DET = 0.
• Exiting Holdover: The active clock for automatic exit of holdover mode is the manually selected clock input.
8.3.4.2 Input Clock Switching - Pin Select Mode
When CLKin_SELECT_MODE is 3, the pins Status_CLKin0 and Status_CLKin1 select which clock input is
active.
• Clock Switch Event: Pins: Changing the state of Status_CLKin0 or Status_CLKin1 pins causes an input
clock switch event.
• Clock Switch Event: PLL1 DLD: To prevent PLL1 DLD high to low transition from causing a input clock
switch event and causing the device to enter holdover mode, disable the PLL1 DLD detect by setting
DISABLE_DLD1_DET = 1. This is the preferred behavior for pin select mode.
• Configuring Pin Select Mode:
– The Status_CLKin0_TYPE must be programmed to an input value for the Status_CLKin0 pin to function
as an input for pin select mode.
– The Status_CLKin1_TYPE must be programmed to an input value for the Status_CLKin1 pin to function
as an input for pin select mode.
– If the Status_CLKinX_TYPE is set as output, the input value is considered 0.
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Feature Description (continued)
– The polarity of Status_CLKin1 and Status_CLKin0 input pins can be inverted with the CLKin_SEL_INV bit.
– Table 1 defines which input clock is active depending on Status_CLKin0 and Status_CLKin1 state.
Table 1. Active Clock Input - Pin Select Mode
STATUS_CLKin1
STATUS_CLKin0
ACTIVE CLOCK
0
0
CLKin0
0
1
CLKin1
1
0
CLKin2
1
1
Holdover
The pin select mode overrides the EN_CLKinX bits such that the CLKinX buffer operates even if CLKinX is is
disabled with EN_CLKinX = 0. To switch as fast as possible, keep the clock input buffers enabled
(EN_CLKinX = 1) that could be switched to.
8.3.4.2.1 Pin Select Mode and Host
When in the pin select mode, the host can monitor conditions of the clocking system which could cause the host
to switch the active clock input. The LMK04816 device can also provide indicators on the Status_LD and
Status_HOLDOVER like DAC Rail, PLL1 DLD, PLL1 and PLL2 DLD which the host can use in determining which
clock input to use as active clock input.
8.3.4.2.2 Switch Event Without Holdover
When an input clock switch event is triggered and holdover mode is disabled, the active clock input immediately
switches to the selected clock. When PLL1 is designed with a narrow loop bandwidth, the switching transient is
minimized.
8.3.4.2.3 Switch Event With Holdover
When an input clock switch event is triggered and holdover mode is enabled, the device enters holdover mode
and remains in holdover until a holdover exit condition is met as described in Holdover Mode. Then, the device
completes the reference switch to the pin selected clock input.
8.3.4.3 Input Clock Switching - Automatic Mode
When CLKin_SELECT_MODE is 4, the active clock is selected in priority order of enabled clock inputs starting
upon an input clock switch event. The priority order of the clocks is CLKin0 → CLKin1 → CLKin2, and so forth.
For a clock input to be eligible to be switched through, it must be enabled using EN_CLKinX.
• Starting Active Clock: Upon programming this mode, the currently active clock remains active if PLL1 lock
detect is high. To ensure a particular clock input is the active clock when starting this mode, program
CLKin_SELECT_MODE to the manual mode which selects the desired clock input (CLKin0, 1, or 2). Wait for
PLL1 to lock PLL1_DLD = 1, then select this mode with CLKin_SELECT_MODE = 4.
• Clock Switch Event: PLL1 DLD: A loss of lock as indicated by the DLD signal of the PLL1 (PLL1_DLD = 0)
causes an input clock switch event if DISABLE_DLD1_DET = 0. PLL1 DLD must go high (PLL1_DLD = 1) in
between input clock switching events.
• Clock Switch Event: PLL1 Vtune Rail: If Vtune_RAIL_DET_EN is set and the PLL1 Vtune voltage crosses
the DAC high or low threshold, holdover mode is entered. Because PLL1_DLD = 0 in holdover a clock input
switching event occurs.
• Clock Switch Event with Holdover: If holdover is enabled and an input clock switch event occurs, holdover
mode is entered and the active clock is set to the next enabled clock input in priority order. When the new
active clock meets the holdover exit conditions, holdover is exited and the active clock continues to be used
as a reference until another PLL1 loss of lock event. PLL1 DLD must go high in between input clock switching
events.
• Clock Switch Event without Holdover: If holdover is not enabled and an input clock switch event occurs,
the active clock is set to the next enabled clock in priority order. The LMK04816 keeps this new input clock as
the active clock until another input clock switching event. PLL1 DLD must go high in between input clock
switching events.
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8.3.4.4 Input Clock Switching - Automatic Mode With Pin Select
When CLKin_SELECT_MODE is 6, the active clock is selected using the Status_CLKinX pins upon an input
clock switch event according to Table 2.
• Starting Active Clock: Upon programming this mode, the currently active clock remains active if PLL1 lock
detect is high. To ensure a particular clock input is the active clock when starting this mode, program
CLKin_SELECT_MODE to the manual mode which selects the desired clock input (CLKin0 or 1). Wait for
PLL1 to lock PLL1_DLD = 1, then select this mode with CLKin_SELECT_MODE = 6.
• Clock Switch Event: PLL1 DLD: An input clock switch event is generated by a loss of lock as indicated by
the DLD signal of the PLL! (PLL1 DLD = 0).
• Clock Switch Event: PLL1 Vtune Rail: If Vtune_RAIL_DET_EN is set and the PLL1 Vtune voltage crosses
the DAC threshold, holdover mode is entered. Because PLL1_DLD = 0 in holdover, a clock input switching
event occurs.
• Clock Switch Event with Holdover: If holdover is enabled and an input clock switch event occurs, holdover
mode is entered and the active clock is set to the clock input defined by the Status_CLKinX pins. When the
new active clock meets the holdover exit conditions, holdover is exited and the active clock continues to be
used as a reference until another input clock switch event. PLL1 DLD must go high in between input clock
switching events.
• Clock Switch Event without Holdover: If holdover is not enabled and an input clock switch event occurs,
the active clock is set to the clock input defined by the Status_CLKinX pins. The LMK04816 keeps this new
input clock as the active clock until another input clock switching event. PLL1 DLD must go high in between
input clock switching events.
Table 2. Active Clock Input - Auto Pin Mode
STATUS_CLKin1
STATUS_CLKin0
ACTIVE CLOCK
X
1
CLKin0
1
0
CLKin1
0
0
CLKin2
The polarity of Status_CLKin1 and Status_CLKin0 input pins can be inverted with the CLKin_SEL_INV bit.
8.3.5 Holdover Mode
Holdover mode causes PLL2 to stay locked on frequency with minimal frequency drift when an input clock
reference to PLL1 becomes invalid. While in holdover mode, the PLL1 charge pump is tri-stated and a fixed
tuning voltage is set on CPout1 to operate PLL1 in open-loop.
8.3.5.1 Enable Holdover
Program HOLDOVER_MODE to enable holdover mode. Holdover mode can be manually enabled by
programming the FORCE_HOLDOVER bit.
The holdover mode can be set to operate in 2 different sub-modes.
• Fixed CPout1 (EN_TRACK = 0 or 1, EN_MAN_DAC = 1).
• Tracked CPout1 (EN_TRACK = 1, EN_MAN_DAC = 0).
– Not valid when EN_VTUNE_RAIL_DET = 1.
Updates to the DAC value for the Tracked CPout1 sub-mode occurs at the rate of the PLL1 phase detector
frequency divided by DAC_CLK_DIV. These updates occur any time EN_TRACK = 1.
The DAC update rate must be programmed for 100 × loop bandwidth may experience increased
lock time due to cycle slipping.
3. PLL Loop Filter Design
– TI recommends using clock design tool or clock architect to design your loop filter.
– Best loop filter design and simulation can be achieved when:
– Custom reference and VCXO phase noise profiles are loaded into the software.
– VCO gain of the external VCXO or possible external VCO device are entered.
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Typical Application (continued)
– The clock design tool returns solutions with high reference and phase detector frequencies by default. In
the clock design tool the user may increase the reference divider to reduce the frequency if desired. Due
to the narrow loop bandwidth used on PLL1, it is common to lower the phase detector frequency on PLL1
to reduce component size.
– While designing loop filter, adjusting the charge-pump current or N value can help with loop filter
component selection. Lower charge-pump currents and larger N values result in smaller component
values but may increase impacts of leakage and reduce PLL phase noise performance. – More detailed
understanding of loop filter design can found in PLL Performance, Simulation, and Design
(www.ti.com/tool/pll_book).
4. Clock Output Assignment
– At this time the design software does not take into account frequency assignment to specific outputs
except to ensure that the output frequencies can be achieved. It is best to consider proximity of each
clock output to each other and other PLL circuitry when choosing final clock output locations. Here are
some guidelines to help achieve best performance when assigning outputs to specific CLKout and
OSCout pins.
– Group common frequencies together.
– PLL charge-pump circuitry can cause crosstalk at charge pump frequency. Place outputs sharing
charge-pump frequency or lower priority outputs not sensitive to charge-pump frequency spurs
together.
– Muxes can create a path for noise coupling. Consider all frequencies which may have some bleed
through from non-selected mux inputs.
– For example, LMK04816 CLKout6/7 and CLKout8/9 share a mux with OSCin.
– Some clock targets require low close-in phase noise. If possible, use a VCXO based PLL1 output for
such a clock target. An example is a clock to a PLL reference.
– Some clock targets require excellent noise floor performance. Outputs driven by the internal VCO have
the best noise floor performance. An example is an ADC or DAC.
5. Other device specific configuration. For LMK04816, consider the following:
– PLL lock time based on programming:
– In addition to the time it takes the device to lock to frequency, there is a digital filter to avoid false lock
time detects which can also be used to ensure a specific PPM frequency accuracy. This also impacts
the time it takes for the digital lock detect (DLD) pin to be asserted. Refer to Digital Lock Detect
Frequency Accuracy for more information.
– Holdover configuration:
– Specific PPM frequency accuracy required to exit holdover can be programmed. Refer to Digital Lock
Detect Frequency Accuracy for more information.
– Digital delay: phase alignment of the output clocks.
– Analog delay: another method to shift phases of clocks with finer resolution with the penalty of increase
noise floor. Clock design tool can simulate analog delay impact on phase noise floor.
– Dynamic digital delay: ability to shift phase alignment of clocks with minimum disruption during operation.
6. Device Programming
– The software tool CodeLoader for EVM programming can be used to set up the device in the desired
configuration, then export a hex register map suitable for use in application.
Some additional information on each part of the design procedure for the RRU example is in the following
subsections.
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Typical Application (continued)
9.2.2.1 Device Selection
Use the WEBENCH clock architect tool or clock design tool. Enter the required frequencies and formats into the
tool. To use this device, find a solution using the LMK04816.
9.2.2.1.1 Clock Architect
When viewing resulting solutions, it is possible to narrow the parts used in the solution by setting a filter.
Under advanced tab, filtering of specific parts can be done using regular expressions in the part filter box.
LMK04816 filters for only the LMK04816 devices.
9.2.2.1.2 Clock Design Tool
In wizard-mode, select Dual Loop PLL to find the LMK04816 device. If a high frequency and clean reference is
available, Although dual-loop mode is selected as a customer requirement, it is not required to use dual loop;
PLL1 can be powered down and input is then provided through the OSCin port. When simulating single-loop
solutions, set PLL1 loop filter block to 0 Hz LBW and use VCXO as the reference block.
9.2.2.1.3 Calculation Using LCM
In this example, the LCM (245.76 MHz, 491.52 MHz, 122.88 MHz) = 491.52 MHz. A valid VCO frequency for
LMK04816 is 2457.6 MHz = 5 × 491.52 MHz. Therefore the LMK04816 may be used to produce these output
frequencies.
9.2.2.2 Device Configuration
The tools automatically configure the simulation to meet the input and output frequency requirements given and
make assumptions about other parameters to give some default simulations. The assumptions made are to
maximize input frequencies, phase detector frequencies, and charge-pump currents while minimizing VCO
frequency and divider values.
For this example, when using the clock design tool, the reference would have been manually entered as 30.72
MHz according to input frequency requirements, but the tool allows VCXO1 frequency either to be set manually,
auto-selected according to standard frequencies, or auto-selected for best frequency. With the best-frequency
option, the highest possible VCXO frequency which gives the highest possible PLL2 PDF frequency is
recommended first. In this case: 421 + 53 / 175 MHz VCXO resulting in a 140 + 76 / 175 MHz phase detector
frequency. This is a high phase detector frequency, but the VCXO is likely going to be a custom order. The
select configuration page just before simulation shows before some different configurations possible with different
VCO divider values. For example, a more common 491.52-MHz frequency provides a 122.88-MHz PDF. This is a
more logical configuration.
From the simulation page of clock design tool, it can be seen that the VCXO frequency of 491.52 MHz is too high
for feedback into the PLL1_N divider. Reducing the VCXO frequency to 245.76 MHz resolves the PLL1_N divider
maximum input frequency problem. The PLL2 R divider must be updated to 2 so that the VCO of PLL2 is still at
2457.6 MHz.
At this point the design meets all input and output frequency requirements and it is possible to design a loop filter
for system and simulate performance on CLKouts. However, consider also the following:
• At this time the clock design tool does not assign outputs strategically for jitter, such as PLL1 vs PLL2. If
PLL1 output frequency is high enough, it may have improved jitter performance depending on the noise floor
and application required integration range.
• The clock design tool does not consider power on reset clocks in the clock requirements or assignments.
• The clock design tool simplifies the LMK04816 architecture not showing the mux complexity around
OSCout0/1 and not showing OSCout1. Simulation of OSCout0 is equivalent to OSCout1.
The next section addresses how the user may alter the design when considering these items.
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Typical Application (continued)
9.2.2.2.1 PLL LO Reference
PLL1 outputs have the best phase noise performance for LO references. As such OSCout0 can be used to
provide the 122.88-MHz LO reference clock. To achieve this with the 245.76-MHz VCXO the OSCout_DIV can
be set to 2 to provide 122.88 MHz at OSCout0. However, in the next section it is determined that for the POR
clock, a 122.88-MHz VCXO is chosen which results in not needing to change this parameter.
9.2.2.2.2 POR Clock
If OSCout1 is to be used for LVPECL POR 122.88-MHz clock, the POR value of the OSCout_DIV is 1, so a
122.88-MHz VCXO frequency must be chosen. This may be desired anyway because the phase detector
frequency is limited to 122.88 MHz and lower frequency VCXOs tend to cost less. With this change the OSCin
frequency and phase detector frequency are the same, so the doubler must be enabled and the PLL2 R divider
programmed = 2 to follow the rule stated in PLL2 Frequency Doubler . Because the clock design tool does not
show the doubler, PLL2_Rstill reflects the value one for simulation purposes.
If LVDS was required for POR clock, a voltage divider could be used to convert from LVPECL to LVDS.
At this time the main design updates have been made to support the POR clock and loop filter design may begin.
9.2.2.3 PLL Loop Filter Design
The PLL structure for the LMK04816 is shown in Loop Filter.
At this time the user may choose to make adjustments to the simulation tools for more accurate simulations to
their application. For example:
• Clock design tool allows loading a custom phase noise plot for any block. Typically, a custom phase noise
plot is entered for CLKin to match the reference phase noise to the device; a phase noise plot for the VCXO
can additionally be provided to match the performance of VCXO used. For improved accuracy in simulation
and optimum loop filter design, be sure to load these custom noise profiles for use in application. After
loading a phase noise plot, user must recalculate the recommended loop filter design.
• The clock design tool returns solutions with high reference or phase detector frequencies by default. In the
clock design tool the user may increase the reference divider to reduce the frequency if desired. Due to the
narrow loop bandwidth used on PLL1, it is common to reduce the phase detector frequency on PLL1 by
increasing PLL1 R.
For this example, for PLL1 to perform jitter cleaning and to minimize jitter from PLL2 used for frequency
multiplication:
• PLL1: A narrow loop bandwidth PLL1 filter was design by updating the loop bandwidth to 50 Hz and phase
margin to 50 degrees.
• PLL2:
– VCXO noise profile is measured, then loaded into VCXO block in clock design tool.
– The recommended loop filter is redesigned. Updates to the PLL1 loop filter and VCXO phase noise may
change the loop filter recommendation.
The next two sections discuss PLL1 and PLL2 loop filter design specific to this example using default phase
noise profiles.
NOTE
Clock Design Tool provides some recommend loop filters upon first load of the simulation.
Anytime PLL related inputs change like an input phase noise, charge-pump current,
divider values, and so forth. it is best to re-design the PLL1 loop filter to the recommended
design or your desired parameters. After PLL1, then update the PLL2 loop filter in the
same way to keep the loop filters designed and optimized for the application. Because
PLL1 loop filter design may impact PLL2 loop filter design, be sure to update the designs
in order.
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Typical Application (continued)
9.2.2.3.1 PLL1 Loop Filter Design
For this example, in the clock design tool simulator click on the PLL1 loop filter design button, then update the
loop bandwidth for 0.05 kHz and the phase margin for 50 degrees and press calculate. With the 30.72-MHz
phase detector frequency and 1.6-mA charge pump; the largest capacitor of the designed loop filter, the C2, is
27 μF. Supposing a goal of < 10 μF; setting PLL1 R = 4 and pressing the calculate again shows that C2 is 6.8
μF. Suppose that a reduction to < 1 μF is desired, continuing to increase the PLL1 R to 8 resulting in a phase
detector frequency of 3.84 MHz and reducing the charge pump current from 1.6 mA to 0.4 mA and calculating
again shows that C2 is 820 nF. As N was increased and charge pump decreased, this final design has R2 = 12
kΩ. The first design with low N value and high charge-pump current result in R2 = 390 Ω. The impact of the
thermal resistance is calculated in the tool. Viewing the simulation of the loop filter with the 12-kΩ resistor shows
that the thermal noise in the loop is not impacting performance.
It may be desired to design a 3rd order loop filter for additional attenuation input noise and spurs.
With the PLL1 loop filter design complete, loop filter of the PLL2 is ready to be designed.
9.2.2.3.2 PLL2 Loop Filter Design
In the clock design tool simulator, click on the PLL2 loop filter design button, then press recommend design. For
PLL2's loop filter maximum phase detector frequency and maximum charge-pump current are typically used.
Typically the jitter integration bandwidth includes the loop filter bandwidth for PLL2. The recommended loop filter
by the tools are designed to minimize jitter. The integrated loop filter components are minimized with this
recommendation as to allow maximum flexibility in achieve wide loop bandwidths for low PLL noise. With the
recommended loop filter calculated, this loop filter is ready to be simulated.
If using integrated components is desired, open the bode plot for the PLL2 loop filter, then make adjustments to
the integrated components. The effective loop bandwidth and phase margin with these updates is calculated.
The integrated loop filter components are good to use when attempting to eliminate some spurs because they
provide filtering after the bond wires. The recommended procedure is to increase C3 and C4 capacitance, then
R3 and R4 resistance. Large R3/R4 resistance can result in degraded VCO phase noise performance.
9.2.2.4 Clock Output Assignment
At this time the Clock Design Tool and Clock Architect only assign outputs to specific clock outputs numerically;
not necessarily by optimum configuration. The user may wish to make some educated re-assignment of outputs.
During device configuration, some output assignment was discussed because of the impact on the configuration
of the device relating to loop filter design, such as:
• In this example, OSCout1 can be used to provide the power-on reset (POR) start-up clock to the FPGA at
122.88 MHz because the VCXO frequency is the required output frequency.
• Because PLL1 outputs have best in-band noise, OSCout0 is used to provide LVCMOS output to the PLL
reference for the LO. LVCMOS (Norm/Inv) is used instead of LVCMOS (Norm/Norm) to reduce crosstalk. It is
also possible to use CLKout6/7 or CLKout8/9 for a PLL reference being driven from the VCXO. The noise
floor is higher, but close-in noise is typically of more concern because noise above the loop bandwidth of the
LO is dominated by the VCO of the LO. See Figure 40.
Because CLKout6/7 and CLKout8/9 have a mux allowing them to be driven by the VCXO and due there is a
chance for some 122.88-MHz crosstalk from the VCXO. The 122.88-MHz SERDES clock is placed on
CLKout6 because it is not sensitive to crosstalk as it is operating at the same frequency.
The two 245.76-MHz clocks and four 491.52-MHz clocks for the converters need to be discussed. There is
some flexibility in assignment. For example CLKout0/1 could operate at 245.76 MHz for the ADCs and then
CLKout2/3 and CLKout4/5 could operate at 491.52 MHz for the DAC. It is also possible to consider
CLKout2/3 for the ADC and position CLKout0/1 and CLKout10/11 for the DAC. The ADCs clock was placed
as far as possible from other clock which could result in sub-harmonic spurs because the ADC clock is often
the most sensitive.
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Typical Application (continued)
9.2.2.5 Other Device Specific Configuration
9.2.2.5.1 Digital Lock Detect
Digital lock time for PLL1 is ultimately dependent upon the programming of the PLL1_DLD_CNT register as
discussed in Digital Lock Detect Frequency Accuracy. Because the PLL1 phase detector frequency in this
example is 3.84 MHz, the lock time is equal to Equation 19.
1 / (PLL1_DLD_CNT × 3.84 MHz)
(19)
Digital lock time for PLL1 if PLL1_DLD_CNT = 10000 is just over 2.6 ms. When using holdover, it is very
important to program the PLL1_DLD_CNT to a value large enough to prevent false digital lock detect signals.
If PLL1_DLD_CNT is too small, when the device exits holdover and is re-locking, the DLD goes high while the
phase of the reference and feedback are within the specified window size because the programmed
PLL1_DLD_CNT is satisfied. However, if the loop has not yet settled to without the window size, when the
phases of the reference and feedback once again exceed the window size, the DLD returns low. Provided that
DISABLE_DLD1_DET = 0, the device once again enter holdover. Assuming that the reference clock is valid
because holdover was just exited, the exit criteria is met again, holdover exits, and PLL1 starts locking.
Unfortunately, the same sequence of events repeat resulting in oscillation out-of and back-into holdover. Setting
the PLL1_DLD_CNT to an appropriately large value prevents chattering of the PLL1 DLD signal and stable
holdover operation can be achieved.
Refer to Digital Lock Detect Frequency Accuracy for more detail on calculating exit times and how the
PLL1_DLD_CNT and PLL1_WND_SIZE work together.
9.2.2.5.2 Holdover
For this example, when the recovered clock is lost, the goal is to set the VCXO to Vcc / 2 until the recovered
clock returns. Holdover Mode contains detailed information on how to program holdover.
To
•
•
•
•
•
achieve the above goal, fixed holdover is used. Program:
HOLDOVER_MODE = 2 (Holdover enabled)
EN_TRACK = 0 (Tracking disabled)
EN_MAN_DAC = 1 (Use manual DAC for holdover voltage value)
MAN_DAC = 512 (Approximately Vcc / 2)
DISABLE_DLD1_DET = 0 (Use PLL1 DLD = Low to start holdover)
9.2.2.6 Device Programming
The CodeLoader software is used to program the LMK04816 evaluation board using the LMK04816 profile. It
also allows the exporting of a register map which can be used to program the device to the user’s desired
configuration.
Once a configuration of dividers has been achieved using the Clock Design Tool to meet the requested input and
output frequencies with the desired performance, the CodeLoader software is manually updated with this
information to meet the required application. At this time no automatic import exists.
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Typical Application (continued)
9.2.3 Application Curve
-130
VCO CLKoutX
VCXO CLKout6/7/8/9
VCXO OSCout0/1
VCXO Direct
Phase Noise (dBc/Hz)
-135
-140
-145
-150
-155
-160
-165
-170
1k
10k
100k
1M
Frequency Offset (Hz)
10M
D001
Figure 40. LVPECL Phase Noise, 122.88-MHz Illustration of Different Performance
Depending on Signal Path
9.3 System Examples
Figure 41 and Figure 42 show an LMK04816 with external circuitry for clocking and for power supply to serve as
a guideline for good practices when designing with the LMK04816. Refer to Pin Connection Recommendations
for more details on the pin connections and bypassing recommendations. Also refer to the evaluation board
TSW3085EVM ACPR and EVM Measurements (SLAA509). PCB design also plays a role in device performance.
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System Examples (continued)
Status_CLKin0
240:
Status_CLKin1
To Host
processor
0.1 PF
CLKout0, 1
Status_LD
CLKout0*,1*
Status_HOLDOVER
0.1 PF
SYNC
2x LVPECL
output clocks
to DAC
240:
LEuWire
CLKuWire
240:
DATAuWire
0.1 PF
CLKout2, 3, 4, 5
Recovered
Reference
Clock
0.1 PF
CLKin0
CLKout2*,3*,4*,5*
0.1 PF
CLKin0*
50:
240:
0.1 PF
CLKin1
0.1 PF
LMK04816
100:
3x LVDS clocks
to FPGAs and
microcontrollers
CLKout6, 7, 8
CLKout6*,7*,8*
CLKin1*
TCXO
CLKout 6 and 8 active at startup
0.1 PF
CLKout9
CLKin2
Differential
Reference
CLKout9*
0.1 PF
100:
CLKin2*
LVDS Low
Frequency
System
Synchronization
Clock
CLKout10
0.1 PF
CLKout10*
0.1 PF OSCin*
CLKout11
CLKout11*
OSCin
240:
0.1 PF
VCXO
4x LVPECL
output clocks
to ADC
Rterm
LDObyp1
0.1 PF
OSCout0
LDObyp2
OSCout0*
CPout2
0.1 PF
CPout1
0.1 PF
10 PF
LVPECL
OSCout clock
to PLL
references
240:
OSCout0 on at startup
PLL1 Loop Filter
Up to 13 total differential clocks
2 clock outputs unused in above design
PLL2 External
Loop Filter
Figure 41. Example Application – System Schematic Except for Power
Figure 41 shows the primary reference clock input is at CLKin0/0*. A secondary reference clock is driving
CLKin1/1*. A third reference clock is driving CLKin2/2*. All three clocks are depicted as AC-coupled differential
drivers. The VCXO attached to the OSCin and OSCin* port is configured as an AC-coupled single-ended driver.
Any of the input ports (CLKin0/0*, CLKin1/1*, CLKin2/2*, or OSCin/OSCin*) may be configured as either
differential or single-ended. These options are discussed later in the data sheet.
See Loop Filter for more information on PLL1 and PLL2 loop filters.
The clock outputs are all AC-coupled with 0.1-µF capacitors. Some clock outputs are depicted as LVPECL with
240-Ω emitter resistors and some clock outputs as LVDS. However, the output format of the clock outputs vary
by user programming, so the user must use the appropriate source termination for each clock output. Later
sections of this data sheet illustrate alternative methods for AC-coupling, DC-coupling and terminating the clock
outputs.
PCB design influences crosstalk performance. Tightly coupled clock traces have less crosstalk than loosely
coupled clock traces. Also, proximity to other clocks traces influence crosstalk.
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System Examples (continued)
PLL Supply Plane
Vcc1
FB
Vcc4
Vcc5
10 µF, 1 µF, 0.1 µF
1 µF, 0.1 µF, 10 nF
Vcc7
Vcc9
LDO
LP3878-ADJ
Vcc6
FB
0.1 µF
0.1 µF
Digital
CLKin/OSCout1
OSCin/OSCout0/
PLL2 Circuitry
PLL2 N Divider
PLL1 CP
0.1 µF
PLL2 CP
FB
FB = Ferrite bead
VCO LDO
0.1 µF
Vcc8
LMK04816
Clock Supply Plane
FB
FB
10 µF, 1 µF, 0.1 µF
FB
Do not directly copy schematic for
CLKout Vcc13/2/3/10/11/12. This
is for example frequency plan only.
Vcc13
Vcc2
Vcc3
FB
Vcc10
Vcc11
Recommendation is to group
supplies by same frequency and
share a ferrite bead among outputs
of the same frequency.
Vcc12
CLKout0/1
CLKout2/3
CLKout4/5
Example
Frequency 1
Example
Frequency 2
CLKout6/7
CLKout8/9
Example
Frequency 3
CLKout10/11
Figure 42. Example Application – Power System Schematic
Figure 42 shows an example decoupling and bypassing scheme for the LMK04816. Components drawn in dotted
lines are optional. Two power planes are used in this design, one for the clock outputs and one for other PLL
circuits.
PCB design influences impedance to the supply. Vias and traces increase the impedance to the power supply.
Ensure good direct return current paths.
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10 Power Supply Recommendations
10.1 Pin Connection Recommendations
10.1.1 Vcc Pins and Decoupling
All Vcc pins must always be connected.
Integrated capacitance on the LMK04816 makes external high frequency decoupling capacitors (≤ 1 nF)
unnecessary. The internal capacitance is more effective at filtering high-frequency noise than off device bypass
capacitance because there is no bond wire inductance between the LMK04816 circuit and the bypass capacitor.
10.1.1.1 Vcc2, Vcc3, Vcc10, Vcc11, Vcc12, Vcc13 (CLKout Vccs)
Each of these pins has an internal 200 pF of capacitance.
Ferrite beads may be used to reduce crosstalk between different clock output frequencies on the same
LMK04816 device. Ferrite beads placed between the power supply and a clock Vcc pin reduce noise between
the Vcc pin and the power supply. When several output clocks share the same frequency a single ferrite bead
can be used between the power supply and each same frequency CLKout Vcc pin.
When using ferrite beads on CLKout Vcc pins, care must be taken to ensure the power supply can source the
needed switching current.
• In most cases a ferrite bead may be placed and the internal capacitance is sufficient.
• If a ferrite bead is used with a low frequency output (typically ≤ 10 MHz) and a high current switching clock
output format such as non-complementary LVCMOS or high swing LVPECL is used, then...
– the ferrite bead can be removed to the lower impedance to the main power supply and bypass capacitors,
or
– localized capacitance can be placed between the ferrite bead and Vcc pin to support the switching current.
– Decoupling capacitors used between the ferrite bead and a CLKout Vcc pin can permit high frequency
switching noise to couple through the capacitors into the ground plane and onto other CLKout Vcc pins
with decoupling capacitors. This can degrade crosstalk performance.
10.1.1.2 Vcc1 (VCO), Vcc4 (Digital), and Vcc9 (PLL2)
Each of these pins has internal bypass capacitance.
Ferrite beads must not be used between these pins and the power supply/large bypass capacitors because
these Vcc pins don’t produce much noise or a ferrite bead can cause phase noise disturbances and resonances.
The typical application diagram in Figure 42 shows all these Vccs connected to together to Vcc without a ferrite
bead.
10.1.1.3 Vcc6 (PLL1 Charge Pump) and Vcc8 (PLL2 Charge Pump)
Each of these pins has an internal bypass capacitor.
Use of a ferrite bead between the power supply and large bypass capacitors and PLL1 is optional. PLL1 charge
pump can be connected directly to Vcc along with Vcc1, Vcc4, and Vcc9. Depending on the application, a 0.1-µF
capacitor may be placed close to PLL1 charge pump Vcc pin.
A ferrite bead must be placed between the power supply and large bypass capacitors and Vcc8. Most
applications have high PLL2 phase detector frequencies and (> 50 MHz) such that the internal bypassing is
sufficient and a ferrite bead can be used to isolate this switching noise from other circuits. For lower phase
detector frequencies a ferrite bead is optional and depending on application a 0.1-µF capacitor may be added on
Vcc8.
10.1.1.4 Vcc5 (CLKin), Vcc7 (OSCin and OSCout0)
Each of these pins has an internal 100 pF of capacitance. No ferrite bead must be placed between the power
supply/large bypass capacitors and Vcc5 or Vcc7.
These pins are unique becausÆe they supply an output clock and other circuitry.
Vcc5 supplies CLKin. Vcc7 supplies OSCin, OSCout0, and PLL2 circuitry.
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Pin Connection Recommendations (continued)
10.1.2 LVPECL Outputs
When using an LVPECL output, TI does not recommend placing a capacitor to ground on the output as might be
done when using a capacitor input LC lowpass filter. The capacitor appears as a short to the LVPECL output
drivers which are able to supply large amounts of switching current. The effect of the LVPECL sourcing large
switching currents can result in:
1. Large switching currents through the Vcc pin of the LVPECL power supply resulting in more Vcc noise and
possible Vcc spikes.
2. Large switching currents injected into the ground plane through the capacitor which could couple onto other
Vcc pins with bypass capacitors to ground resulting in more Vcc noise and possible Vcc spikes.
10.1.3 Unused Clock Outputs
Leave unused clock outputs floating and powered down.
10.1.4 Unused Clock Inputs
Unused clock inputs can be left floating.
10.1.5 LDO Bypass
The LDObyp1 and LDObyp2 pins must be connected to GND through external capacitors, as shown in the
diagram.
10.2 Current Consumption and Power Dissipation Calculations
From Table 118 the current consumption can be calculated for any configuration.
For example, the current for the entire device with 1 LVDS (CLKout0) and 1 LVPECL 1.6 Vpp with 240-Ω emitter
resistors (CLKout1) output active with a clock output divide = 1, and no other features enabled can be calculated
by adding up the following blocks: core current, clock buffer, one LVDS output buffer current, and one LVPECL
output buffer current. There is also one LVPECL output drawing emitter current, which means some of the power
from the current draw of the device is dissipated in the external emitter resistors which doesn't add to the power
dissipation budget for the device but is important for LDO ICC calculations.
For total current consumption of the device, add up the significant functional blocks. In this example, 228.1 mA =
• 140 mA (core current)
• 17.3 mA (base clock distribution)
• 25.5 mA (CLKout0 and 1 divider)
• 14.3 mA (LVDS buffer)
• 31 mA (LVPECL 1.6-Vpp buffer with 240-Ω emitter resistors)
Once total current consumption has been calculated, power dissipated by the device can be calculated. The
power dissipation of the device is equation to the total current entering the device multiplied by the voltage at the
device minus the power dissipated in any emitter resistors connected to any of the LVPECL outputs. If no emitter
resistors are connected to the LVPECL outputs, this power is 0 watts. Continuing the above example which has
228.1 mA total Icc and one output with 240-Ω emitter resistors. Total IC power = 717.7 mW = 3.3 V × 228.1
mA – 35 mW.
116
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Current Consumption and Power Dissipation Calculations (continued)
Table 118. Typical Current Consumption for Selected Functional Blocks
(TA = 25 °C, VCC = 3.3 V)
BLOCK
CONDITION
TYPICAL
ICC
(mA)
POWER
DISSIPATED IN
DEVICE
(mW)
POWER DISSIPATED
EXTERNALLY (1) (2) (3)
(mW)
CORE AND FUNCTIONAL BLOCKS
MODE = 0: Dual Loop, Internal
VCO
PLL1 and PLL2 locked
140
462
-
MODE = 2: Dual Loop, Internal
VCO, 0-Delay
PLL1 and PLL2 locked; Includes
EN_FEEDBACK_MUX = 1
155
512
-
MODE = 3: Dual Loop, External
VCO
PLL1 and PLL2 locked
127
419
-
MODE = 5: Dual Loop, External
VCO, 0-Delay
PLL1 and PLL2 locked; Includes
EN_FEEDBACK_MUX = 1
142
469
-
MODE = 6: Single Loop (PLL2),
Internal VCO
PLL2 locked
116
383
-
MODE = 11: Single Loop (PLL2),
External VCO
PLL2 locked
103
340
-
PD_OSCin = 0
42
139
-
PD_OSCin = 1
34.5
114
-
2
6.6
-
17.3
57.1
-
Each CLKout group (CLKout0/1 & 10/11, CLKout2/3 & 4/5, CLKout 6/7
& 8/9)
2.8
9.2
-
Clock Divider/
Digital Delay
When a clock output is enabled, this contributes the divider/delay block
25.5
84.1
-
Divider / digital delay in extended mode
29.6
97.7
-
VCO Divider
VCO Divider current
7.7
25.4
-
HOLDOVER mode
When in holdover mode
2.2
7.2
-
Feedback Mux
Feedback mux must be enabled for 0-delay modes and digital delay
mode (SYNC_QUAL = 1)
4.9
16.1
-
SYNC Asserted
While SYNC is asserted, this extra current is drawn
1.7
5.6
-
EN_SYNC = 1
Required for SYNC functionality. May be turned off once SYNC is
complete to save power.
6
19.8
-
SYNC_QUAL = 1
Delay enabled, delay > 7 (CLKout_MUX = 2, 3)
Core
MODE = 16: Clock Distribution
EN_TRACK
Tracking is enabled (EN_TRACK = 1)
Base Clock
Distribution
At least 1 CLKoutX_Y_PD = 0
CLKout Group
Crystal Mode
OSCin Doubler
Enabling the Crystal Oscillator
8.7
28.7
-
XTAL_LVL = 0
1.8
5.9
-
XTAL_LVL = 1
2.7
9
-
XTAL_LVL = 2
3.6
12
-
XTAL_LVL = 3
4.5
15
-
2.8
9.2
-
CLKoutX_Y_ANLG_DLY = 0 to 3
3.4
11.2
-
CLKoutX_Y_ANLG_DLY = 4 to 7
3.8
12.5
-
CLKoutX_Y_ANLG_DLY = 8 to 11
4.2
13.9
-
CLKoutX_Y_ANLG_DLY = 12 to
15
4.7
15.5
-
CLKoutX_Y_ANLG_DLY = 16 to
23
5.2
17.2
-
2.8
9.2
-
EN_PLL2_REF_2X = 1
Analog Delay Value
Analog Delay
Only Single Output Of Clock Pair Has Analog Delay Selected. Example:
CLKout0_ADLY_SEL = 1 and CLKout1_ADLY_SEL = 0, or
CLKout0_ADLY_SEL = 0 and CLKout1_ADLY_SEL = 1.
(1)
(2)
(3)
Power is dissipated externally in LVPECL emitter resistors. The externally dissipated power is calculated as twice the DC voltage level
of one LVPECL clock output pin squared over the emitter resistance. That is to say power dissipated in emitter resistors = 2 × Vem2 /
Rem.
Assuming RθJA = 15°C/W, the total power dissipated on chip must be less than (125°C – 85°C) / 16°C/W = 2.5 W to ensure a junction
temperature is less than 125°C.
Worst case power dissipation can be estimated by multiplying typical power dissipation with a factor of 1.15.
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Current Consumption and Power Dissipation Calculations (continued)
Table 118. Typical Current Consumption for Selected Functional Blocks
(TA = 25 °C, VCC = 3.3 V) (continued)
BLOCK
CONDITION
TYPICAL
ICC
(mA)
POWER
DISSIPATED IN
DEVICE
(mW)
POWER DISSIPATED
EXTERNALLY (1) (2) (3)
(mW)
CORE AND FUNCTIONAL BLOCKS
CLOCK OUTPUT BUFFERS
LVDS
100-Ω differential termination
LVPECL
LVCMOS
118
14.3
47.2
-
LVPECL 2.0 Vpp, AC coupled using 240-Ω emitter resistors
32
70.6
35
LVPECL 1.6 Vpp, AC coupled using 240-Ω emitter resistors
31
67.3
35
LVPECL 1.6 Vpp, AC coupled using 120-Ω emitter resistors
46
91.8
60
LVPECL 1.2 Vpp, AC coupled using 240-Ω emitter resistors
30
59
40
LVPECL 0.7 Vpp, AC coupled using 240-Ω emitter resistors
29
55.7
40
LVCMOS Pair (CLKoutX_TYPE
= 6 to 9)
CL = 5 pF
3 MHz
24
79.2
-
30 MHz
26.5
87.5
-
150 MHz
36.5
120.5
-
3 MHz
15
49.5
-
30 MHz
16
52.8
-
150 MHz
21.5
71
-
LVCMOS Single (CLKoutX_TYPE
= 10 to 13)
CL = 5 pF
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11 Layout
11.1 Layout Guidelines
Power consumption of the LMK04816 can be high enough to require attention to thermal management. For
reliability and performance reasons the die temperature must be limited to a maximum of 125°C. That is, as an
estimate, TA (ambient temperature) plus device power consumption times RθJA must not exceed 125°C.
The package of the device has an exposed pad that provides the primary heat removal path as well as excellent
electrical grounding to a printed-circuit-board. To maximize the removal of heat from the package a thermal land
pattern including multiple vias to a ground plane must be incorporated on the PCB within the footprint of the
package. The exposed pad must be soldered down to ensure adequate heat conduction out of the package.
A recommended land and via pattern is shown in Figure 43. More information on soldering WQFN, previously
referred to as LLP packages, see Absolute Maximum Ratings for Soldering (SNOA549).
To minimize junction temperature, TI recommends that a simple heat sink be built into the PCB (if the ground
plane layer is not exposed). This is done by including a copper area on the opposite side of the PCB from the
device. This copper area may be plated or solder coated to prevent corrosion, but must not have conformal
coating (if possible), which could provide thermal insulation. The vias shown in Figure 43 must connect these top
and bottom copper layers and to the ground layer. These vias act as heat pipes to carry the thermal energy away
from the device side of the board to where it can be more effectively dissipated. Avoid routing traces close to
exposed ground pad to ensure proper thermal flow on the PCB.
7.2 mm
0.2 mm
1.46 mm
1.15 mm
Figure 43. Recommended Land and Via Pattern
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11.2 Layout Example
CLKin and OSCin path ± if differential input (preferred) route trace
tightly coupled like clock outputs. If single ended, have at least 3 trace
width (of CLKin/OSCin trace) separation from other RF traces.
Example shown is hybrid for both differential and single ended ± not
tightly couple to compromise for both configurations. RF Terminations
should be placed as close to IC as possible. When using CLKin1 for
high frequency input for external VCO or distribution, a 3 dB pi pad is
suggested for termination.
)RU &/.RXW 9FF¶V SODFH IHUULWH EHDGV RQ WRS OD\HU FORVH WR SLQV WR FKRNH
high frequency noise from via.
Charge pump output ± shorter traces are better.
Place all resistors and caps closer to IC except for
a single capacitor next to VCXO. In a 2nd order
filter place C1 close to VCXO Vtune pin. In a 3rd
and 4th order filter place C3 or C4 respectively
close to VCXO.
Clock outputs ± differential signals, should be
routed tightly coupled to minimize PCB crosstalk.
Trace impedance and terminations should be
designed according to output type being used (i.e.
LVDS, LVPECL...)
Figure 44. LMK04816 Layout Example
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12 Device and Documentation Support
12.1 Device Support
12.1.1 Development Support
For additional support, see the following:
• Clock Design Tool: http://www.ti.com/tool/clockdesigntool
• Clock Architect: http://www.ti.com/lsds/ti/analog/webench/clock-architect.page
12.2 Documentation Support
12.2.1 Related Documentation
For additional information, see the following:
• User's Guide, LMK04816 Evaluation Board Operating Instructions, SNLU107
• Application Note AN-912, Common Data Transmission Parameters and their Definitions, SNLA036
• Application Note AN-1939, Crystal Based Oscillator Design with the LMK04000 Family, SNAA065
• Application Note AN-1865, Frequency Synthesis and Planning for PLL Architectures, SNAA061
• Clock Conditioner Owner’s Manual, SNAA103
• TSW3085EVM ACPR and EVM Measurements, SLAA509
• Application Report, Absolute Maximum Ratings for Soldering, SNOA549
12.3 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
12.4 Trademarks
PLLATINUM, E2E are trademarks of Texas Instruments.
All other trademarks are the property of their respective owners.
12.5 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
12.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
(3)
Device Marking
(4/5)
(6)
LMK04816BISQ/NOPB
ACTIVE
WQFN
NKD
64
1000
RoHS & Green
SN
Level-3-260C-168 HR
-40 to 85
K04816BISQ
LMK04816BISQE/NOPB
ACTIVE
WQFN
NKD
64
250
RoHS & Green
SN
Level-3-260C-168 HR
K04816BISQ
LMK04816BISQX/NOPB
ACTIVE
WQFN
NKD
64
2000
RoHS & Green
SN
Level-3-260C-168 HR
K04816BISQ
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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