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LMK61E0-050M, LMK61E0-155M, LMK61E0-156M, LMK61E2-100M, LMK61E2-125M
LMK61E2-156M, LMK61E2-312M, LMK61A2-100M, LMK61A2-125M, LMK61A2-156M
LMK61A2-312M, LMK61A2-644M, LMK61I2-100M
SNAS676D – OCTOBER 2015 – REVISED OCTOBER 2017
LMK61XX High-Performance Ultra-Low Jitter Oscillator
1 Features
3 Description
•
The LMK61XX is an ultra-low jitter oscillator that
generates a commonly used reference clock. The
device is pre-programmed in factory to support any
reference clock frequency; supported output formats
are LVPECL up to 1 GHz, LVDS up to 900 MHz, and
HCSL up to 400 MHz. Internal power conditioning
provide excellent power supply ripple rejection
(PSRR), reducing the cost and complexity of the
power delivery network. The device operates from a
single 3.3 V ± 5% supply.
1
•
•
Ultra-low Noise, High Performance
– Jitter: 90 fs RMS Typical Fout > 100 MHz
– PSRR: –70 dBc, Robust Supply Noise
Immunity
Supported Output Format
– LVPECL up to 1 GHz
– LVDS up to 900 MHz
– HCSL up to 400 MHz
Total Frequency Tolerance of ± 50 ppm
(LMK61X2) and ± 25 ppm (LMK61X0)
3.3-V Operating Voltage
Industrial Temperature Range (–40ºC to +85ºC)
7 mm × 5 mm 6-Pin Package, Pin-Compatible
With Industry Standard 7050 XO Package
Device Information(1)
PART
NUMBER
OUTPUT FREQ
(MHz) AND
FORMAT
TOTAL FREQ
STABILITY (PPM)
LMK61A2100M00
100 LVDS
± 50
LMK61A2125M00
125 LVDS
± 50
2 Applications
LMK61A2156M25
156.25 LVDS
± 50
•
LMK61A2312M50
312.5 LVDS
± 50
LMK61A2644M53
644.53125 LVDS
± 50
LMK61E0050M00
50 LVPECL
± 25
LMK61E0155M52
155.52 LVPECL
± 25
LMK61E0156M25
156.25 LVPECL
± 25
LMK61E2100M00
100 LVPECL
± 50
LMK61E2125M00
125 LVPECL
± 50
LMK61E2156M25
156.25 LVPECL
± 50
LMK61E2312M50
312.5 LVPECL
± 50
LMK61I2100M00
100 HCSL
± 50
•
•
•
•
•
•
•
High-Performance Replacement for Crystal, SAW,
or Silicon-Based Oscillators
Switches, Routers, Network Line Cards, Base
Band Units (BBU), Servers, Storage/SAN
Test and Measurement
Medical Imaging
FPGA, Processor Attach
PACKAGE
6-pin QFM
(7.0 mm x 5.0
mm)
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Pinout
6
OE
1
6
VDD
NC
2
5
OUTN
GND
3
4
OUTP
1
2
5
4
3
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
LMK61E0-050M, LMK61E0-155M, LMK61E0-156M, LMK61E2-100M, LMK61E2-125M
LMK61E2-156M, LMK61E2-312M, LMK61A2-100M, LMK61A2-125M, LMK61A2-156M
LMK61A2-312M, LMK61A2-644M, LMK61I2-100M
SNAS676D – OCTOBER 2015 – REVISED OCTOBER 2017
www.ti.com
Table of Contents
1
2
3
4
5
6
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
4
6.1
6.2
6.3
6.4
6.5
6.6
6.7
6.8
6.9
6.10
6.11
6.12
4
4
4
4
5
5
5
6
6
6
6
7
Absolute Maximum Ratings ......................................
ESD Ratings ............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics - Power Supply .................
LVPECL Output Characteristics................................
LVDS Output Characteristics ....................................
HCSL Output Characteristics....................................
OE Input Characteristics ...........................................
Frequency Tolerance Characteristics .....................
Power-On/Reset Characteristics (VDD)..................
PSRR Characteristics .............................................
6.13 PLL Clock Output Jitter Characteristics ..................
6.14 Typical 156.25-MHz Output Phase Noise
Characteristics ...........................................................
6.15 Additional Reliability and Qualification ....................
6.16 Typical Characteristics ............................................
7
7
7
8
7
Parameter Measurement Information ................ 10
8
9
Power Supply Recommendations...................... 12
Layout ................................................................... 12
7.1 Device Output Configurations ................................. 10
9.1 Layout Guidelines ................................................... 12
10 Device and Documentation Support ................. 14
10.1
10.2
10.3
10.4
10.5
10.6
Related Links ........................................................
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
14
14
14
14
14
14
11 Mechanical, Packaging, and Orderable
Information ........................................................... 15
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision C (September 2017) to Revision D
Page
•
Added LMK61A2-644M ......................................................................................................................................................... 1
•
Added LMK61E0-156M ......................................................................................................................................................... 1
Changes from Revision B (March 2017) to Revision C
•
Page
Added LMK61E0-155M ......................................................................................................................................................... 1
Changes from Revision A (November 2015) to Revision B
Page
•
Updated data sheet text to the latest documentation and translations standards ................................................................ 1
•
Added LMK61E0-050M ......................................................................................................................................................... 1
•
Updated key graphic .............................................................................................................................................................. 1
•
Added Receiving Notification of Documentation Updates section ...................................................................................... 14
Changes from Original (October 2015) to Revision A
•
2
Page
Product Preview to Production Data Datasheet .................................................................................................................... 1
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Product Folder Links: LMK61E0-050M LMK61E0-155M LMK61E0-156M LMK61E2-100M LMK61E2-125M LMK61E2156M LMK61E2-312M LMK61A2-100M LMK61A2-125M LMK61A2-156M LMK61A2-312M LMK61A2-644M
LMK61I2-100M
LMK61E0-050M, LMK61E0-155M, LMK61E0-156M, LMK61E2-100M, LMK61E2-125M
LMK61E2-156M, LMK61E2-312M, LMK61A2-100M, LMK61A2-125M, LMK61A2-156M
LMK61A2-312M, LMK61A2-644M, LMK61I2-100M
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SNAS676D – OCTOBER 2015 – REVISED OCTOBER 2017
5 Pin Configuration and Functions
SIA Package
6-Pin QFM
Top View
OE
1
6
VDD
NC
2
5
OUTN
GND
3
4
OUTP
Pin Functions
PIN
NAME
NO.
I/O
DESCRIPTION
POWER
GND
3
Ground
Device Ground.
VDD
6
Analog
3.3 V Power Supply.
4, 5
Universal
OUTPUT BLOCK
OUTP,
OUTN
Differential Output Pair (LVPECL, LVDS or HCSL).
DIGITAL CONTROL / INTERFACES
NC
2
N/A
OE
1
LVCMOS
No Connect.
Output Enable (internal pullup). When set to low, output pair is disabled and set at high
impedance.
Copyright © 2015–2017, Texas Instruments Incorporated
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LMK61I2-100M
3
LMK61E0-050M, LMK61E0-155M, LMK61E0-156M, LMK61E2-100M, LMK61E2-125M
LMK61E2-156M, LMK61E2-312M, LMK61A2-100M, LMK61A2-125M, LMK61A2-156M
LMK61A2-312M, LMK61A2-644M, LMK61I2-100M
SNAS676D – OCTOBER 2015 – REVISED OCTOBER 2017
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
MIN
MAX
UNIT
VDD
Device supply voltage
–0.3
3.6
V
VIN
Output voltage for logic inputs
–0.3
VDD + 0.3
V
VOUT
Output voltage for clock outputs
–0.3
VDD + 0.3
V
TJ
Junction temperature
150
°C
TSTG
Storage temperature
125
°C
(1)
–40
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute maximum-rated conditions for extended periods may affect device reliability.
6.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic
discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001
(1)
UNIT
±4000
Charged-device model (CDM), per JEDEC specification JESD22-C101 (2)
V
±1500
JEDEC document JEP155 states that 500 V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250 V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
VDD
Device supply voltage
TA
Ambient temperature
TJ
Junction temperature
tRAMP
VDD power-up ramp time
MIN
NOM
MAX
UNIT
3.135
3.3
3.465
V
–40
25
85
°C
LMK61X2
125
°C
LMK61X0
115
°C
100
ms
0.1
6.4 Thermal Information
LMK61XX
SIA (QFM)
THERMAL METRIC (1)
RθJA
UNIT
6 PINS
Airflow (LFM) 0
Airflow (LFM) 200
Airflow (LFM) 400
55.2
46.4
43.7
°C/W
RθJC(top) Junction-to-case (top) thermal resistance
34.6
n/a
n/a
°C/W
RθJB
Junction-to-board thermal resistance
37.7
n/a
n/a
°C/W
ψJT
Junction-to-top characterization parameter
11.3
17.6
22.5
°C/W
ψJB
Junction-to-board characterization parameter
37.7
41.5
40.1
°C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance
n/a
n/a
n/a
°C/W
(1)
(2)
(3)
(4)
4
Junction-to-ambient thermal resistance
(2) (3) (4)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
The package thermal resistance is calculated on a 4 layer JEDEC board.
Connected to GND with 3 thermal vias (0.3-mm diameter).
ψJB (junction to board) is used when the main heat flow is from the junction to the GND pad. Please refer to Thermal Considerations
section for more information on ensuring good system reliability and quality.
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LMK61I2-100M
LMK61E0-050M, LMK61E0-155M, LMK61E0-156M, LMK61E2-100M, LMK61E2-125M
LMK61E2-156M, LMK61E2-312M, LMK61A2-100M, LMK61A2-125M, LMK61A2-156M
LMK61A2-312M, LMK61A2-644M, LMK61I2-100M
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SNAS676D – OCTOBER 2015 – REVISED OCTOBER 2017
6.5 Electrical Characteristics - Power Supply (1)
VDD = 3.3 V ± 5%, TA = -40C to 85°C
PARAMETER
IDD
Device current consumption
IDD-PD
(1)
(2)
Device current consumption
when output is disabled
TEST CONDITIONS
LVPECL
MIN
(2)
TYP
MAX
UNIT
mA
162
208
LVDS
152
196
HCSL
155
196
OE = GND
136
mA
Refer to Parameter Measurement Information for relevant test conditions.
On-chip power dissipation should exclude 40 mW, dissipated in the 150 ohm termination resistors, from total power dissipation.
6.6 LVPECL Output Characteristics (1)
VDD = 3.3 V ± 5%, TA = -40C to 85°C
PARAMETER
fOUT
Output frequency (2)
VOD
Output voltage swing
(VOH – VOL) (2)
VOUT, DIFF, PP
Differential output peak-topeak swing
VOS
Output common-mode voltage
tR / tF
Output rise/fall time (20% to
80%) (3)
PN-Floor
Output phase noise floor
(fOFFSET > 10 MHz)
ODC
Output duty cycle (3)
(1)
(2)
(3)
TEST CONDITIONS
MIN
TYP
10
700
800
UNIT
MHz
1200
mV
2×
|VOD|
V
VDD –
1.55
V
120
156.25 MHz
MAX
1000
200
–165
45%
ps
dBc/Hz
55%
Refer to Parameter Measurement Information for relevant test conditions.
An output frequency over fOUT max spec is possible, but output swing may be less than VOD min spec.
Ensured by characterization.
6.7 LVDS Output Characteristics (1)
VDD = 3.3 V ± 5%, TA = –40°C to 85°C
PARAMETER
fOUT
Output frequency (1)
VOD
Output voltage swing
(VOH – VOL) (1)
VOUT, DIFF, PP
Differential output peak-topeak swing
VOS
TEST CONDITIONS
MIN
TYP
10
300
390
MAX
UNIT
900
MHz
480
mV
2×
|VOD|
V
Output common-mode voltage
1.2
V
tR / tF
Output rise/fall time (20% to
80%) (2)
150
PN-Floor
Output phase noise floor
(fOFFSET > 10 MHz)
ODC
Output duty cycle (2)
ROUT
Differential output impedance
(1)
(2)
156.25 MHz
250
–162
45%
ps
dBc/Hz
55%
125
Ohm
An output frequency over fOUT max spec is possible, but output swing may be less than VOD min spec.
Ensured by characterization.
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6.8 HCSL Output Characteristics (1)
VDD = 3.3 V ± 5%, TA = –40°C to 85°C
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
fOUT
Output frequency
10
400
MHz
VOH
Output high voltage
600
850
mV
VOL
Output low voltage
–100
100
mV
VCROSS
Absolute crossing voltage (2) (3)
250
475
mV
0
140
mV
0.8
2
V/ns
VCROSS-DELTA Variation of VCROSS
(2) (3)
dV/dt
Slew rate (4)
PN-Floor
Output phase noise floor
(fOFFSET > 10 MHz)
ODC
Output duty cycle (4)
(1)
(2)
(3)
(4)
100 MHz
–164
45%
dBc/Hz
55%
Refer to Parameter Measurement Information for relevant test conditions.
Measured from -150 mV to +150 mV on the differential waveform with the 300 mVpp measurement window centered on the differential
zero crossing.
Ensured by design.
Ensured by characterization.
6.9 OE Input Characteristics
VDD = 3.3 V ± 5%, TA = –40°C to 85°C
PARAMETER
TEST CONDITIONS
VIH
Input high voltage
VIL
Input low voltage
IIH
Input high current
VIH = VDD
IIL
Input low current
VIL = GND
CIN
Input capacitance
MIN
TYP
MAX
1.4
UNIT
V
0.6
V
–40
40
uA
–40
40
uA
2
pF
6.10 Frequency Tolerance Characteristics (1)
VDD = 3.3 V ± 5%, TA = –40°C to 85°C
PARAMETER
fT
(1)
Total frequency tolerance
TEST CONDITIONS
MIN
MAX
UNIT
LMK61X2: All output formats, frequency
bands and device junction temperature up to
125°C; includes initial freq tolerance,
temperature & supply voltage variation, solder
reflow and aging (10 years)
–50
TYP
50
ppm
LMK61X0: All output formats, frequency
bands and device junction temperature up to
115°C; includes initial freq tolerance,
temperature & supply voltage variation, solder
reflow and aging (5 years at 40°C)
–25
25
ppm
MAX
UNIT
2.95
V
Ensured by characterization.
6.11 Power-On/Reset Characteristics (VDD)
VDD = 3.3 V ± 5%, TA = –40°C to 85°C
PARAMETER
VTHRESH
VDROOP
Allowable voltage droop
tSTARTUP
Start-up time
tOE-EN
tOE-DIS
(1)
(2)
6
TEST CONDITIONS
MIN
Threshold voltage (1)
2.72
(2)
TYP
0.1
V
Time elapsed from VDD at 3.135 V to output
enabled
10
ms
Output enable time (2)
Time elapsed from OE at VIH to output enabled
50
us
Output disable time (2)
Time elapsed from OE at VIL to output disabled
50
us
(1)
Ensured by characterization.
Ensured by design.
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SNAS676D – OCTOBER 2015 – REVISED OCTOBER 2017
6.12 PSRR Characteristics (1)
VDD = 3.3 V, TA = 25°C, FS[1:0] = NC, NC
PARAMETER
PSRR
(1)
(2)
(3)
TEST CONDITIONS
Spurs induced by 50-mV
power supply ripple (2) (3) at
156.25-MHz output, all
output types
MIN
TYP
Sine wave at 50 kHz
–70
Sine wave at 100 kHz
–70
Sine wave at 500 kHz
–70
Sine wave at 1 MHz
–70
MAX
UNIT
dBc
Refer to Parameter Measurement Information for relevant test conditions.
Measured max spur level with 50 mVpp sinusoidal signal between 50 kHz and 1 MHz applied on VDD pin
DJSPUR (ps, pk-pk) = [2*10(SPUR/20) / (π*fOUT)]*1e6, where PSRR or SPUR in dBc and fOUT in MHz.
6.13 PLL Clock Output Jitter Characteristics (1) (2)
VDD = 3.3 V ± 5%, TA = –40°C to 85°C
TYP
MAX
UNIT
RJ
RMS phase jitter (3)
(12 kHz – 20 MHz)
(1 kHz – 5 MHz)
PARAMETER
fOUT < 100 MHz, all output types
200
300
fs RMS
RJ
RMS phase jitter (3)
(12 kHz – 20 MHz)
(1 kHz – 5 MHz)
fOUT ≥ 100 MHz (except 155.52 MHz and
644.53125 MHz), all output types
100
200
fs RMS
RJ
RMS phase jitter (3)
(12 kHz – 20 MHz)
(1 kHz – 5 MHz)
fOUT = 155.52 MHz or 644.53125 MHz, all
output types
150
300
fs RMS
(1)
(2)
(3)
TEST CONDITIONS
MIN
Refer to Parameter Measurement Information for relevant test conditions.
Phase jitter measured with Agilent E5052 signal source analyzer using a differential-to-single ended converter (balun or buffer).
Ensured by characterization.
6.14 Typical 156.25-MHz Output Phase Noise Characteristics (1) (2)
VDD = 3.3 V, TA = 25°C, Output Type = LVPECL/LVDS/HCSL
PARAMETER
OUTPUT TYPE
UNITS
LVPECL
LVDS
HCSL
phn10k
Phase noise at 10-kHz offset
–143
–143
–143
dBc/Hz
Phn20k
Phase noise at 20-kHz offset
–143
–143
–143
dBc/Hz
phn100k
Phase noise at 100-kHz offset
–144
–144
–144
dBc/Hz
Phn200k
Phase noise at 200-kHz offset
–145
–145
–145
dBc/Hz
phn1M
Phase noise at 1-MHz offset
–150
–150
–150
dBc/Hz
phn2M
Phase noise at 2-MHz offset
–154
–154
–154
dBc/Hz
phn10M
Phase noise at 10-MHz offset
–165
–162
–164
dBc/Hz
phn20M
Phase noise at 20-MHz offset
–165
–162
–164
dBc/Hz
(1)
(2)
Refer to Parameter Measurement Information for relevant test conditions.
Phase jitter measured with Agilent E5052 signal source analyzer using a differential-to-single ended converter (balun or buffer).
6.15 Additional Reliability and Qualification
PARAMETER
CONDITION / TEST METHOD
Mechanical Shock
MIL-STD-202, Method 213
Mechanical Vibration
MIL-STD-202, Method 204
Moisture Sensitivity Level
J-STD-020, MSL3
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6.16 Typical Characteristics
Figure 1. Phase Noise of 156.25-MHz LVPECL Differential
Output
Figure 2. Phase Noise of 156.25-MHz LVDS Differential
Output
10
0
Amplitude (dBm)
-10
-20
-30
-40
-50
-60
-70
-80
-90
78.125
10
203.125
234.375
D007
10
0
0
-10
-10
-20
-20
Amplitude (dBm)
Amplitude (dBm)
140.625
171.875
Frequency (MHz)
Figure 4. 156.25 ± 78.125-MHz LVPECL Differential Output
Spectrum
Figure 3. Phase Noise of 156.25-MHz HCSL Differential
Output
-30
-40
-50
-60
-30
-40
-50
-60
-70
-70
-80
-80
-90
78.125
109.375
140.625
171.875
Frequency (MHz)
203.125
234.375
D008
Figure 5. 156.25 ± 78.125-MHz LVDS Differential Output
Spectrum
8
109.375
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-90
78.125
109.375
140.625
171.875
Frequency (MHz)
203.125
234.375
D009
Figure 6. 156.25 ± 78.125-MHz HCSL Differential Output
Spectrum
Copyright © 2015–2017, Texas Instruments Incorporated
Product Folder Links: LMK61E0-050M LMK61E0-155M LMK61E0-156M LMK61E2-100M LMK61E2-125M LMK61E2156M LMK61E2-312M LMK61A2-100M LMK61A2-125M LMK61A2-156M LMK61A2-312M LMK61A2-644M
LMK61I2-100M
LMK61E0-050M, LMK61E0-155M, LMK61E0-156M, LMK61E2-100M, LMK61E2-125M
LMK61E2-156M, LMK61E2-312M, LMK61A2-100M, LMK61A2-125M, LMK61A2-156M
LMK61A2-312M, LMK61A2-644M, LMK61I2-100M
www.ti.com
SNAS676D – OCTOBER 2015 – REVISED OCTOBER 2017
Typical Characteristics (continued)
0.9
1.7
Output Differential Swing (Vp-p)
Output Differential Swing (Vp-p)
1.8
1.6
1.5
1.4
1.3
1.2
1.1
0.8
0.7
0.6
0.5
0
200
400
600
Output Frequency (MHz)
800
1000
0
200
D013
Figure 7. LVPECL Differential Output Swing vs Frequency
400
600
Output Frequency (MHz)
800
1000
D014
Figure 8. LVDS Differential Output Swing vs Frequency
Output Differential Swing (Vp-p)
1.5
1.48
1.46
1.44
1.42
1.4
0
100
200
300
Output Frequency (MHz)
400
500
D015
Figure 9. HCSL Differential Output Swing vs Frequency
Copyright © 2015–2017, Texas Instruments Incorporated
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Product Folder Links: LMK61E0-050M LMK61E0-155M LMK61E0-156M LMK61E2-100M LMK61E2-125M LMK61E2156M LMK61E2-312M LMK61A2-100M LMK61A2-125M LMK61A2-156M LMK61A2-312M LMK61A2-644M
LMK61I2-100M
9
LMK61E0-050M, LMK61E0-155M, LMK61E0-156M, LMK61E2-100M, LMK61E2-125M
LMK61E2-156M, LMK61E2-312M, LMK61A2-100M, LMK61A2-125M, LMK61A2-156M
LMK61A2-312M, LMK61A2-644M, LMK61I2-100M
SNAS676D – OCTOBER 2015 – REVISED OCTOBER 2017
www.ti.com
7 Parameter Measurement Information
7.1 Device Output Configurations
High impedance differential probe
LMK61XX
LVPECL
150
Oscilloscope
150
Figure 10. LVPECL Output DC Configuration During Device Test
High impedance differential probe
LMK61XX
LVDS
Oscilloscope
Figure 11. LVDS Output DC Configuration During Device Test
High impedance differential probe
HCSL
LMK61XX
50
Oscilloscope
50
Figure 12. HCSL Output DC Configuration During Device Test
LMK61XX
Balun/
Buffer
LVPECL
150
Phase Noise/
Spectrum
Analyzer
150
Figure 13. LVPECL Output AC Configuration During Device Test
LMK61XX
LVDS
Balun/
Buffer
Phase Noise/
Spectrum
Analyzer
Figure 14. LVDS Output AC Configuration During Device Test
10
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Product Folder Links: LMK61E0-050M LMK61E0-155M LMK61E0-156M LMK61E2-100M LMK61E2-125M LMK61E2156M LMK61E2-312M LMK61A2-100M LMK61A2-125M LMK61A2-156M LMK61A2-312M LMK61A2-644M
LMK61I2-100M
LMK61E0-050M, LMK61E0-155M, LMK61E0-156M, LMK61E2-100M, LMK61E2-125M
LMK61E2-156M, LMK61E2-312M, LMK61A2-100M, LMK61A2-125M, LMK61A2-156M
LMK61A2-312M, LMK61A2-644M, LMK61I2-100M
www.ti.com
SNAS676D – OCTOBER 2015 – REVISED OCTOBER 2017
Device Output Configurations (continued)
LMK61XX
Balun/
Buffer
HCSL
50
Phase Noise/
Spectrum
Analyzer
50
Figure 15. HCSL Output AC Configuration During Device Test
Sine wave
Modulator
Power Supply
LMK61XX
Balun
150 (LVPECL)
Open (LVDS)
50 (HCSL)
Phase Noise/
Spectrum
Analyzer
150 (LVPECL)
Open (LVDS)
50 (HCSL)
Figure 16. PSRR Test Setup
OUT_P
VOD
OUT_N
80%
VOUT,DIFF,PP = 2 x VOD
0V
20%
tR
tF
Figure 17. Differential Output Voltage and Rise/Fall Time
Copyright © 2015–2017, Texas Instruments Incorporated
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Product Folder Links: LMK61E0-050M LMK61E0-155M LMK61E0-156M LMK61E2-100M LMK61E2-125M LMK61E2156M LMK61E2-312M LMK61A2-100M LMK61A2-125M LMK61A2-156M LMK61A2-312M LMK61A2-644M
LMK61I2-100M
11
LMK61E0-050M, LMK61E0-155M, LMK61E0-156M, LMK61E2-100M, LMK61E2-125M
LMK61E2-156M, LMK61E2-312M, LMK61A2-100M, LMK61A2-125M, LMK61A2-156M
LMK61A2-312M, LMK61A2-644M, LMK61I2-100M
SNAS676D – OCTOBER 2015 – REVISED OCTOBER 2017
www.ti.com
8 Power Supply Recommendations
For best electrical performance of LMK61XX, TI recommends using a combination of 10 µF, 1 µF and 0.1 µF on
its power supply bypass network. TI also recommends using component side mounting of the power supply
bypass capacitors and it is best to use 0201 or 0402 body size capacitors to facilitate signal routing. Keep the
connections between the bypass capacitors and the power supply on the device as short as possible. Ground the
other side of the capacitor using a low impedance connection to the ground plane. Figure 18 shows the layout
recommendation for power supply decoupling of LMK61XX.
9 Layout
9.1 Layout Guidelines
The following sections provides recommendations for board layout, solder reflow profile and power supply
bypassing when using LMK61XX to ensure good thermal / electrical performance and overall signal integrity of
entire system.
9.1.1 Ensuring Thermal Reliability
The LMK61XX is a high performance device. Therefore, pay careful attention to device configuration and printedcircuit board (PCB) layout with respect to power consumption. The ground pin needs to be connected to the
ground plane of the PCB through three vias or more, as shown in Figure 18, to maximize thermal dissipation out
of the package.
Equation 1 describes the relationship between the PCB temperature around the LMK61XX and its junction
temperature.
TB = TJ – ΨJB × P
where
•
•
•
•
TB: PCB temperature around the LMK61XX
TJ: Junction temperature of LMK61XX
ΨJB: Junction-to-board thermal resistance parameter of LMK61XX (37.7°C/W without airflow)
P: On-chip power dissipation of LMK61XX
(1)
To ensure that the maximum junction temperature of LMK61X2 is below 125°C, the maximum PCB temperature
without airflow should be at 99°C or below (89°C or below for LMK61X0) when the device is optimized for best
performance resulting in maximum on-chip power dissipation of 0.68 W.
9.1.2 Best Practices for Signal Integrity
For best electrical performance and signal integrity of entire system with LMK61XX, TI recommends routing vias
into decoupling capacitors and then into the LMK61XX. TI also recommends increasing the via count and width
of the traces wherever possible. These steps ensure lowest impedance and shortest path for high frequency
current flow. Figure 18 shows the layout recommendation for LMK61XX.
12
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LMK61I2-100M
LMK61E0-050M, LMK61E0-155M, LMK61E0-156M, LMK61E2-100M, LMK61E2-125M
LMK61E2-156M, LMK61E2-312M, LMK61A2-100M, LMK61A2-125M, LMK61A2-156M
LMK61A2-312M, LMK61A2-644M, LMK61I2-100M
www.ti.com
SNAS676D – OCTOBER 2015 – REVISED OCTOBER 2017
Layout Guidelines (continued)
Figure 18. LMK61XX Layout Recommendation for Power Supply and Ground
9.1.3 Recommended Solder Reflow Profile
TI recommends following the solder paste supplier's recommendations to optimize flux activity and to achieve
proper melting temperatures of the alloy within the guidelines of J-STD-20. It is preferrable for the LMK61XX to
be processed with the lowest peak temperature possible while also remaining below the components peak
temperature rating as listed on the MSL label. The exact temperature profile would depend on several factors
including maximum peak temperature for the component as rated on the MSL label, Board thickness, PCB
material type, PCB geometries, component locations, sizes, densities within PCB, as well solder manufactures
recommended profile, and capability of the reflow equipment to as confirmed by the SMT assembly operation.
Copyright © 2015–2017, Texas Instruments Incorporated
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LMK61I2-100M
13
LMK61E0-050M, LMK61E0-155M, LMK61E0-156M, LMK61E2-100M, LMK61E2-125M
LMK61E2-156M, LMK61E2-312M, LMK61A2-100M, LMK61A2-125M, LMK61A2-156M
LMK61A2-312M, LMK61A2-644M, LMK61I2-100M
SNAS676D – OCTOBER 2015 – REVISED OCTOBER 2017
www.ti.com
10 Device and Documentation Support
10.1 Related Links
The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to sample or buy.
Table 1. Related Links
PARTS
PRODUCT FOLDER
SAMPLE & BUY
TECHNICAL
DOCUMENTS
TOOLS &
SOFTWARE
SUPPORT &
COMMUNITY
LMK61E0-050M
Click here
Click here
Click here
Click here
Click here
LMK61E0-155M
Click here
Click here
Click here
Click here
Click here
LMK61E0-156M
Click here
Click here
Click here
Click here
Click here
LMK61E2-100M
Click here
Click here
Click here
Click here
Click here
LMK61E2-125M
Click here
Click here
Click here
Click here
Click here
LMK61E2-156M
Click here
Click here
Click here
Click here
Click here
LMK61E2-312M
Click here
Click here
Click here
Click here
Click here
LMK61A2-100M
Click here
Click here
Click here
Click here
Click here
LMK61A2-125M
Click here
Click here
Click here
Click here
Click here
LMK61A2-156M
Click here
Click here
Click here
Click here
Click here
LMK61A2-312M
Click here
Click here
Click here
Click here
Click here
LMK61A2-644M
Click here
Click here
Click here
Click here
Click here
LMK61I2-100M
Click here
Click here
Click here
Click here
Click here
10.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
10.3 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
10.4 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
10.5 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
10.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
14
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Product Folder Links: LMK61E0-050M LMK61E0-155M LMK61E0-156M LMK61E2-100M LMK61E2-125M LMK61E2156M LMK61E2-312M LMK61A2-100M LMK61A2-125M LMK61A2-156M LMK61A2-312M LMK61A2-644M
LMK61I2-100M
LMK61E0-050M, LMK61E0-155M, LMK61E0-156M, LMK61E2-100M, LMK61E2-125M
LMK61E2-156M, LMK61E2-312M, LMK61A2-100M, LMK61A2-125M, LMK61A2-156M
LMK61A2-312M, LMK61A2-644M, LMK61I2-100M
www.ti.com
SNAS676D – OCTOBER 2015 – REVISED OCTOBER 2017
11 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
Copyright © 2015–2017, Texas Instruments Incorporated
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Product Folder Links: LMK61E0-050M LMK61E0-155M LMK61E0-156M LMK61E2-100M LMK61E2-125M LMK61E2156M LMK61E2-312M LMK61A2-100M LMK61A2-125M LMK61A2-156M LMK61A2-312M LMK61A2-644M
LMK61I2-100M
15
LMK61E0-050M, LMK61E0-155M, LMK61E0-156M, LMK61E2-100M, LMK61E2-125M
LMK61E2-156M, LMK61E2-312M, LMK61A2-100M, LMK61A2-125M, LMK61A2-156M
LMK61A2-312M, LMK61A2-644M, LMK61I2-100M
SNAS676D – OCTOBER 2015 – REVISED OCTOBER 2017
www.ti.com
PACKAGE OUTLINE
SIA0006A
QFM - 1.15 mm max height
SCALE 2.200
QUAD FLAT MODULE
5.1
4.9
A
B
PIN 1 INDEX
AREA
7.1
6.9
C
1.15 MAX
0.1 C
3X 3.7
6X (0.15)
3
4
4X (0.26)
SYMM
2X
5.08
4X
2.54
6X
0.1
0.05
6
1
SYMM
1.43
1.37
6X
C A
C
B
1.03
0.97
4222361/B 10/2015
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
www.ti.com
16
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Product Folder Links: LMK61E0-050M LMK61E0-155M LMK61E0-156M LMK61E2-100M LMK61E2-125M LMK61E2156M LMK61E2-312M LMK61A2-100M LMK61A2-125M LMK61A2-156M LMK61A2-312M LMK61A2-644M
LMK61I2-100M
LMK61E0-050M, LMK61E0-155M, LMK61E0-156M, LMK61E2-100M, LMK61E2-125M
LMK61E2-156M, LMK61E2-312M, LMK61A2-100M, LMK61A2-125M, LMK61A2-156M
LMK61A2-312M, LMK61A2-644M, LMK61I2-100M
www.ti.com
SNAS676D – OCTOBER 2015 – REVISED OCTOBER 2017
EXAMPLE BOARD LAYOUT
SIA0006A
QFM - 1.15 mm max height
QUAD FLAT MODULE
SYMM
6X (1)
1
6
6X (1.4)
SYMM
4X (2.54)
4
3
(R0.05) TYP
(3.7)
LAND PATTERN EXAMPLE
1:1 RATIO WITH PACKAGE SOLDER PADS
SCALE:8X
0.07 MIN
ALL AROUND
METAL
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
NOT TO SCALE
4222361/B 10/2015
NOTES: (continued)
3. For more information, see Texas Instruments literature number SLUA271 (www.ti.com/lit/slua271).
www.ti.com
Copyright © 2015–2017, Texas Instruments Incorporated
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Product Folder Links: LMK61E0-050M LMK61E0-155M LMK61E0-156M LMK61E2-100M LMK61E2-125M LMK61E2156M LMK61E2-312M LMK61A2-100M LMK61A2-125M LMK61A2-156M LMK61A2-312M LMK61A2-644M
LMK61I2-100M
17
LMK61E0-050M, LMK61E0-155M, LMK61E0-156M, LMK61E2-100M, LMK61E2-125M
LMK61E2-156M, LMK61E2-312M, LMK61A2-100M, LMK61A2-125M, LMK61A2-156M
LMK61A2-312M, LMK61A2-644M, LMK61I2-100M
SNAS676D – OCTOBER 2015 – REVISED OCTOBER 2017
www.ti.com
EXAMPLE STENCIL DESIGN
SIA0006A
QFM - 1.15 mm max height
QUAD FLAT MODULE
SYMM
12X (1)
1
6
12X (0.6)
METAL TYP
(R0.05)
SYMM
4X (2.54)
4
3
(0.4) TYP
(3.7)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
PRINTED SOLDER COVERAGE BY AREA
ALL PADS: 86%
SCALE:10X
4222361/B 10/2015
NOTES: (continued)
4. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
18
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Product Folder Links: LMK61E0-050M LMK61E0-155M LMK61E0-156M LMK61E2-100M LMK61E2-125M LMK61E2156M LMK61E2-312M LMK61A2-100M LMK61A2-125M LMK61A2-156M LMK61A2-312M LMK61A2-644M
LMK61I2-100M
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
LMK61A2-100M00SIAR
ACTIVE
QFM
SIA
6
2500
RoHS & Green
NIAU
Level-3-260C-168 HR
-40 to 85
LMK61A2
100M00
LMK61A2-100M00SIAT
ACTIVE
QFM
SIA
6
250
RoHS & Green
NIAU
Level-3-260C-168 HR
-40 to 85
LMK61A2
100M00
LMK61A2-125M00SIAR
ACTIVE
QFM
SIA
6
2500
RoHS & Green
NIAU
Level-3-260C-168 HR
-40 to 85
LMK61A2
125M00
LMK61A2-125M00SIAT
ACTIVE
QFM
SIA
6
250
RoHS & Green
NIAU
Level-3-260C-168 HR
-40 to 85
LMK61A2
125M00
LMK61A2-156M25SIAR
ACTIVE
QFM
SIA
6
2500
RoHS & Green
NIAU
Level-3-260C-168 HR
-40 to 85
LMK61A2
156M25
LMK61A2-156M25SIAT
ACTIVE
QFM
SIA
6
250
RoHS & Green
NIAU
Level-3-260C-168 HR
-40 to 85
LMK61A2
156M25
LMK61A2-312M50SIAR
ACTIVE
QFM
SIA
6
2500
RoHS & Green
NIAU
Level-3-260C-168 HR
-40 to 85
LMK61A2
312M50
LMK61A2-312M50SIAT
ACTIVE
QFM
SIA
6
250
RoHS & Green
NIAU
Level-3-260C-168 HR
-40 to 85
LMK61A2
312M50
LMK61A2-644M53SIAR
ACTIVE
QFM
SIA
6
2500
RoHS & Green
NIAU
Level-3-260C-168 HR
-40 to 85
LMK61A2
644M53
LMK61A2-644M53SIAT
ACTIVE
QFM
SIA
6
250
RoHS & Green
NIAU
Level-3-260C-168 HR
-40 to 85
LMK61A2
644M53
LMK61E0-050M00SIAR
ACTIVE
QFM
SIA
6
2500
RoHS & Green
NIAU
Level-3-260C-168 HR
-40 to 85
LMK61E0
050M00
LMK61E0-050M00SIAT
ACTIVE
QFM
SIA
6
250
RoHS & Green
NIAU
Level-3-260C-168 HR
-40 to 85
LMK61E0
050M00
LMK61E0-155M52SIAR
ACTIVE
QFM
SIA
6
2500
RoHS & Green
NIAU
Level-3-260C-168 HR
-40 to 85
LMK61E0
155M52
LMK61E0-155M52SIAT
ACTIVE
QFM
SIA
6
250
RoHS & Green
NIAU
Level-3-260C-168 HR
-40 to 85
LMK61E0
155M52
LMK61E0-156M25SIAR
ACTIVE
QFM
SIA
6
2500
RoHS & Green
NIAU
Level-3-260C-168 HR
-40 to 85
LMK61E0
156M25
LMK61E0-156M25SIAT
ACTIVE
QFM
SIA
6
250
RoHS & Green
NIAU
Level-3-260C-168 HR
-40 to 85
LMK61E0
156M25
LMK61E2-100M00SIAR
ACTIVE
QFM
SIA
6
2500
RoHS & Green
NIAU
Level-3-260C-168 HR
-40 to 85
LMK61E2
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
Orderable Device
10-Dec-2020
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
100M00
LMK61E2-100M00SIAT
ACTIVE
QFM
SIA
6
250
RoHS & Green
NIAU
Level-3-260C-168 HR
-40 to 85
LMK61E2
100M00
LMK61E2-125M00SIAR
ACTIVE
QFM
SIA
6
2500
RoHS & Green
NIAU
Level-3-260C-168 HR
-40 to 85
LMK61E2
125M00
LMK61E2-125M00SIAT
ACTIVE
QFM
SIA
6
250
RoHS & Green
NIAU
Level-3-260C-168 HR
-40 to 85
LMK61E2
125M00
LMK61E2-156M25SIAR
ACTIVE
QFM
SIA
6
2500
RoHS & Green
NIAU
Level-3-260C-168 HR
-40 to 85
LMK61E2
156M25
LMK61E2-156M25SIAT
ACTIVE
QFM
SIA
6
250
RoHS & Green
NIAU
Level-3-260C-168 HR
-40 to 85
LMK61E2
156M25
LMK61E2-312M50SIAR
ACTIVE
QFM
SIA
6
2500
RoHS & Green
NIAU
Level-3-260C-168 HR
-40 to 85
LMK61E2
312M50
LMK61E2-312M50SIAT
ACTIVE
QFM
SIA
6
250
RoHS & Green
NIAU
Level-3-260C-168 HR
-40 to 85
LMK61E2
312M50
LMK61I2-100M00SIAR
ACTIVE
QFM
SIA
6
2500
RoHS & Green
NIAU
Level-3-260C-168 HR
-40 to 85
LMK61I2
100M00
LMK61I2-100M00SIAT
ACTIVE
QFM
SIA
6
250
RoHS & Green
NIAU
Level-3-260C-168 HR
-40 to 85
LMK61I2
100M00
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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