LMK61PD0A2-SIAR

Product Folder Sample & Buy Support & Community Tools & Software Technical Documents LMK61PD0A2 SNAS675A – OCTOBER 2015 – REVISED NOVEMBER 2015 LMK61PD0A2 Ultra-Low Jitter Pin Selectable Oscillator 1 Features 3 Description • The LMK61PD0A2 is an ultra-low jitter PLLatinumTM pin selectable oscillator that generates commonly used reference clocks. The device is preprogrammed in factory to support seven unique reference clock frequencies that can be selected by pin-strapping each of FS[1:0] to VDD, GND or NC (no connect). Output format is selected between LVPECL, LVDS, or HCSL by pin-strapping OS to VDD, GND or NC. Internal power conditioning provide excellent power supply ripple rejection (PSRR), reducing the cost and complexity of the power delivery network. The device operates from a single 3.3 V ± 5% supply. 1 • • • • • • Ultra-low Noise, High Performance – Jitter: 90 fs RMS typical fOUT > 100 MHz – PSRR: -70 dBc, robust supply noise immunity Flexible Output Frequency and Format; User Selectable – Frequencies: 62.5 MHz, 100 MHz, 106.25 MHz, 125 MHz, 156.25 MHz, 212.5 MHz, 312.5 MHz – Formats: LVPECL, LVDS or HCSL Total frequency tolerance of ± 50 ppm Internal memory stores multiple start-up configurations, selectable through pin control 3.3V operating voltage Industrial temperature range (-40ºC to +85ºC) 7 mm x 5 mm 8-pin package Device Information(1) PART NUMBER LMK61PD0A2 PACKAGE 8-pin QFM (SIA) BODY SIZE (NOM) 7.0 mm x 5.0 mm (1) For all available packages, see the orderable addendum at the end of the data sheet. 2 Applications • • • • • High-performance replacement for crystal-, SAW-, or silicon-based Oscillators Switches, Routers, Network Line Cards, Base Band Units (BBU), Servers, Storage/SAN Test and Measurement Medical Imaging FPGA, Processor Attach Pinout and Simplified Block Diagram FS1 Power Conditioning 7 OE 1 6 VDD OS 2 5 OUTN GND 3 4 OUTP Integrated Oscillator PLL Output Divider Interface ROM (Pin Control) 8 FS0 Output Buffer LMK61PD0A2 Ultra-high performance oscillator 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. LMK61PD0A2 SNAS675A – OCTOBER 2015 – REVISED NOVEMBER 2015 www.ti.com Table of Contents 1 2 3 4 5 6 7 Features .................................................................. Applications ........................................................... Description ............................................................. Revision History..................................................... Device Control........................................................ Pin Configuration and Functions ......................... Specifications......................................................... 1 1 1 2 3 4 5 7.1 7.2 7.3 7.4 7.5 7.6 7.7 7.8 7.9 7.10 7.11 7.12 7.13 7.14 5 5 5 5 6 6 6 7 7 7 7 8 8 9 Absolute Maximum Ratings ...................................... ESD Ratings ............................................................ Recommended Operating Conditions....................... Thermal Information .................................................. Electrical Characteristics - Power Supply ................. LVPECL Output Characteristics................................ LVDS Output Characteristics .................................... HCSL Output Characteristics.................................... OE Input Characteristics ........................................... OS, FS[1:0] Input Characteristics ........................... Frequency Tolerance Characteristics ..................... Power-On/Reset Characteristics (VDD).................. PSRR Characteristics ............................................. PLL Clock Output Jitter Characteristics .................. 7.15 Additional Reliability and Qualification .................... 9 7.16 Typical Performance Characteristics .................... 10 8 Parameter Measurement Information ................ 11 9 Detailed Description ............................................ 13 8.1 Device Output Configurations ................................. 11 9.1 Overview ................................................................. 13 9.2 Functional Block Diagram ....................................... 13 9.3 Feature Description................................................. 13 10 Application and Implementation........................ 14 10.1 Application Information.......................................... 14 10.2 Typical Application ................................................ 14 11 Power Supply Recommendations ..................... 16 12 Layout................................................................... 17 12.1 Layout Guidelines ................................................. 17 13 Device and Documentation Support ................. 19 13.1 13.2 13.3 13.4 Community Resources.......................................... Trademarks ........................................................... Electrostatic Discharge Caution ............................ Glossary ................................................................ 19 19 19 19 14 Mechanical, Packaging, and Orderable Information ........................................................... 19 4 Revision History Changes from Original (October 2015) to Revision A • 2 Page Product Preview to Production Data Release ....................................................................................................................... 1 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: LMK61PD0A2 LMK61PD0A2 www.ti.com SNAS675A – OCTOBER 2015 – REVISED NOVEMBER 2015 5 Device Control Table 1. Output Frequency Mapping for FS[1:0] Selection FS1 FS0 OUT FREQUENCY (MHz) RELEVANT STANDARDS 0 0 100 PCI Express 0 NC 312.5 10 Gbps Ethernet 0 1 125 1 Gbps Ethernet NC 0 106.25 Fiber Channel NC NC 156.25 10 Gbps Ethernet NC 1 212.5 Fiber Channel 1 0 62.5 1 Gbps Ethernet 1 NC Reserved n/a 1 1 Reserved n/a Table 2. Output Type Mapping for OS, OE Selection OS OE OUTPUT TYPE X 0 Disabled (PLL functional) 0 1 LVPECL NC 1 LVDS 1 1 HCSL Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: LMK61PD0A2 3 LMK61PD0A2 SNAS675A – OCTOBER 2015 – REVISED NOVEMBER 2015 www.ti.com 6 Pin Configuration and Functions SIA Package 8 pin QFM FS1 7 OE 1 6 VDD OS 2 5 OUTN GND 3 4 OUTP 8 FS0 Table 3. Pin Functions PIN NAME NO. I/O DESCRIPTION POWER GND 3 Ground Device Ground. VDD 6 Analog 3.3 V Power Supply. 4, 5 Universal OUTPUT BLOCK OUTP, OUTN Differential Output Pair (LVPECL, LVDS or HCSL). DIGITAL CONTROL / INTERFACES FS[1:0] 7, 8 LVCMOS Output Frequency Select. Refer toTable 1. OE 1 LVCMOS Output Enable (internal pullup). Refer toTable 2. OS 3 LVCMOS Output Type Select. Refer toTable 2. 4 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: LMK61PD0A2 LMK61PD0A2 www.ti.com SNAS675A – OCTOBER 2015 – REVISED NOVEMBER 2015 7 Specifications 7.1 Absolute Maximum Ratings over operating free-air temperature range (unless otherwise noted) (1) MIN MAX UNIT VDD Device Supply Voltage -0.3 3.6 V VIN Output Voltage Range for Logic Inputs -0.3 VDD + 0.3 V VOUT Output Voltage Range for Clock Outputs -0.3 VDD + 0.3 V TJ Junction Temperature 150 °C TSTG Storage Temperature 125 °C (1) -40 Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute maximum-rated conditions for extended periods may affect device reliability. 7.2 ESD Ratings VALUE Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 V(ESD) (1) (2) Electrostatic discharge (1) UNIT ±4000 Charged-device model (CDM), per JEDEC specification JESD22C101 (2) V ±1500 JEDEC document JEP155 states that 500 V HBM allows safe manufacturing with a standard ESD control process. JEDEC document JEP157 states that 250 V CDM allows safe manufacturing with a standard ESD control process. 7.3 Recommended Operating Conditions over operating free-air temperature range (unless otherwise noted) MIN NOM MAX UNIT VDD Device Supply Voltage 3.135 3.3 3.465 V TA Ambient Temperature -40 25 85 °C TJ Junction Temperature tRAMP VDD Power-Up Ramp Time 0.1 125 °C 100 ms 7.4 Thermal Information LMK61PD0A2 QFM (SIA) THERMAL METRIC (1) UNIT 8 PINS Airflow (LFM) 0 RθJA (2) (3) (4) Junction-to-ambient thermal resistance RθJC(top) Junction-to-case (top) thermal resistance Airflow (LFM) 200 Airflow (LFM) 400 54 44 41.2 34 n/a n/a RθJB Junction-to-board thermal resistance 36.7 n/a n/a ψJT Junction-to-top characterization parameter 11.2 16.9 21.9 ψJB Junction-to-board characterization parameter 36.7 37.8 38.9 RθJC(bot) Junction-to-case (bottom) thermal resistance n/a n/a n/a (1) (2) (3) (4) °C/W For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953. The package thermal resistance is calculated on a 4 layer JEDEC board. Connected to GND with 3 thermal vias (0.3-mm diameter). ψJB (junction to board) is used when the main heat flow is from the junction to the GND pad. Please refer to Thermal Considerations section for more information on ensuring good system reliability and quality. Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: LMK61PD0A2 5 LMK61PD0A2 SNAS675A – OCTOBER 2015 – REVISED NOVEMBER 2015 www.ti.com 7.5 Electrical Characteristics - Power Supply (1) VDD = 3.3 V ± 5%, TA = -40C to 85°C PARAMETER IDD Device Current Consumption IDD-PD (1) (2) TEST CONDITIONS Device Current Consumption when output is disabled LVPECL MIN (2) TYP MAX UNIT mA 162 208 LVDS 152 196 HCSL 155 196 OE = GND 136 Refer to Parameter Measurement Information for relevant test conditions. On-chip power dissipation should exclude 40 mW, dissipated in the 150 ohm termination resistors, from total power dissipation. 7.6 LVPECL Output Characteristics (1) VDD = 3.3 V ± 5%, TA = -40C to 85°C PARAMETER TEST CONDITIONS MIN fOUT Output Frequency (2) 62.5 VOD Output Voltage Swing (VOH - VOL) (2) 700 VOUT, DIFF, PP Differential Output Peak-toPeak Swing VOS Output Common Mode Voltage tR / tF Output Rise/Fall Time (20% to 80%) (3) PN-Floor Output Phase Noise Floor (fOFFSET > 10 MHz) ODC Output Duty Cycle (3) (1) (2) (3) TYP 800 UNIT MHz 1200 mV 2x |VOD| V VDD – 1.55 V 120 156.25 MHz MAX 312.5 200 -165 45% ps dBc/Hz 55% Refer to Parameter Measurement Information for relevant test conditions. An output frequency over fOUT max spec is possible, but output swing may be less than VOD min spec. Ensured by characterization. 7.7 LVDS Output Characteristics (1) VDD = 3.3 V ± 5%, TA = -40°C to 85°C PARAMETER TEST CONDITIONS (1) fOUT Output Frequency VOD Output Voltage Swing (VOH - VOL) (1) VOUT, DIFF, PP Differential Output Peak-toPeak Swing VOS MIN TYP 62.5 300 390 MAX UNIT 312.5 MHz 480 mV 2x |VOD| V Output Common Mode Voltage 1.2 V tR / tF Output Rise/Fall Time (20% to 80%) (2) 150 PN-Floor Output Phase Noise Floor (fOFFSET > 10 MHz) ODC Output Duty Cycle (2) ROUT Differential Output Impedance (1) (2) 6 156.25 MHz 250 -162 45% ps dBc/Hz 55% 125 Ohm An output frequency over fOUT max spec is possible, but output swing may be less than VOD min spec. Ensured by characterization. Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: LMK61PD0A2 LMK61PD0A2 www.ti.com SNAS675A – OCTOBER 2015 – REVISED NOVEMBER 2015 7.8 HCSL Output Characteristics (1) VDD = 3.3 V ± 5%, TA = -40°C to 85°C PARAMETER TEST CONDITIONS MIN TYP MAX UNIT fOUT Output Frequency 62.5 312.5 MHz VOH Output High Voltage 600 850 mV VOL Output Low Voltage -100 100 mV VCROSS Absolute Crossing Voltage (2) (3) 250 475 mV 0 140 mV 0.8 2 V/ns VCROSS-DELTA Variation of VCROSS (2) (3) dV/dt Slew Rate (4) PN-Floor Output Phase Noise Floor (fOFFSET > 10 MHz) ODC Output Duty Cycle (4) (1) (2) (3) (4) 100 MHz -164 45% dBc/Hz 55% Refer to Parameter Measurement Information for relevant test conditions. Measured from -150 mV to +150 mV on the differential waveform with the 300 mVpp measurement window centered on the differential zero crossing. Ensured by design. Ensured by characterization. 7.9 OE Input Characteristics VDD = 3.3 V ± 5%, TA = -40°C to 85°C PARAMETER TEST CONDITIONS MIN VIH Input High Voltage VIL Input Low Voltage IIH Input High Current VIH = VDD -40 IIL Input Low Current VIL = GND -40 CIN Input Capacitance TYP MAX UNIT 1.4 V 0.6 V 40 uA 40 uA 2 pF 7.10 OS, FS[1:0] Input Characteristics VDD = 3.3 V ± 5%, TA = -40°C to 85°C PARAMETER TEST CONDITIONS MIN TYP MAX 1.4 UNIT VIH Input High Voltage V VIL Input Low Voltage 0.4 V IIH Input High Current VIH = VDD -40 40 uA IIL Input Low Current VIL = GND -40 40 uA CIN Input Capacitance 2 pF 7.11 Frequency Tolerance Characteristics (1) VDD = 3.3 V ± 5%, TA = -40°C to 85°C PARAMETER fT (1) Total Frequency Tolerance TEST CONDITIONS All output formats, frequency bands and device junction temperature up to 125°C; includes initial freq tolerance, temperature & supply voltage variation, solder reflow and aging (10 years) MIN -50 TYP MAX UNIT 50 ppm Ensured by characterization. Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: LMK61PD0A2 7 LMK61PD0A2 SNAS675A – OCTOBER 2015 – REVISED NOVEMBER 2015 www.ti.com 7.12 Power-On/Reset Characteristics (VDD) VDD = 3.3 V ± 5%, TA = -40°C to 85°C PARAMETER TEST CONDITIONS (1) VTHRESH Threshold Voltage VDROOP Allowable Voltage Droop (2) tSTARTUP Startup Time tOE-EN tOE-DIS (1) (2) MIN TYP 2.72 MAX UNIT 2.95 V 0.1 V Time elapsed from VDD at 3.135 V to output enabled 10 ms Output enable time (2) Time elapsed from OE at VIH to output enabled 50 us Output disable time (2) Time elapsed from OE at VIL to output disabled 50 us MAX UNIT (1) Ensured by characterization. Ensured by design. 7.13 PSRR Characteristics (1) VDD = 3.3 V, TA = 25°C, FS[1:0] = NC, NC PARAMETER PSRR (1) (2) (3) 8 Spurs Induced by 50 mV Power Supply Ripple (2) (3) at 156.25 MHz output, all output types TEST CONDITIONS MIN TYP Sine wave at 50 kHz -70 Sine wave at 100 kHz -70 Sine wave at 500 kHz -70 Sine wave at 1 MHz -70 dBc Refer to Parameter Measurement Information for relevant test conditions. Measured max spur level with 50 mVpp sinusoidal signal between 50 kHz and 1 MHz applied on VDD pin DJSPUR (ps, pk-pk) = [2*10(SPUR/20) / (π*fOUT)]*1e6, where PSRR or SPUR in dBc and fOUT in MHz. Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: LMK61PD0A2 LMK61PD0A2 www.ti.com SNAS675A – OCTOBER 2015 – REVISED NOVEMBER 2015 7.14 PLL Clock Output Jitter Characteristics (1) (2) VDD = 3.3 V ± 5%, TA = -40°C to 85°C PARAMETER TEST CONDITIONS (3) MIN TYP MAX UNIT RJ RMS Phase Jitter (12 kHz – 20 MHz) (1 kHz – 5 MHz) fOUT ≥ 100 MHz, All output frequencies and output types 100 200 fs RMS RJ RMS Phase Jitter (3) (12 kHz – 20 MHz) (1 kHz – 5 MHz) fOUT = 62.5 MHz, All output frequencies and output types 200 400 fs RMS (1) (2) (3) Refer to Parameter Measurement Information for relevant test conditions. Phase jitter measured with Agilent E5052 signal source analyzer using a differential-to-single ended converter (balun or buffer). Ensured by characterization. 7.15 Additional Reliability and Qualification PARAMETER CONDITION / TEST METHOD Mechanical Shock MIL-STD-202, Method 213 Mechanical Vibration MIL-STD-202, Method 204 Moisture Sensitivity Level J-STD-020, MSL3 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: LMK61PD0A2 9 LMK61PD0A2 SNAS675A – OCTOBER 2015 – REVISED NOVEMBER 2015 www.ti.com 7.16 Typical Performance Characteristics Figure 1. Phase Noise of LVPECL Differential Output at 156.25 MHz with FS[1:0] = NC, NC, OS = GND Figure 2. Phase Noise of LVDS Differential Output at 156.25 MHz with FS[1:0] = NC, NC, OS = NC Output Differential Swing (Vp-p) 1.8 1.75 1.7 1.65 1.6 1.55 1.5 0 50 100 150 200 250 Output Frequency (MHz) 300 350 D016 Figure 4. LVPECL Differential Output Swing vs Frequency Figure 3. Phase Noise of HCSL Differential Output at 156.25 MHz with FS[1:0] = NC, NC, OS = VDD 1.48 Output Differential Swing (Vp-p) Output Differential Swing (Vp-p) 0.95 0.9 0.85 0.8 0.75 0.7 1.46 1.45 1.44 1.43 1.42 0 50 100 150 200 250 Output Frequency (MHz) 300 350 0 D017 Figure 5. LVDS Differential Output Swing vs Frequency 10 1.47 50 100 150 200 250 Output Frequency (MHz) 300 350 D018 Figure 6. HCSL Differential Output Swing vs Frequency Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: LMK61PD0A2 LMK61PD0A2 www.ti.com SNAS675A – OCTOBER 2015 – REVISED NOVEMBER 2015 8 Parameter Measurement Information 8.1 Device Output Configurations High impedance differential probe LMK61PD0A2 LVPECL 150 Oscilloscope 150 Figure 7. LVPECL Output DC Configuration during Device Test High impedance differential probe LMK61PD0A2 LVDS Oscilloscope Figure 8. LVDS Output DC Configuration during Device Test High impedance differential probe HCSL LMK61PD0A2 50 Oscilloscope 50 Figure 9. HCSL Output DC Configuration during Device Test LMK61PD0A2 Balun/ Buffer LVPECL 150 Phase Noise/ Spectrum Analyzer 150 Figure 10. LVPECL Output AC Configuration during Device Test LMK61PD0A2 LVDS Balun/ Buffer Phase Noise/ Spectrum Analyzer Figure 11. LVDS Output AC Configuration during Device Test Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: LMK61PD0A2 11 LMK61PD0A2 SNAS675A – OCTOBER 2015 – REVISED NOVEMBER 2015 www.ti.com Device Output Configurations (continued) LMK61PD0A2 Balun/ Buffer HCSL 50 Phase Noise/ Spectrum Analyzer 50 Figure 12. HCSL Output AC Configuration during Device Test Sine wave Modulator Power Supply LMK61PD0A2 Balun 150 (LVPECL) Open (LVDS) 50 (HCSL) Phase Noise/ Spectrum Analyzer 150 (LVPECL) Open (LVDS) 50 (HCSL) Figure 13. PSRR Test Setup OUT_P VOD OUT_N 80% VOUT,DIFF,PP = 2 x VOD 0V 20% tR tF Figure 14. Differential Output Voltage and Rise/Fall Time 12 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: LMK61PD0A2 LMK61PD0A2 www.ti.com SNAS675A – OCTOBER 2015 – REVISED NOVEMBER 2015 9 Detailed Description 9.1 Overview The LMK61PD0A2 is a pin selectable oscillator that generates commonly used reference clocks, greater than 100 MHz, with less than 200 fs, rms max random jitter. 9.2 Functional Block Diagram VDD Power Conditioning PLL Integrated Oscillator Output XO Integer Div ¥ LVPECL or LVDS or HCSL Control FS1 N Div 3 ™û fractional FS0 3 OS 3 ROM (Pin Control) OE 3 = tri-state GND NOTE Control blocks are compatible with 1.8/2.5/3.3 V I/O voltage levels. 9.3 Feature Description 9.3.1 Device Block-Level Description The LMK61PD0A2 comprises of an integrated oscillator that includes a 50 MHz crystal, a fractional PLL with integrated VCO. Completing the device is the combination of an integer output divider and a universal differential output buffer. The on-chip ROM contains seven pre-programmed output frequency plans that selects the appropriate settings for the integrated oscillator, PLL blocks and output divider. Table 1 lists the supported output frequency plans that can be selected by pin-strapping FS[1:0] as required. Table 2 lists the supported output types that can be selected by pin-strapping OS and OE as required. The device is powered by on-chip low dropout (LDO) linear voltage regulators and the regulated supply network is partitioned such that the sensitive analog supplies are running from separate LDOs than the digital supplies which use their own LDO. The LDOs provide isolation from any noise in the external power supply rail with a PSRR of better than -70 dBc at 50 kHz to 1 MHz ripple frequencies at 3.3 V device supply. 9.3.2 Device Configuration Control The LMK61PD0A2 selects an output frequency plan and output type using control pins FS[1:0]. Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: LMK61PD0A2 13 LMK61PD0A2 SNAS675A – OCTOBER 2015 – REVISED NOVEMBER 2015 www.ti.com 10 Application and Implementation NOTE Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality. 10.1 Application Information The LMK61PD0A2 is an ultra-low jitter pin selectable oscillator that can be used to provide reference clocks for high-speed serial links resulting in improved system performance. 10.2 Typical Application 10.2.1 Jitter Considerations in Serdes Systems Jitter-sensitive applications such as 10 Gbps or 100 Gbps Ethernet, deploy a serial link utilizing a Serializer in the transmit section (TX) and a De-serializer in the receive section (RX). These SERDES blocks are typically embedded in an ASIC or FPGA. Estimating the clock jitter impact on the link budget requires understanding of the TX PLL bandwidth and the RX CDR bandwidth. As can be seen in Figure 15, the pass band region between the TX low pass cutoff and RX high pass cutoff frequencies is the range over which the reference clock jitter adds without any attenuation to the jitter budget of the link. Outside of these frequencies, the SERDES link will attenuate the reference clock jitter with a 20 dB/dec or even steeper roll-off. Modern ASIC or FPGA designs have some flexibility on deciding the optimal RX CDR bandwidth and TX PLL bandwidth. These bandwidths are typically set based on what is achievable in the ASIC or FPGA process node, without increasing design complexity, and on any jitter tolerance or wander specification that needs to be met, as related to the RX CDR bandwidth. The overall allowable jitter in a serial link is dictated by IEEE or other relevant standards. For example, IEEE802.3ba states that the maximum transmit jitter (peak-peak) for 10 Gbps Ethernet should be no more than 0.28 * UI and this equates to a 27.1516 ps, p-p for the overall allowable transmit jitter. The jitter contributing elements are made up of the reference clock, generated potentially from a device like LMK61PD0A2, the transmit medium, transmit driver etc. Only a portion of the overall allowable transmit jitter is allocated to the reference clock, typically 20% or lower. Therefore, the allowable reference clock jitter, for a 20% clock jitter budget, is 5.43 ps, p-p. Jitter in a reference clock is made up of deterministic jitter (arising from spurious signals due to supply noise or mixing from other outputs or from the reference input) and random jitter (usually due to thermal noise and other uncorrelated noise sources). A typical clock tree in a serial link system consists of clock generators and fanout buffers. The allowable reference clock jitter of 5.43 ps, p-p is needed at the output of the fanout buffer. Modern fanout buffers have low additive random jitter (less than 100 fs, rms) with no substantial contribution to the deterministic jitter. Therefore, the clock generator and fanout buffer contribute to the random jitter while the primary contributor to the deterministic jitter is the clock generator. Rule of thumb, for modern clock generators, is to allocate 25% of allowable reference clock jitter to the deterministic jitter and 75% to the random jitter. This amounts to an allowable deterministic jitter of 1.36 ps, p-p and an allowable random jitter of 4.07 ps, p-p. For serial link systems that need to meet a bit error rate (BER) of 10-12, the allowable random jitter in root-meansquare is 0.29 ps, rms. This is calculated by dividing the p-p jitter by 14 for a BER of 10-12. Accounting for random jitter from the fanout buffer, the random jitter needed from the clock generator is 0.27 ps, rms. This is calculated by the root-mean-square subtraction from the desired jitter at the fanout buffer's output assuming 100 fs, rms of additive jitter from the fanout buffer. With careful frequency planning techniques, like spur optimization (covered in the Spur Mitigation Techniques section) and on-chip LDOs to suppress supply noise, the LMK61PD0A2 is able to generate clock outputs with deterministic jitter that is below 1 ps, p-p and random jitter that is below 0.2 ps, rms. This gives the serial link system with additional margin on the allowable transmit jitter resulting in a BER better than 10-12. 14 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: LMK61PD0A2 LMK61PD0A2 www.ti.com SNAS675A – OCTOBER 2015 – REVISED NOVEMBER 2015 Typical Application (continued) TX Parallel Data RX Serializer Parallel Data Sampler Serialized clock/data Recovered Clock TX PLL CDR Deserializer Ref Clk HRXCDR(f) F1 = TX_PLL_BWmax Jitter Transfer (on clock) HRXCDR(f) Jitter Tolerance (on data) HTXPLL(f) Jitter Transfer (on clock) F2 = RX_CDR_BWmin F2 = RX_CDR_BWmin H(f) Jitter Tolerance (on data) F2 SoC trend: Increase stop band Less % of jitter budget H(f) Jitter Transfer (on clock) F2 F1 SoC trend: Decrease stop band Improved LO design Figure 15. Dependence of Clock Jitter in Serial Links Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: LMK61PD0A2 15 LMK61PD0A2 SNAS675A – OCTOBER 2015 – REVISED NOVEMBER 2015 www.ti.com 11 Power Supply Recommendations For best electrical performance of LMK61PD0A2, it is preferred to utilize a combination of 10 uF, 1 uF and 0.1 uF on its power supply bypass network. It is also recommended to utilize component side mounting of the power supply bypass capacitors and it is best to use 0201 or 0402 body size capacitors to facilitate signal routing. Keep the connections between the bypass capacitors and the power supply on the device as short as possible. Ground the other side of the capacitor using a low impedance connection to the ground plane. Figure 16 shows the layout recommendation for power supply decoupling of LMK61PD0A2. 16 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: LMK61PD0A2 LMK61PD0A2 www.ti.com SNAS675A – OCTOBER 2015 – REVISED NOVEMBER 2015 12 Layout 12.1 Layout Guidelines The following sections provides recommendations for board layout, solder reflow profile and power supply bypassing when using LMK61PD0A2 to ensure good thermal / electrical performance and overall signal integrity of entire system. 12.1.1 Ensuring Thermal Reliability The LMK61PD0A2 is a high performance device. Therefore careful attention must be paid to device configuration and printed circuit board (PCB) layout with respect to power consumption. The ground pin needs to be connected to the ground plane of the PCB through three vias or more, as shown in Figure 16, to maximize thermal dissipation out of the package. Equation 1 describes the relationship between the PCB temperature around the LMK61PD0A2 and its junction temperature. TB = TJ – ΨJB * P where • • • • TB: PCB temperature around the LMK61PD0A2 TJ: Junction temperature of LMK61PD0A2 ΨJB: Junction-to-board thermal resistance parameter of LMK61PD0A2 (36.7°C/W without airflow) P: On-chip power dissipation of LMK61PD0A2 (1) In order to ensure that the maximum junction temperature of LMK61PD0A2 is below 125°C, it can be calculated that the maximum PCB temperature without airflow should be at 100°C or below when the device is optimized for best performance resulting in maximum on-chip power dissipation of 0.68 W. 12.1.2 Best Practices for Signal Integrity For best electrical performance and signal integrity of entire system with LMK61PD0A2, it is recommended to route vias into decoupling capacitors and then into the LMK61PD0A2. It is also recommended to increase the via count and width of the traces wherever possible. These steps ensure lowest impedance and shortest path for high frequency current flow. Figure 16 shows the layout recommendation for LMK61PD0A2. Figure 16. LMK61PD0A2 Layout Recommendation for Power Supply and Ground Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: LMK61PD0A2 17 LMK61PD0A2 SNAS675A – OCTOBER 2015 – REVISED NOVEMBER 2015 www.ti.com Layout Guidelines (continued) 12.1.3 Recommended Solder Reflow Profile It is recommended to follow the solder paste supplier's recommendations to optimize flux activity and to achieve proper melting temperatures of the alloy within the guidelines of J-STD-20. It is preferrable for the LMK61PD0A2 to be processed with the lowest peak temperature possible while also remaining below the components peak temperature rating as listed on the MSL label. The exact temperature profile would depend on several factors including maximum peak temperature for the component as rated on the MSL label, Board thickness, PCB material type, PCB geometries, component locations, sizes, densities within PCB, as well solder manufactures recommended profile, and capability of the reflow equipment to as confirmed by the SMT assembly operation. 18 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: LMK61PD0A2 LMK61PD0A2 www.ti.com SNAS675A – OCTOBER 2015 – REVISED NOVEMBER 2015 13 Device and Documentation Support 13.1 Community Resources The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve problems with fellow engineers. Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and contact information for technical support. 13.2 Trademarks E2E is a trademark of Texas Instruments. 13.3 Electrostatic Discharge Caution These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. 13.4 Glossary SLYZ022 — TI Glossary. This glossary lists and explains terms, acronyms, and definitions. 14 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: LMK61PD0A2 19 PACKAGE OPTION ADDENDUM www.ti.com 10-Dec-2020 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) (4/5) (6) LMK61PD0A2-SIAR ACTIVE QFM SIA 8 2500 RoHS & Green NIAU Level-3-260C-168 HR -40 to 85 LMK61 PD0A2 LMK61PD0A2-SIAT ACTIVE QFM SIA 8 250 RoHS & Green NIAU Level-3-260C-168 HR -40 to 85 LMK61 PD0A2 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of