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LMK61E0M
SNAS692A – JANUARY 2017 – REVISED MAY 2017
LMK61E0M Ultra-Low Jitter Programmable Oscillator With Internal EEPROM
1 Features
3 Description
•
The LMK61E0 family of ultra-low jitter PLLatinumTM
programmable oscillators use fractional-N frequency
synthesizers with integrated VCOs to generate
commonly used reference clocks. The LMK61E0M
supports 3.3-V LVCMOS outputs. The device
features self start-up from on-chip EEPROM to
generate a factory programmed default output
frequency, or the device registers and EEPROM
settings are fully programmable in-system through I2C
serial interface. The device provides fine and coarse
frequency margining control through I2C serial
interface, making it a digitally-controlled oscillator
(DCXO).
1
•
•
•
•
•
Ultra-Low Noise, High Performance
– Jitter: 500-fs RMS Typical fOUT > 50 MHz on
LMK61E0M
LMK61E0M Supports 3.3-V LVCMOS Output up
to 200 MHz
Total Frequency Tolerance of ±25 ppm
System Level Features
– Glitch-Less Frequency Margining: Up to ±1000
ppm From Nominal
– Internal EEPROM: User Configurable Start-Up
Settings
Other Features
– Device Control: Fast Mode I2C up to 1000 kHz
– 3.3-V Operating Voltage
– Industrial Temperature Range (–40ºC to
+85ºC)
– 7-mm × 5-mm 8-Pin Package
Default Frequency: 70.656 MHz
The PLL feedback divider can be updated to adjust
the output frequency without spikes or glitches in
steps of > To VCO
>>
C1
C3
Loop Filter Control
R36
R37
R38
R39
Copyright © 2016, Texas Instruments Incorporated
Figure 5. Loop Filter Structure of PLL
8.3.12 VCO Calibration
The PLL in LMK61E0 is made of LC VCO that is designed using high-Q monolithic inductors to oscillate between
4.6 GHz and 5.6 GHz and has low phase noise characteristics. The VCO must be calibrated to ensure that the
clock outputs deliver optimal phase noise performance. Fundamentally, a VCO calibration establishes an optimal
operating point within the tuning range of the VCO. Setting R72[1] to 1 causes a VCO recalibration and is
necessary after device reconfiguration. VCO calibration automatically occurs on device power up.
8.3.13 High-Speed Output Divider
LMK61E0M has two integer dividers in series in the output signal path. The VCO post-divider divides the VCO
frequency by 4 or 5 and is programmed in R22[5]. The following high-speed output divider supports divide values
of 6 to 256 and is programmed in R22 and R23. The output divider also supports coarse frequency margining
that can initiate as low as a 5% change in the output frequency. To change the output divider, R23 needs to be
programmed first and then R22. This is necessary for the CMOS divider to load the correct divide value.
8.3.14 High-Speed Clock Output
The clock outputs on LMK61E0M support 3.3-V LVCMOS levels. Both pins can be individually set to be the
same polarity or opposite polarity of the other, or can be set to high impedance or tri-state. By default, OUT0 is
enabled and OUT1 is tristate. OUT0 is controlled by R20[2] and OUT1 is controlled by R24[4]. The slew rate of
the LVCMOS output can be set to fast or slow by programming R22[7:6] = 0x0 or 0x2.
12
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Feature Description (continued)
8.3.15 Device Status
The PLL loss of lock and PLL calibration status can be monitored by reading R66[1:0]. These bits represent a
logic-high interrupt output and are self-cleared once the readback is complete.
8.3.15.1 Loss of Lock
The PLL loss of lock detection circuit is a digital circuit that detects any frequency error, even a single cycle slip.
Loss of lock may occur when an incorrect PLL configuration is programmed or the VCO has not been
recalibrated.
8.4 Device Functional Modes
8.4.1 Interface and Control
The host (DSP, Microcontroller, FPGA, etc) configures and monitors the LMK61E0 through the I2C port. The host
reads and writes to a collection of control and status bits called the register map. The device blocks can be
controlled and monitored through a specific grouping of bits located within the register file. The host controls and
monitors certain device Wide critical parameters directly through register control and status bits. In the absence
of the host, the LMK61E0 can be configured to operate from its on-chip EEPROM. The EEPROM array is
automatically copied to the device registers upon power up. The user has the flexibility to rewrite the contents of
EEPROM from the SRAM up to 100 times.
Within the device registers, there are certain bits that have read or write access. Other bits are read-only (an
attempt to write to a read-only bit will not change the state of the bit). Certain device registers and bits are
reserved meaning that they must not be changed from their default reset state. Figure 6 shows interface and
control blocks within LMK61E0 and the arrows refer to read access from and write access to the different
embedded memories (EEPROM, SRAM).
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Device Functional Modes (continued)
Device Registers
Reg72
7
6
5
4
3
2
1
0
6
5
4
3
2
1
0
6
5
4
3
2
1
0
6
5
4
3
2
1
0
6
5
4
3
2
1
0
6
5
4
3
2
1
0
6
5
4
3
2
1
0
6
5
4
3
2
1
0
Reg66
7
Reg56
Control/
Status Pins
I2C
Port
7
Device
Control
And
Status
OE
ADD
SCL
SDA
Reg53
7
Device
Hardware
Reg3
7
Reg2
7
Reg1
7
Reg 0
7
Reg35
7
Reg35
6
5
4
3
2
1
0
7
Reg34
7
6
5
4
3
2
1
0
6
5
4
3
2
1
0
6
5
4
3
2
1
0
6
5
4
3
2
1
0
6
5
4
3
2
1
0
7
Reg33
7
7
7
7
7
1
0
6
5
4
3
2
1
0
6
5
4
3
2
1
0
6
5
4
3
2
1
0
6
5
4
3
2
1
0
6
5
4
3
2
1
0
6
5
4
3
2
1
0
6
5
4
3
2
1
0
Reg1
6
5
4
3
2
1
0
6
5
4
3
2
1
0
7
Reg 0
7
2
Reg2
Reg1
7
3
Reg3
Reg2
7
4
Reg32
Reg3
7
5
Reg33
Reg32
7
6
Reg34
Reg 0
7
EEPROM
SRAM
Figure 6. LMK61E0 Interface and Control Block
8.4.2 DCXO Mode and Frequency Margining
8.4.2.1 DCXO Mode
In applications that require the LMK61E0 as part of a PLL that is implemented in another device like an FPGA, it
can be used as a digitally controlled oscillator (DCXO) where the frequency control word can be passed along
through I2C to the LMK61E0 on a regular basis which in turn updates the numerator of its fractional feedback
divider by the required amount. In such a scenario, the entire portion of numerator for the fractional feedback
divider must be written on every attempt MSB first and LSB last to ensure that the output frequency does not
jump during the update, as described in Feedback Divider (N). In every update cycle, a total of 46 bits needs to
be updated leading to a maximum update rate of 8.7 kHz with a maximum I2C rate of 1 Mbps. The minimum step
size of 0.55 ppb (parts per billion) is achieved for the maximum VCO frequency of 5.6 GHz and when reference
input doubler is disabled and reference divider is set to 4. The minimum step size of 4.96 ppb (parts per billion) is
achieved for the maximum VCO frequency of 4.8 GHz and when reference input doubler is enabled and
reference divider is bypassed.
14
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Device Functional Modes (continued)
8.4.2.2 Fine Frequency Margining
IEEE802.3 dictates that Ethernet frames stay compliant to the standard specifications when clocked with a
reference clock that is within ±100 ppm of its nominal frequency. In the worst case, an RX node with its local
reference clock at –100 ppm from its nominal frequency should be able to work seamlessly with a TX node that
has its own local reference clock at +100 ppm from its nominal frequency. Without any clock compensation on
the RX node, the read pointer will severely lag behind the write pointer and cause FIFO overflow errors. On the
contrary, when the RX node’s local clock operates at +100 ppm from its nominal frequency and the TX node’s
local clock operates at –100 ppm from its nominal frequency, FIFO underflow errors occur without any clock
compensation.
To prevent such overflow and underflow errors from occurring, modern ASICs and FPGAs include a clock
compensation scheme that introduces elastic buffers. Such a system, shown in Figure 7, is validated thoroughly
during the validation phase by interfacing slower nodes with faster ones and ensuring compliance to IEEE802.3.
The LMK61E0 provides the ability to fine tune the frequency of its outputs based on changing its load
capacitance for the integrated oscillator. This fine tuning can be done through I2C as described in Integrated
Oscillator. The change in load capacitance is implemented in a manner such that the output of LMK61E0
undergoes a smooth monotonic change in frequency.
8.4.2.3 Coarse Frequency Margining
Certain systems require the processors to be tested at clock frequencies that are slower or faster by 5% or 10%.
The LMK61E0 offers the ability to change its output divider for the desired change from its nominal output
frequency as explained in High-Speed Output Divider.
TX
RX
Serializer
Post Processing
w/ clock
compensation
Sampler
Serialized clock/data
Parallel
Data
Recovered
Clock
Parallel
Data
+/- 100 ppm
TX PLL
CDR
Ref Clk
+/- 100 ppm
Ref Clk
Deserializer
Elastic Buffer
(clock compensation)
FIFO
circular
Latency
Write
Pointer
Read
Pointer
Figure 7. System Implementation With Clock Compensation for Standards Compliance
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8.5 Programming
8.5.1 I2C Serial Interface
The I2C port on the LMK61E0 works as a slave device and supports both the 100-kHz standard mode and 1MHz fast mode operations. Fast mode imposes a glitch tolerance requirement on the control signals. Therefore,
the input receivers ignore pulses of less than 50-ns duration. The I2C timing is given in I2C-Compatible Interface
Characteristics (SDA, SCL) (1) (2). The timing diagram is given in Figure 8.
STOP
START
ACK
tW(SCLL)
tW(SCLH)
STOP
tf(SM)
tr(SM)
~
~
VIH(SM)
SCL
VIL(SM)
~
~
th(START)
tr(SM)
tSU(SDATA)
th(SDATA)
tSU(START)
tSU(STOP)
tf(SM)
tBUS
~
~
~
~
VIH(SM)
SDA
VIL(SM)
~
~
Figure 8. I2C Timing Diagram
In an I2C bus system, the LMK61E0 acts as a slave device and is connected to the serial bus (data bus SDA and
lock bus SCL). These are accessed via a 7-bit slave address transmitted as part of an I2C packet. Only the
device with a matching slave address responds to subsequent I2C commands. In soft pin mode, the LMK61E0
allows up to three unique slave devices to occupy the I2C bus based on the pin strapping of ADD (tied to VDD,
GND or left open). The device slave address is 10110xx (the two LSBs are determined by the ADD pin).
During the data transfer through the I2C interface, one clock pulse is generated for each data bit transferred. The
data on the SDA line must be stable during the high period of the clock. The high or low state of the data line can
change only when the clock signal on the SCL line is low. The start data transfer condition is characterized by a
high-to-low transition on the SDA line while SCL is high. The stop data transfer condition is characterized by a
low-to-high transition on the SDA line while SCL is high. The start and stop conditions are always initiated by the
master. Every byte on the SDA line must be eight bits long. Each byte must be followed by an acknowledge bit
and bytes are sent MSB first. The I2C register structure of the LMK61E0 is shown in Figure 9.
I2C PROTOCOL
7
1
8
8
W/R
REGISTER ADDRESS
DATA BYTE
A6 A5 A4 A3 A2 A1 A0
I2C ADDRESS
Figure 9. I2C Register Structure
The acknowledge bit (A) or non-acknowledge bit (A’) is the 9th bit attached to any 8-bit data byte and is always
generated by the receiver to inform the transmitter that the byte has been received (when A = 0) or not (when A’
= 0). A = 0 is done by pulling the SDA line low during the 9th clock pulse and A’ = 0 is done by leaving the SDA
line high during the 9th clock pulse.
(1)
(2)
16
Total capacitive load for each bus line ≤ 400 pF.
Ensured by design.
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Programming (continued)
The I2C master initiates the data transfer by asserting a start condition which initiates a response from all slave
devices connected to the serial bus. Based on the 8-bit address byte sent by the master over the SDA line
(consisting of the 7-bit slave address (MSB first) and an R/W’ bit), the device whose address corresponds to the
transmitted address responds by sending an acknowledge bit. All other devices on the bus remain idle while the
selected device waits for data transfer with the master.
After the data transfer has occurred, stop conditions are established. In write mode, the master asserts a stop
condition to end data transfer during the 10th clock pulse following the acknowledge bit for the last data byte
from the slave. In read mode, the master receives the last data byte from the slave but does not pull SDA low
during the 9th clock pulse. This is known as a non-acknowledge bit. By receiving the non-acknowledge bit, the
slave knows the data transfer is finished and enters the idle mode. The master then takes the data line low
during the low period before the 10th clock pulse, and high during the 10th clock pulse to assert a stop condition.
A generic transaction is shown in Figure 10.
1
S
7
Slave Address
1
R/W
MSB
1
A
8
Data Byte
LSB
S
Start Condition
Sr
Repeated Start Condition
MSB
1
A
1
P
LSB
R/W 1 = Read (Rd) from slave; 0 = Write (Wr) to slave
A
Acknowledge (ACK = 0 and NACK = 1)
P
Stop Condition
Master to Slave Transmission
Slave to Master Transmission
Figure 10. Generic Programming Sequence
The LMK61E0 I2C interface supports Block Register Write/Read, Read/Write SRAM, and Read/Write EEPROM
operations. For Block Register Write/Read operations, the I2C master can individually access addressed
registers that are made of an 8-bit data byte. The offset of the indexed register is encoded in the register
address, as described in Table 1 below.
Table 1. Slave Address Byte
DEVICE
A6
A5
A4
A3
A2
ADD pin
R/W
LMK61E0
1
0
1
1
0
0x0, 0x1 or 0x3
1/0
8.5.2 Block Register Write
The I2C Block Register Write transaction is illustrated in Figure 11 and consists of the following sequence.
1. Master issues a Start Condition.
2. Master writes the 7-bit Slave Address following by a Write bit.
3. Master writes the 8-bit Register address as the CommandCode of the programming sequence.
4. Master writes one or more data bytes each of which should be acknowledged by the slave. The slave
increments the internal register address after each byte.
5. Master issues a Stop Condition to terminate the transaction.
1
S
7
Slave Address
8
Data Byte 0
1
Wr
1
A
...
1
A
8
CommandCode
1
A
8
Data Byte N-1
1
A
1
P
Figure 11. Block Register Write Programming Sequence
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8.5.3 Block Register Read
The I2C Block Register Read transaction is illustrated in Figure 12 and consists of the following sequence.
1. Master issues a Start Condition.
2. Master writes the 7-bit Slave Address followed by a Write bit.
3. Master writes the 8-bit Register address as the CommandCode of the programming sequence.
4. Master issues a Repeated Start Condition.
5. Master writes the 7-bit Slave Address following by a Read bit.
6. Slave returns one or more data bytes as long as the Master continues to acknowledge them. The slave
increments the internal register address after each byte.
7. Master issues a Stop Condition to terminate the transaction.
1
S
7
Slave Address
8
Data Byte 0
1
Wr
1
A
1
A
8
CommandCode
1
A
...
1
Sr
7
Slave Address
8
Data Byte N-1
1
Rd
1
A
1
A
1
P
Figure 12. Block Register Read Programming Sequence
8.5.4 Write SRAM
The on-chip SRAM is a volatile, shadow memory array used to temporarily store register data, and is intended
only for programming the non-volatile EEPROM. The SRAM has the identical data format as the EEPROM map.
The register configuration data can be transferred to the SRAM array through special memory access registers in
the register map. To successfully program the SRAM, the complete base array and at least one page should be
written. The following details the programming sequence to transfer the device registers into the SRAM.
1. Program the device registers to match a desired setting.
2. Write a 1 to R49[6]. This ensures that the device registers are copied to the SRAM.
The SRAM can also be written with particular values according to the following programming sequence.
1. Write the SRAM address in R51.
2. Write the desired data byte in R53 in the same I2C transaction and this data byte will be written to the
address specified in the step above. Any additional access that is part of the same transaction will cause the
SRAM address to be incremented and a write will take place to the next SRAM address. Access to SRAM
will terminate at the end of current I2C transaction.
NOTE
It is possible to increment SRAM address incorrectly when 2 successive accesses are
made to R51.
8.5.5 Write EEPROM
The on-chip EEPROM is a non-volatile memory array used to permanently store register data for a custom
device start-up configuration setting to initialize registers upon power up or POR. The EEPROM is comprised of
bits shown in the EEPROM Map. The transfer must first happen to the SRAM and then to the EEPROM. During
“EEPROM write”, R49[2] is a 1 and the EEPROM contents cannot be accessed. The following details the
programming sequence to transfer the entire contents of SRAM to EEPROM.
1. Make sure the "Write SRAM" procedure (Write SRAM) was done to commit the register settings to the SRAM
with start-up configurations intended for programming to the EEPROM.
2. Write 0xBE to R56. This provides basic protection from inadvertent programming of EEPROM.
3. Write a 1 to R49[0]. This programs the entire SRAM contents to EEPROM. Once completed, the contents in
R48 will increment by 1. R48 contains the total number of EEPROM programming cycles that are
successfully completed.
4. Write 0x00 to R56 to protect against inadvertent programming of EEPROM.
18
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8.5.6 Read SRAM
The contents of the SRAM can be read out, one word at a time, starting with that of the requested address.
Following details the programming sequence for an SRAM read by address.
1. Write the SRAM address in R51.
2. The SRAM data located at the address specified in the step above can be obtained by reading R53 in the
same I2C transaction. Any additional access that is part of the same transaction will cause the SRAM
address to be incremented and a read will take place of the next SRAM address. Access to SRAM will
terminate at the end of current I2C transaction.
NOTE
It is possible to increment SRAM address incorrectly when 2 successive accesses are
made to R51.
8.5.7 Read EEPROM
The contents of the EEPROM can be read out, one word at a time, starting with that of the requested address.
Following details the programming sequence for an EEPROM read by address.
1. Write the EEPROM address in R51.
2. The EEPROM data located at the address specified in the step above can be obtained by reading R52 in the
same I2C transaction. Any additional access that is part of the same transaction will cause the EEPROM
address to be incremented and a read will take place of the next EEPROM address. Access to EEPROM will
terminate at the end of current I2C transaction.
NOTE
It is possible to increment EEPROM address incorrectly when 2 successive accesses are
made to R51.
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8.6 Register Maps
Any bit that is labeled as RESERVED should be written with a 0.
Table 2. EEPROM Map
BYTE
NO.
BIT7
BIT6
BIT5
BIT4
BIT3
BIT2
BIT1
BIT0
0
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
1
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
2
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
3
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
4
NVMSCRC[7]
NVMSCRC[6]
NVMSCRC[5]
NVMSCRC[4]
NVMSCRC[3]
NVMSCRC[2]
NVMSCRC[1]
NVMSCRC[0]
5
NVMCNT[7]
NVMCNT[6]
NVMCNT[5]
NVMCNT[4]
NVMCNT[3]
NVMCNT[2]
NVMCNT[1]
NVMCNT[0]
6
1
RESERVED
RESERVED
RESERVED
RESERVED
1
RESERVED
RESERVED
7
RESERVED
RESERVED
1
RESERVED
RESERVED
RESERVED
RESERVED
1
8
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
9
SLAVEADR[7]
SLAVEADR[6]
SLAVEADR[5]
SLAVEADR[4]
SLAVEADR[3]
RESERVED
RESERVED
RESERVED
10
EEREV[7]
EEREV[6]
EEREV[5]
EEREV[4]
EEREV[3]
EEREV[2]
EEREV[1]
EEREV[0]
11
RESERVED
PLL_PDN
RESERVED
RESERVED
RESERVED
RESERVED
AUTOSTRT
RESERVED
14
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
1
RESERVED
1
15
RESERVED
XO_CAPCTRL[1]
XO_CAPCTRL[0]
XO_CAPCTRL[9]
XO_CAPCTRL[8]
XO_CAPCTRL[7]
XO_CAPCTRL[6]
XO_CAPCTRL[5]
16
XO_CAPCTRL[4]
XO_CAPCTRL[3]
XO_CAPCTRL[2]
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
19
RESERVED
RESERVED
OUT0_HIZ
CMOS_MUTE
RESERVED
OUT1_INV
OUT0_INV
RESERVED
20
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
21
RESERVED
RESERVED
RESERVED
OUT1_HIZ
RESERVED
RESERVED
RESERVED
PLL_RDIV
22
PLL_NDIV[11]
PLL_NDIV[10]
PLL_NDIV[9]
PLL_NDIV[8]
PLL_NDIV[7]
PLL_NDIV[6]
PLL_NDIV[5]
PLL_NDIV[4]
23
PLL_NDIV[3]
PLL_NDIV[2]
PLL_NDIV[1]
PLL_NDIV[0]
PLL_NUM[21]
PLL_NUM[20]
PLL_NUM[19]
PLL_NUM[18]
24
PLL_NUM[17]
PLL_NUM[16]
PLL_NUM[15]
PLL_NUM[14]
PLL_NUM[13]
PLL_NUM[12]
PLL_NUM[11]
PLL_NUM[10]
25
PLL_NUM[9]
PLL_NUM[8]
PLL_NUM[7]
PLL_NUM[6]
PLL_NUM[5]
PLL_NUM[4]
PLL_NUM[3]
PLL_NUM[2]
26
PLL_NUM[1]
PLL_NUM[0]
PLL_DEN[21]
PLL_DEN[20]
PLL_DEN[19]
PLL_DEN[18]
PLL_DEN[17]
PLL_DEN[16]
27
PLL_DEN[15]
PLL_DEN[14]
PLL_DEN[13]
PLL_DEN[12]
PLL_DEN[11]
PLL_DEN[10]
PLL_DEN[9]
PLL_DEN[8]
28
PLL_DEN[7]
PLL_DEN[6]
PLL_DEN[5]
PLL_DEN[4]
PLL_DEN[3]
PLL_DEN[2]
PLL_DEN[1]
PLL_DEN[0]
29
PLL_
DTHRMODE[1]
PLL_DTHRMODE[0]
PLL_ORDER[1]
PLL_ORDER[0]
RESERVED
RESERVED
PLL_D
PLL_CP[3]
30
PLL_CP[2]
PLL_CP[1]
PLL_CP[0]
PLL_CP_PHASE_
SHIFT[2]
PLL_CP_PHASE_
SHIFT[1]
PLL_CP_PHASE_
SHIFT[0]
PLL_ENABLE_
C3[2]
PLL_ENABLE_
C3[1]
31
PLL_ENABLE_
C3[0]
PLL_LF_R2[7]
PLL_LF_R2[6]
PLL_LF_R2[5]
PLL_LF_R2[4]
PLL_LF_R2[3]
PLL_LF_R2[2]
PLL_LF_R2[1]
20
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Register Maps (continued)
Table 2. EEPROM Map (continued)
BYTE
NO.
BIT7
BIT6
BIT5
BIT4
BIT3
BIT2
BIT1
BIT0
32
PLL_LF_R2[0]
PLL_LF_C1[2]
PLL_LF_C1[1]
PLL_LF_C1[0]
PLL_LF_R3[6]
PLL_LF_R3[5]
PLL_LF_R3[4]
PLL_LF_R3[3]
33
PLL_LF_R3[2]
PLL_LF_R3[1]
PLL_LF_R3[0]
PLL_LF_C3[2]
PLL_LF_C3[1]
PLL_LF_C3[0]
CMOS_SLEWRATE[ CMOS_SLEWRATE[
1]
0]
34
PRE_DIV
OUT_DIV[8]
OUT_DIV[7]
OUT_DIV[6]
OUT_DIV[5]
OUT_DIV[4]
OUT_DIV[3]
OUT_DIV[2]
35
OUT_DIV[1]
OUT_DIV[0]
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
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The default/reset values for each register is specified for LMK61E0.
Table 3. Register Map
NAME
ADD
R
RES
ET
BIT7
BIT6
VNDRID_BY
1
0
0x10
VNDRID[15:8]
VNDRID_BY
0
1
0x0B VNDRID[7:0]
PRODID
2
0x33
PRODID[7:0]
REVID
3
0x00
REVID[7:0]
SLAVEADR
8
0xB0 SLAVEADR[7:1]
EEREV
9
0x00
EEREV[7:0]
DEV_CTL
10
0x01
RESERVED
XO_CAPCTR 16
L_
BY1
0x00
RESERVED
XO_CAPCTR 17
L_
BY0
0x00
XO_CAPCTRL[9:2]
CMOSCTL
20
0x00
RESERVED
DIFFCTL
BIT5
BIT4
BIT2
BIT1
BIT0
RESERVED
PLL_PDN
RESERVED
ENCAL
AUTOSTRT
XO_CAPCTRL[1:0]
OUT0_
HIZ
21
0x01
RESERVED
OUT1_INV
OUT0_INV
OUTDIV_BY1 22
0x00
CMOS_SLEWRATE[1:0]
PRE_DIV
RESERVED
OUTDIV_BY0 23
0x20
OUT_DIV[7:0]
RDIVCMOSC 24
TL
0x00
RESERVED
PLL_NDIV_B
Y1
25
0x00
RESERVED
PLL_NDIV_B
Y0
26
0x64
PLL_NDIV[7:0]
PLL_FRACN
UM_
BY2
27
0x00
RESERVED
PLL_FRACN
UM_
BY1
28
0x00
PLL_NUM[15:8]
PLL_FRACN
UM_
BY0
29
0x00
PLL_NUM[7:0]
PLL_FRACD
EN_
BY2
30
0x00
RESERVED
PLL_FRACD
EN_
BY1
31
0x00
PLL_DEN[15:8]
PLL_FRACD
EN_
BY0
32
0x00
PLL_DEN[7:0]
PLL_MASHC
TRL
33
0x0C RESERVED
PLL_CTRL0
34
0x24
RESERVED
PLL_CTRL1
35
0x03
RESERVED
PLL_LF_R2
36
0x28
PLL_LF_R2[7:0]
PLL_LF_C1
37
0x00
RESERVED
PLL_LF_R3
38
0x00
RESERVED
PLL_LF_C3
39
0x00
RESERVED
22
BIT3
OUT1_HIZ
CMOS_M
UTE
RESERVED
RESERVED
OUT_DIV[8]
RESERVED
PLL_RDIV
PLL_NDIV[11:8]
PLL_NUM[21:16]
PLL_DEN[21:16]
PLL_DTHRMODE[1:0] PLL_ORDER[1:0]
PLL_D
RESERVED PLL_CP[3:0]
PLL_CP_PHASE_SHIFT[2:0]
RESERVED PLL_ENABLE_C3[2:0]
PLL_LF_C1[2:0]
PLL_LF_R3[6:0]
PLL_LF_C3[2:0]
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Table 3. Register Map (continued)
NAME
ADD
R
RES
ET
BIT7
BIT6
BIT5
BIT4
BIT3
BIT2
PLL_CALCT
RL
42
0x00
RESERVED
NVMSCRC
47
0x00
NVMSCRC[7:0]
NVMCNT
48
0x00
NVMCNT[7:0]
NVMCTL
49
0x10
RESERVED
NVMLCRC
50
0x00
NVMLCRC[7:0]
MEMADR
51
0x00
RESERVED
NVMDAT
52
0x00
NVMDAT[7:0]
RAMDAT
53
0x00
RAMDAT[7:0]
NVMUNLK
56
0x00
NVMUNLK[7:0]
INT_LIVE
66
0x00
RESERVED
LOL
CAL
SWRST
72
0x00
RESERVED
SWR2PLL
RESERVED
PLL_CLSDWAIT[1:0]
REGCOMMI NVMCRCE
T
RR
NVMAUTO
CRC
BIT1
BIT0
PLL_VCOWAIT[1:0]
NVMCOMM NVMBU NVMERAS NVMPROG
IT
SY
E
MEMADR[6:0]
8.6.1 Register Descriptions
8.6.1.1 VNDRID_BY1 Register; R0
VNDRID_BY1 and VNDRID_BY0 registers are used to store the unique 16-bit Vendor Identification number
assigned to I2C vendors.
BIT NO.
FIELD
TYPE
RESET
EEPROM
DESCRIPTION
[7:0]
VNDRID[15:8]
R
0x10
N
Vendor Identification Number Byte 1.
8.6.1.2 VNDRID_BY0 Register; R1
VNDRID_BY1 and VNDRID_BY0 registers are used to store the unique 16-bit Vendor Identification number
assigned to I2C vendors.
BIT NO.
FIELD
TYPE
RESET
EEPROM
DESCRIPTION
[7:0]
VNDRID[7:0]
R
0x0B
N
Vendor Identification Number Byte 0.
8.6.1.3 PRODID Register; R2
The Product Identification Number is a unique 8-bit identification number used to identify the LMK61E0.
BIT NO.
FIELD
TYPE
RESET
EEPROM
DESCRIPTION
[7:0]
PRODID[7:0]
R
0x33
N
Product Identification Number.
8.6.1.4 REVID Register; R3
The REVID register is used to identify the LMK61E0 mask revision.
BIT NO.
FIELD
TYPE
RESET
EEPROM
DESCRIPTION
[7:0]
REVID[7:0]
R
0x00
N
Device Revision Number. The Device Revision Number
is used to identify the LMK61E0 mask-set revision used
to fabricate this device.
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8.6.1.5 SLAVEADR Register; R8
The SLAVEADR register reflects the 7-bit I2C Slave Address value initialized from from on-chip EEPROM.
BIT NO.
FIELD
TYPE
RESET
EEPROM
DESCRIPTION
[7:1]
SLAVEADR[7:1]
R
0x58
Y
I2C Slave Address. This field holds the 7-bit Slave
Address used to identify this device during I2C
transactions. The two least significant bits of the address
can be configured using ADD pin as shown.
[0]
24
RESERVED
-
-
N
SLAVEADR[2:1]
ADD pin
0 (0x0)
0
1 (0x1)
Float
3 (0x3)
1
Reserved.
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8.6.1.6 EEREV Register; R9
The EEREV register provides an EEPROM image revision record. EEPROM Image Revision is automatically
retrieved from EEPROM and stored in the EEREV register after a reset or after a EEPROM commit operation.
BIT NO.
FIELD
TYPE
RESET
EEPROM
DESCRIPTION
[7:0]
EEREV[7:0]
R
0x00
Y
EEPROM Image Revision ID
8.6.1.7 DEV_CTL Register; R10
The DEV_CTL register holds the control functions described in the following table.
BIT NO.
FIELD
TYPE
RESET
EEPROM
DESCRIPTION
[7]
RESERVED
-
0
Y
Reserved.
[6]
PLL_PDN
RW
0
Y
PLL Powerdown. The PLL_PDN bit determines whether
PLL is automatically enabled and calibrated after a
hardware reset. If the PLL_PDN bit is set to 1 during
normal operation then PLL is disabled and the calibration
circuit is reset. When PLL_PDN is then cleared to 0 PLL
is re-enabled and the calibration sequence is
automatically restarted.
PLL_PDN
Value
0
PLL Enabled
1
PLL Disabled
[5]
CMOS_SEL
RW
1
Y
Set to 1 for LMK61E0M.
[4:2]
RESERVED[5:2]
RW
0
Y
Reserved.
[1]
ENCAL
RWSC
0
N
Enable Frequency Calibration. Triggers PLL/VCO
calibration on both PLLs in parallel on 0 –> 1 transition
of ENCAL. This bit is self-clearing and set to a 0 after
PLL/VCO calibration is complete. In powerup or software
rest mode, AUTOSTRT takes precedence.
[0]
AUTOSTRT
RW
1
Y
Autostart. If AUTOSTRT is set to 1 the device will
automatically attempt to achieve lock and enable outputs
after a device reset. A device reset can be triggered by
the power-on-reset, RESETn pin or by writing to the
RESETN_SW bit. If AUTOSTRT is 0 then the device will
halt after the configuration phase, a subsequent write to
set the AUTOSTRT bit to 1 will trigger the PLL Lock
sequence.
8.6.1.8 XO_CAPCTRL_BY1 Register; R16
XO Margining Offset Value bits[9:8]
BIT NO.
FIELD
TYPE
RESET
EEPROM
DESCRIPTION
[7:2]
RESERVED[5:0]
-
-
N
Reserved.
[1:0]
XO_CAPCTRL [1:0]
RW
0x0
Y
XO Offset Value bits [1:0]
8.6.1.9 XO_CAPCTRL_BY0 Register; R17
XO Margining Offset Value bits[7:0]
BIT NO.
FIELD
TYPE
RESET
EEPROM
DESCRIPTION
[7:0]
XO_CAPCTRL [9:2]
RW
0x80
Y
XO Offset Value bits[9:2]
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8.6.1.10 CMOSCTL Register; R20
The CMOSCTL register provides control over Output for LMK61E0M.
BIT NO.
FIELD
TYPE
RESET
EEPROM
DESCRIPTION
[7:3]
RESERVED
-
-
N
Reserved.
[2]
OUT0_HIZ
RW
0
Y
Controls OUT0 in LMK61E0M. When set to 1, the output
is tri-stated with high impedance. When set to 0, the
output is in normal operation.
[1]
CMOS_MUTE
RW
0
Y
Output channel mute in LMK61E0M.
[0]
RESERVED
-
-
N
Reserved.
8.6.1.11 DIFFCTL Register; R21
LVCMOS channel inversion is controlled by the OUT0_INV and OUT1_INV registers.
BIT NO.
FIELD
TYPE
RESET
EEPROM
DESCRIPTION
[7:6]
RESERVED
-
-
N
Reserved.
[5]
OUT1_INV
RW
0
Y
Inversion for CMOS output channel 1.
[4]
OUT0_INV
RW
0
Y
Inversion for CMOS output channel 0.
[3:0]
RESERVED
-
-
N
Reserved.
8.6.1.12 OUTDIV_BY1 Register; R22
The 9-bit output integer divider value is set by the OUTDIV_BY1 and OUTDIV_BY0 registers.
BIT NO.
FIELD
TYPE
RESET
EEPROM DESCRIPTION
[7:6]
CMOS_SLEWRATE[1:0]
RW
0x0
Y
Sets LVCMOS output slew rate in LMK61E0M. 0x0 sets
to fast mode and 0x2 sets to slow mode.
[5]
PRE_DIV
RW
0
Y
Sets LVCMOS output pre-divider in LMK61E0M. 0 sets to
divide-by-4 and 1 sets to divide-by-5.
[4:1]
RESERVED
RW
0x0
Y
Reserved.
[0]
OUT_DIV[8]
RW
0
Y
Channel's Output Divider Byte 1 (Bit 8). The Channel
Divider, OUT_DIV, is a 9-bit divider. The valid register
values range from 5-255, which correspond with divide
ratios of 6-256. To change the output divider, R23 needs
to be programmed first and then R22. This is necessary
for the CMOS divider to load the correct divide value.
OUT_DIV
DIVIDE RATIO
0-4
RESERVED
5 (0x006)
6
6 (0x007)
7
254 (0x0FF)
255
255 (0x100)
256
8.6.1.13 OUTDIV_BY0 Register; R23
The 9-bit output integer divider value is set by the OUTDIV_BY1 and OUTDIV_BY0 registers.
BIT NO.
FIELD
TYPE
RESET
EEPROM
DESCRIPTION
[7:0]
OUT_DIV[7:0]
RW
0x20
Y
Channel's Output Divider Byte 0 (Bits 7-0). To change the
output divider, R23 needs to be programmed first and
then R22. This is necessary for the CMOS divider to load
the correct divide value.
26
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8.6.1.14 RDIVCMOSCTL Register; R24
Sets R divider and CMOS OUT1 control for LMK61E0M.
BIT NO.
FIELD
TYPE
RESET
EEPROM
DESCRIPTION
[7:5]
RESERVED
-
-
N
Reserved.
[4]
OUT1_HIZ
RW
1
Y
Controls OUT1 in LMK61E0M. When set to 1, the output
is tri-stated with high impedance. When set to 0, the
output is in normal operation.
[3:1]
RESERVED
-
-
N
Reserved.
[0]
PLL_RDIV
RW
0
Y
On LMK61E0M, R divider is set to divide-by-4 when set
to 1 and R divider is bypassed when set to 0.
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8.6.1.15 PLL_NDIV_BY1 Register; R25
The 12-bit N integer divider value for PLL is set by the PLL_NDIV_BY1 and PLL_NDIV_BY0 registers.
BIT NO.
FIELD
TYPE
RESET
EEPROM
DESCRIPTION
[7:4]
RESERVED
-
-
N
Reserved.
[3:0]
PLL_NDIV[11:8]
RW
0x0
Y
PLL N Divider Byte 1. PLL Integer N Divider bits [11:8].
8.6.1.16 PLL_NDIV_BY0 Register; R26
The PLL_NDIV_BY0 register is described in the following table.
BIT NO.
FIELD
TYPE
RESET
EEPROM
DESCRIPTION
[7:0]
PLL_NDIV[7:0]
RW
0x32
Y
PLL N Divider Byte 0. PLL Integer N Divider bits [7:0].
8.6.1.17 PLL_FRACNUM_BY2 Register; R27
The 22-bit Fractional Divider Numerator value for PLL is set by registers PLL_FRACNUM_BY2,
PLL_FRACNUM_BY1 and PLL_FRACNUM_BY0.
BIT NO.
FIELD
TYPE
RESET
EEPROM
DESCRIPTION
[7:6]
RESERVED
-
-
N
Reserved.
[5:0]
PLL_NUM[21:16]
RW
0x00
Y
PLL Fractional Divider Numerator Byte 2. Bits [21:16]
8.6.1.18 PLL_FRACNUM_BY1 Register; R28
The PLL_FRACNUM_BY1 register is described in the following table.
BIT NO.
FIELD
TYPE
RESET
EEPROM
DESCRIPTION
[7:0]
PLL_NUM[15:8]
RW
0x00
Y
PLL Fractional Divider Numerator Byte 1. Bits [15:8].
8.6.1.19 PLL_FRACNUM_BY0 Register; R29
The PLL_FRACNUM_BY0 register is described in the following table.
BIT NO.
FIELD
TYPE
RESET
EEPROM
DESCRIPTION
[7:0]
PLL_NUM[7:0]
RW
0x00
Y
PLL Fractional Divider Numerator Byte 0. Bits [7:0]. When
using DCXO mode, the fractional numerator bits in R27,
R28, and R29 should be written in that order (MSB first
and LSB last) to avoid intermediate frequency jumps.
8.6.1.20 PLL_FRACDEN_BY2 Register; R30
The 22-bit Fractional Divider Denominator value for PLL is set by registers PLL_FRACDEN_BY2,
PLL_FRACDEN_BY1 and PLL_FRACDEN_BY0.
BIT NO.
FIELD
TYPE
RESET
EEPROM
DESCRIPTION
[7:6]
RESERVED
-
-
N
Reserved.
[5:0]
PLL_DEN[21:16]
RW
0x00
Y
PLL Fractional Divider Denominator Byte 2. Bits [21:16].
8.6.1.21 PLL_FRACDEN_BY1 Register; R31
The PLL_FRACDEN_BY1 register is described in the following table.
BIT NO.
FIELD
TYPE
RESET
EEPROM
DESCRIPTION
[7:0]
PLL_DEN[15:8]
RW
0x00
Y
PLL Fractional Divider Denominator Byte 1. Bits [15:8].
28
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8.6.1.22 PLL_FRACDEN_BY0 Register; R32
The PLL_FRACDEN_BY0 register is described in the following table.
BIT NO.
FIELD
TYPE
RESET
EEPROM
DESCRIPTION
[7:0]
PLL_DEN[7:0]
RW
0x00
Y
PLL Fractional Divider Denominator Byte 0. Bits [7:0].
8.6.1.23 PLL_MASHCTRL Register; R33
The PLL_MASHCTRL register provides control of the fractional divider for PLL.
BIT NO.
FIELD
TYPE
RESET
EEPROM
DESCRIPTION
[7:4]
RESERVED
-
-
N
Reserved.
[3:2]
PLL_DTHRMODE[1:0]
RW
0x3
Y
Mash Engine dither mode control.
[1:0]
PLL_ORDER[1:0]
RW
0x0
Y
DITHERMODE
Dither Configuration
0 (0x0)
Weak
1 (0x1)
Reserved
2 (0x2)
Reserved
3 (0x3)
Dither Disabled
Mash Engine Order.
ORDER
Order Configuration
0 (0x0)
Integer Mode Divider
1 (0x1)
Reserved
2 (0x2)
Reserved
3 (0x3)
3rd order
8.6.1.24 PLL_CTRL0 Register; R34
The PLL_CTRL1 register provides control of PLL. The PLL_CTRL1 register fields are described in the following
table.
BIT NO.
FIELD
TYPE
RESET
EEPROM
DESCRIPTION
[7:6]
RESERVED
RW
0x0
Y
Reserved.
[5]
PLL_D
RW
1
Y
PLL R Divider Frequency Doubler Enable. If PLL_D is 1
the R Divider Frequency Doubler is enabled.
[4]
RESERVED
-
-
N
Reserved.
[3:0]
PLL_CP[3:0]
RW
0x8
Y
PLL Charge Pump Current. Other combinations of
PLL_CP[3:0] not in table below are reserved and not
supported.
PLL_CP[3:0]
PLL Charge Pump Current
4 (0x4)
1.6 mA
8 (0x8)
6.4 mA
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8.6.1.25 PLL_CTRL1 Register; R35
The PLL_CTRL3 register provides control of PLL. The PLL_CTRL3 register fields are described in the following
table.
BIT NO.
FIELD
TYPE
RESET
EEPROM
DESCRIPTION
[7]
RESERVED
-
-
N
Reserved.
[6:4]
PLL_CP_PHASE_SHIFT RW
[2:0]
0x0
Y
Program Charge Pump Phase Shift.
PLL_CP_PHASE_SHIFT[ Phase Shift
2:0]
0 (0x0)
No delay
1 (0x1)
1.3 ns for 100 MHz fPD
2 (0x2)
1 ns for 100 MHz fPD
3 (0x3)
0.9 ns for 100 MHz fPD
4 (0x4)
1.3 ns for 50 MHz fPD
5 (0x5)
1 ns for 50 MHz fPD
6 (0x6)
0.9 ns for 50 MHz fPD
7 (0x7)
0.7 ns for 50 MHz fPD
[3]
RESERVED
-
-
N
Reserved.
[2]
PLL_ENABLE_C3
RW
0
Y
Disable third order capacitor in the low pass filter.
[1:0]
RESERVED
-
0x3
Y
PLL_ENABLE_C3
MODE
0
2nd order loop filter
recommended setting
1
Enables C3, 3rd order loop
filter enabled
Reserved.
8.6.1.26 PLL_LF_R2 Register; R36
The PLL_LF_R2 register controls the value of the PLL Loop Filter R2.
BIT NO.
FIELD
TYPE
RESET
EEPROM
DESCRIPTION
[7:0]
PLL_LF_R2[7:0]
RW
0x08
Y
PLL Loop Filter R2. NOTE: Table below lists commonly
used R2 values but more selections are available.
PLL_LF_R2[7:0]
R2 (Ω)
1 (0x01)
200
4 (0x04)
500
8 (0x08)
700
32 (0x20)
1600
48 (0x30)
2400
64 (0x40)
3200
8.6.1.27 PLL_LF_C1 Register; R37
The PLL_LF_C1 register controls the value of the PLL Loop Filter C1.
BIT NO.
FIELD
TYPE
RESET
EEPROM
DESCRIPTION
[7:3]
RESERVED
-
-
N
Reserved.
[2:0]
PLL_LF_C1[2:0]
RW
0x0
Y
PLL Loop Filter C1. The value in pF is given by 5 + 50 *
PLL_LF_C1 (in decimal).
30
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8.6.1.28 PLL_LF_R3 Register; R38
The PLL_LF_R3 register controls the value of the PLL Loop Filter R3.
BIT NO.
FIELD
TYPE
RESET
EEPROM
DESCRIPTION
[7]
RESERVED
-
-
N
Reserved.
[6:0]
PLL_LF_R3[6:0]
RW
0x00
Y
PLL Loop Filter R3. NOTE: Table below lists commonly
used R3 values but more selections are available.
PLL_LF_R3[6:0]
R3 (Ω)
0 (0x00)
18
3 (0x03)
205
8 (0x08)
854
9 (0x09)
1136
12 (0x0C)
1535
17 (0x11)
1936
20 (0x14)
2335
8.6.1.29 PLL_LF_C3 Register; R39
The PLL_LF_C3 register controls the value of the PLL Loop Filter C3.
BIT NO.
FIELD
TYPE
RESET
EEPROM
DESCRIPTION
[7:3]
RESERVED
-
-
N
Reserved.
[2:0]
PLL_LF_C3[2:0]
RW
0x0
Y
PLL Loop Filter C3. The value in pF is given by 5 *
PLL_LF_C3 (in decimal).
8.6.1.30 PLL_CALCTRL Register; R42
The PLL_CALCTRL register is described in the following table.
BIT NO.
FIELD
TYPE
RESET
EEPROM
DESCRIPTION
[7:4]
RESERVED
-
-
N
Reserved.
[3:2]
PLL_CLSDWAIT[1:0]
RW
0x2
Y
Closed Loop Wait Period. The CLSDWAIT field sets the
closed loop wait period. Recommended value is 0x2.
[1:0]
PLL_VCOWAIT[1:0]
RW
0x1
Y
CLSDWAIT
Anlog closed loop VCO
stabilization time
0 (0x0)
150 µs
1 (0x1)
300 µs
2 (0x2)
500 µs
3 (0x3)
2000 µs
VCO Wait Period. Recommended value is 0x1.
VCOWAIT
VCO stabilization time
0 (0x0)
20 µs
1 (0x1)
400 µs
2 (0x2)
4000 µs
3 (0x3)
10000 µs
8.6.1.31 NVMSCRC Register; R47
The NVMSCRC register holds the Stored CRC (Cyclic Redundancy Check) byte that has been retreived from onchip EEPROM.
BIT NO.
FIELD
TYPE
RESET
EEPROM
DESCRIPTION
[7:0]
NVMSCRC[7:0]
R
0x00
Y
EEPROM Stored CRC.
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8.6.1.32 NVMCNT Register; R48
The NVMCNT register is intended to reflect the number of on-chip EEPROM Erase/Program cycles that have
taken place in EEPROM. The count is automatically incremented by hardware and stored in EEPROM.
BIT NO.
FIELD
TYPE
RESET
EEPROM
DESCRIPTION
[7:0]
NVMCNT[7:0]
R
0x00
Y
EEPROM Program Count. The NVMCNT increments
automatically after every EEPROM Erase/Program Cycle.
The NVMCNT value is retreived automatically after reset,
after a EEPROM Commit operation or after a Erase/Program
cycle. The NVMCNT register will increment until it reaches its
maximum value of 255 after which no further increments will
take place.
8.6.1.33 NVMCTL Register; R49
The NVMCTL register allows control of the on-chip EEPROM Memories.
BIT NO.
FIELD
TYPE
RESET
EEPROM
DESCRIPTION
[7]
RESERVED
-
-
N
Reserved.
[6]
REGCOMMIT
RWSC
0
N
REG Commit to EEPROM SRAM Array. The REGCOMMIT bit
is used to initiate a transfer from the on-chip registers back to
the corresponding location in the EEPROM SRAM Array. The
REGCOMMIT bit is automatically cleared to 0 when the
transfer is complete.
[5]
NVMCRCERR
R
0
N
EEPROM CRC Error Indication. The NVMCRCERR bit is set
to 1 if a CRC Error has been detected when reading back from
on-chip EEPROM during device configuration.
[4]
NVMAUTOCRC
RW
1
N
EEPROM Automatic CRC. When NVMAUTOCRC is 1 then
the EEPROM Stored CRC byte is automatically calculated
whenever a EEPROM program takes place.
[3]
NVMCOMMIT
RWSC
0
N
EEPROM Commit to Registers. The NVMCOMMIT bit is used
to initiate a transfer of the on-chip EEPROM contents to
internal registers. The transfer happens automatically after
reset or when NVMCOMMIT is set to 1. The NVMCOMMIT bit
is automatically cleared to 0. The I2C registers cannot be read
while a EEPROM Commit operation is taking place.
[2]
NVMBUSY
R
0
N
EEPROM Program Busy Indication. The NVMBUSY bit is 1
during an on-chip EEPROM Erase/Program cycle. While
NVMBUSY is 1 the on-chip EEPROM cannot be accessed.
[1]
NVMERASE
RWSC
0
N
EEPROM Erase Start. The NVMERASE bit is used to begin
an on-chip EEPROM Erase cycle. The Erase cycle is only
initiated if the immediately preceding I2C transaction was a
write to the NVMUNLK register with the appropriate code. The
NVMERASE bit is automatically cleared to 0. The EEPROM
Erase operation takes around 115ms.
[0]
NVMPROG
RWSC
0
N
EEPROM Program Start. The NVMPROG bit is used to begin
an on-chip EEPROM Program cycle. The Program cycle is
only initiated if the immediately preceding I2C transaction was
a write to the NVMUNLK register with the appropriate code.
The NVMPROG bit is automatically cleared to 0. If the
NVMERASE and NVMPROG bits are set simultaneously then
an ERASE/PROGRAM cycle will be executed The EEPROM
Program operation takes around 115ms.
32
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8.6.1.34 MEMADR Register; R51
The MEMADR register holds 7-bits of the starting address for on-chip SRAM or EEPROM access.
BIT NO.
FIELD
TYPE
RESET
EEPROM
DESCRIPTION
[7]
RESERVED
-
-
N
Reserved.
[6:0]
MEMADR[6:0]
RW
0x00
N
Memory Address. The MEMADR value determines the starting
address for on-chip SRAM read/write access or on-chip
EEPROM access. The internal address to access SRAM or
EEPROM is automatically incremented; however the MEMADR
register does not reflect the internal address in this way. When
the SRAM or EEPROM arrays are accessed using the I2C
interface only bits [4:0] of MEMADR are used to form the byte
Wise address.
8.6.1.35 NVMDAT Register; R52
The NVMDAT register returns the on-chip EEPROM contents from the starting address specified by the
MEMADR register.
BIT NO.
FIELD
TYPE
RESET
EEPROM
DESCRIPTION
[7:0]
NVMDAT[7:0]
R
0x00
N
EEPROM Read Data. The first time an I2C read transaction
accesses the NVMDAT register address, either because it was
explicitly targeted or because the address was autoincremented, the read transaction will return the EEPROM
data located at the address specified by the MEMADR
register. Any additional read's which are part of the same
transaction will cause the EEPROM address to be
incremented and the next EEPROM data byte will be returned.
The I2C address will no longer be auto-incremented, i.e the
I2C address will be locked to the NVMDAT register after the
first access. Access to the NVMDAT register will terminate at
the end of the current I2C transaction.
8.6.1.36 RAMDAT Register; R53
The RAMDAT register provides read and write access to the SRAM that forms part of the on-chip EEPROM
module.
BIT NO.
FIELD
TYPE
RESET
EEPROM
DESCRIPTION
[7:0]
RAMDAT[7:0]
RW
0x00
N
RAM Read/Write Data. The first time an I2C read or write
transaction accesses the RAMDAT register address, either
because it was explicitly targeted or because the address was
auto-incremented, a read transaction will return the RAM data
located at the address specified by the MEMADR register and
a write transaction will cause the current I2C data to be written
to the address specified by the MEMADR register. Any
additional accesses which are part of the same transaction will
cause the RAM address to be incremented and a read or write
access will take place to the next SRAM address. The I2C
address will no longer be auto-incremented, i.e the I2C
address will be locked to the RAMDAT register after the first
access. Access to the RAMDAT register will terminate at the
end of the current I2C transaction.
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8.6.1.37 NVMUNLK Register; R56
The NVMUNLK register provides a rudimentary level of protection to prevent inadvertent programming of the onchip EEPROM.
BIT NO.
FIELD
TYPE
RESET
EEPROM
DESCRIPTION
[7:0]
NVMUNLK[7:0]
RW
0x00
N
EEPROM Prog Unlock. The NVMUNLK register must be
written immediately prior to setting the NVMPROG bit of
register NVMCTL, otherwise the Erase/Program cycle will not
be triggered. NVMUNLK must be written with a value of 0xBE.
8.6.1.38 INT_LIVE Register; R66
The INT_LIVE register reflects the current status of the interrupt sources.
BIT NO.
FIELD
TYPE
RESET
EEPROM
DESCRIPTION
[7:2]
RESERVED
-
-
N
Reserved.
[1]
LOL
R
0
N
Loss of Lock PLL.
[0]
CAL
R
0
N
Calibration Active PLL.
8.6.1.39 SWRST Register; R72
The SWRST1 register provides software reset control for specific on-chip modules. Each bit in this register is
individually self cleared after a write operation. The SWRST1 register will always return 0x00 in a read
transaction.
BIT NO.
FIELD
TYPE
RESET
EEPROM
DESCRIPTION
[7:2]
RESERVED
-
-
N
Reserved.
[1]
SWR2PLL
RWSC
0
N
Software Reset PLL. Setting SWR2PLL to 1 resets the PLL
calibrator and clock dividers. This bit is automatically cleared to
0.
[0]
RESERVED
-
-
N
Reserved.
34
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9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
The LMK61E0 features fine and coarse frequency margining capabilities which allow it to be used in applications
requiring the output frequency to be adjusted on the fly. In fractional PLL mode, the numerator of the PLL
fractional feedback divider can be updated over I2C to update the output frequency without glitches or spikes,
allowing the device to be used as a DCXO. The output frequency step size for every bit change in the numerator
of the PLL fractional feedback divider is given in Configuring the PLL. The Application Curves section below
illustrates the glitch-less switch in output frequency when the numerator is updated. The frequency margining
features can also aid the hardware designer during the system debug and validation phase.
9.2 Typical Application
3.3 V
3.3 V 3.3 V
VDD
4.7 kŸ
4.7 kŸ
SDA
OUT0
CMOS Clock
(DC Coupled)
SCL
OUT1
CMOS Clock
(AC Coupled)
OE
ADD
To/From CPU
GND
Figure 13. LMK61E0M Typical Application
9.2.1 Design Requirements
Consider a typical digital subscriber line (DSL) application, in which a local modem must track the clock signal of
a network modem to ensure accurate and efficient data transfer. In such systems, a DCXO is implemented to
allow a local processor to digitally control the oscillator frequency to maintain synchronization. An example of
such a clock frequency would be 70.656 MHz.
The typical schematic above shows the I2C connection to the processor and output configurations for AC or DC
coupling. OE and ADD can be left floating. The internal pullup resistor on OE enables OUT0. Leaving ADD
floating sets the LSB of the I2C slave address to 01.
The Detailed Design Procedure below describes the procedure to generate and adjust the required output
frequency for the above scenario using LMK61E0M.
9.2.2 Detailed Design Procedure
This design procedure will give a quick outline of the process of configuring the LMK61E0M in the above use
case. Typically, the easiest approach to configuring the PLL is to start with the desired output frequency and
work backwards.
1. VCO Frequency Selection
– The first step is to calculate the possible VCO frequencies given the required output frequency of 70.656
MHz. The LMK61E0M output dividers consist of the VCO post divider that can be set to /4 or /5, and the
output divider that can be set from /6 to /256. The VCO can output frequencies from 4.6 GHz to 5.6 GHz.
Therefore, the output frequency multiplied by the total divide value must fall within this range.
– To determine the boundary of the total divide value, we can divide the VCO frequency limits by the output
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Typical Application (continued)
frequency, resulting in a range of 65.1 to 79.3. Any combination of dividers that result in a total divide
value within this range will result in a valid VCO frequency. The possible divider combinations and the
resulting VCO frequencies are listed in columns 1 and 2, respectively, of Table 4, below.
2. Input Divider and Doubler/Phase Detector Frequency Configuration
– The next step is to set the reference divider and doubler in the reference frequency path to the PLL. The
reference divider can be set to /1 or /4, and the doubler can be set to x1 or x2. The main trade-off is that
a higher phase detector frequency will result in better output phase noise performance and a lower phase
detector frequency will result in a finer output frequency step size when adjusting the feedback divider
numerator in DCXO mode.
– In the DSL application, a finer step size is desired so the reference divider will be set to /4 and the
doubler to x1 to minimize the phase detector frequency. The phase detector frequency can then be
calculated by multiplying and dividing the reference frequency of 50 MHz by those values, resulting in
12.5 MHz.
– Note that in some applications, a trade-off in step size to obtain better phase noise performance is
acceptable. In that case the design procedure can be continued, substituting the relevant reference
divider and doubler configuration and phase detector frequency.
36
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Typical Application (continued)
3. Feedback Divider Selection
– The possible feedback divider values can then be calculated by dividing the VCO frequency by the phase
detector frequency. The possible values are listed in column 3 of Table 4.
– Glitch-less frequency margining in DCXO mode is achieved by adjusting the numerator of the feedback
divider without changing the integer value of the divider, which could cause a frequency glitch. Therefore,
the output frequency tuning range is limited by which VCO frequency and feedback divider we select out
of the valid combinations. To obtain as equal of a tuning range above and below the nominal output
frequency as possible, a feedback divider value with fractional portion as close to 1/2 as possible should
be chosen.
– The VCO frequency of 5369.856 MHz results in a feedback divider of 429.58848, which has a fractional
portion closest to 1/2. The decimal converted to a fraction is 429+58848/100000. To minimize step size,
the fraction can be converted to the maximum equivalent fraction of 2412768/4100000 as limited by the
maximum denominator of 4194303.
4. Frequency Margining
– With the device configured to output the nominal frequency of 70.656 MHz, the numerator can be
adjusted over I2C to tune the output frequency.
– Using equation 3 in Configuring the PLL, the step size of this configuration can be calculated to be
approximately 4x10–8 MHz or 0.58 ppb.
– The maximum and minimum tuning range limits can be determined by calculating the maximum shift in
frequency from nominal without changing the integer portion of the feedback divider (including setting the
numerator to zero or equal to the denominator). In this case, the limits are a maximum of +955 ppm and a
minimum of –1365 ppm from nominal.
Table 4. PLL Configuration Options
1. POSSIBLE OUTPUT DIVIDER 2. POSSIBLE VCO
COMBINATIONS
FREQUENCIES (MHz)
3. FEEDBACK DIVIDER WITH
PDF=12.5 MHz
4. EQUIVALENT FRACTIONAL
FEEDBACK DIVIDER VALUES
68 (/4, /17)
4804.608
384.36864
384+1511424/4100000
70 (/5, /14)
4945.92
395.6736
395+2822384/4190000
72 (/4, /18)
5087.232
406.97856
406+4012096/4100000
75 (/5, /15)
5299.2
423.936
423+3925584/4194000
76 (/4, /19)
5369.856
429.58848
429+2412768/4100000
9.2.2.1 PLL Loop Filter Design
The EVM software tool TICS Pro/Oscillator Programming Tool can be used to aid loop filter design. The Easy
Configuration GUI is able to generate a suggested set of loop filter values given a desired output frequency. The
tool recommends a PLL configuration that is designed to minimize jitter. As of the publication of this document, it
is not yet able to optimize for desired tuning range in DCXO mode. When configuring the device for operation in
DCXO mode, TI recommends using the software suggested loop filter settings as a starting point and then
perform the procedure described in Detailed Design Procedure to optimize the PLL configuration to suit the
application needs.
A general set of loop filter design guidelines are given below:
• There are many device configurations to achieve the desired output frequency from a device. However there
are some optimizations and trade-offs to be considered.
• The guidelines below may be followed when configuring PLL related dividers or other related registers:
– For lowest possible in-band PLL flat noise, maximize phase detector frequency to minimize N divide value.
– For fractional divider values, keep the denominator at highest value possible to minimize spurs. It is also
best to use a higher order modulator whenever possible for the same reason.
– As a rule of thumb, keep the phase detector frequency approximately between 10 × PLL loop bandwidth
and 100 × PLL loop bandwidth. A phase detector frequency less than 5 × PLL bandwidth may be
unstable.
– While designing the loop filter, adjusting the charge pump current or N value can help with loop filter
component selection. Lower charge pump currents and larger N values result in smaller component values
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but may increase impacts of leakage and reduce PLL phase noise performance.
– A more detailed understanding of loop filter design can be found in Dean Banerjee's PLL Performance,
Simulation, and Design.
9.2.2.2 Spur Mitigation Techniques
The LMK61E0M offers several programmable features for optimizing fractional spurs. To get the best out of
these features, it makes sense to understand the different kinds of spurs as well as their behaviors, causes, and
remedies. Although optimizing spurs may involve some trial and error, there are ways to make this process more
systematic. TI offers the Clock Design Tool (SNAU082) for more information and estimation of fractional spurs.
9.2.2.2.1 Phase Detection Spur
The phase detector spur occurs at an offset from the carrier equal to the phase detector frequency, fPD. To
minimize this spur, consider a lower phase detector frequency. In some cases where the loop bandwidth is very
wide relative to the phase detector frequency, some benefit might be gained from using a narrower loop
bandwidth or adding poles to the loop filter by using R3 and C3 if previously unused, but otherwise the loop filter
has minimal impact. Bypassing at the supply pins and board layout can also have an impact on this spur,
especially at higher phase detector frequencies.
9.2.2.2.2 Integer Boundary Fractional Spur
This spur occurs at an offset equal to the difference between the VCO frequency and the closest integer channel
for the VCO. For instance, if the phase detector frequency is 100 MHz and the VCO frequency is 5003 MHz,
then the integer boundary spur would be at 3-MHz offset. This spur can be either PLL or VCO dominated. If it is
PLL dominated, decreasing the loop bandwidth and some of the programmable fractional words may impact this
spur. If the spur is VCO dominated, then reducing the loop filter will not help, but rather reducing the phase
detector and having good slew rate and signal integrity at the selected reference input will help.
9.2.2.2.3 Primary Fractional Spur
These spurs occur at multiples of fPD/DEN and are not the integer boundary spur. For instance, if the phase
detector frequency is 100 MHz and the fraction is 3/100, the primary fractional spurs would be at 1 MHz, 2 MHz,
4 MHz, 5 MHz, 6 MHz, and so forth. These are impacted by the loop filter bandwidth and modulator order. If a
small frequency error is acceptable, then a larger equivalent fraction may improve these spurs. This larger
unequivalent fraction pushes the fractional spur energy to much lower frequencies that where they are not
impactful to the system performance.
9.2.2.2.4 Sub-Fractional Spur
These spurs appear at a fraction of fPD/DEN and depend on modulator order. With the first order modulator, there
are no sub-fractional spurs. The second order modulator can produce 1/2 sub-fractional spurs if the denominator
is even. A third order modulator can produce sub-fractional spurs at 1/2, 1/3, or 1/6 of the offset, depending if it is
divisible by 2 or 3. For instance, if the phase detector frequency is 100 MHz and the fraction is 3/100, no subfractional spurs for a first order modulator or sub-fractional spurs at multiples of 1.5 MHz for a second or third
order modulator would be expected. Aside from strategically choosing the fractional denominator and using a
lower order modulator, another tactic to eliminate these spurs is to use dithering and express the fraction in
larger equivalent terms. Because dithering also adds phase noise, its level needs to be managed to achieve
acceptable phase noise and spurious performance.
Table 5 summarizes spur and mitigation techniques.
Table 5. Spur and Mitigation Techniques
38
SPUR TYPE
OFFSET
WAYS TO REDUCE
TRADE-OFFS
Phase Detector
fPD
Reduce Phase Detector
Frequency.
Although reducing the phase
detector frequency does improve
this spur, it also degrades phase
noise.
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Table 5. Spur and Mitigation Techniques (continued)
SPUR TYPE
OFFSET
WAYS TO REDUCE
Integer Boundary
fVCO mod fPD
Methods for PLL Dominated
Spurs
-
TRADE-OFFS
Avoid the worst case VCO
frequencies if possible.
- Ensure good slew rate and
signal integrity at reference input.
Reducing the loop bandwidth
may degrade the total integrated
noise if the bandwidth is too
narrow.
- Reduce loop bandwidth or
add more filter poles to suppress
out of band spurs.
Methods for VCO Dominated
Spurs
-
Avoid the worst case VCO
frequencies if possible.
-
Reduce Phase Detector
Frequency.
Reducing the phase detector
may degrade the phase noise.
- Ensure good slew rate and
signal integrity at reference input.
Primary Fractional
Sub-Fractional
fPD/DEN
-
Decrease Loop Bandwidth.
-
Change Modulator Order.
-
Use Larger Unequivalent
Fractions.
fPD/DEN/k k=2,3, or 6
-
Decreasing the loop bandwidth
may degrade in-band phase
noise. Also, larger unequivalent
fractions don’t always reduce
spurs.
Use Dithering.
Use Larger Equivalent
Fractions.
Use Larger Unequivalent
Fractions.
Dithering and larger fractions
may increase phase noise.
Reduce Modulator Order.
Eliminate factors of 2 or 3 in
denominator.
9.2.2.3 Device Programming
The EVM software tool TICS Pro/Oscillator Programming Tool can be used to program the device with the
desired configuration. Simply select the Program EEPROM option and the software will automatically load the
current configuration to EEPROM. The settings will then be available upon subsequent startup without the need
to reload the registers over I2C.
9.2.3 Application Curves
Figure 14. Increasing Output Frequency in DCXO Mode
Figure 15. Decreasing Output Frequency in DCXO Mode
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10 Power Supply Recommendations
For best electrical performance of the LMK61E0 device, TI recommends using a combination of 10 µF, 1 µF and
0.1 µF on its power supply bypass network. TI also recommends using component side mounting of the power
supply bypass capacitors, and it is best to use 0201 or 0402 body size capacitors to facilitate signal routing.
Keep the connections between the bypass capacitors and the power supply on the device as short as possible.
Ground the other side of the capacitor using a low impedance connection to the ground plane. Figure 16 shows
the layout recommendation for power supply decoupling of LMK61E0.
11 Layout
11.1 Layout Guidelines
Ensured Thermal Reliability, Best Practices for Signal Integrity and Recommended Solder Reflow Profile provide
recommendations for board layout, solder reflow profile and power supply bypassing when using LMK61E0 to
ensure good thermal and electrical performance and overall signal integrity of entire system.
11.1.1 Ensured Thermal Reliability
The LMK61E0 is a high performance device. Therefore careful attention must be paid to device configuration and
printed-circuit board (PCB) layout with respect to power consumption. The ground pin needs to be connected to
the ground plane of the PCB through three vias or more, as shown in Figure 16, to maximize thermal dissipation
out of the package.
Equation 4 describes the relationship between the PCB temperature around the LMK61E0 and its junction
temperature.
TB = TJ – ΨJB * P
where
•
•
•
•
TB: PCB temperature around the LMK61E0
TJ: Junction temperature of LMK61E0
ΨJB: Junction-to-board thermal resistance parameter of LMK61E0 (36.7°C/W without airflow)
P: On-chip power dissipation of LMK61E0
(4)
To ensure that the maximum junction temperature of LMK61E0 is below 115°C, it can be calculated that the
maximum PCB temperature without airflow should be at 93°C or below when the device is optimized for best
performance resulting in maximum on-chip power dissipation of 0.6 W.
11.1.2 Best Practices for Signal Integrity
For best electrical performance and signal integrity of entire system with LMK61E0, TI recommends routing vias
into decoupling capacitors and then into the LMK61E0. TI also recommends increasing the via count and width of
the traces wherever possible. These steps ensure lowest impedance and shortest path for high-frequency current
flow. Figure 16 shows the layout recommendation for LMK61E0.
11.1.3 Recommended Solder Reflow Profile
TI also recommends following the solder paste supplier's recommendations to optimize flux activity and to
achieve proper melting temperatures of the alloy within the guidelines of J-STD-20. It is preferable for the
LMK61E0 to be processed with the lowest peak temperature possible while also remaining below the
components peak temperature rating as listed on the MSL label. The exact temperature profile would depend on
several factors including maximum peak temperature for the component as rated on the MSL label, Board
thickness, PCB material type, PCB geometries, component locations, sizes, densities within PCB, as well solder
manufactures recommended profile, and capability of the reflow equipment to as confirmed by the SMT
assembly operation.
40
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11.2 Layout Example
Figure 16. LMK61E0 Layout Recommendation for Power Supply and Ground
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12 Device and Documentation Support
12.1 Documentation Support
12.1.1 Related Documentation
For related documentation see the following:
• Clock Design Tool (SNAU082)
• PLL Performance, Simulation, and Design
12.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
12.3 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
12.4 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
12.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
12.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
42
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Copyright © 2017, Texas Instruments Incorporated
Product Folder Links: LMK61E0M
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
LMK61E0M-SIAR
ACTIVE
QFM
SIA
8
2500
RoHS & Green
NIAU
Level-3-260C-168 HR
-40 to 85
LMK61E0
M
LMK61E0M-SIAT
ACTIVE
QFM
SIA
8
250
RoHS & Green
NIAU
Level-3-260C-168 HR
-40 to 85
LMK61E0
M
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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