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LMP7701, LMP7702, LMP7704
SNOSAI9I – SEPTEMBER 2005 – REVISED NOVEMBER 2015
LMP770x Precision, CMOS Input, RRIO, Wide Supply Range Amplifiers
1 Features
3 Description
•
The LMP770x are single, dual, and quad low-offset
voltage, rail-to-rail input and output precision
amplifiers, each with a CMOS input stage and a wide
supply voltage range. The LMP770x are part of the
LMP™ precision amplifier family and are ideal for
sensor
interface
and
other
instrumentation
applications.
1
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Unless Otherwise Noted,
Typical Values at VS = 5 V
Input Offset Voltage (LMP7701): ±200-µV
(Maximum)
Input Offset Voltage (LMP7702/LMP7704): ±220µV (Maximum)
Input Bias Current: ±200 fA
Input Bias Current: ±200 fA
Input Voltage Noise: 9 nV/√Hz
CMRR: 130 dB
Open-Loop Gain: 130 dB
Temperature Range: −40°C to 125°C
Unity-Gain Bandwidth: 2.5 MHz
Supply Current (LMP7701): 715 µA
Supply Current (LMP7702): 1.5 mA
Supply Current (LMP7704): 2.9 mA
Supply Voltage Range: 2.7 V to 12 V
Rail-to-Rail Input and Output
The specified low-offset voltage of less than ±200 µV,
along with the specified low input bias current of less
than ±1 pA, make the LMP7701 ideal for precision
applications. The LMP770x are built using VIP50
technology, which allows the combination of a CMOS
input stage and a 12-V common-mode and supply
voltage range. This makes the LMP770x ideal for
applications where conventional CMOS parts cannot
operate under the desired voltage conditions.
Device Information(1)
PART NUMBER
LMP7701
LMP7702
2 Applications
•
•
•
•
•
•
High Impedance Sensor Interface
Battery-Powered Instrumentation
High Gain Amplifiers
DAC Buffer
Instrumentation Amplifier
Active Filters
LMP7704
PACKAGE
BODY SIZE (NOM)
SOT-23 (5)
1.60 mm × 2.90 mm
SOIC (8)
3.91 mm × 4.90 mm
VSSOP (8)
3.00 mm × 3.00 mm
SOIC (8)
3.91 mm × 4.90 mm
TSSOP (14)
4.40 mm × 5.00 mm
SOIC (14)
3.91 mm × 8.65 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Typical Application Schematic
R
R
V1
V
+
-
RS
I = (V2 ± V1)
A1
RS
+
V
-
V
+
Z
R
LOAD
-
R
V2
A2
+
-
V
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
LMP7701, LMP7702, LMP7704
SNOSAI9I – SEPTEMBER 2005 – REVISED NOVEMBER 2015
www.ti.com
Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Description (continued).........................................
Pin Configuration and Functions .........................
Specifications.........................................................
7.1
7.2
7.3
7.4
7.5
7.6
7.7
7.8
8
1
1
1
2
3
3
5
Absolute Maximum Ratings ..................................... 5
ESD Ratings.............................................................. 5
Recommended Operating Conditions ...................... 6
Thermal Information .................................................. 6
Electrical Characteristics 3-V .................................... 6
Electrical Characteristics 5-V .................................... 9
Electrical Characteristics ±5-V ................................ 11
Typical Characteristics ............................................ 14
Detailed Description ............................................ 21
8.1 Overview ................................................................. 21
8.2 Functional Block Diagram ....................................... 21
8.3 Feature Description................................................. 21
8.4 Device Functional Modes........................................ 25
9
Application and Implementation ........................ 25
9.1 Application Information............................................ 25
9.2 Typical Application .................................................. 27
10 Power Supply Recommendations ..................... 30
11 Layout................................................................... 31
11.1 Layout Guidelines ................................................. 31
11.2 Layout Example .................................................... 31
12 Device and Documentation Support ................. 32
12.1
12.2
12.3
12.4
12.5
Related Links ........................................................
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
32
32
32
32
32
13 Mechanical, Packaging, and Orderable
Information ........................................................... 32
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision H (March 2013) to Revision I
•
Page
Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation
section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and
Mechanical, Packaging, and Orderable Information section. ................................................................................................ 1
Changes from Revision G (March 2013) to Revision H
•
2
Page
Changed layout of National Data Sheet to TI format ........................................................................................................... 27
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SNOSAI9I – SEPTEMBER 2005 – REVISED NOVEMBER 2015
5 Description (continued)
The LMP770x each have a rail-to-rail input stage that significantly reduces the CMRR glitch commonly
associated with rail-to-rail input amplifiers. This is achieved by trimming both sides of the complimentary input
stage, thereby reducing the difference between the NMOS and PMOS offsets. The output of the LMP770x
swings within 40 mV of either rail to maximize the signal dynamic range in applications requiring low supply
voltage.
The LMP7701 is offered in the space-saving 5-Pin SOT-23 and 8-Pin SOIC package. The LMP7702 is offered in
the 8-Pin SOIC and 8-Pin VSSOP package. The quad LMP7704 is offered in the 14-Pin SOIC and 14-Pin
TSSOP package. These small packages are ideal solutions for area constrained PC boards and portable
electronics.
6 Pin Configuration and Functions
LMP7701 DBV Package
5-Pin SOT-23
Top View
OUT
-
V
LMP7701 D Package
8-Pin SOIC
Top View
5
1
+
V
N/C
2
-IN
+
+IN
IN+
4
3
1
8
2
7
-
3
6
+
N/C
+
V
OUTPUT
IN-
4
5
V
N/C
Pin Functions - LMP7701
PIN
NAME
I/O
DESCRIPTION
SOT-23
SOIC
IN+
3
3
I
Noninverting Input
IN–
4
2
I
Inverting Input
IN A +
—
—
I
Noninverting Input for Amplifier A
–
IN A
—
—
I
Inverting Input for Amplifier A
IN B+
—
—
I
Noninverting Input for Amplifier B
IN B–
—
—
I
Inverting Input for Amplifier B
+
IN C
—
—
I
Noninverting Input for Amplifier C
IN C–
—
—
I
Inverting Input for Amplifier C
IN D+
—
—
I
Noninverting Input for Amplifier D
–
IN D
—
—
I
Inverting Input for Amplifier D
NC
—
1, 5, 8
—
No connection
OUT
1
6
O
Output
OUT A
—
—
O
Output for Amplifier A
OUT B
—
—
O
Output for Amplifier B
OUT C
—
—
O
Output for Amplifier C
OUT D
—
—
O
Output for Amplifier D
+
V
5
7
P
Positive Supply
V–
2
4
P
Negative Supply
Copyright © 2005–2015, Texas Instruments Incorporated
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SNOSAI9I – SEPTEMBER 2005 – REVISED NOVEMBER 2015
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LMP7702 D or DGK Package
8-Pin SOIC or VSSOP
Top View
Pin Functions - LMP7702
PIN
NAME
SOIC, VSSOP
I/O
DESCRIPTION
IN+
—
I
Noninverting Input
IN–
—
I
Inverting Input
+
IN A
3
I
Noninverting Input for Amplifier A
IN A–
2
I
Inverting Input for Amplifier A
IN B+
5
I
Noninverting Input for Amplifier B
IN B–
6
I
Inverting Input for Amplifier B
+
IN C
—
I
Noninverting Input for Amplifier C
IN C–
—
I
Inverting Input for Amplifier C
IN D+
—
I
Noninverting Input for Amplifier D
–
IN D
—
I
Inverting Input for Amplifier D
NC
—
—
No connection
OUT
—
O
Output
OUT A
1
O
Output for Amplifier A
OUT B
7
O
Output for Amplifier B
OUT C
—
O
Output for Amplifier C
OUT D
—
O
Output for Amplifier D
+
V
8
P
Positive Supply
V–
4
P
Negative Supply
LMP7704 D or PW Package
14-Pin SOIC or TSSOP
Top View
4
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Product Folder Links: LMP7701 LMP7702 LMP7704
LMP7701, LMP7702, LMP7704
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SNOSAI9I – SEPTEMBER 2005 – REVISED NOVEMBER 2015
Pin Functions - LMP7704
PIN
NAME
SOIC, TSSOP
I/O
DESCRIPTION
IN+
—
I
Noninverting Input
IN–
—
I
Inverting Input
+
IN A
3
I
Noninverting Input for Amplifier A
IN A–
2
I
Inverting Input for Amplifier A
IN B+
5
I
Noninverting Input for Amplifier B
IN B–
6
I
Inverting Input for Amplifier B
IN C
10
I
Noninverting Input for Amplifier C
IN C–
9
I
Inverting Input for Amplifier C
IN D+
12
I
Noninverting Input for Amplifier D
–
IN D
13
I
Inverting Input for Amplifier D
NC
—
—
No connection
OUT
—
O
Output
OUT A
1
O
Output for Amplifier A
OUT B
7
O
Output for Amplifier B
OUT C
8
O
Output for Amplifier C
OUT D
14
O
Output for Amplifier D
V
4
P
Positive Supply
V–
11
P
Negative Supply
+
+
7 Specifications
7.1 Absolute Maximum Ratings
See
(1) (2)
MAX
UNIT
VIN differential
MIN
±300
mV
Supply voltage (VS = V+ – V−)
13.2
V
V++ 0.3, V− − 0.3
V
Voltage at input/output pins
Input current
Junction temperature
(3)
Soldering information
Infrared or convection (20 sec)
Wave soldering lead temp. (10 sec)
−65
Storage temperature, Tstg
(1)
(2)
(3)
10
mA
+150
°C
235
°C
260
°C
150
°C
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions . Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
If Military/Aerospace specified devices are required, contact the TI Sales Office/ Distributors for availability and specifications.
The maximum power dissipation is a function of TJ(MAX), θJA. The maximum allowable power dissipation at any ambient temperature is
PD = (TJ(MAX) – TA)/ θJA. All numbers apply for packages soldered directly onto a PC Board.
7.2 ESD Ratings
VALUE
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001
V(ESD)
(1)
(2)
(3)
Electrostatic
discharge
(1) (2)
UNIT
±2000
Charged-device model (CDM), per JEDEC specification JESD22-C101 (3)
±1000
Machine Model (MM)
±200
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
Human Body Model, applicable std. MIL-STD-883, Method 3015.7. Machine Model, applicable std. JESD22-A115-A (ESD MM std. of
JEDEC) Field-Induced Charge-Device Model, applicable std. JESD22-C101-C (ESD FICDM std. of JEDEC).
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
Copyright © 2005–2015, Texas Instruments Incorporated
Product Folder Links: LMP7701 LMP7702 LMP7704
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7.3 Recommended Operating Conditions
MIN
Temperature range
(1)
Supply voltage (VS = V+ – V−)
(1)
MAX
UNIT
−40
NOM
125
°C
2.7
12
V
The maximum power dissipation is a function of TJ(MAX), θJA. The maximum allowable power dissipation at any ambient temperature is
PD = (TJ(MAX) – TA)/ θJA. All numbers apply for packages soldered directly onto a PC Board.
7.4 Thermal Information
THERMAL METRIC
(1)
(2)
LMP7701
LMP7701,
LMP7702
LMP7702
DBV
(SOT-23)
D
(SOIC)
DGK
(VSSOP)
D
(SOIC)
PW
(TSSOP)
5 PINS
8 PINS
8 PINS
14 PINS
14 PINS
122.9
114.3
167.5
79.9
107.5
°C/W
LMP7704
UNIT
RθJA
Junction-to-ambient thermal resistance
RθJC(top)
Junction-to-case (top) thermal resistance
69.3
59.5
58.7
36.9
33.0
°C/W
RθJB
Junction-to-board thermal resistance
63.3
54.8
87.5
34.7
50.4
°C/W
ψJT
Junction-to-top characterization parameter
19.4
12.1
6.6
5.5
1.8
°C/W
ψJB
Junction-to-board characterization
parameter
62.8
54.2
86.1
34.4
49.7
°C/W
(1)
(2)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report (SPRA953).
The maximum power dissipation is a function of TJ(MAX), θJA. The maximum allowable power dissipation at any ambient temperature is
PD = (TJ(MAX) – TA)/ θJA. All numbers apply for packages soldered directly onto a PC Board.
7.5 Electrical Characteristics 3-V
Unless otherwise specified, all limits are ensured for TA = 25°C, V+ = 3 V, V− = 0 V, VCM = V+/2, and RL > 10 kΩ to V+/2. (1)
PARAMETER
TEST CONDITIONS
MIN
(2)
TYP
(3)
±37
LMP7701
VOS
Input Offset Voltage
Input Offset Voltage Temperature
Drift
at the temperature
extremes
(4)
Input Bias Current
See
−40°C ≤ TA ≤ 125°C
(1)
(2)
(3)
(4)
(5)
6
±200
±220
μV
±520
at the temperature
extremes
±5
±0.2
at the temperature
extremes
at the temperature
extremes
Input Offset Current
μV/°C
±1
±50
±0.2
(4) (5)
IOS
UNIT
±1
See
See (4) (5)
−40°C ≤ TA ≤ 85°C
IB
(2)
±500
±56
LMP7702/LMP7704
TCVOS
at the temperature
extremes
MAX
±1
pA
±400
40
fA
Electrical Table values apply only for factory testing conditions at the temperature indicated. Factory testing conditions result in very
limited self-heating of the device such that TJ = TA. No specification of parametric performance is indicated in the electrical tables under
conditions of internal self-heating where TJ > TA.
Limits are 100% production tested at 25°C. Limits over the operating temperature range are specified through correlations using the
Statistical Quality Control (SQC) method.
Typical values represent the most likely parametric norm as determined at the time of characterization. Actual typical values may vary
over time and will also depend on the application and configuration. The typical values are not tested and are not specified on shipped
production material.
This parameter is specified by design and/or characterization and is not tested in production.
Positive current corresponds to current flowing into the device.
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SNOSAI9I – SEPTEMBER 2005 – REVISED NOVEMBER 2015
Electrical Characteristics 3-V (continued)
Unless otherwise specified, all limits are ensured for TA = 25°C, V+ = 3 V, V− = 0 V, VCM = V+/2, and RL > 10 kΩ to V+/2.(1)
PARAMETER
TEST CONDITIONS
0 V ≤ VCM ≤ 3 V
LMP7701
CMRR
Common-Mode Rejection Ratio
0 V ≤ VCM ≤ 3 V
LMP7702/LMP7704
MIN
(2)
86
at the temperature
extremes
Power Supply Rejection Ratio
CMVR
Common-Mode Voltage Range
2.7 V ≤ V+ ≤ 12 V, Vo = V+/2 at the temperature
extremes
CMRR ≥ 80 dB
CMRR ≥ 77 dB
RL = 2 kΩ (LMP7701)
VO = 0.3 V to 2.7 V
AVOL
Open-Loop Voltage Gain
RL = 2 kΩ
(LMP7702/LMP7704)
VO = 0.3 V to 2.7 V
RL = 10 kΩ
VO = 0.2 V to 2.8 V
VOUT
RL = 2 kΩ to V+/2
LMP7701
RL = 2 kΩ to V+/2
LMP7702/LMP7704
Output Voltage Swing High
RL = 10 kΩ to V+/2
LMP7701
RL = 10 kΩ to V+/2
LMP7702/LMP7704
RL = 2 kΩ to V+/2
LMP7701
RL = 2 kΩ to V+/2
LMP7702/LMP7704
Output Voltage Swing Low
RL = 10 kΩ to V+/2
LMP7701
RL = 10 kΩ to V+/2
LMP7702/LMP7704
at the temperature
extremes
98
dB
–0.2
3.2
96
114
dB
94
124
96
40
at the temperature
extremes
80
150
30
at the temperature
extremes
mV
+
40 from V
60
35
at the temperature
extremes
50
100
40
at the temperature
extremes
60
80
45
at the temperature
extremes
100
170
20
at the temperature
extremes
40
mV
50
20
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80
120
40
Copyright © 2005–2015, Texas Instruments Incorporated
V
114
at the temperature
extremes
at the temperature
extremes
dB
130
3.2
100
at the temperature
extremes
UNIT
130
–0.2
100
at the temperature
extremes
(2)
82
100
at the temperature
extremes
MAX
78
86
PSRR
(3)
80
84
at the temperature
extremes
TYP
50
90
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Electrical Characteristics 3-V (continued)
Unless otherwise specified, all limits are ensured for TA = 25°C, V+ = 3 V, V− = 0 V, VCM = V+/2, and RL > 10 kΩ to V+/2.(1)
PARAMETER
TEST CONDITIONS
Sourcing VO = V+/2
VIN = 100 mV
IOUT
Output Current
Sinking VO = V+/2
VIN = −100 mV (LMP7701)
(6) (7)
Sinking VO = V+/2
VIN = −100 mV
(LMP7702/LMP7704)
MIN
(2)
25
at the temperature
extremes
at the temperature
extremes
Supply Current
LMP7702
at the temperature
extremes
LMP7704
at the temperature
extremes
mA
42
15
AV = +1, VO = 2 VPP
10% to 90%
(8)
Slew Rate
GBW
Gain Bandwidth
THD+N Total Harmonic Distortion + Noise
f = 1 kHz, AV = 1, R.L = 10 kΩ
1
1.2
1.8
2.1
2.9
SR
UNIT
42
1.4
IS
(2)
42
0.670
LMP7701
MAX
20
25
at the temperature
extremes
(3)
15
25
at the temperature
extremes
TYP
mA
3.5
4.5
0.9
V/μs
2.5
MHz
0.02%
en
Input Referred Voltage Noise
Density
f = 1 kHz
9
nV/√Hz
in
Input Referred Current Noise
Density
f = 100 kHz
1
fA/√Hz
(6)
(7)
(8)
8
The maximum power dissipation is a function of TJ(MAX), θJA. The maximum allowable power dissipation at any ambient temperature is
PD = (TJ(MAX) – TA)/ θJA. All numbers apply for packages soldered directly onto a PC Board.
The short circuit test is a momentary test.
The number specified is the slower of positive and negative slew rates.
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SNOSAI9I – SEPTEMBER 2005 – REVISED NOVEMBER 2015
7.6 Electrical Characteristics 5-V
Unless otherwise specified, all limits are ensured for TA = 25°C, V+ = 5 V, V− = 0 V, VCM = V+/2, and RL > 10 kΩ to V+/2. (1)
PARAMETER
TEST CONDITIONS
MIN
(2)
TYP
(3)
±37
LMP7701
VOS
Input Offset Voltage
Input Offset Voltage
Temperature Drift
(4)
See (4) (5)
−40°C ≤ TA ≤ 85°C
IB
at the temperature
extremes
Input Bias Current
IOS
±0.2
at the temperature
extremes
Common-Mode Rejection Ratio
0 V ≤ VCM ≤ 5 V
LMP7702/LMP7704
at the temperature
extremes
CMVR
Common-Mode Voltage Range
88
at the temperature
extremes
2.7 V ≤ V+ ≤ 12 V, VO = V+/2
at the temperature
extremes
CMRR ≥ 78 dB
RL = 2 kΩ (LMP7701)
VO = 0.3 V to 4.7 V
Open-Loop Voltage Gain
RL = 2 kΩ
(LMP7702/LMP7704)
VO = 0.3 V to 4.7 V
RL = 10 kΩ
VO = 0.2 V to 4.8 V
(1)
(2)
(3)
(4)
(5)
at the temperature
extremes
100
dB
–0.2
5.2
–0.2
5.2
V
119
96
119
dB
94
100
at the temperature
extremes
dB
130
82
100
at the temperature
extremes
fA
130
81
100
at the temperature
extremes
pA
83
86
CMRR ≥ 80 dB
AVOL
±1
±400
86
Power Supply Rejection Ratio
±1
±50
±0.2
at the temperature
extremes
μV
±5
40
0 V ≤ VCM ≤ 5 V
LMP7701
PSRR
±220
μV/°C
Input Offset Current
CMRR
±200
at the temperature
extremes
(4) (5)
See
−40°C ≤ TA ≤ 125°C
UNIT
±520
±1
See
(2)
±500
±32
LMP7702/LMP7704
TCVOS
at the temperature
extremes
MAX
130
96
Electrical Table values apply only for factory testing conditions at the temperature indicated. Factory testing conditions result in very
limited self-heating of the device such that TJ = TA. No specification of parametric performance is indicated in the electrical tables under
conditions of internal self-heating where TJ > TA.
Limits are 100% production tested at 25°C. Limits over the operating temperature range are specified through correlations using the
Statistical Quality Control (SQC) method.
Typical values represent the most likely parametric norm as determined at the time of characterization. Actual typical values may vary
over time and will also depend on the application and configuration. The typical values are not tested and are not ensured on shipped
production material.
This parameter is specified by design and/or characterization and is not tested in production.
Positive current corresponds to current flowing into the device.
Copyright © 2005–2015, Texas Instruments Incorporated
Product Folder Links: LMP7701 LMP7702 LMP7704
Submit Documentation Feedback
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LMP7701, LMP7702, LMP7704
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Electrical Characteristics 5-V (continued)
Unless otherwise specified, all limits are ensured for TA = 25°C, V+ = 5 V, V− = 0 V, VCM = V+/2, and RL > 10 kΩ to V+/2.(1)
PARAMETER
TEST CONDITIONS
RL = 2 kΩ to V+/2
LMP7701
RL = 2 kΩ to V+/2
LMP7702/LMP7704
Output Voltage Swing High
MIN
(2)
RL = 10 kΩ to V+/2
LMP7702/LMP7704
VOUT
RL = 2 kΩ to V+/2
LMP7701
RL = 2 kΩ to V+/2
LMP7702/LMP7704
Output Voltage Swing Low
RL = 10 kΩ to V+/2
LMP7701
RL = 10 kΩ to V+/2
LMP7702/LMP7704
Sourcing VO = V+/2
VIN = 100 mV (LMP7701)
IOUT
Output Current
(6) (7)
Sourcing VO = V+/2
VIN = 100 mV
(LMP7702/LMP7704)
60
at the temperature
extremes
at the temperature
extremes
40
Sinking VO = V+/2
VIN = −100 mV
(LMP7702/LMP7704)
50
50
at the temperature
extremes
30
40
at the temperature
extremes
66
(8)
Slew Rate
GBW
Gain Bandwidth
(6)
(7)
(8)
10
AV = +1, VO = 4 VPP
10% to 90%
mA
76
76
23
1
1.2
1.9
2.2
2.9
SR
50
28
40
LMP7704
mV
25
40
at the temperature
extremes
40
28
38
LMP7702
120
66
1.5
Supply Current
80
100
0.715
IS
60
50
at the temperature
extremes
at the temperature
extremes
mV
+
50 from V
190
30
LMP7701
120
90
at the temperature
extremes
at the temperature
extremes
110
120
at the temperature
extremes
at the temperature
extremes
UNIT
70
at the temperature
extremes
at the temperature
extremes
(2)
200
40
at the temperature
extremes
MAX
130
60
+
Sinking VO = V /2
VIN = −100 mV (LMP7701)
(3)
at the temperature
extremes
+
RL = 10 kΩ to V /2
LMP7701
TYP
mA
3.7
4.6
1
V/μs
2.5
MHz
The maximum power dissipation is a function of TJ(MAX), θJA. The maximum allowable power dissipation at any ambient temperature is
PD = (TJ(MAX) – TA)/ θJA. All numbers apply for packages soldered directly onto a PC Board.
The short circuit test is a momentary test.
The number specified is the slower of positive and negative slew rates.
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SNOSAI9I – SEPTEMBER 2005 – REVISED NOVEMBER 2015
Electrical Characteristics 5-V (continued)
Unless otherwise specified, all limits are ensured for TA = 25°C, V+ = 5 V, V− = 0 V, VCM = V+/2, and RL > 10 kΩ to V+/2.(1)
PARAMETER
TEST CONDITIONS
MIN
(2)
TYP
(3)
MAX
(2)
UNIT
THD+N
Total Harmonic Distortion +
Noise
f = 1 kHz, AV = 1, RL = 10 kΩ
en
Input Referred Voltage Noise
Density
f = 1 kHz
9
nV/√Hz
in
Input Referred Current Noise
Density
f = 100 kHz
1
fA/√Hz
0.02%
7.7 Electrical Characteristics ±5-V
Unless otherwise specified, all limits are ensured for TA = 25°C, V+ = 5 V, V− = −5 V, VCM = 0 V, and RL > 10 kΩ to 0 V. (1)
PARAMETER
TEST CONDITIONS
MIN
(2)
TYP
(3)
±37
LMP7701
VOS
Input Offset Voltage
Input Offset Voltage
Temperature Drift
(4)
Input Bias Current
See (4) (5)
−40°C ≤ TA ≤ 125°C
IOS
at the temperature
extremes
at the temperature
extremes
±5
±0.2
Common-Mode Rejection Ratio
−5 V ≤ VCM ≤ 5 V
LMP7702/LMP7704
at the temperature
extremes
±0.2
at the temperature
extremes
CMVR
Common-Mode Voltage Range
at the temperature
extremes
2.7 V ≤ V+ ≤ 12 V, VO = 0 V
at the temperature
extremes
(2)
(3)
(4)
(5)
CMRR ≥ 78 dB
at the temperature
extremes
pA
fA
138
88
90
CMRR ≥ 80 dB
(1)
1
±400
92
at the temperature
extremes
μV/°C
±50
dB
138
86
86
Power Supply Rejection Ratio
μV
1
40
−5 V ≤ VCM ≤ 5 V
LMP7701
PSRR
±220
±520
Input Offset Current
CMRR
UNIT
±200
±1
See
See (4) (5)
−40°C ≤ TA ≤ 85°C
IB
(2)
±500
±37
LMP7702/LMP7704
TCVOS
at the temperature
extremes
MAX
98
dB
82
−5.2
5.2
−5.2
5.2
V
Electrical Table values apply only for factory testing conditions at the temperature indicated. Factory testing conditions result in very
limited self-heating of the device such that TJ = TA. No specification of parametric performance is indicated in the electrical tables under
conditions of internal self-heating where TJ > TA.
Limits are 100% production tested at 25°C. Limits over the operating temperature range are specified through correlations using the
Statistical Quality Control (SQC) method.
Typical values represent the most likely parametric norm as determined at the time of characterization. Actual typical values may vary
over time and will also depend on the application and configuration. The typical values are not tested and are not ensured on shipped
production material.
This parameter is specified by design and/or characterization and is not tested in production.
Positive current corresponds to current flowing into the device.
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Electrical Characteristics ±5-V (continued)
Unless otherwise specified, all limits are ensured for TA = 25°C, V+ = 5 V, V− = −5 V, VCM = 0 V, and RL > 10 kΩ to 0 V.(1)
PARAMETER
TEST CONDITIONS
RL = 2 kΩ (LMP7701)
VO = −4.7 V to 4.7 V
RL = 2 kΩ
(LMP7702/LMP7704)
VO = −4.7 V to 4.7 V
AVOL
Open Loop Voltage Gain
RL = 10 kΩ (LMP7701)
VO = −4.8 V to 4.8 V
RL = 10 kΩ
(LMP7702/LMP7704)
VO = −4.8 V to 4.8 V
RL = 2 kΩ to 0 V
LMP7701
RL = 2 kΩ to 0 V
LMP7702/LMP7704
Output Voltage Swing High
RL = 10 kΩ to 0 V
LMP7701
RL = 10 kΩ to 0 V
LMP7702/LMP7704
VOUT
RL = 2 kΩ to 0 V
LMP7701
RL = 2 kΩ to 0 V
LMP7702/LMP7704
Output Voltage Swing Low
RL = 10 kΩ to 0 V
LMP7701
RL = 10 kΩ to 0 V
LMP7702/LMP7704
Sourcing VO = 0 V
VIN = 100 mV (LMP7701)
IOUT
Output Current
(6) (7)
Sourcing VO = 0 V
VIN = 100 mV
(LMP7702/LMP7704)
Sinking VO = 0 V
VIN = −100 mV
(6)
(7)
12
MIN
(2)
100
at the temperature
extremes
121
134
97
150
170
90
at the temperature
extremes
180
290
40
at the temperature
extremes
mV
+
80 from V
100
40
at the temperature
extremes
80
150
90
at the temperature
extremes
130
150
90
at the temperature
extremes
180
260
40
at the temperature
extremes
mV
–
50 from V
60
40
at the temperature
extremes
60
110
50
86
35
48
86
mA
33
50
at the temperature
extremes
dB
134
90
at the temperature
extremes
UNIT
121
at the temperature
extremes
at the temperature
extremes
(2)
98
100
at the temperature
extremes
MAX
94
100
at the temperature
extremes
(3)
98
100
at the temperature
extremes
TYP
84
35
The maximum power dissipation is a function of TJ(MAX), θJA. The maximum allowable power dissipation at any ambient temperature is
PD = (TJ(MAX) – TA)/ θJA. All numbers apply for packages soldered directly onto a PC Board.
The short circuit test is a momentary test.
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SNOSAI9I – SEPTEMBER 2005 – REVISED NOVEMBER 2015
Electrical Characteristics ±5-V (continued)
Unless otherwise specified, all limits are ensured for TA = 25°C, V+ = 5 V, V− = −5 V, VCM = 0 V, and RL > 10 kΩ to 0 V.(1)
PARAMETER
TEST CONDITIONS
MIN
(2)
TYP
(3)
0.790
LMP7701
at the temperature
extremes
Supply Current
LMP7702
at the temperature
extremes
(8)
SR
Slew Rate
GBW
Gain Bandwidth
Total Harmonic Distortion +
THD+N
Noise
at the temperature
extremes
AV = +1, VO = 9 VPP
10% to 90%
f = 1 kHz, AV = 1, RL = 10 kΩ
UNIT
1.1
2.1
mA
2.5
3.2
LMP7704
(2)
1.3
1.7
IS
MAX
4.2
5
1.1
V/μs
2.5
MHz
0.02%
en
Input Referred Voltage Noise
Density
f = 1 kHz
9
nV/√Hz
in
Input Referred Current Noise
Density
f = 100 kHz
1
fA/√Hz
(8)
The number specified is the slower of positive and negative slew rates.
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7.8 Typical Characteristics
TA = 25°C, VCM = VS/2, RL > 10 kΩ (unless otherwise noted)
20
25
VS = 3V
VS = 3V
-40°C d TA d 125°C
16
PERCENTAGE (%)
PERCENTAGE (%)
20
TA = 25°C
15
10
12
8
4
5
0
-200
0
-100
0
100
200
-3
-2
OFFSET VOLTAGE (PV)
-1
0
Figure 1. Figure 1. Offset Voltage Distribution
VS = 5V
TA = 25°C
-40°C d TA d 125°C
16
PERCENTAGE (%)
20
PERCENTAGE (%)
3
20
VS = 5V
15
10
12
8
4
5
0
-200
0
-100
0
100
OFFSET VOLTAGE (PV)
200
-3
-2
-1
0
1
2
3
TCVOS (PV/°C)
Figure 3. Offset Voltage Distribution
Figure 4. TCVOS Distribution
20
25
VS = 10V
VS = 10V
-40°C d TA d 125°C
TA = 25°C
16
PERCENTAGE (%)
20
PERCENTAGE (%)
2
Figure 2. TCVOS Distribution
25
15
10
12
8
4
5
0
-200
0
-100
0
100
OFFSET VOLTAGE (PV)
200
Figure 5. Offset Voltage Distribution
14
1
TCVOS (PV/°C)
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-3
-2
-1
0
1
2
3
TCVOS (PV/°C)
Figure 6. TCVOS Distribution
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Typical Characteristics (continued)
200
0
150
-20
VS = 3V
100
-40
VS = 3V
50
VS = 5V
CMRR (dB)
OFFSET VOLTAGE (PV)
TA = 25°C, VCM = VS/2, RL > 10 kΩ (unless otherwise noted)
0
-50
VS = 5V
VS = 10V
-80
-100
-100
VS = 10V
-120
-150
-200
-140
-40 -20
0
20
40
60
80 100 120125
10
100k
1M
FREQUENCY (Hz)
Figure 7. Offset Voltage vs Temperature
Figure 8. CMRR vs Frequency
200
200
150
150
VS = 3V
100
-40°C
50
0
25°C
-50
-100
125°C
-40°C
100
50
25°C
0
-50
125°C
-100
-150
-150
-200
2
4
6
8
10
-200
-0.5
12
0
0.5 1
1.5
2
2.5
3
3.5
VCM (V)
SUPPLY VOLTAGE (V)
Figure 10. Offset Voltage vs VCM
Figure 9. Offset Voltage vs Supply Voltage
200
200
VS = 10V
VS = 5V
150
150
OFFSET VOLTAGE (PV)
OFFSET VOLTAGE (PV)
10k
1k
100
TEMPERATURE (°C)
OFFSET VOLTAGE (PV)
OFFSET VOLTAGE (PV)
-60
100
-40°C
50
0
25°C
-50
-100
125°C
-150
100
-40°C
50
0
25°C
-50
-100
-150
125°C
-200
-200
-1
0
1
2
3
4
5
6
-1 0
1
VCM (V)
2
3
4
5
6
7
8
9 10 11
VCM (V)
Figure 11. Offset Voltage vs VCM
Figure 12. Offset Voltage vs VCM
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Typical Characteristics (continued)
TA = 25°C, VCM = VS/2, RL > 10 kΩ (unless otherwise noted)
300
200
VS = 3V
VS = 3V
200
100
IBIAS (pA)
IBIAS (fA)
100
-40°C
0
85°C
0
-100
-100
-200
125°C
25°C
-300
-200
0
0.5
1
2
1.5
2.5
0
3
0.5
1.5
1
2
3
Figure 14. Input Bias Current vs VCM
Figure 13. Input Bias Current vs VCM
300
300
VS = 5V
VS = 5V
200
200
100
100
IBIAS (pA)
IBIAS (fA)
2.5
VCM (V)
VCM (V)
-40°C
0
85°C
0
-100
-100
-200
-200
25°C
125°C
-300
-300
0
1
2
3
4
0
5
1
2
3
4
5
VCM (V)
VCM (V)
Figure 16. Input Bias Current vs VCM
Figure 15. Input Bias Current vs VCM
300
500
VS = 10V
VS = 10V
200
250
IBIAS (pA)
IBIAS (fA)
100
-40°C
0
85°C
0
-100
-250
-200
25°C
125°C
-500
-300
0
2
4
6
8
10
0
VCM (V)
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4
6
8
10
VCM (V)
Figure 17. Input Bias Current vs VCM
16
2
Figure 18. Input Bias Current vs VCM
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Typical Characteristics (continued)
TA = 25°C, VCM = VS/2, RL > 10 kΩ (unless otherwise noted)
120
1.2
VS = 10V
VS = 5V
1
SUPPLY CURRENT (mA)
100
VS = 3V
+PSRR
PSRR (dB)
80
VS = 10V
60
VS = 5V
VS = 3V
40
20
125°C
25°C
0.8
0.6
-40°C
0.4
0.2
-PSRR
0
0
10
10k
1k
100
100k
1M
2
4
FREQUENCY (Hz)
6
8
10
12
SUPPLY VOLTAGE (V)
Figure 19. PSRR vs Frequency
Figure 20. Supply Current vs Supply Voltage (Per Channel)
120
120
-40°C
100
-40°C
100
25°C
25°C
60
ISOURCE (mA)
ISINK (mA)
80
125°C
40
20
125°C
60
40
20
0
0
2
4
6
8
10
12
2
4
6
8
10
12
SUPPLY VOLTAGE (V)
SUPPLY VOLTAGE (V)
Figure 21. Sinking Current vs Supply Voltage
Figure 22. Sourcing Current vs Supply Voltage
+
1.5
V
TA = -40°C, 25°C, 125C
(V ) -1
VIN = 2 VPP
(V ) -2
|
|
3V
2
SLEW RATE (V/Ps)
1.3
+
RL = 10 k:
FALLING EDGE
1.2
CL = 10 pF
1.1
1
0.9
RISING EDGE
0.8
0.7
1
VS = 3V, 5V, 10V
0
AV = +1
1.4
+
VOUT FROM RAIL (V)
80
0.6
0.5
0
20
40
60
80
100
2
OUTPUT CURRENT (mA)
Figure 23. Output Voltage vs Output Current
4
6
8
10
12
SUPPLY VOLTAGE (V)
Figure 24. Slew Rate vs Supply Voltage
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Typical Characteristics (continued)
TA = 25°C, VCM = VS/2, RL > 10 kΩ (unless otherwise noted)
100
225
GAIN
80
60
180
80
135
60
90
40
CL = 20 pF, 50 pF, 100 pF 180
RL = 10 k:
VS = 10V
20
125°C
45
125°C
0
0
25°C
-20 VS = 5V
C = 20 pF
-40 L
RL = 10 k:
-60
100
10k
1k
-40°C
-45
-90
GAIN (dB)
25°C
PHASE
PHASE (°)
GAIN (dB)
-40°C
40
CL = 20 pF
PHASE
20
0
-45
-20
VS = 3V
-40
100k
1M
-135
10M 100M
-60
100
1k
-90
10k
100k
1M
FREQUENCY (Hz)
VS = 5V
f = 10 kHz
VS = 5V
f = 10 kHz
AV = +1
AV = +1
VIN = 2 VPP
VIN = 100 mVPP
RL = 10 k:
RL = 10 k:
CL = 10 pF
CL = 10 pF
10 Ps/DIV
10 Ps/DIV
Figure 28. Small Signal Step Response
200 mV/DIV
Figure 27. Large Signal Step Response
VS = 5V
f = 10 kHz
VS = 5V
f = 10 kHz
AV = +10
AV = +10
VIN = 400 mVPP
VIN = 100 mVPP
RL = 10 k:
RL = 10 k:
CL = 10 pF
CL = 10 pF
10 Ps/DIV
10 Ps/DIV
Figure 29. Large Signal Step Response
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-135
10M 100M
Figure 26. Open-Loop Frequency Response
20 mV/DIV
500 mV/DIV
90
45
0
FREQUENCY (Hz)
1V/DIV
135
CL = 100 pF
Figure 25. Open-Loop Frequency Response
18
225
VS = 3V, 5V, 10V
GAIN
PHASE (°)
100
Figure 30. Small Signal Step Response
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Typical Characteristics (continued)
TA = 25°C, VCM = VS/2, RL > 10 kΩ (unless otherwise noted)
150
VS = 10V
VS = 5V
140
100
OPEN LOOP GAIN (dB)
INPUT REFERRED VOLTAGE NOISE
(nV/ Hz)
120
80
VS = 3V
60
VS = 5V
40
130
120
RL = 10 k:
110
VS = 3V
100
90
80
20
0
1
10
RL = 2 k:
70
VS = 10V
100
1k
10k
60
500
100k
400
300
200
100
0
FREQUENCY (Hz)
OUTPUT SWING FROM RAIL (mV)
Figure 31. Input Voltage Noise vs Frequency
Figure 32. Open Loop Gain vs Output Voltage Swing
50
50
RL = 10 k:
RL = 10 k:
25°C
40
125°C
30
VOUT FROM RAIL (mV)
VOUT FROM RAIL (mV)
40
-40°C
20
10
0
2
4
6
8
10
30
25°C
125°C
20
10
0
12
-40°C
2
4
6
8
10
12
SUPPLY VOLTAGE (V)
SUPPLY VOLTAGE (V)
Figure 33. Output Swing High vs Supply Voltage
Figure 34. Output Swing Low vs Supply Voltage
100
100
RL = 2 k:
25°C
25°C
80
80
125°C
VOUT FROM RAIL (mV)
VOUT FROM RAIL (mV)
RL = 2 k:
60
-40°C
40
20
0
2
4
6
8
10
12
125°C
60
-40°C
40
20
0
2
4
6
8
10
12
SUPPLY VOLTAGE (V)
SUPPLY VOLTAGE (V)
Figure 35. Output Swing High vs Supply Voltage
Figure 36. Output Swing Low vs Supply Voltage
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Typical Characteristics (continued)
TA = 25°C, VCM = VS/2, RL > 10 kΩ (unless otherwise noted)
1
1
VS = 5V
f = 1 kHz
VS = 5V
VO = 4.5 VPP
RL = 100 k:
RL = 100 k:
0.1
THD+N (%)
0.1
AV = +10
THD+N (%)
AV = +10
0.01
0.01
AV = +1
AV = +1
0.001
10
100
1k
10k
0.001
0.001
100k
0.01
0.1
1
10
FREQUENCY (Hz)
VOUT (V)
Figure 37. THD+N vs Frequency
Figure 38. THD+N vs Output Voltage
140
CROSSTALK REJECTION (dB)
VS = 12V
120
VS = 5V
VS = 3V
100
80
60
40
100
1k
10k
100k
1M
FREQUENCY (Hz)
Figure 39. Crosstalk Rejection Ratio vs Frequency (LMP7702/LMP7704)
20
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8 Detailed Description
8.1 Overview
The LMP770x are single, dual, and quad low offset voltage, rail-to-rail input and output precision amplifiers each
with a CMOS input stage and wide supply voltage range of 2.7V to 12V. The LMP770x have a very low input
bias current of only ±200 fA at room temperature.
The wide supply voltage range of 2.7V to 12V over the extensive temperature range of −40°C to 125°C makes
the LMP770x excellent choices for low voltage precision applications with extensive temperature requirements.
The LMP770x have only ±37 μV of typical input referred offset voltage and this offset is specified to be less than
±500 μV for the single and ±520 μV for the dual and quad, over temperature. This minimal offset voltage allows
more accurate signal detection and amplification in precision applications.
The low input bias current of only ±200 fA along with the low input referred voltage noise of 9 nV/√Hz gives the
LMP770x superiority for use in sensor applications. Lower levels of noise from the LMP770x mean of better
signal fidelity and a higher signal-to-noise ratio.
Texas Instruments is heavily committed to precision amplifiers and the market segment they serve. Technical
support and extensive characterization data is available for sensitive applications or applications with a
constrained error budget.
The LMP7701 is offered in the space saving 5-Pin SOT-23 and 8-Pin SOIC package. The LMP7702 comes in
the 8-Pin SOIC and 8-Pin VSSOP package. The LMP7704 is offered in the 14-Pin SOIC and 14-Pin TSSOP
package. These small packages are ideal solutions for area constrained PC boards and portable electronics.
8.2 Functional Block Diagram
OUT
-
V
5
1
2
+
IN+
+
V
3
4
IN-
Figure 40. Functional Block Diagram (LMP7701)
8.3 Feature Description
8.3.1 Capacitive Load
The LMP770x can each be connected as a non-inverting unity gain follower. This configuration is the most
sensitive to capacitive loading.
The combination of a capacitive load placed on the output of an amplifier along with the amplifier's output
impedance creates a phase lag which in turn reduces the phase margin of the amplifier. If the phase margin is
significantly reduced, the response will be either underdamped or it will oscillate.
To drive heavier capacitive loads, an isolation resistor, RISO, in Figure 41 should be used. By using this isolation
resistor, the capacitive load is isolated from the amplifier's output, and hence, the pole caused by CL is no longer
in the feedback loop. The larger the value of RISO, the more stable the output voltage will be. If values of RISO are
sufficiently large, the feedback loop will be stable, independent of the value of CL. However, larger values of RISO
result in reduced output swing and reduced output current drive.
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Feature Description (continued)
Figure 41. Isolating Capacitive Load
8.3.2 Input Capacitance
CMOS input stages inherently have low input bias current and higher input referred voltage noise. The LMP770x
enhance this performance by having the low input bias current of only ±200 fA, as well as, a very low input
referred voltage noise of 9 nV/√Hz. To achieve this a larger input stage has been used. This larger input stage
increases the input capacitance of the LMP770x. The typical value of this input capacitance, CIN, for the
LMP770x is 25 pF. The input capacitance will interact with other impedances such as gain and feedback
resistors, which are seen on the inputs of the amplifier, to form a pole. This pole will have little or no effect on the
output of the amplifier at low frequencies and DC conditions, but will play a bigger role as the frequency
increases. At higher frequencies, the presence of this pole will decrease phase margin and will also cause gain
peaking. To compensate for the input capacitance, care must be taken in choosing the feedback resistors. In
addition to being selective in picking values for the feedback resistor, a capacitor can be added to the feedback
path to increase stability.
The DC gain of the circuit shown in Figure 42 is simply –R2/R1.
CF
R2
R1
+
VIN
CIN
+
+
-
-
AV = -
VOUT
VIN
=-
VOUT
R2
R1
Figure 42. Compensating for Input Capacitance
For the time being, ignore CF. The AC gain of the circuit in Figure 42 can be calculated as follows:
VOUT
-R2/R1
(s) =
VIN
s2
s
+
1+
§ A0 R 1
§ A0
¨
¨C R
+
R
R
2
© 1
© IN 2
(1)
§
¨
©
§
¨
©
This equation is rearranged to find the location of the two poles:
22
1
1
+
r
R1
R2
§1
1
+
¨
R2
© R1
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§
¨
©
-1
P1,2 =
2CIN
2
-
4 A0CIN
R2
(2)
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Feature Description (continued)
As shown in Equation 2, as values of R1 and R2 are increased, the magnitude of the poles is reduced, which in
turn decreases the bandwidth of the amplifier. Whenever possible, it is best to choose smaller feedback resistors.
Figure 43 shows the effect of the feedback resistor on the bandwidth of the LMP770x.
2
VS = 5V
CF = 0 pF
NORMALIZED GAIN (dB)
0
AV = -1
-2
R1 = R2 = 100 k:
-4
R1 = R2 = 30 k:
-6
R1 = R2 = 10 k:
-8
R1 = R2 = 1 k:
-10
1k
10k
100k
1M
10M
FREQUENCY (Hz)
Figure 43. Closed-Loop Gain vs Frequency
Equation 2 has two poles. In most cases, it is the presence of pairs of poles that causes gain peaking. To
eliminate this effect, the poles should be placed in Butterworth position, because poles in Butterworth position do
not cause gain peaking. To achieve a Butterworth pair, the quantity under the square root in Equation 2 should
be set to equal −1. Using this fact and the relation between R1 and R2, R2 = −AV R1, the optimum value for R1
can be found. This is shown in Equation 3. If R1 is chosen to be larger than this optimum value, gain peaking will
occur.
R1 <
(1 - AV)
2
2A0AVCIN
(3)
In Figure 42, CF is added to compensate for input capacitance and to increase stability. Additionally, CF reduces
or eliminates the gain peaking that can be caused by having a larger feedback resistor. Figure 44 shows how CF
reduces gain peaking.
2
CF = 0 pF
NORMALIZED GAIN (dB)
0
CF = 1 pF
-2
CF = 5 pF
-4
CF = 3 pF
-6
VS = 5V
-8
R1 = R2 = 100 k:
AV = -1
-10
1k
10k
100k
1M
10M
FREQUENCY (Hz)
Figure 44. Closed-Loop Gain vs Frequency With Compensation
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Feature Description (continued)
8.3.3 Diodes Between the Inputs
The LMP770x have a set of anti-parallel diodes between the input pins, as shown in Figure 45. These diodes are
present to protect the input stage of the amplifier. At the same time, they limit the amount of differential input
voltage that is allowed on the input pins. A differential signal larger than one diode voltage drop might damage
the diodes. The differential signal between the inputs needs to be limited to ±300 mV or the input current needs
to be limited to ±10 mA.
V
V
D1
ESD
IN
+
+
R1
ESD
R2
+
IN
ESD
ESD
D2
V
-
-
-
V
Figure 45. Input of LMP7701
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8.4 Device Functional Modes
8.4.1 Precision Current Source
The LMP770x can each be used as a precision current source in many different applications. Figure 46 shows a
typical precision current source. This circuit implements a precision voltage controlled current source. Amplifier
A1 is a differential amplifier that uses the voltage drop across RS as the feedback signal. Amplifier A2 is a buffer
that eliminates the error current from the load side of the RS resistor that would flow in the feedback resistor if it
were connected to the load side of the RS resistor. In general, the circuit is stable as long as the closed loop
bandwidth of amplifier A2 is greater then the closed loop bandwidth of amplifier A1. If A1 and A2 are the same
type of amplifiers, then the feedback around A1 will reduce its bandwidth compared to A2.
R
R
V1
V
+
-
RS
I = (V2 ± V1)
A1
RS
+
V
-
V
+
Z
LOAD
-
R
R
V2
A2
+
-
V
Figure 46. Precision Current Source
The equation for output current can be derived as shown in Equation 4.
V2R
R+R
+
(V0 ± IRS)R
R+R
=
V1R
R+R
+
V0R
R+R
(4)
Solving for the current I results in the Equation 5.
V2 ± V1
I=
R
S
(5)
9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
9.1.1 Low Input Voltage Noise
The LMP770x have the very low input voltage noise of 9 nV/√Hz. This input voltage noise can be further reduced
by placing N amplifiers in parallel as shown in Figure 47. The total voltage noise on the output of this circuit is
divided by the square root of the number of amplifiers used in this parallel combination. This is because each
individual amplifier acts as an independent noise source, and the average noise of independent sources is the
quadrature sum of the independent sources divided by the number of sources. For N identical amplifiers, this
means:
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Application Information (continued)
REDUCED INPUT VOLTAGE NOISE =
1
N
en1+en2+
=
1
N
Nen =
=
1
2
2
2
2
+enN
N
en
N
en
N
(6)
Figure 47 shows a schematic of this input voltage noise reduction circuit. Typical resistor values are:
RG = 10Ω, RF = 1 kΩ, and RO = 1 kΩ.
+
V
+
-
VIN
VOUT
-
RG
RO
V
RF
+
V
+
RG
V
-
RO
RF
+
V
+
RG
V
-
RO
RF
+
V
+
RG
V
-
RO
RF
Figure 47. Noise Reduction Circuit
9.1.2 Total Noise Contribution
The LMP770x have very low input bias current, very low input current noise, and very low input voltage noise. As
a result, these amplifiers are ideal choices for circuits with high impedance sensor applications.
Figure 48 shows the typical input noise of the LMP770x as a function of source resistance where:
en denotes the input referred voltage noise
ei is the voltage drop across source resistance due to input referred current noise or ei = RS * in
et shows the thermal noise of the source resistance
eni shows the total noise on the input.
Where:
eni =
26
2
2
2
en + ei + et
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Application Information (continued)
The input current noise of the LMP770x is so low that it will not become the dominant factor in the total noise
unless source resistance exceeds 300 MΩ, which is an unrealistically high value.
As is evident in Figure 48, at lower RS values, total noise is dominated by the amplifier's input voltage noise.
Once RS is larger than a few kilo-Ohms, then the dominant noise factor becomes the thermal noise of RS. As
mentioned before, the current noise will not be the dominant noise factor for any practical application.
VOLTAGE NOISE DENSITY (nV/ Hz)
1000
100
eni
en
10
et
ei
1
0.1
10
10k
1k
100
1M
100k
10M
RS (:)
Figure 48. Total Input Noise
9.2 Typical Application
+
V
pH ELECTRODE TEMPERATURE
0.01 PF
0.01 PF
0.1 PF
0.1 PF
10 PF
10 PF
+
75:
V
1 PF
+
1
A1
R2
10 k:
R1
10 k:
-
V+
+
V
VD
+
V
R3
10 k:
R4
10 k:
VA
+
CH0
-
VOUT
A2
CH1
+
RT
+
V
VOFFSET = 0.5012V
LM35
-V+
2
3
LM4140A
6
R5
10 k:
-
ADC12034
V
R6
3.3 k:
1,4,7,8
AGND
VREFVREF+
DGND
pH ELECTRODE
Figure 49. pH Measurement Circuit
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Typical Application (continued)
9.2.1 Design Requirements
pH electrodes are very high impedance sensors. As their name indicates, they are used to measure the pH of a
solution. They usually do this by generating an output voltage which is proportional to the pH of the solution. pH
electrodes are calibrated so that they have zero output for a neutral solution, pH = 7, and positive and negative
voltages for acidic or alkaline solutions. This means that the output of a pH electrode is bipolar and must be level
shifted to be used in a single supply system. The rate of change of this voltage is usually shown in mV/pH and is
different for different pH sensors. Temperature is also an important factor in a pH electrode reading. The output
voltage of the senor will change with temperature.
9.2.2 Detailed Design Procedure
Many sensors have high source impedances that may range up to 10 MΩ. The output signal of sensors often
needs to be amplified or otherwise conditioned by means of an amplifier. The input bias current of this amplifier
can load the sensor's output and cause a voltage drop across the source resistance as shown in Figure 50,
where VIN+ = VS – IBIAS*RS
The last term, IBIAS*RS, shows the voltage drop across RS. To prevent errors introduced to the system due to this
voltage, an op amp with very low input bias current must be used with high impedance sensors. This is to keep
the error contribution by IBIAS*RS less than the input voltage noise of the amplifier, so that it will not become the
dominant noise factor.
SENSOR
+
V
IB
RS
VIN+
+
VS
+
-
-
V
Figure 50. Noise Due to IBIAS
Figure 51 shows a typical output voltage spectrum of a pH electrode. The exact values of output voltage will be
different for different sensors. In this example, the pH electrode has an output voltage of 59.15 mV/pH at 25°C.
ACID
2
0
+414 mV
BASE
4
7
10
+177 mV
0 mV
-177 mV
12
14 pH
-414 mV
Figure 51. Output Voltage of a pH Electrode
The temperature dependence of a typical pH electrode is shown in Figure 52. As is evident, the output voltage
changes with changes in temperature.
The schematic shown in Figure 49 is a typical circuit which can be used for pH measurement. The LM35 is a
precision integrated circuit temperature sensor. This sensor is differentiated from similar products because it has
an output voltage linearly proportional to Celcius measurement, without converting the temperature to Kelvin. The
LM35 is used to measure the temperature of the solution and feeds this reading to the Analog to Digital
Converter, ADC. This information is used by the ADC to calculate the temperature effects on the pH readings.
The LM35 needs to have a resistor, RT in Figure 49, to –V+ to be able to read temperatures less than 0°C. RT is
not needed if temperatures are not expected to be less than zero.
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Typical Application (continued)
The output of pH electrodes is usually large enough that it does not require much amplification; however, due to
the very high impedance, the output of a pH electrode needs to be buffered before it can go to an ADC. Because
most ADCs are operated on single supply, the output of the pH electrode also needs to be level shifted. Amplifier
A1 buffers the output of the pH electrode with a moderate gain of +2, while A2 provides the level shifting. VOUT at
the output of A2 is given by: VOUT = −2VpH + 1.024V.
The LM4140A is a precision, low noise, voltage reference used to provide the level shift needed. The ADC used
in this application is the ADC12032 which is a 12-bit, 2 channel converter with multiplexers on the inputs and a
serial output. The 12-bit ADC enables users to measure pH with an accuracy of 0.003 of a pH unit. Adequate
power supply bypassing and grounding is extremely important for ADCs. Recommended bypass capacitors are
shown in Figure 49. It is common to share power supplies between different components in a circuit. To minimize
the effects of power supply ripples caused by other components, the op amps must have bypass capacitors on
the supply pins. Using the same value capacitors as those used with the ADC are ideal. The combination of
these three values of capacitors ensures that AC noise present on the power supply line is grounded and does
not interfere with the amplifiers' signal.
9.2.3 Application Curves
mV
600
10°C (74.04 mV/pH)
500
400
25°C (59.15 mV/pH)
300
200
100
2
4
12
10
8
14
pH
0
-100
1
3
5
7
9
11
13
-200
-300
-400
-500
0°C (54.20 mV/pH)
-600
Figure 52. Temperature Dependence of a pH Electrode
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10 Power Supply Recommendations
For proper operation, the power supplies must be decoupled. For supply decoupling, TI recommends placing
10-nF to 1-µF capacitors as close as possible to the operational-amplifier power supply pins. For single supply
configurations, place a capacitor between the V+ and V– supply pins. For dual supply configurations, place one
capacitor between V+ and ground, and place a second capacitor between V– and ground. Bypass capacitors
must have a low ESR of less than 0.1 Ω.
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11 Layout
11.1 Layout Guidelines
Take care to minimize the loop area formed by the bypass capacitor connection between supply pins and
ground. A ground plane underneath the device is recommended; any bypass components to ground should have
a nearby via to the ground plane. The optimum bypass capacitor placement is closest to the corresponding
supply pin. Use of thicker traces from the bypass capacitors to the corresponding supply pins will lower the
power supply inductance and provide a more stable power supply.
The feedback components should be placed as close to the device as possible to minimize stray parasitics.
11.2 Layout Example
+3.3V
+3
+3.3V
GND
.3
V
+3.3V
2
GND
+3
G
ND
.3
V
1
+3.3V
1
VOUT
5
+3.3V
2
GND
VOUT
4
V–
3
V+
1
V+
2
VOUT
2
VOUT
1
V–
1
V–
V+
2
+3.3V
+3.3V
V+
2
V+
1
GND
GND GND
1
GND
2
V–
Figure 53. LMP7701 Example Layout
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12 Device and Documentation Support
12.1 Related Links
The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to sample or buy.
Table 1. Related Links
PARTS
PRODUCT FOLDER
SAMPLE AND BUY
TECHNICAL
DOCUMENTS
TOOLS AND
SOFTWARE
SUPPORT AND
COMMUNITY
LMP7701
Click here
Click here
Click here
Click here
Click here
LMP7702
Click here
Click here
Click here
Click here
Click here
LMP7704
Click here
Click here
Click here
Click here
Click here
12.2 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
12.3 Trademarks
LMP, E2E are trademarks of Texas Instruments.
All other trademarks are the property of their respective owners.
12.4 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
12.5 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
www.ti.com
28-Nov-2022
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
Samples
(4/5)
(6)
LMP7701MA/NOPB
ACTIVE
SOIC
D
8
95
RoHS & Green
SN
Level-1-260C-UNLIM
LMP77
01MA
Samples
LMP7701MAX/NOPB
ACTIVE
SOIC
D
8
2500
RoHS & Green
SN
Level-1-260C-UNLIM
LMP77
01MA
Samples
LMP7701MF
NRND
SOT-23
DBV
5
1000
Non-RoHS
& Green
Call TI
Level-1-260C-UNLIM
-40 to 125
AC2A
LMP7701MF/NOPB
ACTIVE
SOT-23
DBV
5
1000
RoHS & Green
SN
Level-1-260C-UNLIM
-40 to 125
AC2A
LMP7701MFX
NRND
SOT-23
DBV
5
3000
Non-RoHS
& Green
Call TI
Level-1-260C-UNLIM
-40 to 125
AC2A
LMP7701MFX/NOPB
ACTIVE
SOT-23
DBV
5
3000
RoHS & Green
SN
Level-1-260C-UNLIM
-40 to 125
AC2A
Samples
LMP7702MA/NOPB
ACTIVE
SOIC
D
8
95
RoHS & Green
SN
Level-1-260C-UNLIM
LMP77
02MA
Samples
LMP7702MAX/NOPB
ACTIVE
SOIC
D
8
2500
RoHS & Green
SN
Level-1-260C-UNLIM
LMP77
02MA
Samples
LMP7702MM
NRND
VSSOP
DGK
8
1000
Non-RoHS
& Green
Call TI
Level-1-260C-UNLIM
-40 to 125
AA3A
LMP7702MM/NOPB
ACTIVE
VSSOP
DGK
8
1000
RoHS & Green
SN
Level-1-260C-UNLIM
-40 to 125
AA3A
Samples
LMP7702MMX/NOPB
ACTIVE
VSSOP
DGK
8
3500
RoHS & Green
SN
Level-1-260C-UNLIM
-40 to 125
AA3A
Samples
LMP7704MA/NOPB
ACTIVE
SOIC
D
14
55
RoHS & Green
SN
Level-1-260C-UNLIM
LMP7704
MA
Samples
LMP7704MAX/NOPB
ACTIVE
SOIC
D
14
2500
RoHS & Green
SN
Level-1-260C-UNLIM
LMP7704
MA
Samples
LMP7704MT
NRND
TSSOP
PW
14
94
Non-RoHS
& Green
Call TI
Level-1-260C-UNLIM
-40 to 125
LMP77
04MT
LMP7704MT/NOPB
ACTIVE
TSSOP
PW
14
94
RoHS & Green
SN
Level-1-260C-UNLIM
-40 to 125
LMP77
04MT
Samples
LMP7704MTX/NOPB
ACTIVE
TSSOP
PW
14
2500
RoHS & Green
SN
Level-1-260C-UNLIM
-40 to 125
LMP77
04MT
Samples
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
28-Nov-2022
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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