LMR62421
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LMR62421 SIMPLE SWITCHER® 24Vout, 2.1A Step-Up Voltage Regulator in SOT-23
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FEATURES
DESCRIPTION
•
•
•
•
•
•
•
•
•
The LMR62421 is an easy-to-use, space-efficient
2.1A low-side switch regulator ideal for Boost and
SEPIC DC-DC regulation. It provides all the active
functions to provide local DC/DC conversion with fasttransient response and accurate regulation in the
smallest PCB area. Switching frequency is internally
set to 1.6 MHz, allowing the use of extremely small
surface mount inductor and chip capacitors while
providing efficiencies near 90%. Current-mode control
and internal compensation provide ease-of-use,
minimal component count, and high-performance
regulation over a wide range of operating conditions.
External shutdown features an ultra-low standby
current of 80 nA ideal for portable applications. Tiny
5-pin SOT-23 and 6-pin WSON packages provide
space-savings. Additional features include internal
soft-start, circuitry to reduce inrush current, pulse-bypulse current limit, and thermal shutdown.
1
2
•
Input Voltage Range of 2.7V to 5.5V
Output Voltage up to 24V
Switch Current up to 2.1A
1.6 MHz Switching Frequency
Low Shutdown Iq, 80 nA
Cycle-by-Cycle Current Limiting
Internally Compensated
Internal Soft-Start
5-Pin SOT-23 (2.92 x 2.84 x 1mm) and 6-Pin
WSON (3 x 3 x 0.8 mm) Packaging
Fully Enabled for WEBENCH® Power Designer
PERFORMANCE BENEFITS
•
•
Extremely Easy to Use
Tiny Overall Solution Reduces System Cost
APPLICATIONS
•
•
•
•
•
Boost / SEPIC Conversions from 3.3V, 5V Rails
Space Constrained Applications
Embedded Systems
LCD Displays
LED Applications
System Performance
Efficiency vs Load Current
VOUT = 20V
Efficiency vs Load Current
VOUT = 12V
1
2
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
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LMR62421
SNVS734B – OCTOBER 2011 – REVISED APRIL 2013
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Typical Application
VOUT
VIN
L1
D1
R2
R3
4
C3
3
C2
2
5
R1
1
C1
GND
Connection Diagrams
SW 1
5
VIN
4
EN
PGND
1
6
SW
VIN
2
5
AGND
EN
3
4
FB
GND 2
FB
3
Figure 1. 5-Pin SOT-23 (Top View)
See DBV Package
2
Figure 2. 6-Pin WSON (Top View)
See NGG0006A Package
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PIN DESCRIPTIONS - 5-Pin SOT-23
Pin
Name
Function
1
SW
2
GND
Switch node. Connect to the inductor, output diode.
3
FB
Feedback pin. Connect FB to external resistor divider to set output voltage.
4
EN
Shutdown control input. Logic high enables operation. Do not allow this pin to float or be greater than VIN + 0.3V.
5
VIN
Supply voltage for power stage, and input supply voltage.
Signal and power ground pin. Place the bottom resistor of the feedback network as close as possible to this pin.
PIN DESCRIPTIONS - 6-Pin WSON
Pin
Name
Function
1
PGND
Power ground pin. Place PGND and output capacitor GND close together.
2
VIN
Supply voltage for power stage, and input supply voltage.
3
EN
Shutdown control input. Logic high enables operation. Do not allow this pin to float or be greater than VIN + 0.3V.
4
FB
Feedback pin. Connect FB to external resistor divider to set output voltage.
5
AGND
6
SW
DAP
GND
Signal ground pin. Place the bottom resistor of the feedback network as close as possible to this pin & pin 4.
Switch node. Connect to the inductor, output diode.
Signal & Power ground. Connect to pin 1 & pin 5 on top layer. Place 4-6 vias from DAP to bottom layer GND plane.
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These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
Absolute Maximum Ratings (1) (2)
VIN
-0.5V to 7V
SW Voltage
-0.5V to 26.5V
FB Voltage
-0.5V to 3.0V
EN Voltage
-0.5V to VIN + 0.3V
ESD Susceptibility (3)
2kV
Junction Temperature (4)
150°C
Storage Temp. Range
-65°C to 150°C
For soldering specifications: SNOA549
(1)
(2)
(3)
(4)
Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for
which the device is intended to be functional, but specific performance is not ensured. For specified specifications and the test
conditions, see Electrical Characteristics.
If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/ Distributors for availability and
specifications.
The human body model is a 100 pF capacitor discharged through a 1.5 kΩ resistor into each pin.
Thermal shutdown will occur if the junction temperature exceeds the maximum junction temperature of the device.
Operating Ratings (1)
VIN
2.7V to 5.5V
VEN (2)
0V to VIN
−40°C to +125°C
Junction Temperature Range
(1)
(2)
4
Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for
which the device is intended to be functional, but specific performance is not ensured. For specified specifications and the test
conditions, see Electrical Characteristics.
Do not allow this pin to float or be greater than VIN +0.3V.
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Electrical Characteristics (1) (2)
Limits in standard type are for TJ = 25°C only; limits in boldface type apply over the junction temperature range of
(TJ = -40°C to 125°C). Minimum and Maximum limits are ensured through test, design, or statistical correlation. Typical values
represent the most likely parametric norm at TJ = 25°C, and are provided for reference purposes only. VIN = 5V unless
otherwise indicated under the Conditions column.
Symbol
VFB
ΔVFB/VIN
Feedback Voltage Line Regulation
Feedback Input Bias Current
Conditions
Min
Typ
Max
−40°C ≤ to TJ ≤ +125°C (SOT-23)
1.230
1.255
1.280
0°C ≤ to TJ ≤ +125°C (SOT-23)
1.236
1.255
1.274
−40°C ≤ to TJ ≤ +125°C (WSON)
1.225
1.255
1.285
−0°C ≤ to TJ ≤ +125°C (WSON)
1.229
1.255
1.281
VIN = 2.7V to 5.5V
0.06
2000
kHz
1200
1600
Maximum Duty Cycle
88
96
DMIN
Minimum Duty Cycle
ICL
Switch Current Limit
Soft Start
UVLO
%/V
µA
Switching Frequency
SS
%
5
%
SOT-23
170
330
WSON
190
350
2.1
Quiescent Current (switching)
A
4
ms
7.0
VEN = 0V
80
Undervoltage Lockout
VIN Rising
2.3
1.7
mΩ
3
Quiescent Current (shutdown)
VIN Falling
V
1
FSW
Switch On Resistance
Units
0.1
DMAX
IQ
11
mA
nA
2.65
V
1.9
Shutdown Threshold Voltage
See
(3)
Enable Threshold Voltage
See
(3)
I-SW
Switch Leakage
VSW = 24V
1.0
µA
I-EN
Enable Pin Current
Sink/Source
100
nA
θJA
Junction to Ambient
0 LFPM Air Flow (4)
WSON
80
SOT-23
118
θJC
Junction to Case
WSON
18
SOT-23
60
TSD
Thermal Shutdown Temperature (5)
160
Thermal Shutdown Hysteresis
10
VEN_TH
(2)
(3)
(4)
(5)
Feedback Voltage
IFB
RDS(ON)
(1)
Parameter
0.4
1.8
V
°C/W
°C/W
°C
Min and Max limits are 100% production tested at 25°C. Limits over the operating temperature range are ensured through correlation
using Statistical Quality Control (SQC) methods. Limits are used to calculate Average Outgoing Quality Level (AOQL).
Typical numbers are at 25°C and represent the most likely parametric norm.
Do not allow this pin to float or be greater than VIN +0.3V.
Applies for packages soldered directly onto a 3” x 3” PC board with 2oz. copper on 4 layers in still air.
Thermal shutdown will occur if the junction temperature exceeds the maximum junction temperature of the device.
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Typical Performance Characteristics
6
Current Limit vs Temperature
FB Pin Voltage vs Temperature
Figure 3.
Figure 4.
Oscillator Frequency vs Temperature
Typical Maximum Output Current vs VIN
Figure 5.
Figure 6.
RDSON vs Temperature
Efficiency vs Load Current, Vo = 20V
Figure 7.
Figure 8.
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Typical Performance Characteristics (continued)
Efficiency vs Load Current, Vo = 12V
Output Voltage Load Regulation
Figure 9.
Figure 10.
Output Voltage Line Regulation
Figure 11.
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Simplified Internal Block Diagram
EN
VIN
ThermalSHDN
Control Logic
+
UVLO = 2.3V
Oscillator
Corrective - Ramp
SW
cv
S
R
R
Q
1.6 MHz
+
+
-
FB
VREF = 1.255V
NMOS
Internal
Compensation
ILIMIT
ISENSE-AMP
Soft-Start
+
-
GND
Figure 12. Simplified Block Diagram
8
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APPLICATION INFORMATION
THEORY OF OPERATION
The following operating description of the LMR62421 will refer to the Simplified Block Diagram (Figure 12) the
simplified schematic (Figure 13), and its associated waveforms (Figure 14). The LMR62421 supplies a regulated
output voltage by switching the internal NMOS control switch at constant frequency and variable duty cycle. A
switching cycle begins at the falling edge of the reset pulse generated by the internal oscillator. When this pulse
goes low, the output control logic turns on the internal NMOS control switch. During this on-time, the SW pin
voltage (VSW) decreases to approximately GND, and the inductor current (IL) increases with a linear slope. IL is
measured by the current sense amplifier, which generates an output proportional to the switch current. The
sensed signal is summed with the regulator’s corrective ramp and compared to the error amplifier’s output, which
is proportional to the difference between the feedback voltage and VREF. When the PWM comparator output goes
high, the output switch turns off until the next switching cycle begins. During the switch off-time, inductor current
discharges through diode D1, which forces the SW pin to swing to the output voltage plus the forward voltage
(VD) of the diode. The regulator loop adjusts the duty cycle (D) to maintain a constant output voltage .
I L (t)
+
VL (t)
-
D1
L1
I C (t)
Control
+
VIN
+
Q1
VSW( t )
C1
VO(t)
-
Figure 13. Simplified Schematic
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VO + VD
Vsw (t)
t
VIN
VL(t)
t
VIN - VOUT - VD
I L (t)
iL
t
I DIODE (t)
t
( iL
- - i OUT
)
I Capacitor (t)
t
- i OUT
'v
VOUT (t)
DTS
TS
Figure 14. Typical Waveforms
CURRENT LIMIT
The LMR62421 uses cycle-by-cycle current limiting to protect the internal NMOS switch. It is important to note
that this current limit will not protect the output from excessive current during an output short circuit. The input
supply is connected to the output by the series connection of an inductor and a diode. If a short circuit is placed
on the output, excessive current can damage both the inductor and diode.
Design Guide
ENABLE PIN / SHUTDOWN MODE
The LMR62421 has a shutdown mode that is controlled by the Enable pin (EN). When a logic low voltage is
applied to EN, the part is in shutdown mode and its quiescent current drops to typically 80 nA. Switch leakage
adds up to another 1 µA from the input supply. The voltage at this pin should never exceed VIN + 0.3V.
THERMAL SHUTDOWN
Thermal shutdown limits total power dissipation by turning off the output switch when the IC junction temperature
exceeds 160°C. After thermal shutdown occurs, the output switch doesn’t turn on until the junction temperature
drops to approximately 150°C.
10
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SOFT-START
This function forces VOUT to increase at a controlled rate during start up. During soft-start, the error amplifier’s
reference voltage ramps to its nominal value of 1.255V in approximately 4.0ms. This forces the regulator output
to ramp up in a more linear and controlled fashion, which helps reduce inrush current.
INDUCTOR SELECTION
The Duty Cycle (D) can be approximated quickly using the ratio of output voltage (VO) to input voltage (VIN):
VOUT
VIN
§1 · 1
=¨
¸= c
©1 - D¹ D
(1)
Therefore:
D=
VOUT - VIN
VOUT
(2)
Power losses due to the diode (D1) forward voltage drop, the voltage drop across the internal NMOS switch, the
voltage drop across the inductor resistance (RDCR) and switching losses must be included to calculate a more
accurate duty cycle (See Calculating Efficiency and Junction Temperature for a detailed explanation). A more
accurate formula for calculating the conversion ratio is:
VOUT
K
= c
D
VIN
where
•
η equals the efficiency of the LMR62421 application.
(3)
The inductor value determines the input ripple current. Lower inductor values decrease the size of the inductor,
but increase the input ripple current. An increase in the inductor value will decrease the input ripple current.
'i L
I L (t)
iL
VIN - VOUT
VIN
L
DTS
L
TS
t
Figure 15. Inductor Current
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2'iL § VIN ·
=¨
¸
DTS © L ¹
§ VIN ·
¸¸ x DTS
ÂiL = ¨¨
© 2L ¹
(4)
A good design practice is to design the inductor to produce 10% to 30% ripple of maximum load. From the
previous equations, the inductor value is then obtained.
§ VIN ·
¸ x DTS
L =¨
©2 x 'iL¹
where
•
1/TS = FSW = switching frequency
(5)
One must also ensure that the minimum current limit (2.1A) is not exceeded, so the peak current in the inductor
must be calculated. The peak current (ILPK ) in the inductor is calculated by:
ILpk = IIN + ΔIL
(6)
ILpk = IOUT / D' + ΔIL
(7)
or
When selecting an inductor, make sure that it is capable of supporting the peak input current without saturating.
Inductor saturation will result in a sudden reduction in inductance and prevent the regulator from operating
correctly. Because of the speed of the internal current limit, the peak current of the inductor need only be
specified for the required maximum input current. For example, if the designed maximum input current is 1.5A
and the peak current is 1.75A, then the inductor should be specified with a saturation current limit of >1.75A.
There is no need to specify the saturation or peak current of the inductor at the 3A typical switch current limit.
Because of the operating frequency of the LMR62421, ferrite based inductors are preferred to minimize core
losses. This presents little restriction since the variety of ferrite-based inductors is huge. Lastly, inductors with
lower series resistance (DCR) will provide better operating efficiency. For recommended inductors see Example
Circuits.
INPUT CAPACITOR
An input capacitor is necessary to ensure that VIN does not drop excessively during switching transients. The
primary specifications of the input capacitor are capacitance, voltage, RMS current rating, and ESL (Equivalent
Series Inductance). The recommended input capacitance is 10 µF to 44 µF depending on the application. The
capacitor manufacturer specifically states the input voltage rating. Make sure to check any recommended
deratings and also verify if there is any significant change in capacitance at the operating input voltage and the
operating temperature. The ESL of an input capacitor is usually determined by the effective cross sectional area
of the current path. At the operating frequencies of the LMR62421, certain capacitors may have an ESL so large
that the resulting impedance (2πfL) will be higher than that required to provide stable operation. As a result,
surface mount capacitors are strongly recommended. Multilayer ceramic capacitors (MLCC) are good choices for
both input and output capacitors and have very low ESL. For MLCCs it is recommended to use X7R or X5R
dielectrics. Consult capacitor manufacturer datasheet to see how rated capacitance varies over operating
conditions.
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OUTPUT CAPACITOR
The LMR62421 operates at frequencies allowing the use of ceramic output capacitors without compromising
transient response. Ceramic capacitors allow higher inductor ripple without significantly increasing output ripple.
The output capacitor is selected based upon the desired output ripple and transient response. The initial current
of a load transient is provided mainly by the output capacitor. The output impedance will therefore determine the
maximum voltage perturbation. The output ripple of the converter is a function of the capacitor’s reactance and
its equivalent series resistance (ESR):
§
·
VOUT x D
¸
ÂVOUT = ÂIL x R ESR + ¨¨
¸
© 2 x FSW x RLoad x C OUT ¹
(8)
When using MLCCs, the ESR is typically so low that the capacitive ripple may dominate. When this occurs, the
output ripple will be approximately sinusoidal and 90° phase shifted from the switching action .
Given the availability and quality of MLCCs and the expected output voltage of designs using the LMR62421,
there is really no need to review any other capacitor technologies. Another benefit of ceramic capacitors is their
ability to bypass high frequency noise. A certain amount of switching edge noise will couple through parasitic
capacitances in the inductor to the output. A ceramic capacitor will bypass this noise while a tantalum will not.
Since the output capacitor is one of the two external components that control the stability of the regulator control
loop, most applications will require a minimum at 4.7 µF of output capacitance. Like the input capacitor,
recommended multilayer ceramic capacitors are X7R or X5R. Again, verify actual capacitance at the desired
operating voltage and temperature.
SETTING THE OUTPUT VOLTAGE
The output voltage is set using the following equation where R1 is connected between the FB pin and GND, and
R2 is connected between VOUT and the FB pin.
VO
R2
C3
VFB
R LOAD
R1
Figure 16. Setting Vout
A good value for R1 is 10kΩ.
§ VOUT ·
- 1¸¸ x R1
R 2 = ¨¨
© VREF ¹
(9)
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COMPENSATION
The LMR62421 uses constant frequency peak current mode control. This mode of control allows for a simple
external compensation scheme that can be optimized for each application. A complicated mathematical analysis
can be completed to fully explain the LMR62421’s internal & external compensation, but for simplicity, a
graphical approach with simple equations will be used. Below is a Gain & Phase plot of a LMR62421 that
produces a 12V output from a 5V input voltage. The Bode plot shows the total loop Gain & Phase without
external compensation.
80
180
gm-Pole
60
RC-Pole
90
40
dB
20
0
-20
Vi = 5V
Vo = 12V
Io = 500 mA
Co = 10 PF
Lo = 5 PH
0
gm-Zero
-90
-40
RHP-Zero
-60
-80
10
100
1k
10k
100k
-180
1M
FREQUENCY
Figure 17. LMR62421 Without External Compensation
One can see that the Crossover frequency is fine, but the phase margin at 0dB is very low (22°). A zero can be
placed just above the crossover frequency so that the phase margin will be bumped up to a minimum of 45°.
Below is the same application with a zero added at 8 kHz.
80
60
40
gm-Pole
RC-Pole
Vi = 5V
Vo = 12V
Io = 500 mA
Co = 10 mF
Lo = 5 mH
180
90
D = 0.625
Cf = 220 pF
gm-zero
0
0 Fz-cf = 8 kHz
RHP-Zero = 107 kHz
-20 Fp-cf = 77 kHz
Fp-rc = 660 Hz
-90
-40
Ext (Cf)
-Zero
-60
Ext (Cf)-Pole
RHP-Zero
-180
-80
10
100
1k
10k
100k
1M
dB
20
FREQUENCY
Figure 18. LMR62421 With External Compensation
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The simplest method to determine the compensation component value is as follows.
Set the output voltage with the following equation.
§ VOUT ·
- 1¸¸ x R1
R 2 = ¨¨
© VREF ¹
where
•
R1 is the bottom resistor
•
R2 is the resistor tied to the output voltage.
and
(10)
The next step is to calculate the value of C3. The internal compensation has been designed so that when a zero
is added between 5 kHz & 10 kHz the converter will have good transient response with plenty of phase margin
for all input & output voltage combinations.
FZERO - CF =
1
= 5 kHz o 10 kHz
2S(R2 x Cf)
(11)
Lower output voltages will have the zero set closer to 10 kHz, and higher output voltages will usually have the
zero set closer to 5 kHz. It is always recommended to obtain a Gain/Phase plot for your actual application. One
could refer to the Typical Appplication section to obtain examples of working applications and the associated
component values.
Pole @ origin due to internal gm amplifier:
FP-ORIGIN
(12)
Pole due to output load and capacitor:
FP- RC =
1
2S(R Load COUT)
(13)
This equation only determines the frequency of the pole for perfect current mode control (CMC). Therefore, it
doesn’t take into account the additional internal artificial ramp that is added to the current signal for stability
reasons. By adding artificial ramp, you begin to move away from CMC to voltage mode control (VMC). The
artifact is that the pole due to the output load and output capacitor will actually be slightly higher in frequency
than calculated. In this example it is calculated at 650 Hz, but in reality it is around 1 kHz.
The zero created with capacitor C3 & resistor R2:
VO
R2
VFB
C3
R LOAD
R1
Figure 19. Setting External Pole-Zero
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1
2S(R2 x C3)
(14)
There is an associated pole with the zero that was created in the above equation.
FPOLE - CF =
1
2S((R1 R2) x C3)
(15)
It is always higher in frequency than the zero.
A right-half plane zero (RHPZ) is inherent to all boost converters. One must remember that the gain associated
with a right-half plane zero increases at 20dB per decade, but the phase decreases by 45° per decade. For most
applications there is little concern with the RHPZ due to the fact that the frequency at which it shows up is well
beyond crossover, and has little to no effect on loop stability. One must be concerned with this condition for large
inductor values and high output currents.
2
RHPZERO =
(D') RLoad
2S x L
(16)
There are miscellaneous poles and zeros associated with parasitics internal to the LMR62421, external
components, and the PCB. They are located well over the crossover frequency, and for simplicity are not
discussed.
PCB Layout Considerations
When planning layout there are a few things to consider when trying to achieve a clean, regulated output. The
most important consideration when completing a Boost Converter layout is the close coupling of the GND
connections of the COUT capacitor and the LMR62421 PGND pin. The GND ends should be close to one another
and be connected to the GND plane with at least two through-holes. There should be a continuous ground plane
on the bottom layer of a two-layer board. The FB pin is a high impedance node and care should be taken to
make the FB trace short to avoid noise pickup and inaccurate regulation. The feedback resistors should be
placed as close as possible to the IC, with the AGND of R1 placed as close as possible to the GND (pin 5 for the
WSON) of the IC. The VOUT trace to R2 should be routed away from the inductor and any other traces that are
switching. High AC currents flow through the VIN, SW and VOUT traces, so they should be as short and wide as
possible. However, making the traces wide increases radiated noise, so the designer must make this trade-off.
Radiated noise can be decreased by choosing a shielded inductor. The remaining components should also be
placed as close as possible to the IC. Please see Application Note AN-1229 SNVA054 for further considerations
and the LMR62421 demo board as an example of a good layout.
SEPIC Converter
The LMR62421 can easily be converted into a SEPIC converter. A SEPIC converter has the ability to regulate an
output voltage that is either larger or smaller in magnitude than the input voltage. Other converters have this
ability as well (CUK and Buck-Boost), but usually create an output voltage that is opposite in polarity to the input
voltage. This topology is a perfect fit for Lithium Ion battery applications where the input voltage for a single cell
Li-Ion battery will vary between 3V & 4.5V and the output voltage is somewhere in between. Most of the analysis
of the LMR62421 Boost Converter is applicable to the LMR62421 SEPIC Converter.
SEPIC Design Guide:
SEPIC Conversion ratio without loss elements:
Vo
D
=
VIN
D'
(17)
Therefore:
D=
16
VO
VO + VIN
(18)
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Small ripple approximation:
In a well-designed SEPIC converter, the output voltage, and input voltage ripple, the inductor ripple and is small
in comparison to the DC magnitude. Therefore it is a safe approximation to assume a DC value for these
components. The main objective of the Steady State Analysis is to determine the steady state duty-cycle, voltage
and current stresses on all components, and proper values for all components.
In a steady-state converter, the net volt-seconds across an inductor after one cycle will equal zero. Also, the
charge into a capacitor will equal the charge out of a capacitor in one cycle.
Therefore:
I L2
§ D·
= ¨ ' ¸ x I L1
©D¹
and
IL1 =
§ D · x § VO ·
¨ D' ¸ ¨ R ¸
© ¹ © ¹
(19)
Substituting IL1 into IL2
VO
IL2 =
R
(20)
The average inductor current of L2 is the average output load.
VL(t)
AREA 1
t (s)
AREA 2
DTS
TS
Figure 20. Inductor Volt-Sec Balance Waveform
Applying Charge balance on C1:
VC1 =
D' (Vo )
D
(21)
Since there are no DC voltages across either inductor, and capacitor C6 is connected to Vin through L1 at one
end, or to ground through L2 on the other end, we can say that
VC1 = VIN
(22)
Therefore:
VIN =
D' (Vo )
D
(23)
This verifies the original conversion ratio equation.
It is important to remember that the internal switch current is equal to IL1 and IL2. During the D interval. Design
the converter so that the minimum ensured peak switch current limit (2.1A) is not exceeded.
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VIN
VO
L1
D1
C6
LMR62421
C1
1
6
2
5
3
4
L2
R2
R3
C2
C5
C4
C3
R1
Figure 21. SEPIC CONVERTER Schematic
Steady State Analysis with Loss Elements
i L1( t )
i sw
iC1( t )
vC1( t )
+
i D1( t )
vD1( t )
i L 2( t )
VIN
i C2( t )
vL2( t )
+
-
+
R L1
vL1( t )
+
vC2( t )
vO ( t )
-
+
R on
R L2
18
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Using inductor volt-second balance & capacitor charge balance, the following equations are derived:
I L2
§ VO ·
=¨R¸
© ¹
and
§ VO · § D ·
¨ R ¸ x ¨ D' ¸
© ¹ © ¹
IL1 =
Vo §
=¨
VIN ¨©
(24)
§
·
¨
¸
¨
¸
1
D·¨
¸
¸
¸
D' ¹ ¨ §
VD R L2 · §¨ D ·¸ § R ON · §¨ D 2 ·¸ § R L1 · ¸
¸+
¨ ¨1+
+
¨
¸+
¸¸
¨
¨ ¨©
VO
R ¸¹ ¨© D' 2 ¸¹ © R ¹ ¨© D' 2 ¸¹ © R ¹ ¸
©
¹
(25)
Therefore:
§
·
¨
¸
¨
¸
1
¸
K= ¨
¨§
VD R L2 · §¨ D ·¸ § R ON · §¨ D 2 ·¸ § R L1 · ¸
¸+
¨ ¨1+
+
¸+
¨
¸¸
¨
¨ ¨©
VO
R ¸¹ ¨© D' 2 ¸¹ © R ¹ ¨© D' 2 ¸¹ © R ¹ ¸
©
¹
(26)
One can see that all variables are known except for the duty cycle (D). A quadratic equation is needed to solve
for D. A less accurate method of determining the duty cycle is to assume efficiency, and calculate the duty cycle.
§ D ·xK
¨1 - D¸
©
¹
(27)
VO
·
§
¨(V x K) +V ¸
O¹
© IN
(28)
VO
=
VIN
D=
Table 1. Efficiencies for Typical SEPIC Application
Vin
2.7V
Vin
3.3V
Vin
Vo
3.1V
lin
770 mA
lo
η
5V
Vo
3.1V
Vo
3.1V
lin
600mA
lin
375 mA
500 mA
lo
500mA
lo
500 mA
75%
η
80%
η
83%
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SEPIC Converter PCB Layout
The layout guidelines described for the LMR62421 Boost-Converter are applicable to the SEPIC Converter.
Below is a proper PCB layout for a SEPIC Converter.
CIN
PCB
VIN
PGND
L1
FB
EN
4
3
AGND
VIN
5
2
PGND
SW
6
1
CIN
COUT
D1
VO
C6
L2
Figure 22. SEPIC PCB Layout
WSON Package
The LMR62421 packaged in the 6–pin WSON:
Figure 23. Internal WSON Connection
20
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For certain high power applications, the PCB land may be modified to a "dog bone" shape (see Figure 24).
Increasing the size of ground plane, and adding thermal vias can reduce the RθJA for the application.
COPPER
PGND 1
6
SW
Vin
2
5
AGND
EN
3
4
FB
COPPER
Figure 24. PCB Dog Bone Layout
LMR62421 Design Example 1
L1
4
VIN
R3
1 M:
EN
6.8 PH
2.9A
3
FB
2
2A 20V
GND
5
Vin
C1
10 PF
10V
12V
1
SW
D1
C2
10 PF
25V
R2
86.6k
C3
220 pF
25V
R LOAD
R1
10.2k
Figure 25. Vin = 3V - 5V, Vout = 12V @ 500 mA
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LMR62421 Design Example 2
L1
10 PH
1.2A
1 M:
3
4
FB
SHDN
R3
2
1A 20V
GND
VIN
5V
1
5
SW
Vin
D1
C1
10 PF
6.3V
R2
30.1k
C2
10 PF
10V
C3
1 nF
R LOAD
R1
10k
Figure 26. Vin = 3V, Vout = 5V @ 500 mA
LMR62421 Design Example 3
L1
10 PH
1.2A
1 M:
4
R3
SHDN
3
FB
2
GND
VIN
5
Vin
C1
22 PF
6.3V
500 mA 30V
20V
1
SW
D1
R2
150k
C2
4.7 PF
50V
C3
470 pF
50V
R LOAD
R1
10k
Figure 27. Vin = 3.3V, Vout = 20V @ 100 mA
22
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SNVS734B – OCTOBER 2011 – REVISED APRIL 2013
LMR62421 SEPIC Design Example 4
VIN
L1
6.8 PH
1.2A
2.2 PF
16V
1A 20V
D1
VO
C6
LMR62421
1
6
2
5
L2
6.8 PH
1.2A
R2
16.5k
3
C1
22 PF
10V
C2
4
R3
100k
C5
2.2 nF
C3
10 PF
10V
C4
(opt)
R1
10.2k
(opt)
Figure 28. Vin = 2.7V - 5V, Vout = 3.3V @ 500mA
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LMR62421
SNVS734B – OCTOBER 2011 – REVISED APRIL 2013
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REVISION HISTORY
Changes from Revision A (April 2013) to Revision B
•
24
Page
Changed layout of National Data Sheet to TI format .......................................................................................................... 23
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PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
LMR62421XMF/NOPB
ACTIVE
SOT-23
DBV
5
1000
RoHS & Green
SN
Level-1-260C-UNLIM
-40 to 125
SH8B
LMR62421XMFE/NOPB
ACTIVE
SOT-23
DBV
5
250
RoHS & Green
SN
Level-1-260C-UNLIM
-40 to 125
SH8B
LMR62421XMFX/NOPB
ACTIVE
SOT-23
DBV
5
3000
RoHS & Green
SN
Level-1-260C-UNLIM
-40 to 125
SH8B
LMR62421XSD/NOPB
ACTIVE
WSON
NGG
6
1000
RoHS & Green
SN
Level-1-260C-UNLIM
-40 to 125
L270B
LMR62421XSDE/NOPB
ACTIVE
WSON
NGG
6
250
RoHS & Green
SN
Level-1-260C-UNLIM
-40 to 125
L270B
LMR62421XSDX/NOPB
ACTIVE
WSON
NGG
6
4500
RoHS & Green
SN
Level-1-260C-UNLIM
-40 to 125
L270B
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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