LMX1501A,LMX1511
LMX1501A LMX1511 PLLatinum(TM) 1.1 GHz Frequency Synthesizer for RF
Personal Communications
Literature Number: SNOS747A
LMX1501A/LMX1511 PLLatinum TM
1.1 GHz Frequency Synthesizer
for RF Personal Communications
General Description
Features
The LMX1501A and the LMX1511 are high performance frequency synthesizers with integrated prescalers designed for
RF operation up to 1.1 GHz. They are fabricated using National’s ABiC IV BiCMOS process.
The LMX1501A and the LMX1511 contain dual modulus
prescalers which can select either a 64/65 or a 128/129
divide ratio at input frequencies of up to 1.1 GHz. Using a
proprietary digital phase locked loop technique, the
LMX1501A/11’s linear phase detector characteristics can
generate very stable, low noise local oscillator signals.
Serial data is transferred into the LMX1501A and the
LMX1511 via a three line MICROWIRETM interface (Data,
Enable, Clock). Supply voltage can range from 2.7V to 5.5V.
The LMX1501A and the LMX1511 feature very low current
consumption, typically 6 mA at 3V.
The LMX1501A is available in a JEDEC 16-pin surface
mount plastic package. The LMX1511 is available in a
TSSOP 20-pin surface mount plastic package.
Y
Y
Y
Y
Y
RF operation up to 1.1 GHz
2.7V to 5.5V operation
Low current consumption:
ICC e 6 mA (typ) at VCC e 3V
Dual modulus prescaler: 64/65 or 128/129
Internal balanced, low leakage charge pump
Small-outline, plastic, surface mount JEDEC, 0.150×
wide, (1501A) or TSSOP, 0.173× wide, (1511) package
e
Y
Applications
Y
et
Y
Cellular telephone systems
(AMPS, NMT, ETACS)
Portable wireless communications
(PCS/PCN, Cordless)
Advanced cordless telephone systems
(CT-1/CT-1 a , CT-2, ISM902-928)
Other wireless communication systems
Y
O
bs
ol
Block Diagram
Y
TL/W/12340 – 1
TRI-STATEÉ is a registered trademark of National Semiconductor Corporation.
MICROWIRETM and PLLatinumTM are trademarks of National Semiconductor Corporation.
C1995 National Semiconductor Corporation
TL/W/12340
RRD-B30M115/Printed in U. S. A.
LMX1501A/LMX1511 PLLatinum 1.1 GHz Frequency
Synthesizer for RF Personal Communications
November 1995
Connection Diagrams
LMX1511
LMX1501A
TL/W/12340–2
JEDEC 16-Lead (0.150× Wide) Small
Outline Molded Package (M)
Order Number LMX1501AM or LMX1501AMX
See NS Package Number M16A
TL/W/12340 – 3
20-Lead (0.173× Wide) Thin Shrink
Small Outline Package (TM)
Order Number LMX1511TM or LMX1511TMX
See NS Package Number MTC20
Pin No.
Pin Name
1501A
1511
1501A/1511
1
1
2
3
e
Pin Descriptions
Pin No.
Description
OSCIN
I
Oscillator input. A CMOS inverting gate input intended for connection to a
crystal resonator for operation as an oscillator. The input has a VCC/2 input
threshold and can be driven from an external CMOS or TTL logic gate. May also
be used as a buffer for an externally provided reference oscillator.
3
OSCOUT
O
4
VP
Power supply for charge pump must be t VCC.
4
5
VCC
Power supply voltage input. Input may range from 2.7V to 5.5V. Bypass
capacitors should be placed as close as possible to this pin and be connected
directly to the ground plane.
5
6
6
7
7
8
8
10
9
11
10
13
11
14
et
I/O
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ol
Oscillator output.
Do
O
GND
Internal charge pump output. For connection to a loop filter for driving the input
of an external VCO.
Ground.
LD
O
Lock detect. Output provided to indicate when the VCO frequency is in ‘‘lock’’.
When the loop is locked, the pin’s output is HIGH with narrow low pulses.
I
Prescaler input. Small signal input from the VCO.
I
High impedance CMOS Clock input. Data is clocked in on the rising edge, into
the various counters and registers.
DATA
I
Binary serial data input. Data entered MSB first. LSB is control bit. High
impedance CMOS input.
LE
I
Load enable input (with internal pull-up resistor). When LE transitions HIGH,
data stored in the shift registers is loaded into the appropriate latch (control bit
dependent). Clock must be low when LE toggles high or low. See Serial Data
Input Timing Diagram.
O
fIN
CLOCK
12
15
FC
I
Phase control select (with internal pull-up resistor). When FC is LOW, the
polarity of the phase comparator and charge pump combination is reversed.
X
16
BISW
O
Analog switch output. When LE is HIGH, the analog switch is ON, routing the
internal charge pump output through BISW (as well as through Do).
13
fr
O
Monitor pin of phase comparator input. Programmable reference divider output.
14
fp
O
Monitor pin of phase comparator input. Programmable divider output.
X
17
fOUT
O
Monitor pin of phase comparator input. CMOS Output.
15
18
wp
O
Output for external charge pump. wp is an open drain N-channel transistor and
requires a pull-up resistor.
O
16
20
wr
X
2,9,12,19
NC
Output for external charge pump. wr is a CMOS logic output.
No connect.
2
Functional Block Diagram
O
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et
e
LMX1501A
3
TL/W/12340 – 40
Functional Block Diagram (Continued)
O
bs
ol
et
e
LMX1511
4
TL/W/12340 – 4
Absolute Maximum Ratings (Note 1)
Recommended Operating
Conditions
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Power Supply Voltage
VCC
VP
b 0.3V to a 6.5V
b 0.3V to a 6.5V
Voltage on Any Pin
with GND e 0V (VI)
b 0.3V to a 6.5V
Storage Temperature Range (TS)
Lead Temperature (TL) (solder, 4 sec.)
Power Supply Voltage
VCC
VP
2.7V to 5.5V
VCC to 5.5V
b 40§ C to a 85§ C
Operating Temperature (TA)
Note 1: Absolute Maximum Ratings indicate limits beyond which damage to
the device may occur. Operating Ratings indicate conditions for which the
device is intended to be functional, but do not guarantee specific performance limits. For guaranteed specifications and test conditions, see the Electrical Characteristics. The guaranteed specifications apply only for the test
conditions listed.
b 65§ C to a 150§ C
a 260§ C
Electrical Characteristics VCC e 5.0V, VP e 5.0V; b40§ C k TA k 85§ C, except as specified
Symbol
ICC
Parameter
Power Supply Current
Typ
Max
Units
VCC e 3.0V
Conditions
Min
6.0
8.0
mA
VCC e 5.0V
6.5
8.5
mA
Maximum Operating Frequency
fOSC
Maximum Oscillator Frequency
fw
Maximum Phase Detector Frequency
PfIN
Input Sensitivity
VCC e 2.7V to 5.5V
VOSC
Oscillator Sensitivity
OSCIN
VIH
High-Level Input Voltage
VIL
Low-Level Input Voltage
IIH
High-Level Input Current (Clock, Data)
IIL
Low-Level Input Current (Clock, Data)
IIL
IIH
IIL
10
b 10
a6
0.5
et
Oscillator Input Current
GHz
20
*
0.7 VCC
*
MHz
MHz
dBm
VPP
V
0.3 VCC
V
VIH e VCC e 5.5V
b 1.0
1.0
mA
VIL e 0V, VCC e 5.5V
b 1.0
1.0
mA
VIH e VCC e 5.5V
bs
ol
IIH
1.1
e
fIN
VIL e 0V, VCC e 5.5V
100
b 100
mA
mA
High-Level Input Current (LE, FC)
VIH e VCC e 5.5V
b 1.0
1.0
mA
Low-Level Input Current (LE, FC)
VIL e 0V, VCC e 5.5V
b 100
1.0
mA
O
*Except fIN and OSCIN
5
Electrical Characteristics VCC e 5.0V, VP e 5.0V; b40§ C k TA k 85§ C, except as specified (Continued)
Parameter
Charge Pump Output Current
IDo-sink
IDo-Tri
Charge Pump TRI-STATEÉ Current
Conditions
Max
Units
mA
VDo e VP/2
5.0
mA
0.5V s VDo s VP b 0.5V
High-Level Output Voltage
IOH e b1.0 mA**
VOL
Low-Level Output Voltage
IOL e 1.0 mA**
VOH
High-Level Output Voltage (OSCOUT)
IOH e b200 mA
VOL
Low-Level Output Voltage (OSCOUT)
IOL e 200 mA
IOL
Open Drain Output Current (wp)
VCC e 5.0V, VOL e 0.4V
IOH
Open Drain Output Current (wp)
VOH e 5.5V
RON
Analog Switch ON Resistance (1511)
tCS
Data to Clock Set Up Time
tCH
Data to Clock Hold Time
See Data Input Timing
tCWH
Clock Pulse Width High
See Data Input Timing
tCWL
Clock Pulse Width Low
See Data Input Timing
tES
Clock to Enable Set Up Time
See Data Input Timing
tEW
Enable Pulse Width
See Data Input Timing
b 5.0
5.0
nA
VCC b 0.8
V
0.4
V
VCC b 0.8
V
0.4
1.0
V
mA
100
mA
100
50
X
ns
10
ns
50
ns
50
ns
50
ns
50
ns
et
See Data Input Timing
O
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**Except OSCOUT
Typ
b 5.0
T e 25§ C
VOH
Min
VDo e VP/2
e
Symbol
IDo-source
6
Typical Performance Characteristics
ICC vs VCC
IDo TRI-STATE vs Do Voltage
TL/W/12340 – 5
TL/W/12340 – 6
Charge Pump Current vs Do Voltage
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Charge Pump Current vs Do Voltage
TL/W/12340 – 7
O
Charge Pump Current Variation
TL/W/12340 – 8
Oscillator Input Sensitivity
TL/W/12340 – 10
TL/W/12340 – 9
7
Typical Performance Characteristics
(Continued)
Input Sensitivity vs Frequency
Input Sensitivity vs Frequency
TL/W/12340–11
TL/W/12340 – 12
Input Sensitivity at Temperature
Variation, VCC e 3V
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et
e
Input Sensitivity at Temperature
Variation, VCC e 5V
TL/W/12340–13
LMX1511 Input Impedance vs Frequency
VCC e 2.7V to 5.5V, fIN e 100 MHz to 1,600 MHz
O
LMX1501A Input Impedance vs Frequency
VCC e 2.7V to 5.5V, fIN e 100 MHz to 1,600 MHz
TL/W/12340 – 14
TL/W/12340–15
Marker
Marker
Marker
Marker
1
2
3
4
e
e
e
e
TL/W/12340 – 16
500 MHz, Real e 67, Imag. e b 317
900 MHz, Real e 24, Imag. e b 150
1 GHz, Real e 19, Imag. e b 126
1,500 MHz, Real e 9, Imag. e b 63
Marker
Marker
Marker
Marker
8
1
2
3
4
e
e
e
e
500 MHz, Real e 69, Imag. e b 330
900 MHz, Real e 36, Imag. e b 193
1 GHz, Real e 35, Imag. e b 172
1,500 MHz, Real e 30, Imag. e b 106
et
e
Charge Pump Current Specification Definitions
TL/W/12340 – 17
I1 e CP sink current at VDo e VP b DV
I2 e CP sink current at VDo e VP/2
I3 e CP sink current at VDo e DV
I4 e CP source current at VDo e VP b DV
I5 e CP source current at VDo e VP/2
I6 e CP source current at VDo e DV
bs
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DV e Voltage offset from positive and negative rails. Dependent on VCO tuning range relative to VCC and ground. Typical values are between 0.5V and 1.0V.
1. IDo vs VDo e Charge Pump Output Current magnitude variation vs Voltage e
[(/2 * l I1 l b l I3 l ]/[(/2 * À l I1 l a l I3 l Ó ] * 100% and [(/2 * l I4 l b l I6 l ]/[(/2 * À l I4 l a l I6 l Ó ] * 100%
2. IDo-sink vs IDo-source e Charge Pump Output Current Sink vs Source Mismatch e
[ l I2 l b l I5 l ]/[(/2 * À l I2 l a l I5 l Ó ] * 100%
3. IDo vs TA e Charge Pump Output Current magnitude variation vs Temperature e
[ l I2 @ temp l b l I2 @ 25§ C l ]/ l I2 @ 25§ C l * 100% and [ l I5 @ temp l b l I5 @ 25§ C l ]/ l I5
@
25§ C l * 100%
4. Kw e Phase detector/charge pump gain constant e (/2* À l I2 l a l I5 l Ó
O
RF Sensitivity Test Block Diagram
TL/W/12340 – 18
Note 1: N e 10,000
R e 50
P e 64
Note 2: Sensitivity limit is reached when the error of the divided RF output, fOUT, is greater than or equal to 1 Hz.
9
Functional Description
e
The simplified block diagram below shows the 19-bit data register, the 14-bit R Counter and the S Latch, and the 18-bit
N Counter (intermediate latches are not shown). The data stream is clocked (on the rising edge) into the DATA input, MSB first.
If the Control Bit (last bit input) is HIGH, the DATA is transferred into the R Counter (programmable reference divider) and the
S Latch (prescaler select: 64/65 or 128/129). If the Control Bit (LSB) is LOW, the DATA is transferred into the N Counter
(programmable divider).
TL/W/12340 – 19
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et
PROGRAMMABLE REFERENCE DIVIDER (R COUNTER) AND PRESCALER SELECT (S LATCH)
If the Control Bit (last bit shifted into the Data Register) is HIGH, data is transferred from the 19-bit shift register into a 14-bit
latch (which sets the 14-bit R Counter) and the 1-bit S Latch (S15, which sets the prescaler: 64/65 or 128/129). Serial data
format is shown below.
14-BIT PROGRAMMABLE REFERENCE DIVIDER RATIO
(R COUNTER)
Divide
S S S S S S S S S S S S S S
Ratio
14 13 12 11 10 9 8 7 6 5 4 3 2 1
R
3
4
#
1-BIT PRESCALER SELECT
(S LATCH)
Prescaler
Select
P
S
15
0
0
0
0
0
0 0 0 0 0 0 0 1 1
128/129
0
0
0
0
0
0
0 0 0 0 0 0 1 0 0
64/65
1
#
#
#
#
#
# # # # # # # # #
1
1
1
1
1
1 1 1 1 1 1 1 1 1
O
16383
TL/W/12340 – 20
Notes: Divide ratios less than 3 are prohibited.
Divide ratio: 3 to 16383
S1 to S14: These bits select the divide ratio of the programmable
reference divider.
C: Control bit (set to HIGH level to load R counter and S Latch)
Data is shifted in MSB first.
10
Functional Description (Continued)
PROGRAMMABLE DIVIDER (N COUNTER)
The N counter consists of the 7-bit swallow counter (A counter) and the 11-bit programmable counter (B counter). If the Control
Bit (last bit shifted into the Data Register) is LOW, data is transferred from the 19-bit shift register into a 7-bit latch (which sets
the 7-bit Swallow (A) Counter) and an 11-bit latch (which sets the 11-bit programmable (B) Counter). Serial data format is shown
below.
TL/W/12340 – 21
Note: S8 to S18: Programmable counter divide ratio control bits (3 to 2047)
S
7
S
6
S
5
S
4
S
3
S
2
S
1
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
1
#
#
#
#
#
#
#
#
127
1
1
1
1
1
1
1
S
18
S
17
S
16
S
15
S
14
S
13
S
12
S
11
S
10
S
9
S
8
3
0
0
0
0
0
0
0
0
0
1
1
4
0
0
0
0
0
0
0
0
1
0
0
#
#
#
#
#
#
#
#
#
#
#
#
2047
1
1
1
1
1
1
1
1
1
1
1
Note: Divide ratio: 3 to 2047 (Divide ratios less than 3 are prohibited)
bs
ol
Note: Divide ratio: 0 to 127
Divide
Ratio
B
et
Divide
Ratio
A
11-BIT PROGRAMMABLE COUNTER DIVIDE RATIO
(B COUNTER)
e
7-BIT SWALLOW COUNTER DIVIDE RATIO
(A COUNTER)
BtA
BtA
O
PULSE SWALLOW FUNCTION
fVCO e [(P c B) a A] c fOSC/R
fVCO: Output frequency of external voltage controlled oscillator (VCO)
B:
Preset divide ratio of binary 11-bit programmable
counter (3 to 2047)
A:
Preset divide ratio of binary 7-bit swallow counter
(0 s A s 127, A s B)
fOSC: Output frequency of the external reference frequency
oscillator
R:
Preset divide ratio of binary 14-bit programmable reference counter (3 to 16383)
P:
Preset modulus of dual moduIus prescaler (64 or
128)
11
Functional Description (Continued)
SERIAL DATA INPUT TIMING
TL/W/12340 – 22
Notes: Parenthesis data indicates programmable reference divider data.
e
Data shifted into register on clock rising edge.
Data is shifted in MSB first.
Test Conditions: The Serial Data Input Timing is tested using a symmetrical waveform around VCC/2. The test waveform has an edge rate of 0.6 V/ns with
amplitudes of 2.2V @ VCC e 2.7V and 2.6V @ VCC e 5.5V.
VCO Characteristics
bs
ol
In normal operation, the FC pin is used to reverse the polarity of the phase detector. Both the internal and any external
charge pump are affected.
Depending upon VCO characteristics, FC pin should be set
accordingly:
When VCO characteristics are like (1), FC should be set
HIGH or OPEN CIRCUIT;
When VCO characteristics are like (2), FC should be set
LOW.
When FC is set HIGH or OPEN CIRCUIT, the monitor pin of
the phase comparator input, fout, is set to the reference
divider output, fr. When FC is set LOW, fout is set to the
programmable divider output, fp.
et
Phase Characteristics
TL/W/12340 – 23
O
PHASE COMPARATOR AND INTERNAL CHARGE PUMP CHARACTERISTICS
TL/W/12340 – 24
Notes: Phase difference detection range: b 2q to a 2q
The minimum width pump up and pump down current pulses occur at the Do pin when the loop is locked.
FC e HIGH
12
Analog Switch (1511 only)
e
The analog switch is useful for radio systems that utilize a frequency scanning mode and a narrow band mode. The purpose of
the analog switch is to decrease the loop filter time constant, allowing the VCO to adjust to its new frequency in a shorter
amount of time. This is achieved by adding another filter stage in parallel. The output of the charge pump is normally through the
Do pin, but when LE is set HIGH, the charge pump output also becomes available at BISW. A typical circuit is shown below. The
second filter stage (LPF-2) is effective only when the switch is closed (in the scanning mode).
TL/W/12340 – 25
Typical Lock Detect Circuit
A typical circuit which can be used to implement a crystal
oscillator is shown below.
A lock detect circuit is needed in order to provide a steady
LOW signal when the PLL is in the locked state. A typical
circuit is shown below.
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et
Typical Crystal Oscillator Circuit
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TL/W/12340 – 26
13
TL/W/12340 – 27
et
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Typical Application Example
TL/W/12340 – 28
Operational Notes:
*VCO is assumed AC coupled.
**RIN increases impedance so that VCO output power is provided to the load rather than the PLL. Typical values are 10X to 200X depending on the VCO power
level. fIN RF impedance ranges from 40X to 100X.
bs
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***50X termination is often used on test boards to allow use of external reference oscillator. For most typical products a CMOS clock is used and no terminating
resistor is required. OSCIN may be AC or DC coupled. AC coupling is recommended because the input circuit provides its own bias. (See Figure below)
TL/W/12340 – 29
Proper use of grounds and bypass capacitors is essential to achieve a high level of performance.
Crosstalk between pins can be reduced by careful board layout.
O
This is a static sensitive device. It should be handled only at static free work stations.
14
Application Information
LOOP FILTER DESIGN
A block diagram of the basic phase locked loop is shown.
TL/W/12340 – 30
e
FIGURE 1. Basic Charge Pump Phase Locked Loop
et
An example of a passive loop filter configuration, including
the transfer function of the loop filter, is shown in Figure 2 .
TL/W/12340 – 31
s (C2 # R2) a 1
s2 (C1 # C2 # R2) a sC1 a sC2
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ol
Z(s) e
FIGURE 2. 2nd Order Passive Filter
Define the time constants which determine the pole and
zero frequencies of the filter transfer function by letting
(1a)
T2 e R2 # C2
and
C1 # C2
T1 e R2 #
C1 a C2
(1b)
The PLL linear model control circuit is shown along with the
open loop transfer function in Figure 3 . Using the phase
detector and VCO gain constants [Kw and KVCO] and the
loop filter transfer function [Z(s)], the open loop Bode plot
can be calculated. The loop bandwidth is shown on the
Bode plot (0p) as the point of unity gain. The phase margin
is shown to be the difference between the phase at the unity
gain point and b180§ .
TL/W/12340 – 32
FIGURE 3. Open Loop Transfer Function
Thus we can calculate the 3rd order PLL Open Loop Gain in
terms of frequency
G(s) # H(s)ls e j # 0 e
# KVCO (1 a j0 # T2) T1
#
02C1 # N(1 a j0 # T1)
T2
b Kw
O
(2)
From equation 2 we can see that the phase term will be
dependent on the single pole and zero such that
w(0) e tanb1 (0 # T2) b tanb1 (0 # T1) a 180§ (3)
By setting
T2
T1
dw
e
b
e0
d0
1 a (0 # T2)2 1 a (0 # T1)2
(4)
we find the frequency point corresponding to the phase inflection point in terms of the filter time constants T1 and T2.
This relationship is given in equation 5.
0p e 1/0T2 # T1
(5)
For the loop to be stable the unity gain point must occur
before the phase reaches b180 degrees. We therefore
want the phase margin to be at a maximum when the magnitude of the open loop gain equals 1. Equation 2 then gives
TL/W/12340 – 33
C1 e
Open Loop Gain e ii/ie e H(s) G(s)
e Kw Z(s) KVCO/Ns
Closed Loop Gain e io/ii e G(s)/[1 a H(s) G(s)]
15
Kw # KVCO # T1 (1 a j0p # T2)
0p2 # N # T2 (1 a j0p # T1)
Ó
Ó
(6)
Application Information (Continued)
Therefore, if we specify the loop bandwidth, 0p, and the
phase margin, wp, Equations 1 through 6 allow us to calculate the two time constants, T1 and T2, as shown in equations 7 and 8. A common rule of thumb is to begin your
design with a 45§ phase margin.
secwp b tanwp
T1 e
0p
(7)
T2 e
In choosing the loop filter components a trade off must be
made between lock time, noise, stability, and reference
spurs. The greater the loop bandwidth the faster the lock
time will be, but a large loop bandwidth could result in higher
reference spurs. Wider loop bandwidths generally improve
close in phase noise but may increase integrated phase
noise depending on the reference input, VCO and division
ratios used. The reference spurs can be reduced by reducing the loop bandwidth or by adding more low pass filter
stages but the lock time will increase and stability will decrease as a result.
1
0p2 # T1
(8)
From the time constants T1, and T2, and the loop bandwidth, 0p, the values for C1, R2, and C2 are obtained in
equations 9 to 11.
T1 Kw # KVCO 1 a (0p # T2)2
#
T2
0p2 # N
1 a (0p # T1)2
(9)
T2
b1
C2 e C1 #
T1
(10)
T2
R2 e
C2
(11)
Voltage Controlled Oscillator (VCO)
KVCO (MHz/V)
Tuning Voltage constant. The frequency vs voltage tuning ratio.
Kw (mA)
Phase detector/charge pump gain
constant. The ratio of the current output to the input phase differential.
N
Main divider ratio. Equal to RFopt/fref
J
Radio Frequency output of the VCO at
which the loop filter is optimized.
fref (kHz)
Frequency of the phase detector inputs. Usually equivalent to the RF
channel spacing.
T2 e
Defining the additional time constant as
T3 e R3 # C3
(13)
Then in terms of the attenuation of the reference spurs added by the low pass pole we have
0
10ATTEN/20 b 1
(14)
(2q # fref)2
We then use the calculated value for loop bandwidth 0c in
equation 11, to determine the loop filter component values
in equations 15 – 17. 0c is slightly less than 0p, therefore
the frequency jump lock time will increase.
T3 e
bs
ol
RFopt (MHz)
e
#
0
et
C1 e
THIRD ORDER FILTER
A low pass filter section may be needed for some applications that require additional rejection of the reference sidebands, or spurs. This configuration is given in Figure 4 . In
order to compensate for the added low pass section, the
component values are recalculated using the new open
loop unity gain frequency. The degradation of phase margin
caused by the added low pass is then mitigated by slightly
increasing C1 and C2 while slightly decreasing R2.
The added attenuation from the low pass filter is:
ATTEN e 20 log[(2qfref # R3 # C3)2 a 1]
(12)
1
0c2 # (T1 a T3)
(T1 a T3)2 a T1 # T3
b1
[tanw # (T1 a T3)] 2
0c e
tanw # (T1 a T3)
#
[(T1 a T3)2 a T1 # T3]
C1 e
(/2
T1 Kw # KVCO
(1 a 0c2 # T22)
#
#
T2
0c2 # N
(1 a 0c2 # T12) (1 a 0c2 # T32)
Ð01
a
(
O
Ð
16
(
(15)
(16)
(17)
Application Information (Continued)
Example Ý1
KVCO e 19.3 MHz/V
Kw e 5 mA (Note 1)
RFopt e 886 MHz
Fref e 25 kHz
N e RFopt/fref e 35440
0p e 2q * 5 kHz e 3.1415e4
wp e 43§
ATTEN e 10 dB
secwp b tanwp
0p
e 1.38e b 5
T3 e
0 (2q # 25e3)
0c e
(tan 43§ ) # (1.38eb5 a 9.361eb6)
[(1.38eb5 a 9.361eb6)2 a 1.38eb5 # 9.361eb6]
10(10/20) b 1
2
#
Ð01
a
e 9.361e b 6
(1.38eb5 a 9.361eb6)2 a 1.38eb5 # 9.361eb6
b1
[(tan 43§ ) # (1.38eb5 a 9.361eb6)] 2
(
et
e 1.8101e4
T2 e
e
T1 e
1
e 1.318e b 4
(1.8101e4)2 # (1.38eb5 a 9.361eb6)
(/2
[1 a (1.8101e4)2 # (1.318eb4)2]
(5eb3) # 19.3e6
1.38eb5
#
[1 a (1.8101e4)2 # (1.38eb5)2] [1 a (1.8101e4)2 # (9.361eb6)2]
1.318eb4 (1.8101e4)2 # (35440)
e 2.153 nF
Ð
C1 e
# 1.384e
1.318eb4
b1
b5
J
e 18.35 nF
bs
ol
C2 e 2.153 nF
R2 e
(
1.318eb4
e 7.18 kX
18.35eb9
if we choose R3 e 120k; then C3 e
9.361eb6
e 78 pF.
120e3
Converting to standard component values gives the following filter values, which are shown in Figure 4 .
C1 e 2200 pF
R2 e 8.2 kX
C2 e 0.018 mF
R3 e 120 kX
C3 e 78 pF
Note 1: See related equation for Kw in Charge Pump Current Specification
Definitions. For this example VP e 5.0V. The value for Kw can then
be approximated using the curves in the Typical Performance Characteristics for Charge Pump Current vs Do Voltage. The units for Kw
are in mA. You may also use Kw e (5 mA/2q rad), but in this case
you must convert KVCO to (rad/V) multiplying by 2q.
O
FIGURE 4. E 5 kHz Loop Filter
17
TL/W/12340 – 41
e
Application Information (Continued)
TL/W/12340–43
TL/W/12340 – 45
et
FIGURE 6. PLL Phase Noise 3.5 kHz Offset
The phase noise level at 3 kHz offset is b65 dBc/Hz.
bs
ol
FIGURE 5. PLL Reference Spurs
The reference spurious level is k b66 dBc, due to the loop
filter attenuation and the low spurious noise level of the
LMX1511.
TL/W/12340–44
TL/W/12340 – 42
FIGURE 8. Frequency Jump Lock Time
Of concern in any PLL loop filter design is the time it takes
to lock in to a new frequency when switching channels. Figure 8 shows the switching waveforms for a frequency jump
of 857 MHz – 915 MHz. By narrowing the frequency span of
the HP53310A Modulation Domain Analyzer enables evaluation of the frequency lock time to within g 1 kHz. The lock
time is seen to be k 1.6 ms for a frequency jump of 58 MHz.
O
FIGURE 7. PLL Phase Noise @ 150 Hz Offset
The phase noise level at 150 Hz offset is b75.5 dBc/Hz.
18
Application Information (Continued)
EXAMPLE
EXTERNAL CHARGE PUMP
The LMX PLLatimum series of frequency synthesizers are
equipped with an internal balanced charge pump as well as
outputs for driving an external charge pump. Although the
superior performance of NSC’s on board charge pump eliminates the need for an external charge pump in most applications, certain system requirements are more stringent. In
these cases, using an external charge pump allows the designer to take direct control of such parameters as charge
pump voltage swing, current magnitude, TRI-STATE leakage, and temperature compensation.
One possible architecture for an external charge pump current source is shown in Figure 9 . The signals wp and wr in
the diagram, correspond to the phase detector outputs of
the LMX1501/1511 frequency synthesizers. These logic
signals are converted into current pulses, using the circuitry
shown in Figure 9 , to enable either charging or discharging
of the loop filter components to control the output frequency
of the PLL.
Referring to Figure 9 , the design goal is to generate a 5 mA
current which is relatively constant to within 5V of the power
supply rail. To accomplish this, it is important to establish as
large of a voltage drop across R5, R8 as possible without
saturating Q2, Q4. A voltage of approximately 300 mV provides a good compromise. This allows the current source
reference being generated to be relatively repeatable in the
absence of good Q1, Q2/Q3, Q4 matching. (Matched transistor pairs is recommended.) The wp and wr outputs are
rated for a maximum output load current of 1 mA while 5 mA
current sources are desired. The voltages developed across
R4, 9 will consequently be approximately 258 mV, or 42 mV
k R8, 5, due to the current density differences À 0.026*1n (5
mA/1 mA)Ó through the Q1, Q2/Q3, Q4 pairs.
In order to calculate the value of R7 it is necessary to first
estimate the forward base to emitter voltage drop (Vfn,p) of
the transistors used, the VOL drop of wp, and the VOH drop
of wr’s under 1 mA loads. (wp’s VOL k 0.1V and wr;s VOH
k 0.1V.)
Knowing these parameters along with the desired current
allow us to design a simple external charge pump. Separating the pump up and pump down circuits facilitates the nodal analysis and give the following equations.
Typical Device Parameters
bn e 100, bp e 50
Typical System Parameters
VP e 5.0V;
Vcntl e 0.5V b 4.5V;
Vwp e 0.0V, Vwr e 5.0V
ISINK e ISOURCE e 5.0 mA;
Vfn e Vfp e 0.8V
Irmax e Ipmax e 1 mA
VR8 e VR5 e 0.3V
VOLwp e VOHwr e 100 mV
R4 e
bs
ol
et
e
Design Parameters
#
isource
VR5 b VT # 1n
ip max
isource
VR8 b VT # 1n
isink
n max
Therefore select
0.3V b 0.026 # 1n(5.0 mA/1.0 mA)
e 51.6X
5 mA
0.3V # (50 a 1)
e 332X
R5 e
1.0 mA # (50 a 1) b 5.0 mA
R4 e R9 e
0.3V # (100 b 1)
e 315.6X
1.0 mA # (100 a 1) b 5.0 mA
(5V b 0.1V) b (0.3V a 0.8V)
e 3.8 kX
R6 e R7 e
1.0 mA
R8 e
J
J
O
R9 e
#i
isink
R5 e
VR5 # (bp a 1)
ip max # (bp a 1) b isource
R8 e
VR8 # (bn a 1)
ir max # (bn a 1) b isink
R6 e
R7 e
TL/W/12340 – 46
FIGURE 9
(Vp b VVOLwp) b (VR5 a Vfp)
ip max
(VP b VVOHwr) b (VR8 a Vfn)
imax
19
20
e
et
bs
ol
O
et
e
Physical Dimensions inches (millimeters)
O
bs
ol
JEDEC 16-Lead (0.150× Wide) Small Outline Molded Package (M)
Order Number LMX1501AM
For Tape and Reel Order Number LMX1501AMX (2500 Units per Reel)
NS Package Number M16A
21
e
et
bs
ol
LMX1501A/LMX1511 PLLatinum 1.1 GHz Frequency
Synthesizer for RF Personal Communications
Physical Dimensions (millimeters) (Continued)
20-Lead (0.173× Wide) Thin Shrink Small Outline Package (TM)
Order Number LMX1511TM
For Tape and Reel Order Number LMX1511TMX (2500 Units per Reel)
NS Package Number MTC20
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O
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