LMX2336TMX

LMX2335,LMX2336,LMX2337 LMX2335/LMX2336/LMX2337 PLLatinum Dual Frequency Synthesizer for RF Personal Communications Literature Number: SNAS100 LMX2335/LMX2336/LMX2337 PLLatinum™ Dual Frequency Synthesizer for RF Personal Communications LMX2335 LMX2336 LMX2337 1.1 GHz/1.1 GHz 2.0 GHz/1.1 GHz 550 MHz/550 MHz General Description The LMX2335, LMX2336 and LMX2337 are monolithic, integrated dual frequency synthesizers, including two high frequency prescalers, and are designed for applications requiring two RF phase-lock loops. They are fabricated using National’s ABiC IV silicon BiCMOS process. The LMX2335/36/37 contains two dual modulus prescalers. A 64/65 or a 128/129 prescaler can be selected for each RF synthesizer. A second reference divider chain is included in the IC for improved system noise. LMX2335/36/37, which employ a digital phase locked loop technique, combined with a high quality reference oscillator and loop filters, provide the tuning voltages for voltage controlled oscillators to generate very stable low noise RF local oscillator signals. Serial data is transferred into the LMX2335/36/37 via a three wire interface (Data, Enable, Clock). Supply voltage can range from 2.7V to 5.5V. The LMX2335/36/37 feature very low current consumption; LMX2335/37 −10 mA at 3V, LMX2336 −13 mA at 3V. The LMX2335/37 are available in both a JEDEC SO and TSSOP 16-pin surface mount plastic package. The LMX2336 is available in a TSSOP 20-pin surface mount plastic package. Features n 2.7V to 5.5V operation n Low current consumption n Selectable powerdown mode: ICC = 1 µA (typ) n Dual modulus prescaler: 64/65 or 128/129 n Selectable charge pump TRI-STATE ® mode n Selectable charge pump current levels n Selectable FastLock™ mode Applications n Cellular telephone systems (AMPS, ETACS, RCR-27) n Cordless telephone systems (DECT, ISM, PHS, CT-1+) n Personal Communication Systems (DCS-1800, PCN-1900) n Dual Mode PCS phones n CATV n Other wireless communication systems Functional Block Diagram DS012332-1 TRI-STATE ® is a registered trademark of National Semiconductor Corporation. Fastlock™, MICROWIRE™ and PLLatinum™ are trademarks of National Semiconductor Corporation. © 2000 National Semiconductor Corporation DS012332 www.national.com LMX2335/LMX2336/LMX2337 PLLatinum Dual Frequency Synthesizer for RF Personal Communications September 1996 LMX2335/LMX2336/LMX2337 Connection Diagrams LMX2335/LMX2337 LMX2336 DS012332-2 Order Number LMX2335M/LMX2335TM or LMX2337M/LMX2337TM NS Package Number M16A and MTC16 DS012332-16 Order Number LMX2336TM NS Package Number MTC20 Pin Descriptions Pin No. 2335/37 Pin No. 2336 Pin Name 1 1 VCC1 2 2 Vp1 3 3 Do1 4 4 GND 5 5 fIN1 I First RF prescaler input. Small signal input from the VCO. X 6 fIN1 I RF1 prescaler complementary input. A bypass capacitor should be placed as close as possible to this pin and be connected directly to the ground plane. Capacitor is optional with loss of some sensitivity. I/O Description Power supply voltage input for RF1 analog and RF1 digital circuits. Input may range from 2.7V to 5.5V. VCC1 must equal VCC2. Bypass capacitors should be placed as close as possible to this pin and be connected directly to the ground plane. Power supply for RF1 charge pump. Must be ≥ VCC. O RF1 charge pump output. For connection to a loop filter for driving the input of an external VCO. LMX2335/37: Ground for RF1 analog and RF1 digital circuits. LMX2336: Ground for RF digital circuitry. X 7 GND 6 8 OSCin I Oscillator input. The input has a VCC/2 input threshold and can be driven from an external CMOS or TTL logic gate. 7 9 OSCout O Oscillator output. 8 10 FoLD O Multiplexed output of the programmable or reference dividers, lock detect signals and Fastlock mode. CMOS output (see Programmable Modes). 9 11 Clock I High impedance CMOS Clock input. Data for the various latches is clocked in on the rising edge, into the 20-bit shift register. 10 12 Data I Binary serial data input. Data entered MSB first. The last two bits are the control bits. High impedance CMOS input. 11 13 LE I Load enable high impedance CMOS input. When LE goes HIGH, data stored in the shift registers is loaded into one of the 4 appropriate latches (control bit dependent). X 14 GND X 15 fIN2 I RF2 prescaler complementary input. A bypass capacitor should be placed as close as possible to this pin and be connected directly to the ground plane. Capacitor is optional with loss of some sensitivity. 12 16 fIN2 I RF2 prescaler input. Small signal input from the VCO. 13 17 GND 14 18 Do2 15 19 V p2 www.national.com Ground for RF1 analog circuitry. Ground for RF2 analog circuitry. LMX2335/37: Ground for RF2 analog, RF2 digital, MICROWIRE™, FoLD and Oscillator circuits. LMX2336: Ground for RF2 digital, MICROWIRE, FoLD and Oscillator circuits. O RF2 charge pump output. For connection to a loop filter for driving the input of an external VCO. Power supply for RF2 charge pump. Must be ≥ VCC. 2 (Continued) Pin No. 2335/37 Pin No. 2336 Pin Name 16 20 VCC2 I/O Description Power supply voltage input for RF2 analog. RF2 digital, MICROWIRE, FoLD and Oscillator circuits. Input may range from 2.7V to 5.5V. VCC2 must equal VCC1. Bypass capacitors should be placed as close as possible to this pin and be connected directly to the ground plane. Block Diagram DS012332-17 Note: VCC1 supplies power to the RF1 prescaler, N-counter, R-counter, and phase detector. VCC2 supplies power to the RF2 prescaler, N-counter, phase detector, R-counter along with the OSCin buffer, MICROWIRE, and FoLD. VCC1 and VCC2 are clamped to each other by diodes and must be run at the same voltage level. VP1 and VP2 can be run separately as long as VP ≥ VCC. LMX2335/37 Pin # → 8/10 ← LMX2336 Pin # Pin Name → FoLD X signifies a function not available 3 www.national.com LMX2335/LMX2336/LMX2337 Pin Descriptions LMX2335/LMX2336/LMX2337 Absolute Maximum Ratings (Notes 1, 2) Lead Temperature (solder 4 sec.) (TL) If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Power Supply Voltage VCC VP Voltage on Any Pin with GND = 0V (VI) Storage Temperature Range (TS) +260˚C Recommended Operating Conditions Power Supply Voltage VCC VP Operating Temperature (TA) −0.3V to +6.5V −0.3V to +6.5V −0.3V to VCC +0.3V −65˚C to +150˚C 2.7V to 5.5V VCC to +5.5V −40˚C to +85˚C Electrical Characteristics VCC = 5.0V, Vp = 5.0V; TA = 25˚C, except as specified Symbol ICC Parameter Power Supply Current LMX2335/37 RF1 and RF2 Conditions Value Min VCC = 2.7V to 5.5V Units Typ Max 10 15 mA ICC LMX2335/37 RF1 only 6 8 mA ICC LMX2336 RF1 and RF2 13 18 mA LMX2336 RF1 only fIN1 fIN2 Operating Frequency fIN1 7 LMX2335 LMX2336 fIN2 fIN1 LMX2337 fIN2 ICC-PWDN Powerdown Current LMX2335/2336 11 mA 0.100 1.1 GHz 0.050 1.1 GHz 0.200 2.0 GHz 0.050 1.1 GHz 100 550 MHz 50 550 MHz VCC = 5.5V 1 LMX2337 fOSC Oscillator Frequency fOSC fφ Phase Detector Frequency PfIN 1 and Pfin 2 RF Input Sensitivity 25 100 µA With resonator load on OSCout 5 20 MHz No load on OSCOUT 5 40 MHz 10 MHz VCC = 3.0V, f > 100 MHz −15 +4 VCC = 5.0V, f > 100 MHz −10 +4 VCC = 2.7 to 5.5V, f > 100 MHz −10 0 dBm VOSC Oscillator Sensitivity OSCIN 0.5 VPP VIH High-Level Input Voltage (Note 4) 0.8 VCC V VIL Low-Level Input Voltage (Note 4) 0.2 VCC V IIH High-Level Input Current VIH = VCC = 5.5V (Note 4) −1.0 1.0 µA IIL Low-Level Input Current VIL = 0V, VCC = 5.5V (Note 4) −1.0 1.0 µA 100 µA IIH Oscillator Input Current VIH = VCC = 5.5V IIL Oscillator Input Current VIL = 0V, VCC = 5.5V IDo-SOURCE Charge Pump Output Current VDo = Vp/2, ICPo = LOW (Note 3) −1.25 mA IDo-SINK VDo = Vp/2, ICPo = LOW (Note 3) 1.25 mA IDo-SOURCE VDo = Vp/2, ICPo = HIGH (Note 3) −5.0 mA IDo-SINK VDo = Vp/2, ICPo = HIGH (Note 3) 5.0 mA www.national.com 4 −100 µA (Continued) VCC = 5.0V, Vp = 5.0V; TA = 25˚C, except as specified Symbol IDo-TRI IDo-TRI Parameter Conditions Charge Pump TRI-STATE CURRENT LMX2335 LMX2336 0.5V ≤ VDo ≤ Vp − 0.5V T = 25˚C Charge Pump TRI-STATE CURRENT LMX2337 0.5V ≤ VDo ≤ Vp − 0.5V T = 25˚C VOH High-Level Output Voltage IOH = −500 µA Value Min Typ −5.0 Max 5.0 ±5 Units nA nA VCC − 0.4 V VOL Low-Level Output Voltage IOL = 500 µA tCS Data to Clock Setup Time See Data Input Timing 50 ns ICH Data to Clock Hold Time See Data Input Timing 10 ns tCWH Clock Pulse Width High See Data Input Timing 50 ns tCWL Clock Pulse Width Low See Data Input Timing 50 ns tES Clock to Load Enable Set Up Time See Data Input Timing 50 ns tEW Load Enable Pulse Width See Data Input Timing 50 ns 0.4 V Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Recommended Operating Conditions indicate conditions for which the device is intended to be functional, but do not guarantee specific performanced limits. For guaranteed specifications and test conditions, see the Electrical Characteristics. The guaranteed specifications apply only for the test conditions listed. Note 2: This device is a high performance RF integrated circuit with an ESD rating be done at ESD protected workstations. < 2 keV and is ESD sensitive. Handling and assembly of this device should only Note 3: See PROGRAMMABLE MODES for ICPo description. Note 4: Clock, Data and LE does not include fIN1, fIN2 and OSCin. Typical Performance Characteristics ICC vs VCC LMX2335/37 ICC vs VCC LMX2336 DS012332-19 DS012332-20 5 www.national.com LMX2335/LMX2336/LMX2337 Electrical Characteristics LMX2335/LMX2336/LMX2337 Typical Performance Characteristics (Continued) Charge Pump Current vs Do Voltage ICP = HIGH Charge Pump Current vs Do Voltage ICP = LOW DS012332-21 LMX2335/37 Input Impedance (for SO package) VCC = 2.7V to 5.5V, fIN = 50 MHz to 1.5 GHz DS012332-22 LMX2335/37 Input Impedance (for TSSOP package) LMX2336 Input Impedance VCC = 2.7V to 5.5V, fIN = 50 MHz to 2.5 GHz DS012332-23 Marker Marker Marker Marker 1 2 3 4 = = = = 1 GHz, Real = 94, Imaginary = −118 1.2 GHz, Real = 72, Imaginary = −88 1.5 GHz, Real = 53, Imaginary = −45 500 MHz, Real = 201, Imaginary = −224 www.national.com DS012332-24 Marker Marker Marker Marker 6 1 2 3 4 = = = = 1 GHz, Real = 97, Imaginary = −146 1.89 GHz, Real = 43, Imaginary = −67 2.5 GHz, Real = 30, Imaginary = −33 500 MHz, Real = 189, Imaginary = −233 (Continued) IDo TRI-STATE vs Do Voltage LMX2335/37 RF1 Sensitivity vs Frequency LMX2335/LMX2336/LMX2337 Typical Performance Characteristics DS012332-26 DS012332-25 LMX2335/37 RF2 Sensitivity vs Frequency LMX2336 RF1 Sensitivity vs Frequency DS012332-27 DS012332-28 LMX2336 RF2 Sensitivity vs Frequency Oscillator Input Sensitivity vs Frequency DS012332-29 DS012332-30 7 www.national.com LMX2335/LMX2336/LMX2337 Functional Description The simplified block diagram below shows the 22-bit data register, two 15-bit R Counters and two 18-bit N Counters (intermediate latches are not shown). The data stream is clocked (on the rising edge of Clock) into the DATA register, MSB first. The data stored in the shift register is loaded into one of the 4 appropriate latches on the rising edge of LE. The last two bits are the Control Bits. The DATA is transferred into the counters as follows: Control Bits DATA Location C1 C2 0 0 RF2 R Counter 0 1 RF1 R Counter 1 0 RF2 N Counter 1 1 RF1 N Counter DS012332-1 PROGRAMMABLE REFERENCE DIVIDERS (RF1 AND RF2 R COUNTERS) If the Control Bits are 00 or 01 (00 for RF2 and 01 for RF1) data is transferred from the 22-bit shift register into a latch which sets the 15-bit R Counter. Serial data format is shown below. DS012332-4 15-BIT PROGRAMMABLE REFERENCE DIVIDER RATIO (R COUNTER) Divide R R R R R R R R R R R R R R R Ratio 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 3 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 4 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 • • • • • • • • • • • • • • • • 32767 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Notes: Divide ratios less than 3 are prohibited. Divide ratio: 3 to 32767 R1 to R15: These bits select the divide ratio of the programmable reference divider. Data is shifted in MSB first. www.national.com 8 (Continued) PROGRAMMABLE DIVIDER (N COUNTER) Each N counter consists of the 7-bit swallow counter (A counter) and the 11-bit programmable counter (B counter). If the Control Bits are 10 or 11 (10 for RF2 counter and 11 for RF1 counter) data is transferred from the 20-bit shift register into a 7-bit latch (which sets the Swallow (A) Counter) and an 11-bit latch (which sets the 11-bit programmable (B) Counter), MSB first. Serial data format is shown below. DS012332-5 7-BIT SWALLOW COUNTER DIVIDE RATIO (A COUNTER) Divide Ratio A N 7 N 6 N 5 N 4 N 3 N 2 N 1 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 1 • 127 • 1 • 1 • 1 • 1 • 1 • 1 1 • Notes: Divide ratio: 0 to 127 B≥A A