LP38841MR-ADJ/NOPB

LP38841-ADJ www.ti.com SNVS305C – FEBRUARY 2005 – REVISED APRIL 2013 LP38841-ADJ 0.8A Ultra Low Dropout Adjustable Linear Regulators Stable with Ceramic Output Capacitors Check for Samples: LP38841-ADJ FEATURES DESCRIPTION • • The LP38841-ADJ is a high current, fast response regulator which can maintain output voltage regulation with minimum input to output voltage drop. Fabricated on a CMOS process, the device operates from two input voltages: Vbias provides voltage to drive the gate of the N-MOS power transistor, while Vin is the input voltage which supplies power to the load. The use of an external bias rail allows the part to operate from ultra low Vin voltages. Unlike bipolar regulators, the CMOS architecture consumes extremely low quiescent current at any output load current. The use of an N-MOS power transistor results in wide bandwidth, yet minimum external capacitance is required to maintain loop stability. 1 2 • • • • • • • • • Ideal for Conversion from 1.8V or 1.5V Inputs Designed for Use with Low ESR Ceramic Capacitors Ultra Low Dropout Voltage (75mV @ 0.8A Typ) 0.56V to 1.5V Adjustable Output Range Load Regulation of 0.1%/A (Typ) 30nA Quiescent Current in Shutdown (Typ) Low Ground Pin Current at all Loads Over Temperature/Over Current Protection Available in 8 Lead SO −40°C to +125°C Junction Temperature Range UVLO Disables Output when VBIAS < 3.8V The fast transient response of these devices makes them suitable for use in powering DSP, Microcontroller Core voltages and Switch Mode Power Supply post regulators. The parts are available in the SO package. APPLICATIONS • • • • ASIC Power Supplies In: – Desktops, Notebooks, and Graphics Cards, Servers – Gaming Set Top Boxes, Printers and Copiers Server Core and I/O Supplies DSP and FPGA Power Supplies SMPS Post-Regulators Dropout Voltage: 75 mV (typ) @ 0.8A load current. Quiescent Current: 30 mA (typ) at full load. Shutdown Current: 30 nA (typ) when S/D pin is low. Precision Reference temperature accuracy. Voltage: 1.5% room Typical Application Circuit 10 PF Ceramic BIAS 5V ± 10% LP38841ADJ BIAS 0.1 PF OUT OUT IN IN R1 S/D S/D GND CFF ADJ R2 GND 4.7 PF * GND * Minimum value required if Tantalum capacitor is used (see APPLICATION HINTS). 1 2 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. All trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2005–2013, Texas Instruments Incorporated LP38841-ADJ SNVS305C – FEBRUARY 2005 – REVISED APRIL 2013 www.ti.com Connection Diagram ADJ 1 OUTPUT 2 BIAS 3 GND 4 DAP 8 N/C 7 INPUT 6 SHUTDOWN 5 GND Figure 1. SO-8 – Top View PIN DESCRIPTION Pin Number Pin Name Pin Description 1 ADJ 2 OUTPUT 3 BIAS The Bias pin is used to provide the low current bias voltage to the chip which operates the internal circuitry and provides drive voltage for the N-FET. 4, 5 GND These are the power and analog grounds for the IC. Connect both pins to ground. 6 SHUTDOWN 7 INPUT 8 N/C This pin is floating, it has no internal connection. DAP DAP The SO DAP is a thermal connection that is physically connected to the backside of the die, and is used as a thermal connection to the PC Board copper. The DAP is not a ground pin connection, but should be connected to ground potential. The Adjust pin is used to set the regulated output voltage by connecting it to the external resistors R1 and R2 (see Typical Application Circuit). The regulated output voltage is connected to this pin. This provides a low power shutdown function which turns the regulated output OFF. Tie to VBIAS if this function is not used. The high current input voltage which is regulated down to the nominal output voltage must be connected to this pin. Because the bias voltage to operate the chip is provided separately, the input voltage can be as low as a few hundred millivolts above the output voltage. Block Diagram Vbias VIN UVLO VOUT ADJ + S/D + VREF GND These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. 2 Submit Documentation Feedback Copyright © 2005–2013, Texas Instruments Incorporated Product Folder Links: LP38841-ADJ LP38841-ADJ www.ti.com SNVS305C – FEBRUARY 2005 – REVISED APRIL 2013 ABSOLUTE MAXIMUM RATINGS (1) (2) −65°C to +150°C Storage Temperature Range Lead Temp. (Soldering, 5 seconds) 260°C Human Body Model (3) ESD Rating 2 kV Machine Model (4) 200V Power Dissipation (5) Internally Limited VIN Supply Voltage (Survival) −0.3V to +6V VBIAS Supply Voltage (Survival) −0.3V to +7V Shutdown Input Voltage (Survival) −0.3V to +7V VADJ -0.3V to +6V IOUT (Survival) (6) Internally Limited −0.3V to +6V Output Voltage (Survival) −40°C to +150°C Junction Temperature (1) Absolute maximum ratings indicate limits beyond which damage to the component may occur. Operating ratings indicate conditions for which the device is intended to be functional, but do not ensure specific performance limits. For ensured specifications, see the ELECTRICAL CHARACTERISTICS. Specifications do not apply when operating the device outside of its rated operating conditions. If Military/Aerospace specified devices are required, please contact the TI Sales Office/ Distributors for availability and specifications. The human body model is a 100 pF capacitor discharged through a 1.5k resistor into each pin. The machine model is a 220 pF capacitor discharged directly into each pin. At elevated temperatures, device power dissipation must be derated based on package thermal resistance and heatsink thermal values. If power dissipation causes the junction temperature to exceed specified limits, the device will go into thermal shutdown. If used in a dual-supply system where the regulator load is returned to a negative supply, the output pin must be diode clamped to ground. (2) (3) (4) (5) (6) OPERATING RATINGS VIN Supply Voltage (VOUT + VDO) to 5.5V Shutdown Input Voltage 0 to +5.5V IOUT 0.8A −40°C to +125°C Operating Junction Temperature Range VBIAS Supply Voltage 4.5V to 5.5V VOUT 0.56V to 1.5V ELECTRICAL CHARACTERISTICS Limits in standard typeface are for TJ = 25°C, and limits in boldface type apply over the full operating temperature range. Unless otherwise specified: VIN = VO(NOM) + 1V, VBIAS = 4.5V, IL = 10 mA, CIN = 10 µF CER, COUT = 22 µF CER, VS/D = VBIAS. Min/Max limits are specified through testing, statistical correlation, or design. Symbol VADJ IADJ Parameter Adjust Pin Voltage Adjust Pin Bias Current Conditions 10 mA < IL < 0.8A VO(NOM) + 1V ≤ VIN ≤ 5.5V 4.5V ≤ VBIAS ≤ 5.5V MAX 0.552 0.56 0.568 0.543 0.577 1 0.01 Output Voltage Line Regulation (2) VO(NOM) + 1V ≤ VIN ≤ 5.5V ΔVO/ΔIL Output Voltage Load Regulation (3) 10 mA < IL < 0.8A VDO Dropout Voltage (4) IL = 0.8A (4) TYP (1) 10 mA < IL < 0.8A VO(NOM) + 1V ≤ VIN ≤ 5.5V 4.5V ≤ VBIAS ≤ 5.5V ΔVO/ΔVIN (1) (2) (3) MIN Units V µA %/V 0.1 0.4 1.3 %/A 75 120 205 mV Typical numbers represent the most likely parametric norm for 25°C operation. Output voltage line regulation is defined as the change in output voltage from nominal value resulting from a change in input voltage. Output voltage load regulation is defined as the change in output voltage from nominal value as the load current increases from no load to full load. Dropout voltage is defined as the minimum input to output differential required to maintain the output with 2% of nominal value. Submit Documentation Feedback Copyright © 2005–2013, Texas Instruments Incorporated Product Folder Links: LP38841-ADJ 3 LP38841-ADJ SNVS305C – FEBRUARY 2005 – REVISED APRIL 2013 www.ti.com ELECTRICAL CHARACTERISTICS (continued) Limits in standard typeface are for TJ = 25°C, and limits in boldface type apply over the full operating temperature range. Unless otherwise specified: VIN = VO(NOM) + 1V, VBIAS = 4.5V, IL = 10 mA, CIN = 10 µF CER, COUT = 22 µF CER, VS/D = VBIAS. Min/Max limits are specified through testing, statistical correlation, or design. Symbol IQ(VIN) Parameter Quiescent Current Drawn from VIN Supply Conditions MIN 10 mA < IL < 0.8A VS/D ≤ 0.3V IQ(VBIAS) Quiescent Current Drawn from VBIAS Supply 10 mA < IL < 0.8A VS/D ≤ 0.3V UVLO VBIAS Voltage Where Regulator Output Is Enabled ISC Short-Circuit Current TYP (1) MAX Units 30 35 40 mA 0.06 1 30 µA 2 4 6 mA 0.03 1 30 µA 3.8 V VOUT = 0V 2.6 A Output = ON 0.7 Shutdown Input VSDT Output Turn-off Threshold Output = OFF 0.3 0.7 Td (OFF) Turn-OFF Delay RLOAD X COUT