LP3913
www.ti.com
SNVS489I – NOVEMBER 2006 – REVISED SEPTEMBER 2013
LP3913 Power Management IC for Flash Memory-Based Portable Media Players
Check for Samples: LP3913
FEATURES
APPLICATIONS
•
•
•
•
1
2
•
•
•
•
•
•
•
•
•
•
•
•
2 Low-Dropout Regulators -- LDO1 is Used for
General Purpose Applications, LDO2 is Used
for Low-Noise Analog Applications. Both
LDOs Have Programmable Output Voltages.
Green and Red LED Charger Status Drivers
4-Channel 8-Bit Dual Slope A/D Converter
3 High-Efficiency DVS Buck Converters
400 kHz I2C Compatible Interface
Linear Constant-Current/Constant-Voltage
Charger for Single Cell Lithium-Ion Batteries
USB and Adapter Charging
System Power Supply Management
6x6 x 0.8 mm 48 WQFN Package
Voltage and Thermal Supervisory Circuits
Continuous Battery Voltage Monitoring
Interrupt Request Output with 8 Sources
LP3913 is Pin-for-Pin and Software-Compatible
with the LP3910 Hard Drive Based PMIC
KEY SPECIFICATIONS
•
•
•
•
•
•
•
•
•
•
•
•
•
LDO1: 150 mA, 1.2V–3.3V
LDO2: 150 mA, 1.3V–3.3V
Buck1: 600 mA, 0.8V–2.0V
Buck2: 600 mA, 1.8V–3.3V
Buck3: 500 mA, 1.8V–3.3V
50 mΩ Battery Path Resistance
100 mA to 1000 mA Full-Rate Charge Current
Using Wall Adapter
Selectable 0.05C and 0.1C EOC Current
USB Current Limit of 100 mA, 500 mA, and 800
mA
USB Pre-Qual Current of 50 mA
Selectable 4.1V, 4.2V or 4.38V battery
termination voltages
0.35% Battery Termination Accuracy
±1 LSB INL/DNL on 8-bit A/D Converter
Flash-Based Portable Media Players
Portable Gaming Devices
Portable Navigation Systems
DESCRIPTION
The LP3913 is a programmable system power
management unit that is optimized for Flash Memory
based Portable Media Players.
The LP3913 incorporates 2 low-dropout LDO voltage
regulators, 3 integrated Buck DC/DC converters with
Dynamic Voltage Scaling (DVS), a 4-channel 8-bit
A/D converter, and a dual source Li-Ion/polymer
battery charger. The charger has the capability to
charge and maintain a single cell battery from a
regulated wall adapter or USB power. When both
USB and adapter sources are present, then the
adapter source takes precedence and switching
between USB and adapter power sources is
seamless. In addition, the battery charger supports
power routing, which allows system usage
immediately after an external power source has been
detected. The LP3913 also incorporates some
advanced battery management functions such as
battery temperature measurement, reverse current
blocking for USB, LED charger status indication,
thermally regulated internal power FETs, battery
voltage monitoring, over-current protection and a
10–hour safety timer.
The 4-channel A/D converter measures the battery
voltage and charge current, which can be used for
fuel gauging. Two undedicated channels can be used
to measure other analog parameters such as
discharge current, battery temperature, keyboard
resistor scanning and more.
The various IC parameters are programmable
through a 400 kHz I2C compatible interface.
The LP3913 is available in a thermally-enhanced
6x6x0.8 mm 48 WQFN package and operates over
an ambient temperature range of –40°C to +85°C.
1
2
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2006–2013, Texas Instruments Incorporated
LP3913
SNVS489I – NOVEMBER 2006 – REVISED SEPTEMBER 2013
www.ti.com
TYPICAL APPLICATION CIRCUIT
Display
Back
Lighting
Cvin1
1 PF
ISENSE
Rsense 4.64k
AC Adapter
4. 5 - 6.0V
Cvin2
10 PF
VIN1
Cvin3
10 PF
VIN2 VIN3
TFT
backlight
Boost
Cvin4
10 PF
VIN4
VDD1
Cchg _det
4.7 PF
Cvdd
4.7PF
ADC1
VDD2
ADC2
VDD3
ADC
CHG_ DET
Vbus
5V
USBPWR
Cusb
4.7 PF
VBUCK3L1
USB2.0
D+ vbus
DUSB
Controller
Lsw3
2. 2 PH
Linear
Charger
USBSUSP
BUCK 3
VBUCK3L2
USBISEL
Flash
VBUCK3
Csw3
22 PF
CHG
VFB3
ThSD
STAT
Lsw2
2. 2 PH
RED
GREEN
Csw2
10 PF
VFB2
VBATT3
Battery
Monitor
VBATT1
Cbatt
4.7 PF
BUCK1EN
OSC
Lsw1
2. 2 PH
BUCK1
Csw1
10 PF
VFB1
ONOFF
VDDIO
22k
ONSTAT
Logic Control
and Registers
VLDO2
LDO 2
Cldo2
1.0 PF
i2c
Touchpad
VLDO1
1.8 k
I2C_ SDA
sda
22k
22k
POWERACK
vrefhi
cpu
SoC
reset
irq
gpio
GND
iref
VREFH
Cvrefh
0.1 PF
2
scl
IRQB
LDO1
Cldo1
1.0 PF
vddio
gpio
1.8 k
I2C_ SCL
NRST
LDO2EN
1.2V
VBUCK1
TS
Audio Analog
IO
VBATT2
Li-ion/ polymer cell
+
SDRAM / DDR
VBUCK2
BUCK 2
IREF
BCK1GND
BCK2GND BCK3GND1
BCK3GND2
AGND DGND
Riref
121k
Submit Documentation Feedback
Copyright © 2006–2013, Texas Instruments Incorporated
Product Folder Links: LP3913
LP3913
www.ti.com
SNVS489I – NOVEMBER 2006 – REVISED SEPTEMBER 2013
Connection Diagram
Device Connection Diagram
36
35
34
33
32
31
30
29
28
27
26
25
37
24
38
23
39
22
40
21
41
20
42
19
43
18
44
17
45
16
46
15
47
14
48
13
1
2
3
4
5
6
7
8
9
10
11
12
Figure 1. 48 WQFN Package (Top View)
Package Number NJV0048A
Table 1. Additional Application Information
LDO1 (V)
LDO2 (V)
Buck1 (V)
Buck2 (V)
Buck 3 (V)
ICHRG (mA)
LP3913SQ-AA/LP3913SQX-AA
Part Number
2.00
3.30
1.20
3.30
3.30
100
LP3913SQ-AC/LP3913SQX-AC
1.30
3.30
1.30
1.80
3.30
100
LP3913SQ-AD/LP3913SQX-AD
2.00
3.30
1.20
1.80
3.30
100
LP3913SQ-ADJ/LP3913SQX-ADJ
1.80
3.30
ADJ
ADJ
3.30
100
LP3913SQ-AE/LP3913SQX-AE
1.30
3.30
1.30
3.30
3.30
100
LP3913SQ-AR/LP3913SQX-AR
1.80
3.30
1.20
1.80
3.30
1000
Pin Descriptions
Pin #
I/O
Type
Functional Description
1
TS
Name
I
A
Battery temperature sense pin. This pin is normally connected to the thermistor pin of the
battery cell.
2
VBATT1
O
A
Positive battery terminal. This pin must be externally shorted to VBATT2 and VBATT3
3
AGND
G
G
Analog Ground
4
VREFH
O
A
Connection to bypass capacitor for internal high reference
5
LDO2EN
I
D
Digital input to enable/disable LDO2
6
VLDO2
O
A
LDO2 Output
7
VIN1
I
PWR
8
VLDO1
O
A
LDO1 Output
9
POWERACK
I
D
Digital power acknowledgment input (see Power On/Off Sequencing)
10
ISENSE
I
A
A 4.64-kΩ resistor must be connected between this pin and GND. A fraction of the charge
current flows through this resistor to enable the A to D converter to measure the charge
current.
11
ADC2
I
A
Channel 2 input to AD converter
12
ADC1
I
A
Channel 1 input to AD converter
13
IRQB
O
Open
Drain
Power input to LDO1 and LDO2. VIN1 pin must be externally shorted to the VDD pins.
Open drain active low interrupt request
Submit Documentation Feedback
Copyright © 2006–2013, Texas Instruments Incorporated
Product Folder Links: LP3913
3
LP3913
SNVS489I – NOVEMBER 2006 – REVISED SEPTEMBER 2013
Pin #
Name
I/O
Type
14
NRST
O
Open
Drain
15
CHG
O
D
This output indicates that a valid charger supply source (USB adapter) has been detected,
and the IC is charging. (Red LED)
16
STAT
O
D
Battery Status output indicator - Off during CC, 50% duty cycle during CV, 100% duty
cycle with a fully charged Li-ion battery (Green LED)
17
BUCK1EN
I
D
Digital input to enable/disable BUCK1
18
VFB1
I
A
Buck1 Feedback input terminal
19
BCKGND1
G
G
Buck1 Ground
20
VBUCK1
O
A
Buck1 Output
21
VIN2
I
PWR
Power input to BUCK1. VIN2 pin must be externally shorted to the VDD pins.
22
VIN3
I
PWR
Power input to BUCK2. VIN3 pin must be externally shorted to the VDD pins.
23
VBUCK2
O
A
Buck2 Output
24
BCKGND2
G
G
Buck2 Ground
25
VFB2
I
A
Buck2 Feedback input terminal
26
ONOFF
I
D
Power ON/OFF pin configured either as level (High or Low) triggered or edge (High or
Low) triggered.
27
I2C_SCL
I
D
I2C-compatible interface clock terminal
28
VDDIO
I
D
Supply to input / output stages of digital I/O
I2C-compatible interface data terminal
2
Functional Description
Open drain active low reset during Standby
29
I C_SDA
I/O
D
30
ONSTAT
O
Open
Drain
31
VFB3
I
A
Buck3 Feedback input terminal
32
VBUCK3
O
A
Buck3Output voltage
33
VBUCK3L2
I
A
Buck3 inductor
34
BCK3GND1
G
G
Buck3t high current ground
35
VBUCK3L1
I
A
Buck3 inductor
36
VIN4
I
PWR
37
USBSUSP
I
D
This pin needs to be pulled high during USB suspend mode.
38
USBISEL
I
D
Pulling this pin low limits the USB charge current to 100 mA. Pulling this pin high limits the
USB charge current to 500 mA.
39
BUCK3GND2
G
G
Buck3 Core Ground
40
DGND
G
G
Digital ground
41
VDD3
I
PWR
Power input to supply application. This pin must be externally shorted to VDD1 and
VDD2.
42
VDD2
I
PWR
Power input to supply application This pin must be externally shorted to VDD1 and VDD3.
43
VBATT3
O
A
Positive battery terminal. This pin must be externally shorted to V\BATT1 and VBATT2.
44
VBATT2
O
A
Positive battery terminal. This pin must be externally shorted to VBATT1 and VBATT3.
45
USBPWR
I
PWR
USB power input pin
46
VDD1
I
PWR
Power input to supply application This pin is shorted to VDD2 and VDD3.
47
CHG_DET
I
A
Wall adapter power input pin
48
IREF
I
A
A 121 kΩ resistor must be connected between this pin and AGND. The resistor value
determines the reference current for the internal bias generator.
A: Analog Pin D: Digital Pin
4
www.ti.com
G: Ground Pin
Open Drain output that reflects the debounced state of ONOFF pin.
Power input to Buck3. VIN4 pin must be externally shorted to the VDD pins.
PWR: Power Pin
I: Input Pin
Submit Documentation Feedback
I/O: Input/Output Pin
O: Output Pin
Copyright © 2006–2013, Texas Instruments Incorporated
Product Folder Links: LP3913
LP3913
www.ti.com
SNVS489I – NOVEMBER 2006 – REVISED SEPTEMBER 2013
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
ABSOLUTE MAXIMUM RATINGS
(1) (2) (3) (4)
Supply voltage range CHG_DET
−0.3V to +6.5V
Voltage range USBPWR,
VIN1,VIN2,VIN3,VIN4, VDD1,VDD2,VDD3
−0.3V to +6.2V
−0.3V to +5V
Battery voltage range VBATT1, 2, 3
−0.3V to VDD +0.3V
All other pins
−45ºC to +150ºC
Storage Temperature Range
Power Dissipation (TA = 70°C
(5)
):
2.6W
ESD Rating (6)
Human Body Model:
Machine Model:
(1)
(2)
(3)
(4)
(5)
(6)
2.0 kV
200V
Absolute Maximum Ratings indicate limits beyond which damage to the component may occur. Operating Ratings are conditions under
which operation of the device is specified. Operating Ratings do not imply performance limits. For performance limits and associated test
conditions, see the Electrical Characteristics tables.
All voltages are with respect to the potential at the GND pin.
In applications where high power dissipation and/or poor package thermal resistance is present, the maximum ambient temperature may
have to be derated. Maximum ambient temperature (TA-MAX) is dependent on the maximum operating junction temperature (TJ-MAX-OP =
125°C), the maximum power dissipation of the device in the application (PD-MAX), and the junction-to-ambient thermal resistance of the
part/package in the application (θJA), as given by the following equation: TA-MAX = TJ-MAX-OP − (θJA × PD-MAX).
If Military/Aerospace specified devices are required, please contact the TI Sales Office/Distributors for availability and specifications.
Internal thermal shutdown circuitry protects the device from permanent damage. Thermal shutdown engages at TJ = 160°C (typ.) and
disengages at TJ = 140°C (typ.).
The Human body model is a 100 pF capacitor discharged through a 1.5 kΩ resistor into each pin. The machine model is a 200 pF
capacitor discharged directly into each pin. MIL-STD-883 3015.7.
RECOMMENDED OPERATING CONDITIONS (1)
(2) (3)
CHG_DET
4.5V to 6.0V
USBPWR
4.35V to 6.0V
VBATT1, 2, 3
0V to 4.5V
VIN1, VIN2, VIN3, VIN4, VDD1, VDD2, VDD3
2.5V to 6.0V
VDDIO
2.5V to VDD
Junction Temperature (TJ) Range
−40°C to +125°C
Ambient Temperature (TA) Range
−40°C to +85°C
Power Dissipation for TJjMAX and TAMAX
(1)
(2)
(3)
1.6W
Junction-to-ambient thermal resistance is highly application and board-layout dependent. In applications where high maximum power
dissipation exists, special care must be paid to thermal dissipation issues in board design.
Min and Max limits are specified by design, test, or statistical analysis. Typical numbers represent the most likely norm.
Typical values and limits appearing in normal type for TJ = 25°C. Limits appearing in boldface type apply over the entire junction
temperature range for operation, −40°C to +125°C.
THERMAL INFORMATION (1)
Junction-to-Ambient Thermal Resistance (θJA),
48-pin WQFN NJV0048A Package (2)
(1)
(2)
25°C/W
In applications where high power dissipation and/or poor package thermal resistance is present, the maximum ambient temperature may
have to be derated. Maximum ambient temperature (TA-MAX) is dependent on the maximum operating junction temperature (TJ-MAX-OP =
125°C), the maximum power dissipation of the device in the application (PD-MAX), and the junction-to-ambient thermal resistance of the
part/package in the application (θJA), as given by the following equation: TA-MAX = TJ-MAX-OP − (θJA × PD-MAX).
Min and Max limits are specified by design, test, or statistical analysis. Typical numbers represent the most likely norm.
Submit Documentation Feedback
Copyright © 2006–2013, Texas Instruments Incorporated
Product Folder Links: LP3913
5
LP3913
SNVS489I – NOVEMBER 2006 – REVISED SEPTEMBER 2013
www.ti.com
GENERAL ELECTRICAL CHARACTERISTICS
Unless otherwise noted, VDD = 5V, VBATT = 3.6V. Typical values and limits appearing in normal type apply for TJ = 25°C.
Limits appearing in boldface type apply over the entire junction temperature range for operation, TJ = 0°C to +125°C.
(1) (2) (3) (4)
Symbol
IQ_BATT
Parameter
Conditions
Battery Standby Supply
Current
Min
All circuits off except for
POR and battery monitor.
No adapter or USB power
connected.
Typ
Max
Units
6
20
µA
VPOR
Power-On Reset Threshold VDD Falling Edge
1.9
V
TSD
Thermal Shutdown
Threshold
160
°C
TSDH
Themal Shutdown
Hysteresis
20
°C
TTH-ALERT
Thermal Interrupt
Threshold
115
°C
VDDIO
IO Supply
FCLK
Internal System Clock
Frequency
(1)
(2)
(3)
(4)
2.5
VDD
2
V
MHz
All voltages are with respect to the potential at the GND pin.
Min and Max limits are specified by design, test, or statistical analysis. Typical numbers represent the most likely norm.
Low ESR Surface-Mount Ceramic Capacitors (MLCCs) are used in setting electrical characteristics.
Specified by design. Not production tested
I2C INTERFACE ELECTRICAL CHARACTERISTICS
Unless otherwise noted, VDDIO = 3.6V. Typical values and limits appearing in normal type apply for TJ = 25°C. Limits
appearing in boldface type apply over the entire junction temperature range for operation, TJ = 0°C to +125°C. (1) (2) (3) (4)
Symbol
Parameter
Conditions
VIL
Low Level Input Voltage
I2C_SDA & I2C_SCL
VIH
High Level Input Voltage
I2C_SDA & I2C_SCL
VOL
Low Level Output Voltage
I2C_SDA & I2C_SCL
VHYS
Schmitt Trigger Input Hysterisis
I2C_SDA & I2C_SCL
FCLK
Clock Frequency
Typ
Max
Units
0.3VDDI
O
V
0.7VDDI
O
0
V
0.2VDDI
O
0.1VDDI
O
Bus-Free Time between START
and STOP
tHOLD
Hold Time Repeated START
Condition
(4)
tCLK-LP
CLK Low Period
tCLK-HP
tSU
V
V
400
(4)
tBF
Min
kHz
1.3
µs
0.6
µs
(4)
1.3
µs
CLK High Period
(4)
0.6
µs
Set-up Time Repeated START
Condition
(4)
0.6
µs
tDATA-HOLD
Data Hold Time
(4)
0
µs
tDATA-SU
Data Set-up Time
(4)
100
ns
tSU
Set-Up Time for STOP Condition
(4)
0.6
µs
tTRANS
Maximum Pulse Width of Spikes
That Must Be Suppressed by the
Input Filter of Both Data and
CLK Signals.
(4)
50
µs
(1)
(2)
(3)
(4)
6
All voltages are with respect to the potential at the GND pin.
Min and Max limits are specified by design, test, or statistical analysis. Typical numbers represent the most likely norm.
Low ESR Surface-Mount Ceramic Capacitors (MLCCs) are used in setting electrical characteristics.
Specified by design. Not production tested.
Submit Documentation Feedback
Copyright © 2006–2013, Texas Instruments Incorporated
Product Folder Links: LP3913
LP3913
www.ti.com
SNVS489I – NOVEMBER 2006 – REVISED SEPTEMBER 2013
LI-ION BATTERY CHARGER ELECTRICAL CHARACTERISTICS
Unless otherwise noted, VDD = 5.0V,VBATT = 3.6V, CBATT = 4.7 µF, CCHG_DET = 10 µF, RIREF = 121 kΩ. Typical values and
limits appearing in normal type apply for TJ = 25°C. Limits appearing in boldface type apply over the entire junction
temperature range for operation, TJ = 0°C to +125°C. (1) (2) (3) (4) (5)
Symbol
Parameter
Conditions
VUSB
Minimum External USB
Supply Soltage
VUSB_HYST
USBPWR Detect
Hysteresis
CHG_DET
Minimum External
Adapter Supply Voltage
Range
USB Current Limit = 500 mA
Min
Typ
Max
Units
4.15
4.25
4.35
V
50
Adapter Current Limit = 1A
VFWD Schottky = 350 mV
4.4
4.5
mV
4.6
VCHG_HYST
CHG_DET Input
Hysteresis
150
IUSB_SUSP
Quiescent Current in USB USB Suspend Mode,
Suspend Mode
VUSB = 5.0V
USBSUSP = USBPWR
USBISEL = 0V
30
60
VTERM_TOL
ICHG_WA
ICHG_USB
Battery Charge
Termination Voltage
Tolerance
VFULL_RATE
4.2V
4.1V
4.38V
+0.35
+0.5
+0.5
TA = 0°C to 125°C,
IPROG = 500 mA,
ICHG = 50 mA
−1
−1.5
−1.5
4.2V
4.1V
4.38V
+1
+1.5
+1.5
Full-rate Charging Current CHG_DET = 5.25V
from Wall Adapter Input
VBATT = 3.6V
(See Full-Rate Charging
IPROG = 500 mA
Mode)
450
500
550
mA
Full-rate Charging Current USB = 5V
from USBPWR Input (See VBATT = 3.6V
Full-Rate Charging Mode) IPROG = 500 mA
USB_ISEL = 800 mA
450
500
550
mA
USB = 5V
VBATT = 3.6V
IPROG = 500 mA
USB_ISEL = 500 mA
405
450
495
mA
USB_ISEL = 100 mA
USB_ISEL= 500 mA
USB_ISEL = 800 mA
90
450
720
95
475
760
100
500
800
mA
VBATT = 2.5V, Wall Adapter
Charge Current.
Percentage of Programmed
Full Rate Current.
8
10
12
VBATT = 2.5V, USB Charge
Current
40
50
60
mA
VBATT Rising, Transition from
Pre-Qualification to Full-rate
Charging
2.75
2.85
2.95
V
2.82
2.87
2.93
V
45°C CHSPV Reg D3 = 0
0.315
0.33
0.345
50°C CHSPV Reg D3 = 1
0.255
0.27
0.285
7.75
8.00
8.25
Pre-qualification Current
Full-rate Qualification
Threshold
Upper TS Comparator
Limit
VTH_L
Lower TS Comparator
Limit
(1)
(2)
(3)
(4)
(5)
µA
-0.35
−0.5
−0.5
VTH_H
ITSENSE
mV
TA = 25°C,
IPROG = 500 mA
ICHG = 50 mA
USB ILIMIT
IPREQUAL
V
Battery Temperature
Sense Current
%
%
V
µA
All voltages are with respect to the potential at the GND pin.
Junction-to-ambient thermal resistance is highly application and board-layout dependent. In applications where high maximum power
dissipation exists, special care must be paid to thermal dissipation issues in board design.
Min and Max limits are specified by design, test, or statistical analysis. Typical numbers represent the most likely norm.
Low ESR Surface-Mount Ceramic Capacitors (MLCCs) are used in setting electrical characteristics.
Typical values and limits appearing in normal type for TJ = 25°C. Limits appearing in boldfacetype apply over the entire junction
temperature range for operation, −40°C to +125°C.
Submit Documentation Feedback
Copyright © 2006–2013, Texas Instruments Incorporated
Product Folder Links: LP3913
7
LP3913
SNVS489I – NOVEMBER 2006 – REVISED SEPTEMBER 2013
www.ti.com
LI-ION BATTERY CHARGER ELECTRICAL CHARACTERISTICS (continued)
Unless otherwise noted, VDD = 5.0V,VBATT = 3.6V, CBATT = 4.7 µF, CCHG_DET = 10 µF, RIREF = 121 kΩ. Typical values and
limits appearing in normal type apply for TJ = 25°C. Limits appearing in boldface type apply over the entire junction
temperature range for operation, TJ = 0°C to +125°C. (1)(2)(3)(4)(5)
Symbol
TREG
Parameter
Conditions
Min
Typ
Max
Units
105
115
125
°C
Min
Typ
Max
Units
IPROG = 500 mA,
10% EOC Setting
40
50
60
mA
IPROG = 500 mA
5% EOC Setting
20
25
30
mA
3.82
3.94
4.14
3.9V
4.0V
4.2 V
3.94
4.06
4.26
V
Regulated Charger
Junction Temperature
DETECTION AND TIMING
Symbol
IEOC
Parameter
Conditions
End-of-Charge Current
VRESTARTl
Battery Restart Charging
Voltage
VTERM = 4.1V
VTERM = 4.2V
VTERM = 4.38V
TCHG_IN
Deglitch Adapter Insertion
28
32
36
ms
TUSB
Deglitch USB Power
Insertion
28
32
36
ms
TPQ_FULL
Deglitch Time for Prequalification to Full-rate
Charge Transition
8
10
12
ms
Deglitch Time for Full-rate
to Pre-qualification
Transition
8
10
12
ms
Deglitch Time for VBATT
Falling below VBATTLOW
Threshold
4
5
6
ms
Deglitch Time for VBATT
Rising above VBATTLOW
Threshold
4
5
6
ms
Deglitch Time for Recovery
from Battery Temperature
Fault
8
10
12
ms
TONOFF_F
Deglitching on Falling
Edge of ONOFF Pin
28
32
36
ms
TONOFF_R
Deglitching on Rising Edge
of ONOFF Pin
28
32
36
ms
TRESTART
Deglitching on Falling
VBATT Crossing VRESTART
8
10
12
ms
TCCCV
Deglitching of CC->CV
Charging Transition
8
10
12
ms
TCvEOC
Deglitching of CV->EOC
(End of Charge)
8
10
12
ms
TPOWERACK
Deglitching of POWERACK
Pin
4
5
6
ms
TTSHD
Deglitching of Thermal
Shutdown
TTOPOFF
Topoff Timer
17
21
25
min
T10HR
10 Hour Safety Timer
9
10
11
hours
T1HR
1 Hour Prequal Safety
Timer
0.9
1
1.1
hour
TFULL_PQ
TBATTLOWF
TBATTLOWR
TBATTEMP
8
2
Submit Documentation Feedback
ms
Copyright © 2006–2013, Texas Instruments Incorporated
Product Folder Links: LP3913
LP3913
www.ti.com
SNVS489I – NOVEMBER 2006 – REVISED SEPTEMBER 2013
OUTPUTS ELECTRICAL CHARACTERISTICS: CHG, STAT
Unless otherwise noted, VDD = 5V, VBATT = 3.6V. CBATT = 4.7 µF, CCHG_DET = 10 µF. Typical values and limits appearing in
normal type apply for TJ = 25°C. Limits appearing in boldface type apply over the entire junction temperature range for
operation, TJ = 0°C to +125°C. (1) (2) (3) (4) (5)
Symbol
ILED
Parameter
Output High Level
ILED
Output High Level
ILEAKAGE
Leakage Current
LEDFREQ
Blinking Frequency
(1)
(2)
(3)
(4)
(5)
Conditions
Min
Typ
Max
Units
VLED = 2.0V
CHSPV Register (02)h bit 5
=1
4
5
6
mA
VLED = 2.0V
CHSPV Register (02)h bit 5
=0
8
10
12
mA
0.1
5
µA
1
1.2
Hz
VLED = 1.5V, LED off
0.8
All voltages are with respect to the potential at the GND pin.
Junction-to-ambient thermal resistance is highly application and board-layout dependent. In applications where high maximum power
dissipation exists, special care must be paid to thermal dissipation issues in board design.
Min and Max limits are specified by design, test, or statistical analysis. Typical numbers represent the most likely norm.
Low ESR Surface-Mount Ceramic Capacitors (MLCCs) are used in setting electrical characteristics.
Typical values and limits appearing in normal type for TJ = 25°C. Limits appearing in boldfacetype apply over the entire junction
temperature range for operation, −40°C to +125°C.
OUTPUTS ELECTRICAL CHARACTERISTICS: NRST, IRQB, ONSTAT
Unless otherwise noted, VDD = 5V, VBATT = 3.6V. CBATT = 4.7 µF, CCHG_DET = 10 µF. Typical values and limits appearing in
normal type apply for TJ = 25°C. Limits appearing in boldface type apply over the entire junction temperature range for
operation, TJ = 0°C to +125°C. (1) (2) (3) (4) (5)
Symbol
Parameter
Conditions
VOL
Output Low Level
IOL = 4 mA
ILEAKAGE
Leakage Current
VDD = 2.5V, Output Logic
High
(1)
(2)
(3)
(4)
(5)
Min
Typ
−1
Max
Units
0.4
V
1
µA
All voltages are with respect to the potential at the GND pin.
Junction-to-ambient thermal resistance is highly application and board-layout dependent. In applications where high maximum power
dissipation exists, special care must be paid to thermal dissipation issues in board design.
Min and Max limits are specified by design, test, or statistical analysis. Typical numbers represent the most likely norm.
Low ESR Surface-Mount Ceramic Capacitors (MLCCs) are used in setting electrical characteristics.
Typical values and limits appearing in normal type for TJ = 25°C. Limits appearing in boldfacetype apply over the entire junction
temperature range for operation, −40°C to +125°C.
INPUTS ELECTRICAL CHARACTERISTICS: USBSUSP, USBISEL
Unless otherwise noted, VUSB = 5V, VBATT = 3.6V. CBATT = 4.7 µF, CCHG_DET = 10 µF. Typical values and limits appearing in
normal type apply for TJ = 25°C. Limits appearing in boldface type apply over the entire junction temperature range for
operation, TJ = 0°C to +125°C. (1) (2) (3) (4) (5) (6)
Symbol
Parameter
VIL
Input Low Level
VIH
Input High Level
ILEAKAGE
Input Leakage
(1)
(2)
(3)
(4)
(5)
(6)
Conditions
Min
Typ
Max
Units
0.3*VUSB
V
1
µA
0.7*VUSB
−1
V
All voltages are with respect to the potential at the GND pin.
Junction-to-ambient thermal resistance is highly application and board-layout dependent. In applications where high maximum power
dissipation exists, special care must be paid to thermal dissipation issues in board design.
Min and Max limits are specified by design, test, or statistical analysis. Typical numbers represent the most likely norm.
Low ESR Surface-Mount Ceramic Capacitors (MLCCs) are used in setting electrical characteristics.
Typical values and limits appearing in normal type for TJ = 25°C. Limits appearing in boldfacetype apply over the entire junction
temperature range for operation, −40°C to +125°C.
LDO2EN, BUCK1EN, and USBSUSP have weak internal pull downs while pins POWERACK, ONOFF do not have this.
Submit Documentation Feedback
Copyright © 2006–2013, Texas Instruments Incorporated
Product Folder Links: LP3913
9
LP3913
SNVS489I – NOVEMBER 2006 – REVISED SEPTEMBER 2013
www.ti.com
INPUTS ELECTRICAL CHARACTERISTICS: POWERACK, ONOFF, LDO2EN, BUCK1EN
Unless otherwise noted, VDD = 5V, VBATT = 3.6V. CBATT = 4.7 µF, CCHG_IN = 10 µF. Typical values and limits appearing in
normal type apply for TJ = 25°C. Limits appearing in boldface type apply over the entire junction temperature range for
operation, TJ = 0°C to +125°C. (1) (2) (3) (4) (5) (6)
Symbol
Parameter
Conditions
Min
VIL
Input Low Level
VIH
Input High Level
1.4
ILEAKAGE
Input Leakage
−1
(1)
(2)
(3)
(4)
(5)
(6)
Typ
Max
Units
0.4
V
V
1
µA
All voltages are with respect to the potential at the GND pin.
Junction-to-ambient thermal resistance is highly application and board-layout dependent. In applications where high maximum power
dissipation exists, special care must be paid to thermal dissipation issues in board design.
Min and Max limits are specified by design, test, or statistical analysis. Typical numbers represent the most likely norm.
Low ESR Surface-Mount Ceramic Capacitors (MLCCs) are used in setting electrical characteristics.
Typical values and limits appearing in normal type for TJ = 25°C. Limits appearing in boldfacetype apply over the entire junction
temperature range for operation, −40°C to +125°C.
LDO2EN, BUCK1EN, and USBSUSP have weak internal pull downs while pins POWERACK, ONOFF do not have this.
LDO1: LOW DROPOUT LINEAR REGULATORS
Unless otherwise noted, VIN1 = 3.6V, IMAX = 150 mA, VOUT = Default Value, CVDD = 10 µF, CLDO1 = 1.0 µF, ESR = 5 mΩ–500
mΩ, CVREFH = 100 nF. Typical values and limits appearing in normal type apply for TJ = 25°C. Limits appearing in boldface
type apply over the entire junction temperature range for operation, 0°C to +125°C.
Symbol
Parameter
Conditions
VIN1
Operational Voltage Range
VOUT Range
Output Voltage
Programming Range
VOUT Accuracy
Output Voltage Accuracy
ΔVOUT
Min
Max
Units
2.5
Typ
6.0
V
TA = 25°C
1.2V–3.3V in 100 mV Steps
1.2
3.3
V
1 mA ≤ IOUT ≤ IMAX, Over
Full Line and Load
Regulation.
VOUT = Default Value.
−3
3
%
Line Regulation
VIN = (VOUT + 500 mV) to
5.5V, Load Current = IMAX
3
mV
Load Regulation
VIN = 3.6V,
Load Current = 1 mA to IMAX
10
mV
ISC
Short Circuit Current Limit
VOUT = 0V
VIN – VOUT
Dropout Voltage
Load Current = IMAX
60
PSRR
Power Supply Ripple
Rejection
F = 10 kHz, Load Current =
IMAX
30
RSHUNT
LDO Output Impedance
LDO Disabled, VOUT =
Default Value
600
750
mA
150
mV
dB
200
Ω
LDO2: LOW DROPOUT LINEAR REGULATOR
Unless otherwise noted VIN1 = 3.6V, IMAX = 150 mA, VOUT = Default Value, CVDD = 10.0 µF, CLDO2 = 1.0 µF, ESR = 5 mΩ–500
mΩ, CVREFH = 100 nF. Typical values and limits appearing in normal type apply for TJ = 25°C. Limits appearing in boldface
type apply over the entire junction temperature range for operation, 0°C to +125°C.
Symbol
Parameter
Conditions
Max
Units
2.5
6.0
V
TA = 25°C
1.3V–3.3V in 100 mV Steps
1.3
3.3
V
Output Voltage Accuracy
(Default VOUT)
1 mA ≤ IOUT ≤ IMAX, Over
Full Line and Load
Regulation.
−3
3
%
Line Regulation
VIN = (VOUT + 500 mV) to
5.5V,
Load Current = IMAX
3
mV
Load Regulation
VIN = 3.6V,
Load Current = 1 mA to IMAX
10
mV
Short Circuit Current Limit
VOUT = 0V
750
mA
VIN2
Operational Voltage Range
VOUT Range
Output Voltage
Programming Range
VOUT Accuracy
ΔVOUT
ISC
10
Submit Documentation Feedback
Min
600
Typ
Copyright © 2006–2013, Texas Instruments Incorporated
Product Folder Links: LP3913
LP3913
www.ti.com
SNVS489I – NOVEMBER 2006 – REVISED SEPTEMBER 2013
LDO2: LOW DROPOUT LINEAR REGULATOR (continued)
Unless otherwise noted VIN1 = 3.6V, IMAX = 150 mA, VOUT = Default Value, CVDD = 10.0 µF, CLDO2 = 1.0 µF, ESR = 5 mΩ–500
mΩ, CVREFH = 100 nF. Typical values and limits appearing in normal type apply for TJ = 25°C. Limits appearing in boldface
type apply over the entire junction temperature range for operation, 0°C to +125°C.
Typ
Max
Units
VIN – VOUT
Symbol
Dropout Voltage
Parameter
Load Current = IMAX
Conditions
60
150
mV
PSRR
Power Supply Ripple
Rejection
F = 1 kHz, Load Current =
IMAX
50
F = 10 kHz, Load Current =
IMAX
35
eN
Analog Supply Output
Noise Voltage
10 Hz < F < 100 kHz
RSHUNT
LDO Output Impedance
LDO Disabled, VOUT =
Default Value
Min
dB
50
µVrms
Ω
200
BUCK1 CONVERTER ELECTRICAL CHARACTERISTICS
Unless otherwise noted, VIN2 = 3.6 V, VOUT = default value, CVIN2 = 10 µF, CSW1 = 10 µF, LSW1 = 2.2 µH Typical values and
limits appearing in normal type apply for TJ = 25°C. Limits appearing in boldface type apply over the entire junction
temperature range for operation, 0°C to +125°C. Modulation mode is PWM mode with automatic switch to PFM at light loads.
Symbol
Parameter
Conditions
VIN2
Input Voltage
VOUT Range
Output Voltage
Programming Range
0.80V–2.00V in 50 mV Steps
ΔVOUT
Static Output Voltage
Tolerance
IOUT = 200 mA, Including
Line and Load Regulation
Line Regulation
IOUT = 10 mA
VIN2 = 2.5V − VDD
Load Regulation
100 mA < IOUT < 300 mA
IOUT
Min
Max
Units
2.7
6.0
V
0.8
2.0
V
−3
3
%
Continuous Output
Current
600
Peak Output Current
Limit
850
IPFM
Max ILOAD, PFM
Mode
IQ
Quiescent Current
Typ
0.2
%/V
0.002
%/mA
mA
1000
Internal Oscillator
Frequency
η
Peak Efficiency
TON
Turn-on Time
(1)
mA
75
IOUT = 0 mA
30
Buck1 Disabled
FOSC
1150
mA
90
µA
1
PWM Mode
2
MHz
90
To 95% Level
(1)
%
1
ms
Specified by design. Not production tested.
BUCK2 CONVERTER ELECTRICAL CHARACTERISTICS
Unless otherwise noted, VIN3 = 3.6V, VOUT = default value, CVIN3 = 10 µF, CSW1 = 10 µF, LSW2 = 2.2 µH Typical values and
limits appearing in normal type apply for TJ = 25°C. Limits appearing in boldface type apply over the entire junction
temperature range for operation, 0°C to +125°C. Modulation mode is PWM mode with automatic switch to PFM at light loads.
Symbol
Parameter
Conditions
Min
Typ
Max
Units
VIN3
Input Voltage
2.7
6.0
V
VOUT Range
Output Voltage
Programming Range
1.80V–3.30V in 100 mV
Steps
1.8
3.3
V
ΔVOUT
Static Output Voltage
Tolerance
IOUT = 200 mA, Including
Line and Load Regulation
−3
3
%
Line Regulation
IOUT = 10 mA
VIN3 = 2.5V − VDD
Load Regulation
100 mA < IOUT < 300 mA
0.2
%/V
0.002
%/mA
Submit Documentation Feedback
Copyright © 2006–2013, Texas Instruments Incorporated
Product Folder Links: LP3913
11
LP3913
SNVS489I – NOVEMBER 2006 – REVISED SEPTEMBER 2013
www.ti.com
BUCK2 CONVERTER ELECTRICAL CHARACTERISTICS (continued)
Unless otherwise noted, VIN3 = 3.6V, VOUT = default value, CVIN3 = 10 µF, CSW1 = 10 µF, LSW2 = 2.2 µH Typical values and
limits appearing in normal type apply for TJ = 25°C. Limits appearing in boldface type apply over the entire junction
temperature range for operation, 0°C to +125°C. Modulation mode is PWM mode with automatic switch to PFM at light loads.
Symbol
IOUT
Parameter
Conditions
Min
Continuous Output
Current
600
Peak Output Current
Limit
850
IPFM
Max ILOAD, PFM
Mode
IQ
Quiescent Current
Typ
1000
Internal Oscillator
Frequency
η
Peak Efficiency
TON
Turn-on Time
(1)
1150
75
IOUT = 0 mA
30
90
2
(1)
µA
MHz
90
To 95% Level
mA
mA
1
PWM Mode
Units
mA
Buck2 Disabled
FOSC
Max
%
1
ms
Specified by design. Not production tested.
BUCK3 ELECTRICAL CHARACTERISTICS
Unless otherwise noted, VIN4 = 3.6V, CVIN4 = 10 µF, CBB = 22 µF, LBB = 2.2 µH Typical values and limits appearing in normal
type apply for TJ = 25°C. Limits appearing in boldface type apply over the entire junction temperature range for operation,
0°C to +125°C. Modulation mode is PWM mode with automatic switch to PFM at light loads.
Symbol
Parameter
Conditions
Min
Typ
Max
Units
VIN4
Input Voltage
IOUTMAX = 500 mA
2.7
5.7
V
VOUT Range
Output Voltage
Programming Range
1.80V – 3.30V in 50 mV
Steps
1.8
3.3
V
ΔVOUT
Static Output Voltage
Tolerance
IOUT = 0 mA–500 mA,
Including Line and Load
Regulation
−4
4
%
Line Regulation
IOUT = 10 mA
Load Regulation
100 mA < IOUT < 500 mA
IOUT
Continuous Output
Current
500
Peak Inductor Current VOUT = 3.3V
Limit
1A Load at VIN = 2.7V
900
IPFM
Max ILOAD, PFM
Mode
IQ
Quiescent Current
0.2
%/V
0.0016
%/mA
mA
1200
75
IOUT = 0 mA PFM No
Switching
FOSC
Internal Oscillator
Frequency
η
Peak Efficiency
TON
Turn-on Time
(1)
12
PWM Mode
mA
80
Buck3 Disabled
µA
1
2
MHz
93
To 95% Level
(1)
mA
%
1
ms
Specified by design. Not production tested.
Submit Documentation Feedback
Copyright © 2006–2013, Texas Instruments Incorporated
Product Folder Links: LP3913
LP3913
www.ti.com
SNVS489I – NOVEMBER 2006 – REVISED SEPTEMBER 2013
ADC ELECTRICAL CHARACTERISTICS
External components:
Symbol
VREF
Parameter
Conditions
Reference Voltage
Min
Typ
Max
Units
T = 25°C
1.220
1.225
1.230
V
T = 0°C to +125°C
1.200
1.225
1.230
V
-1
1
LSB
-0.5
0.5
LSB
2·VREF
V
INL
Core ADC Integral Nonlinearity
VREF = 1.225
(1)
DNL
Core ADC Differential Non- VREF = 1.225
linearity
(1)
VGP_IN
General Purpose ADC
Input Voltage Range
VREF
VBATT,
Battery Max Voltage Scalar VBATT = 3.5V
Output
2.435
2.45
2.465
V
Battery Min Voltage Scalar
Output
1.217
1.225
1.232
V
Battery Max Voltage Scalar VBATT = 4.4V
Output
2.435
2.45
2.465
V
Battery Min Voltage Scalar
Output
VREF = 2.6V
1.217
1.225
1.232
V
ISENSE Max Voltage
Scalar Output
VISENSE = 0.6463V
(ICHG = 0.605A,
RSENSE = 4.64 kΩ)
2.373
2.45
2.519
V
ISENSE Min Voltage
Scalar Output
VISENSE = 0V
(ICHG = 0A,
RSENSE = 4.64 kΩ)
1.186
1.225
1.260
V
ISENSE Max Voltage
Scalar Output
VISENSE = 1.175V
(ICHG = 1.1A,
RSENSE = 4.64 kΩ)
2.373
2.45
2.519
V
ISENSE Min Voltage
Scalar Output
VISENSE = 0V (ICHG = 0A,
RSENSE = 4.64 kΩ)
1.186
1.225
1.260
V
RANGE 0
VBATT,
RANGE 1
VISENSE
RANGE 0
VISENSE
RANGE 1
VBATT = 2.6V
ADC1 & ADC2 MIN
ADC1 & ADC2 Min Voltage VREFH = 1.225
Scalar Output
1.218
1.225
1.230
V
ADC1 & ADC2MAX
ADC1 & ADC2 Max
Voltage Scalar Output
2.436
2.45
2.46
V
5
ms
tCONV
Conversion Time
tWARM
Warm-up Time
(1)
VREFH = 1.225
(1)
2
ms
Specified by design. Not production tested.
Submit Documentation Feedback
Copyright © 2006–2013, Texas Instruments Incorporated
Product Folder Links: LP3913
13
LP3913
SNVS489I – NOVEMBER 2006 – REVISED SEPTEMBER 2013
www.ti.com
TYPICAL CHARACTERISTICS — BATTERY CHARGER
TA = 25°C unless otherwise noted
Vterm 4.2V vs. Temperature
TS Pin Current vs. Temperature
-7.50
4.250
TS PIN SOURCE CURRENT (µ A)
4.240
4.230
VTERM (V)
4.220
4.210
4.200
4.190
4.180
4.170
4 160
.
4.150
-50
-7.90
-8.10
-8.30
-8.50
0
50
100
JUNCTION TEMPERATURE (°C)
-20
150
40
70
100
Figure 2.
Figure 3.
TS Pin Current vs. CHG_DET
ICHG vs. VBATT
CHG_DET = 5.0V, CC
130
540
-7.70
520
-8.10
-20°C
ICHG (mA)
25°C
-7.90
25°C
0°C
125°C
-8.30
-8.50
4.0
10
TEMPERATURE (°C)
-7.50
TS PIN SOURCE CURRENT (éA)
-7.70
125°C
500
480
460
4.5
5.0
5.5
440
2.75
6.0
3.00
3.25
3.50
3.75
4.00
CHG_DET PIN VOLTAGE (V)
VBATT (V)
Figure 4.
Figure 5.
ICHG vs. VBATT
CHG_DET = 5.0V, Prequal
IPROG = 500mA
ICHG vs. USBPWR
VBATT = 2.5V, Prequal
55.0
4.25
56.0
25°C
53.0
ICHG (mA)
ICHG (mA)
54.0
51.0
125°C
0°C
49.0
25°C
0°C
52.0
125°C
50.0
47.0
45.0
1.0
14
1.5
2.0
2.5
3.0
48.0
4.0
4.5
5.0
VBATT(V)
USBPWR (V)
Figure 6.
Figure 7.
Submit Documentation Feedback
5.5
6.0
Copyright © 2006–2013, Texas Instruments Incorporated
Product Folder Links: LP3913
LP3913
www.ti.com
SNVS489I – NOVEMBER 2006 – REVISED SEPTEMBER 2013
TYPICAL CHARACTERISTICS — BATTERY CHARGER (continued)
TA = 25°C unless otherwise noted
ICHG vs. CHG_DET
VBATT = 3.5V, CC
ICHG vs. Temperature
CHG_DET = 5V, VBATT = 3.75V, CC
540
540
520
520
ICHG (mA)
ICHG (mA)
0°C
500
25°C
480
125°C
500
480
460
460
440
440
4.0
4.5
5.0
5.5
0
6.0
25
50
75
100
125
150
JUNCTION TEMPERATURE (°C)
CHG_DET (V)
Figure 8.
Figure 9.
ICHG vs. Temperature
CHG_DET = 5V, VBATT = 2.5V, Prequal
Thermal Regulation of Charge Current
55.0
600
500
CHARGE CURRENT (mA)
ICHG (mA)
53.0
51.0
49.0
47.0
45.0
0
400
300
Active Thermal Regulation
200
100
25
50
75
100
125
0
80
150
VDD = 5V
VBATT = 3.5V
JUNCTION TEMPERATURE (°C)
90
100
110
120
130
JUNCTION TEMPERATURE (°C)
Figure 10.
Figure 11.
USB ILIMIT vs. Temperature
520
USB ILIMIT (mA)
500
480
460
440
420
0
25
50
75
100
125
150
JUNCTION TEMPERATURE (°C)
Figure 12.
Submit Documentation Feedback
Copyright © 2006–2013, Texas Instruments Incorporated
Product Folder Links: LP3913
15
LP3913
SNVS489I – NOVEMBER 2006 – REVISED SEPTEMBER 2013
www.ti.com
TYPICAL CHARACTERISTICS — BATTERY CHARGER (continued)
TA = 25°C unless otherwise noted
16
Wall Adapter Insertion with USBPWR present
CH1 = Charge Current (mA); CH3 = CHG_DET (V);
CH4 = USBPWR (V)
Wall Adapter Removal with USBPWR present
CH1 = Charge Current (mA); CH3 = CHG_DET (V);
CH4 = USBPWR (V)
Figure 13.
Figure 14.
Submit Documentation Feedback
Copyright © 2006–2013, Texas Instruments Incorporated
Product Folder Links: LP3913
LP3913
www.ti.com
SNVS489I – NOVEMBER 2006 – REVISED SEPTEMBER 2013
TYPICAL PERFORMANCE CHARACTERISTICS — LDO
TA = 25°C unless otherwise noted
Output Voltage Change vs Temperature (LDO2)
Vin = 4.3V, Vout = 1.8V, 100 mA load
1.000
1.000
0.500
0.500
VOUT VARIANCE(%)
VOUT VARIANCE(%)
Output Voltage Change vs Temperature (LDO1)
Vin = 4.3V, Vout = 3.3V, 100 mA load
0.000
-0.500
-1.000
0.000
-0.500
-1.000
-1.500
-1.500
-2.000
-40 -25 -10 5 20 35 50 65 80 95 110 125
-2.000
-40 -25 -10 5 20 35 50 65 80 95 110 125
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 15.
Figure 16.
Load Transient (LDO1)
3.6 Vin, 3.3 Vout, 0 – 100 mA load
Load Transient (LDO2)
3.6 Vin, 1.8 Vout, 0 – 100 mA load
Figure 17.
Figure 18.
Line Transient (LDO1)
3.6 - 4.5 Vin, 3.3 Vout, 150 mA load
Line Transient (LDO2)
3 – 4.2 Vin, 1.8 Vout, 150 mA load
Figure 19.
Figure 20.
Submit Documentation Feedback
Copyright © 2006–2013, Texas Instruments Incorporated
Product Folder Links: LP3913
17
LP3913
SNVS489I – NOVEMBER 2006 – REVISED SEPTEMBER 2013
www.ti.com
TYPICAL PERFORMANCE CHARACTERISTICS — LDO (continued)
TA = 25°C unless otherwise noted
18
Enable Startup time (LDO1)
0-3.6 Vin, 3.3 Vout, 1mA load
Enable Startup time (LDO2)
0 – 3.6 Vin, 1.8 Vout, 1 mA load
Figure 21.
Figure 22.
Submit Documentation Feedback
Copyright © 2006–2013, Texas Instruments Incorporated
Product Folder Links: LP3913
LP3913
www.ti.com
SNVS489I – NOVEMBER 2006 – REVISED SEPTEMBER 2013
TYPICAL PERFORMANCE CHARACTERISTICS - BUCK
TA = 25°C unless otherwise noted
Output Voltage vs. Supply Voltage
(Vout = 3.3 V)
Output Voltage vs. Supply Voltage
(Vout = 2.0 V)
3.35
2.05
IOUT = 20 mA
3.33
2.04
IOUT = 600 mA
IOUT = 300 mA
I OUT = 600 mA
VOUT (V)
VOUT (V)
3.31
3.29
2.03 IOUT = 20 mA
2.02
I OUT = 300 mA
3.27
2.01
3.25
4.0
4.3
4.6
4.9
5.2
5.5
2.00
3.0
SUPPLY VOLTAGE (V)
3.5
4.0
4.5
5.0
5.5
SUPPLY VOLTAGE (V)
Figure 23.
Figure 24.
Output Voltage vs. Supply Voltage
(Vout = 1.2V)
Output Voltage vs. Supply Voltage
(Vout = 0.8V)
0.825
1.25
0.820
1.24
1.23
IOUT = 300 mA
0.815
VOUT (V)
VOUT (V)
IOUT = 600 mA
IOUT = 20 mA
0.810
1.22
IOUT = 600 mA
0.805
1.21
IOUT = 300 mA
IOUT = 20 mA
0.800
3.0
1.20
3.0
3.5
4.0
4.5
5.0
3.5
4.0
4.5
5.0
5.5
SUPPLY VOLTAGE (V)
5.5
SUPPLY VOLTAGE (V)
Figure 25.
Figure 26.
Buck 1 Efficiency vs. Output Current
(Forced PWM Mode, Vout =1.2V, L= 2.2µH)
Buck 1 Efficiency vs. Output Current
(Forced PWM Mode, Vout =2.0V, L= 2.2µH)
100.0
90.0
Vin = 3.2V
Vin = 3.2V
80.0
Vin = 4V
80.0
70.0
Vin = 5V
EFFICIENCY (%)
EFFICIENCY (%)
90.0
Vin = 4V
60.0
50.0
40.0
30.0
Vin = 5V
70.0
60 0
.
50.0
40.0
30.0
20.0
20.0
10.0
10.0
0.0
0.0
0.1
1.0
10
100
1000
0.1
1.0
10
100
1000
OUTPUT CURRENT (mA)
OUTPUT CURRENT (mA)
Figure 27.
Figure 28.
Submit Documentation Feedback
Copyright © 2006–2013, Texas Instruments Incorporated
Product Folder Links: LP3913
19
LP3913
SNVS489I – NOVEMBER 2006 – REVISED SEPTEMBER 2013
www.ti.com
TYPICAL PERFORMANCE CHARACTERISTICS - BUCK (continued)
TA = 25°C unless otherwise noted
Buck 1 Efficiency vs. Output Current
(PFM to PWM mode, Vout =1.2V, L= 2.2µH)
Buck 1 Efficiency vs. Output Current
(PFM to PWM mode, Vout =2.0V, L= 2.2µH)
85.0
95.0
Vin = 3.2V
Vin = 3.2V
80.0
75.0
70.0
65.0
60.0
55.0
Vin = 5V
80.0
75.0
70.0
65.0
50.0
60.0
45.0
55.0
40.0
Vin = 4V
85.0
Vin = 5V
EFFICIENCY(%)
EFFICIENCY (%)
90.0
Vin = 4V
50.0
0.1
1.0
10
100
0.1
1000
OUTPUT CURRENT (mA)
100
1000
Figure 30.
Buck 2 Efficiency vs. Output Current
(Forced PWM Mode, Vout =1.8V, L= 2.2µH)
Buck 2 Efficiency vs. Output Current
(Forced PWM Mode, Vout =3.3V, L= 2.2µH)
100.0
Vin = 3.6V
80.0
Vin = 4V
80.0
Vin = 5V
70.0
EFFICIENCY (%)
60.0
50.0
40.0
30.0
Vin = 5V
60.0
50.0
40.0
30.0
20.0
20.0
10.0
10.0
0.0
Vin = 3.6V
90.0
Vin = 4V
70.0
EFFICIENCY (%)
10
Figure 29.
90.0
0.0
0.1
1.0
10
100
0.1
1000
1.0
10
100
1000
OUTPUT CURRENT (mA)
OUTPUT CURRENT (mA)
Figure 31.
Figure 32.
Buck 2 Efficiency vs. Output Current
(PFM to PWM Mode, Vout =1.8V, L= 2.2µH)
Buck 2 Efficiency vs. Output Current
(PFM to PWM Mode, Vout =3.3V, L= 2.2µH)
100.00
95.0
Vin = 3.6V
90.0
V IN = 2.7V
Vin = 4V
85.0
90.00
Vin = 5V
EFFICIENCY (%)
EFFICIENCY(%)
1.0
OUTPUT CURRENT (mA)
80.0
75.0
70.0
65.0
60.0
80.00
70.00
VIN = 4.2V
V IN = 3.6V
60.00
55.0
50.0
0.1
1.0
10
100
1000
OUTPUT CURRENT (mA)
0.1
1.0
10
100
1000
OUTPUT CURRENT (mA)
Figure 33.
20
50.00
Figure 34.
Submit Documentation Feedback
Copyright © 2006–2013, Texas Instruments Incorporated
Product Folder Links: LP3913
LP3913
www.ti.com
SNVS489I – NOVEMBER 2006 – REVISED SEPTEMBER 2013
TYPICAL PERFORMANCE CHARACTERISTICS - BUCK (continued)
TA = 25°C unless otherwise noted
Buck 1 Load Transient Response
VIN = 4.2V, VOUT = 1.2V
ILOAD = 200-400mA (PWM Mode)
Buck 1 Load Transient Response
VIN = 4.2V, VOUT = 1.2V
ILOAD = 50-150mA (PFM to PWM)
Figure 35.
Figure 36.
Buck 2 Load Transient Response
VIN = 4.2V, VOUT = 3.3V
ILOAD = 200-400mA (PWM Mode)
Buck 2 Load Transient Response
VIN = 4.2V, VOUT = 3.3V
ILOAD = 50-150mA (PFM to PWM)
Figure 37.
Figure 38.
Line Transient Response
Vin = 3 – 3.6 V, Vout = 1.2 V, 250 mA load
Line Transient Response
Vin = 3.6 – 4.2 V, Vout = 3.3 V, 250 mA load
Figure 39.
Figure 40.
Submit Documentation Feedback
Copyright © 2006–2013, Texas Instruments Incorporated
Product Folder Links: LP3913
21
LP3913
SNVS489I – NOVEMBER 2006 – REVISED SEPTEMBER 2013
www.ti.com
TYPICAL PERFORMANCE CHARACTERISTICS - BUCK (continued)
TA = 25°C unless otherwise noted
22
Start up into PWM Mode
Vout = 1.8 V, 30 mA load
Start up into PWM Mode
Vout = 3.3 V, 30 mA load
Figure 41.
Figure 42.
Start up into PFM Mode
Vout = 1.8 V, 30 mA load
Start up into PFM Mode
Vout = 3.3 V, 30 mA load
Figure 43.
Figure 44.
Submit Documentation Feedback
Copyright © 2006–2013, Texas Instruments Incorporated
Product Folder Links: LP3913
LP3913
www.ti.com
SNVS489I – NOVEMBER 2006 – REVISED SEPTEMBER 2013
TYPICAL PERFORMANCE CHARACTERISTICS - BUCK3
TA = 25°C unless otherwise noted
Efficiency vs. VIN
ILOAD= 100mA
Forced PWM Efficiency vs ILOAD
VOUT = 3.3V
100.0
100.00
95.00
80.0
EFFICIENCY (%)
EFFICIENCY(%)
90.00
V OUT = 3.3V
85.00
80.00
VOUT = 1.8V
75.00
60.0
VBATT = 3.3V
40.0
V BATT = 4.2V
70.00
20.0
65.00
0.0
60.00
2.5
3.0
3.5
4.0
4.5
5.0
0.1
5.5
V IN (V)
1000
Figure 45.
Figure 46.
AutoMode Efficiency vs. ILOAD
VOUT = 3.3V
AutoMode Efficiency vs. ILOAD
VOUT = 1.8V
100.00
100.00
VIN = 4.2V
V IN = 4.2V
90.00
90.00
80.00
EFFICIENCY (%)
EFFICIENCY (%)
1
10
100
OUTPUT CURRENT (mA)
VIN = 3.6V
70.00
80.00
VIN = 3.6V
70.00
60.00
60.00
50.00
50.00
0.1
1
10
100
OUTPUT CURRENT (mA)
1000
0.1
1
10
100
1000
OUTPUT CURRENT (mA)
Figure 47.
Figure 48.
Buck3 Load Transient Response
VIN = 4.2V, VOUT = 3.3V,
ILOAD = 0-100mA (PFM Mode)
Buck3 Load Transient Response
VIN = 3.6V, VOUT = 3.3V
ILOAD = 150-250mA (PWM Mode)
Figure 49.
Figure 50.
Submit Documentation Feedback
Copyright © 2006–2013, Texas Instruments Incorporated
Product Folder Links: LP3913
23
LP3913
SNVS489I – NOVEMBER 2006 – REVISED SEPTEMBER 2013
www.ti.com
TYPICAL PERFORMANCE CHARACTERISTICS - BUCK3 (continued)
TA = 25°C unless otherwise noted
24
Line Transient Response
VIN = 3.6 - 4.2V, VOUT = 3.3V, ILOAD = 80mA
Line Transient Response
VIN = 3.6 - 4.2V VOUT = 3.3V, ILOAD = 260mA
Figure 51.
Figure 52.
Submit Documentation Feedback
Copyright © 2006–2013, Texas Instruments Incorporated
Product Folder Links: LP3913
LP3913
www.ti.com
SNVS489I – NOVEMBER 2006 – REVISED SEPTEMBER 2013
FUNCTIONAL DESCRIPTION
Operating Modes
The LP3913 can be in 3 different operating modes as illustrated in Figure 53:
BATTERY INSERT VBATT> VBLA
POWER OFF
No Battery
BATTERY INSERT VBATT < VBLA
POWERACK PIN AND BIT = 0
NO WA / USB
STANDBY
WA AND USB REMOVED
ONOFF AND
VBATT > VBLA
WA INSERT
USB INSERT
AND VBATT > VBLA
(CHARGING IF NEEDED)
ACTIVE
VBATT < VBLA AND NO WA
ONOFF
POWERACK PIN OR BIT = 1
WA OR USB
POWERACK PIN AND BIT
FAILED TO GO HIGH DURING
POWERUP SEQUENCE
CHG
STANDBY
WA OR USB
Figure 53. Operating Mode State Diagram
State Machine Definitions
VBLA Battery low alarm threshold
VBATT Battery voltage
WA
Wall Adapter
USB Universal Serial Bus Adapter
ONOFF On off pin event
POWERACK Acknowledgment from the Host Processor
Submit Documentation Feedback
Copyright © 2006–2013, Texas Instruments Incorporated
Product Folder Links: LP3913
25
LP3913
SNVS489I – NOVEMBER 2006 – REVISED SEPTEMBER 2013
www.ti.com
Figure 54. Voltage Threshold Levels
Vterm
Active
4.2V (Typ.)
VBLA
2.4-3.5V (factory
programmable)
Standby
Vuvlo
Battery safety switch on/off threshold
2.4V (Typ.)
2.1V
Vpor
PowerOff
0.9V
Table 2. Power State Table
Power Off
Standby
Active
Charger Standby
LDO1,2
Off
Off
On
Off
BUCK1,2
Off
Off
On
Off
BUCK3
Off
Off
On
Off
CHARGER
Off
Off
On if Charger / USB
Present
On if Charger / USB
Present
A/D Converter
Off
Off
On
Off
NRST
Low
Low
High
Low
I2C interface
Off
Off
On
On
Internal System Oscillator
Off
Off
On
On
Battery Monitor
Off
On
On
On
Current consumption
工商网监
湘ICP备2023018690号
