LP5562
www.ti.com.cn
ZHCSBU9 – APRIL 2013
具有可编程照明序列的四通道发光二极管 (LED) 驱动器
查询样片: LP5562
特性
描述
1
•
2
•
•
•
•
•
•
•
具有 8 位电流设置（从 0mA 到 25.5mA，
，步长
100μA）
）和 8 位脉宽调制 (PWM) 控制的 4 个独立
可编程 LED 输出
典型 LED 输出饱和电压 60mV 和 1% 电流匹配
针对 LED 输出的灵活 PWM 控制
具有外部时钟的自动节电模式
3 个具有灵活指令集的程序执行引擎
具有程序执行引擎的自主运行
针对照明模式程序的 SRAM 程序存储器
芯片尺寸球栅阵列 (DSBGA)，
，12 焊锡凸点封
装，0.4mm 焊球间距
LP5562 是一款设计用于产生多种照明效果的四通道
LED 驱动器。 该器件具有一个产生多种照明序列的程
序存储器。 当程序存储器已被载入时，LP5562 能够
在无需处理器控制的情况下独立运行。
LP5562 能够自动进入省电模式，此时 LED 输出未被
激活，从而降低流耗。
四个独立的 LED 通道具有准确的可编程电流吸收能
力，从 0mA 到 25.5mA（步长 100μA），以及灵活的
PWM 控制。 每个通道可被配置为三个程序后执行引
擎中的任何一个。 程序执行引擎具有使用 PWM 控制
来产生所需照明序列的程序存储器。
应用范围
•
•
•
LP5562 具有四个引脚可选 I2C™ 地址。 这可以在一
条 I2C 总线内连接多达四个并联器件。 此器件只需一
个小型、低成本陶瓷电容器。
彩灯
指示器灯
袖珍键盘 RGB 背光和手机挂饰
LP5562 采用 DSBGA 封装。
TYPICAL APPLICATION
+
VDD
VDD
CIN
1 PF
RGB LED
0...25.5 mA/LED
-
SCL
SDA
MCU
EN/VCC
LP5562
CLK_32K
R
G
B
ADDR_SEL0
ADDR_SEL1
WLED
GND
1
2
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
I2C is a trademark of Philips Semiconductor Corp..
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2013, Texas Instruments Incorporated
English Data Sheet: SNVS820
LP5562
ZHCSBU9 – APRIL 2013
www.ti.com.cn
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
Connection Diagrams
Bottom View
Top View
C
SDA
SCL
EN/VCC
R
A
W
VDD
CLK32K
B
B
ADDR
SEL1
ADDR
SEL0
GND
G
B
ADDR
SEL1
ADDR
SEL0
GND
G
A
W
VDD
CLK_ 32K
B
C
SDA
SCL
EN/VCC
R
1
2
3
4
1
2
3
4
12-Bump DSBGA (0.4 mm Pitch)
BIAS
LED
DRIVER
DIGITAL
SVA-30197401
Figure 1. Top and Bottom View
PIN DESCRIPTIONS
Pin #
Name
Type
Description
A1
W
A
LED driver current sink terminal
B1
ADDR_SEL1
I
C1
SDA
A2
VDD
I/O
I2C address selection pin
2
I C serial interface data input/output
Power Supply
2
B2
ADDR_SEL0
I
I C address selection pin
C2
SCL
I
I2C serial interface clock
A3
CLK_32K
I
External 32 kHz clock input
B3
GND
C3
EN/VCC
A4
B
A
LED driver current sink terminal
B4
G
A
LED driver current sink terminal
C4
R
A
LED driver current sink terminal
Ground
Enable/Logic power supply
A: Analog Pin, I/O: Digital Bidirectional Pin, I: Digital Input Pin
2
Copyright © 2013, Texas Instruments Incorporated
LP5562
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ZHCSBU9 – APRIL 2013
ABSOLUTE MAXIMUM RATINGS (1)
V(VDD , VEN/VCC, R, G, B, W)
Voltage on Logic Pins
Continuous Power Dissipation (2)
Junction Temperature (TJ-MAX)
Storage Temperature Range
Maximum Lead Temperature (Soldering)
(1)
(2)
(3)
−0.3V to +6.0V
−0.3V to VDD +0.3V
with 6.0V max
Internally Limited
125°C
−65°C to +150°C
see (3)
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
Internal thermal shutdown circuitry protects the device from permanent damage. Thermal shutdown engages at TJ = 150°C (typ.) and
disengages at TJ = 130°C (typ.).
For detailed soldering specifications and information, please refer to Texas Instruments Application Note AN1112 : DSBGA Wafer Level
Chip Scale Package.
RECOMMENDED OPERATING CONDITIONS (1) (2)
VDD
2.7V to 5.5V
VEN/VCC
1.65V to VDD
Junction Temperature (TJ) Range
Ambient Temperature (TA) Range (3)
(1)
(2)
(3)
−40°C to +125°C
−40°C to +85°C
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltages are with respect to the potential at the GND pins.
In applications where high power dissipation and/or poor package thermal resistance is present, the maximum ambient temperature may
have to be derated. Maximum ambient temperature (TA-MAX) is dependent on the maximum operating junction temperature (TJ-MAX-OP
= 125°C), the maximum power dissipation of the device in the application (PD-MAX), and the junction-to ambient thermal resistance of the
part/package in the application (θJA), as given by the following equation: TA-MAX = TJ-MAX-OP – (θJA × PD-MAX).
THERMAL PROPERTIES (1)
Junction-to-Ambient Thermal Resistance (θJA),
YQE0012ABAB Package (2)
(1)
(2)
68°C/W
Junction-to-ambient thermal resistance is highly application and board-layout dependent. Number given here is based on 4-layer
standard JEDEC thermal test board or 4LJEDEC 4"x3" in size. The board has 2 embedded copper layers which cover roughly the same
size as the board. The copper thickness for the four layers, starting from the top one, is 2 oz./1oz./1oz./2 oz. Detailed description of the
board can be found in JESD 51-7. In applications where high maximum power dissipation exists, special care must be paid to thermal
dissipation issues in board design.
In applications where high power dissipation and/or poor package thermal resistance is present, the maximum ambient temperature may
have to be derated. Maximum ambient temperature (TA-MAX) is dependent on the maximum operating junction temperature (TJ-MAX-OP
= 125°C), the maximum power dissipation of the device in the application (PD-MAX), and the junction-to ambient thermal resistance of the
part/package in the application (θJA), as given by the following equation: TA-MAX = TJ-MAX-OP – (θJA × PD-MAX).
Copyright © 2013, Texas Instruments Incorporated
3
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ELECTRICAL CHARACTERISTICS (1) (2) (3)
Limits in standard typeface are for TA = 25°C. Limits in boldface type apply over the operating ambient temperature range
(−40°C < TA < +85°C). Unless otherwise specified: VIN = 3.6V, VEN/VCC = 1.8V.
Symbol
Parameter
Condition
Min
Typ
Max
Units
EN = 0 (pin), CHIP_EN = 0 (bit), external 32
kHz clock running or not running
0.2
2
µA
EN = 1 (pin), CHIP_EN = 0 (bit), external 32
kHz clock not running
2
µA
EN = 1 (pin), CHIP_EN = 0 (bit), external 32
kHz clock running
2.4
µA
LED drivers disabled
0.25
mA
LED drivers enabled
1
mA
External 32 kHz clock running
10
µA
0.25
mA
Current Consumption and Oscillator electrical Characteristics
Standby supply current
IVDD
Normal mode supply current
Powersave mode supply current
fOSC
Internal oscillator running
Internal oscillator frequency
accuracy
–4
4
–7
7
%
LED Driver Electrical Characteristics (R, G, B, W Outputs)
ILEAKAGE
IMAX
IOUT
IMATCH
R, G, B, W pin leakage current
Maximum source current
Matching (4)
Output current set to 17.5 mA, VDD = 3.6V
VSAT
Saturation voltage (5)
(4)
(5)
4
1
25.5
Output current set to 17.5 mA, VDD = 3.6V
LED PWM switching frequency
(2)
(3)
Outputs R, G, B, W
Accuracy of output current (4)
fLED
(1)
0.1
mA
–4
4
–5
5
1
PWM_HF = 1
558
PWM_HF = 0
256
Output current set to 17.5 mA
60
µA
2
%
%
Hz
100
mV
The Electrical characteristics tables list ensured specifications under the listed Recommended Conditions except as otherwise modified
or specified by the Electrical Characteristics Conditions and/or Notes. Typical specifications are estimations only and are not verified by
production testing.
All voltages are with respect to the potential at the GND pins.
Min and Max limits are ensured by design, test, or statistical analysis. Typical numbers are not verified by production, but do represent
the most likely norm.
Output Current Accuracy is the difference between the actual value of the output current and programmed value of this current.
Matching is the maximum difference from the average. For the constant current outputs on the part, the following are determined: the
maximum output current (MAX), the minimum output current (MIN), and the average output current of all outputs (AVG). Two matching
numbers are calculated: (MAX-AVG)/AVG and (AVG-MIN)/AVG. The largest number of the two (worst case) is considered the matching
figure. Note that some manufacturers have different definitions in use.
Saturation voltage is defined as the voltage when the LED current has dropped 10% from the set value.
Copyright © 2013, Texas Instruments Incorporated
LP5562
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ZHCSBU9 – APRIL 2013
Logic Interface Characteristics
V(EN) = 1.65V unless otherwise noted
Symbol
Parameter
Conditions
Min
Typ
Max
Units
0.5
V
LOGIC INPUT EN
VIL
Input Low Level
VIH
Input High Level
1.2
II
Logic Input Current
–1.0
tDELAY
Input delay (1)
V
1.0
2
µA
µs
LOGIC INPUT SCL, SDA, CLK_32K, ADDR_SEL0, ADDR_SEL1, VEN = 1.8V
VIL
Input Low Level
VIH
Input High Level
II
Input Current
fCLK_32K
Clock frequency
fSCL
Clock frequency
0.2xV(EN)
V
0.8xV(EN)
–1.0
1.0
32
µA
kHz
400
kHz
0.5
V
1.0
µA
Max
Units
LOGIC OUTPUT SDA
VOL
Output Low Level
IL
(1)
IOUT = 3 mA (pull-up
current)
0.3
Output Leakage Current
2
The I C host should allow at least 1ms before sending data to the LP5562 after the rising edge of the enable line.
Recommended External Clock Source Conditions (2) (3)
Symbol
Parameter
Condition
Min
Typ
LOGIC INPUT CLK_32K
fCLK_32K
Clock Frequency
tCLKH
High Time
6
tCLKL
Low Time
6
tr
Clock Rise Time
10% to 90%
2
tf
Clock Fall Time
90% to 10%
2
(2)
(3)
32.7
kHz
µs
Specification is ensured by design and is not tested in production. VEN = 1.65V to VDD.
The ideal external clock signal for the LP5562 is a 0V to VEN 25% to 75% duty-cycle square wave. At frequencies above 32.7kHz,
program execution will be faster and at frequencies below 32.7 kHz program execution will be slower.
SVA-30197417
Figure 2. External Clock Timing
Copyright © 2013, Texas Instruments Incorporated
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I2C Timing Parameters (SDA, SCL) (1)
Symbol
Parameter
Limit
Min
fSCL
(1)
Clock Frequency
Units
Max
400
1
Hold Time (repeated) START Condition
0.6
2
Clock Low Time
1.3
3
Clock High Time
600
4
Setup Time for a Repeated START Condition
600
5
Data Hold Time
50
6
Data Setup Time
100
7
Rise Time of SDA and SCL
20+0.1Cb
300
8
Fall Time of SDA and SCL
15+0.1Cb
300
9
Set-up Time for STOP condition
600
10
Bus Free Time between a STOP and a START Condition
1.3
Cb
Capacitive Load for Each Bus Line
10
kHz
µs
ns
µs
200
pF
Specification is ensured by design and is not tested in production. VEN = 1.65V to VDD.
SVA-30197402
Figure 3. I2C Timing Parameters
6
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LP5562
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ZHCSBU9 – APRIL 2013
TYPICAL CURRENT CONSUMPTION PERFORMANCE CHARACTERISTICS
Unless otherwise specified: VDD = 3.6V, VEN = 3.3V.
Here are presented input current consumption measurements. Current consumption is measured during a LED blink
program execution. Program code sets every LED output to full PWM value for 2 seconds and then PWM is set to 0
for 2 seconds. This is looped endlessly. 750 measurements are taken during one measurement cycle.
50
50
Input current, external clock
Input current, internal clock
40
Input current, mA
Input current, mA
40
30
20
30
20
10
10
0
0
0
100
200
300
400
500
600
0
700
100
200
300
400
500
600
700
Measurement number
Measurement number
C005
C001
Figure 4. Input Current Consumption in Normal Mode With
External Clock Running. 4 LEDs (RGBW) Set as Load. Every
LED Driver Current Value Is Set to 10 mA.
Figure 5. Input Current Consumption in Normal Mode With
Internal Clock Running. 4 LEDs (RGBW) Set as Load. Every
LED Driver Current Value Is Set to 10 mA.
1.2
1.2
Input current, internal clock,
powersave mode
1
1
0.8
0.8
Input current, mA
Input current, mA
Input current, external clock,
powersave mode
0.6
0.6
0.4
0.4
0.2
0.2
0
0
0
100
200
300
400
500
600
700
0
Measurement number
200
300
400
500
600
700
Measurement number
C002
Figure 6. Input Current Consumption in Power Save Mode
With External Clock Running. Here Is No LEDs as Load. All
4 LED Drivers Are Enabled During Program Execution.
Copyright © 2013, Texas Instruments Incorporated
100
C003
Figure 7. Input Current Consumption in Power Save Mode
With Internal Clock Running. Here Is No LEDs as Load. All 4
LED Drivers Are Enabled During Program Execution.
7
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TYPICAL CURRENT CONSUMPTION PERFORMANCE CHARACTERISTICS (continued)
Unless otherwise specified: VDD = 3.6V, VEN = 3.3V.
0.5
0.5
Input current, external clock,
powersave, 1 LED
0.45
0.4
0.4
Input current, mA
Inpiut current, mA
0.35
0.3
0.2
0.3
0.25
0.2
0.15
0.1
0.1
Input current, internal clock,
powersave mode, 1 LED
0.05
0
0
0
100
200
300
400
500
600
0
700
100
200
Measurement number
300
400
500
600
700
Measurement number
C006
Figure 8. Input Current Consumption in Power Save Mode
With External Clock Running. Here Is No LEDs as Load.
Only 1 LED Driver Is Enabled During Program Execution.
C004
Figure 9. Input Current Consumption in Power Save Mode
With Internal Clock Running. Here Is No LEDs as Load.
Only 1 LED Driver Is Enabled During Program Execution.
1.40E+01
1.20E+01
Input current, uA
1.00E+01
8.00E+00
6.00E+00
4.00E+00
2.00E+00
Input current, external clock,
powersave mode, no LEDs
0.00E+00
0
100
200
300
400
500
600
700
Measurement number
C007
Figure 10. Input Current Consumption in Power Save Mode With External Clock Running. Here Is No LEDs as Load. No LED
Drivers Are Enabled During Program Execution.
8
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ZHCSBU9 – APRIL 2013
TYPICAL LED OUTPUT PERFORMANCE CHARACTERISTICS
LED driver typical performance images.
3.00E+01
20.00
18.00
2.50E+01
16.00
2.00E+01
LED current, mA
LED current, mA
14.00
12.00
WLED
10.00
RLED
GLED
8.00
1.50E+01
1.00E+01
BLED
6.00
WLED current
RLED current
GLED current
BLED current
5.00E+00
4.00
2.00
0.00E+00
0
0.00
0.2
0.18
0.16
0.14
0.12
0.1
0.08
0.06
0.04
0.02
25
50
75
100
LED voltage, V
125
150
175
200
225
250
Current code
0
C009
C008
Figure 11. Every LED Driver Saturation Voltage, When
Current Setting Is 17.5 mA.
Figure 12. LED Driver Currents Compared to Current
Setting Code.
7
10
9
6
Current accuracy, %
7
6
WLED
RLED
GLED
BLED
LED current matching, %
8
5
4
3
5
4
Matching
3
2
2
1
1
0
0
0
5
10
15
20
25
LED current, mA
Copyright © 2013, Texas Instruments Incorporated
5
10
15
20
25
LED current, mA
C010
Figure 13. LED Driver Current Accuracy With Different
Current Setting.
0
C011
Figure 14. LED Driver Current Matching Between All LED
Drivers With Different Current Setting.
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FUNCTIONAL BLOCK DIAGRAM
REF
TSD
POR
CLK
DET
BIAS
OSC
VDD
CIN
1PF
Command Based
PWM Pattern Generator
PROGRAM
MEMORY
ADDR_SEL0
ADDR_SEL1
VDD_ IO
VDD
IDAC
W
SCL
SDA
2
I C
R
Control
MCU
EN/VCC
G
CLK_32K
B
LP5562
GND
10
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LP5562
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ZHCSBU9 – APRIL 2013
MODES OF OPERATION
RESET:
In the reset mode all the internal registers are reset to the default values. Reset is done always if
FFh is written to Reset Register (0Dh) or internal Power On Reset is activated. Power On Reset
(POR) will activate when supply voltage is connected or when the supply voltage VDD falls below
1.5V (typ). Once VDD rises above 1.9V (typ), POR will inactivate and the chip will continue to the
standby mode. CHIP_EN control bit is low after POR by default.
STANDBY: The standby mode is entered if the register bit CHIP_EN or EN pin is low and Reset is not active.
This is the low power consumption mode, when all circuit functions are disabled. Registers can be
written in this mode if EN pin is high. Control bits are effective after start up.
STARTUP: When CHIP_EN bit is written high and EN pin is high, the internal startup sequence powers up all
the needed internal blocks (VREF, Bias, Oscillator etc.). Startup delay after setting EN pin high is
1 ms (typ.). Startup delay after setting chip_en bit to '1' is 500μs (typ.). If the device temperature
rises too high, the Thermal Shutdown (TSD) disables the device operation and the device state is
in startup mode, until no thermal shutdown event is present.
NORMAL:
During normal mode the user controls the device using the Control Registers. If EN pin is set low,
the CHIP_EN bit is reset to 0.
POWER
SAVE:
In power save mode analog blocks are disabled to minimize power consumption. See chapter
Power Save Mode for further information.
POR
RESET
2
I C reset=H and EN=H (pin)
or
POR=H
STANDBY
EN=H (pin) and
CHIP_EN=H (bit)
EN=L (pin) or
CHIP_EN=L (bit)
INTERNAL
STARTUP
SEQUENCE
TSD = H
TSD = L
NORMAL MODE
Exit power save
Enter power save
POWER SAVE
SVA-30197404
Figure 15. Modes of Operation
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FUNCTIONAL DESCRIPTION
LED Drivers Operational Description
The LP5562 have 4 LED drivers that are constant current sinks with 8-bit current and 8-bit PWM control. Current
is controlled from I2C registers. PWM can be controlled with program execution engines or direct I2C register
writes.
LED Driver Current Control
LED driver output current can be programmed with I2C register from 0 mA up to 25.5 mA. Current setting
resolution is 100 μA (8-bit control).
Table 1. B_CURRENT Register (05h), G_CURRENT Register (06h), R_CURRENT
Register (07h), W CURRENT Register (0Fh):
Name
Bit(s)
Description
Current setting
CURRENT
7:0
bin
hex
dec
mA
0000 0000
00
0
0.0
0000 0001
01
1
0.1
0000 0010
02
2
0.2
0000 0011
03
3
0.3
0000 0100
04
4
0.4
0000 0101
05
5
0.5
0000 0110
06
6
0.6
...
...
...
...
1010 1111
AF
175
17.5 (def)
...
...
...
...
1111 1011
FB
251
25.1
1111 1100
FC
252
25.2
1111 1101
FS
253
25.3
1111 1110
FE
254
25.4
1111 1111
FF
255
25.5
Controlling LED Driver Output PWM
PWM can be controlled by either with program execution engines (1, 2 and 3) or via I2C registers (02h for B, 03h
for G, 04h for R and 0Eh for W).
Control of LED driver output PWM selection is managed with 2 bits for each LED output from register 70h. The
Table 3 describes the selection options. With these bits for example all LED outputs can be controlled from one
program execution engine.
12
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W_ENG_SEL bits
W PWM
Register
00
W LED
PWM
01
10
R PWM
Register
11
R_ENG_SEL bits
00
G PWM
Register
01
R LED
PWM
10
11
B PWM
Register
G_ENG_SEL bits
00
ENG1_MODE bits
01
G LED
PWM
10
ENGINE 1
11
00 - 10
B_ENG_SEL bits
11
00
ENG2_MODE bits
01
B LED
PWM
10
11
ENGINE 2
00 - 10
11
ENG3_MODE bits
ENGINE 3
00 - 10
11
SVA-30197406
Figure 16. Controlling LED Outputs
The LED driver PWM control with 8-bit I2C register is defined in table Table 2.
Table 2. LED Driver PWM Control Bits Register 70h
Name
Bit(s)
Description
LED PWM value during I2C
control operation mode
PWM
7:0
0000 0000 = 0% PWM
1111 1111 = 100% PWM
If the LED driver outputs are controlled with engines, the engine adjusts the PWM according to the program
code. However, when the engine mode bits are set to ‘11’, the engine is set to direct mode. In direct mode the
PWM controls of engines comes:
• Engine 1 PWM control comes from B PWM I2C register (02h)
• Engine 2 PWM control comes from G PWM I2C register (03h)
• Engine 3 PWM control comes from R PWM I2C register (04h)
When the engine mode bits are set to '11' along with the LED PWM Output selection bits, it is possible to control
all LED outputs from one I2C register.
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Table 3. LED PWM Output Selection Bits
B_ENG_SEL bits[1:0]
G_ENG_SEL bits[3:2]
Description
R_ENG_SEL bits[5:4]
W_ENG_SEL bits[7:6]
00
Output is controlled via I2C registers
01
ENG1_MODE and ENG1_EXEC register control LED output PWM instead of
I2C register
10
ENG2_MODE and ENG2_EXEC register control LED output PWM instead of
I2C register
11
ENG3_MODE and ENG3_EXEC register control LED output PWM instead of
I2C register
Direct I2C Register PWM Control Example
• Device Start-up
– Supply 3.6V to VDD
– Supply 1.8V to EN
– Wait 1 ms
– Write to address 00h 0100 0000b (chip_en to '1')
– Wait 500 μs (startup delay)
• Use internal clock
– Write to address 08h 0000 0001b (enable internal clock)
• Direct PWM control
– Write to address 70h 0000 0000b (Configure all LED outputs to be controlled from I2C registers)
• Write PWM values
– Write to address 02h 1000 0000b (B driver PWM 50% duty cycle)
– Write to address 03h 1100 0000b (G driver PWM 75% duty cycle)
– Write to address 04h 1111 1111b (R driver PWM 100% duty cycle)
LEDs are turned on after the PWM values are written. Changes to the PWM value registers are reflected
immediately to the LED brightness. Default LED current (17.5mA) is used for LED outputs, if no other values are
written.
PWM frequency is either 256 Hz or 558 Hz. Frequency is set with PWM_HF bit in register 08h. When PWM_HF
is 0, the frequency is 256Hz. When the PWM_HF bit is 1, the PWM frequency is 558 Hz. Brightness adjustment
is either linear or logarithmic. This can be set with LOG_EN bit in register 00h. When LOG_EN = 0 linear
adjustment scale is used and when LOG_EN = 1 logarithmic scale is used. By using logarithmic scale the visual
effect seems linear to the eye. Register control bits are presented in following tables:
Table 4. ENABLE Register (00h):
Name
Bit(s)
Description
Logarithmic PWM adjustment enable bit
LOG_EN
7
0 = Linear adjustment
1 = Logarithmic adjustment
Table 5. CONFIG Register (08h):
Name
Bit(s)
Description
PWM clock frequency
PWM_HF
6
0 = 256 Hz
1 = 558 Hz
14
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100
95
90
85
80
75
70
BRIGHTNESS (%)
65
60
55
50
LOG_EN = 0
45
40
LOG_EN = 1
35
30
25
20
15
10
5
0
0
16 32 48 64 80 96 112 128 144 160 176 192 208 224 240 255
CONTROL (DEC)
SVA-30197405
Figure 17. Logarithmic and Linear PWM Adjustment Curves
Program Execution Engines
Use of program execution engines is the other LED output PWM control method available in the LP5562. The
device has 3 program execution engines. These engines create PWM controlled lighting patterns to the mapped
LED outputs according to program codes developed by the user. Program coding is done using programming
commands (see Program Execution Engine Programming Commands.) Programs are loaded into SRAM memory
and engine control bits are used to run these programs autonomously. LED outputs can be mapped into these 3
engines with register 70h bit settings (see Table 3). The engines have different operation modes, program
execution states, and program counters. Each engine has its own section of the SRAM memory.
Program Execution Engine States
Engine program execution is controlled from ENABLE register (00h). There are four different states for each
engine, and these states are described in Table 6.
Table 6. ENABLE register (00h)
Name
ENG1_EXEC
ENG2_EXEC
Bit
Description
5:4
Engine 1 program execution
00b = Hold: Wait until current command is finished then stop while EXEC
mode is hold. PC can be read or written only in this mode.
01b = Step: Execute instruction defined by current Engine 1 PC value,
increment PC, and change ENG1_EXEC to 00b (Hold).
10b = Run: Start at program counter value defined by current Engine 1 PC
value.
11b = Execute instruction defined by current Engine 1 PC value and
change ENG1_EXEC to 00b (Hold).
3:2
Engine 2 program execution
00b = Hold: Wait until current command is finished then stop while EXEC
mode is hold. PC can be read or written only in this mode.
01b = Step: Execute instruction defined by current Engine 2 PC value,
increment PC, and change ENG2_EXEC to 00b (Hold).
10b = Run: Start at program counter value defined by current Engine 2 PC
value.
11b = Execute instruction defined by current Engine 2 PC value and
change ENG2_EXEC to 00b (Hold).
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Table 6. ENABLE register (00h) (continued)
Name
ENG3_EXEC
Bit
Description
1:0
Engine 3 program execution
00b = Hold: Wait until current command is finished then stop while EXEC
mode is hold. PC can be read or written only in this mode.
01b = Step: Execute instruction defined by current engine 3 PC value,
increment PC, and change ENG3_EXEC to 00b (Hold).
10b = Run: Start at program counter value defined by current engine 3 PC
value.
11b = Execute instruction defined by current engine 3 PC value and
change ENG3_EXEC to 00b (Hold).
Program Execution Engine Operation Modes
Operation modes are defined in register address 01h. Each engine (1, 2, 3) operation mode can be configured
separately. Mode registers are synchronized to a 32 kHz clock. Delay between consecutive I2C writes to
OP_MODE register (01h) need to be longer than 153 μs (typ).
Table 7. Operation Mode Register (OP_MODE (01h)):
Name
ENG1_MODE
ENG2_MODE
ENG3_MODE
Bit
Description
5:4
Engine 1 operation mode
00b = Disabled, reset engine 1 PC
01b = Load program to SRAM, reset engine 1 PC
10b = Run program defined by ENG1_EXEC
11b = Direct control from B PWM I2C register, reset engine 1 PC
3:2
Engine 2 operation mode
00b = Disabled, reset engine 2 PC
01b = Load program to SRAM, reset engine 2 PC
10b = Run program defined by ENG2_EXEC
11b = Direct control from G PWM I2C register, reset engine 2 PC
1:0
Engine 3 operation mode
00b = Disabled, reset engine 3 PC
01b = Load program to SRAM, reset engine 3 PC
10b = Run program defined by ENG3_EXEC
11b = Direct control from R PWM I2C register, reset engine 3 PC
Operation Modes
•
•
•
16
Disabled
– Each channel can be configured to disabled mode. For the current engine mapped LED output brightness
will be 0 during this mode. Disabled mode resets respective engine’s PC.
Load program
– LP5562 can store 16 commands for each engine (1, 2, 3). Each command consists of 16 bits. Because
one register has only 8 bits, one command requires two I2C register addresses. In order to reduce
program load time the LP5562 supports address auto increment. Register address is incremented after
each 8 data bits. The whole program memory can be written in one I2C write sequence. Program memory
is defined in the LP5562 register table, from address 10h to address 2Fh for engine 1, from address 30h
to address 4Fh for engine 2, and from address 50h to address 6Fh for engine 3. In order to access
program memory at least one channel operation mode needs to be load program.
– SRAM memory writes are allowed only to the channel in load program mode. All engines are in hold while
one or several engines are in load program mode, and PWM values are frozen for the engines which are
not in load programmode. Program execution continues when all engines are out of load program mode.
Load program mode resets respective engine’s Program Counter (PC).
Run program
– Run program mode executes the commands defined in program memory for respective engine (1, 2, 3).
Execution register bits in ENABLE register (00h) define how the program is executed. The program start
position can be programmed to Program Counter register (see Table 8). By manually selecting the PC
start value, user can write different lighting sequences to the SRAM memory, and select appropriate
sequence with the PC register. If program counter runs to end (15), next command will be executed from
program location 0. If internal clock is used in the run program mode, operation mode needs to be written
disabled (00b) before disabling the chip (with CHIP_EN bit or EN pin) to ensure that the sequence starts
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from the correct program counter (PC) value when restarting the sequence. PC registers are synchronized
to 32 kHz clock. Delay between consecutive I2C writes to Program Counter (PC) registers (09h, 0Ah, 0Bh)
need to be longer than 153μs (typ.).
– Execution registers are synchronized to 32kHz clock. Delay between consecutive I2C writes to ENABLE
register (00h) need to be longer than 488μs (typ.).
– Note that entering LOAD program or Direct Control Mode from RUN PROGRAM mode is not allowed.
Engine execution mode should be set to Hold, and Operation Mode to disabled, when changing operation
mode from RUN mode.
Direct control
– In Direct control mode the engine PWM output is controlled by R, G and B PWM I2C registers.
– When engine 1 is in Direct control mode, the engine 1 PWM output is controlled by B PWM I2C register
(02h).
– When engine 2 is in Direct control mode, the engine 2 PWM output is controlled by G PWM I2C register
(03h).
– When engine 3 is in Direct control mode, the engine 3 PWM output is controlled by R PWM I2C register
(04h).
Program Execution Engine Program Counter (PC)
Program execution engine Program Counter tells the current program code command, which engine is executing.
By setting the program counter value before starting the engine execution, user can set the starting point of the
program execution.
Table 8. Engine1 PC Register (09h), Engine2 PC
Register (0Ah), Engine3 PC Register (0Bh)
Name
Bit
PC
3:0
Description
Program counter value from 0 to 15d
Program Execution Engine Programming Commands
The LP5562 has three independent programmable engines (1, 2, 3). Trigger connections between engines are
common for all engines. All engines have own program memory sections for storing LED lighting patterns.
Brightness control and patterns are done with 8-bit PWM control (256 steps) to get accurate and smooth color
control. Program execution is timed with 32.7 kHz clock. This clock can be generated internally or an external
32kHz clock can be connected to the CLK_32K pin. Using an external clock enables synchronization of LED
timing to this clock rather than an internal clock. Selection of the clock is made with address 08H bits
INT_CLK_EN and CLK_DET_EN. See External Clock for details. Supported commands are listed in the table
below.
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Table 9. LED Controller Programming Commands (1)
(1)
18
Command
15
14
13
12
11
10
RampWait
0
Prescale
Step time
Set PWM
0
1
0
Go to Start
0
0
0
Branch
1
0
1
End
1
1
0
Int
Reset
Trigger
1
1
1
X
X
9
8
7
6
5
Sign
4
3
2
1
0
0
0
Increment (number of steps)
PWM Value
0
Loop count
0
0
0
0
x
0
Step / command number
X
X
Wait for trigger on engines
1, 2, 3
X
X
X
Send trigger to engines 1,2,
3
X
X means do not care whether 1 or 0.
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Ramp/Wait
The ramp command generates a PWM ramp starting from current value. At each ramp step the output is
incremented by one. Time for one step is defined with Prescale and Step time bits. Minimum time for one step is
0.49 ms and maximum time is 63 x 15.6 ms = 1 second/step, so it is possible to program very fast and also very
slow ramps. Increment value defines how many steps are taken in one command. Number of actual steps is
Increment + 1. Maximum value is 127d, which corresponds to half of full scale (128 steps). If during ramp
command PWM reaches minimum/maximum (0/255) ramp command will be executed to the end and PWM will
stay at minimum/maximum. This enables the ramp command to be used as combined ramp and wait command
in a single instruction.
The ramp command can be used as wait instruction when increment is zero.
Setting register 00h bit LOG_EN sets the scale as either linear to logarithmic. When LOG_EN = 0, linear scale is
used, and when LOG_EN = 1, logarithmic scale is used. By using logarithmic scale the visual effect of the ramp
command seems linear to the eye.
Table 10. Ramp/Wait Command
Ramp/Wait command
15
14
0
Prescale
13
12
11
10
9
8
7
Step time
6
5
4
Sign
3
2
1
0
Increment
Table 11. Ramp/Wait Command Bits
Name
Prescale
Step time
Sign
Increment
Value(d)
Description
0
Divides master clock (32.768 Hz) by 16 = 2048 Hz, 0.49 ms cycle time
1
Divides master clock (32.768 Hz) by 512 = 64 Hz, 15.6 ms cycle time
One ramp increment done in (step time) x (clock after prescale) Note: 0 means set PMW
command.
1-63
0
Increase PWM output
1
Decrease PWM output
0-127
The number of steps is Increment + 1. Note: 0 is a wait instruction.
Application Example:
For example if following parameters are used for ramp:
• Prescale = 1 => cycle time = 15.6 ms
• Step time = 2 => time = 15.6 ms x 2 = 31.2 ms
• Sign = 0 => rising ramp Increment = 4 => 5 cycles
Ramp command will be: 0100 0010 0000 0100b = 4204h
If current PWM value is 3, and the first command is as described above, the next command is a ramp with
otherwise same the parameters, but with Sign = 1 (Command = 4284h), the result will be like in the following
figure:
End of 1st Ramp command,
start next command
PWM Control
Value
8
End of 2nd Ramp command,
start next command
Rising ramp,
Sign = 0
7
6
Increment = 4
=> 5 cycles
5
4
Current value
3
2
Downward
ramp, Sign = 1
Step time = 31.2 ms
1
Steps
1
2
3
4
5
6
7
8
9
10
SVA-30197407
Figure 18. Example of 2 sequential ramp commands
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Set PWM
Set PWM output value from 0 to 255. Command takes sixteen 32 kHz clock cycles (= 488 μs). Setting register
00h bit LOG_EN sets the scale from linear to logarithmic.
Table 12. Set PWM command bits
Set PWM command
15
14
13
12
11
10
9
8
0
1
0
0
0
0
0
0
7
6
5
4
3
2
1
0
PWM value
Go-to-Start
Go-to-start command resets the Program Counter register and continues executing program from the 00h
location. Command takes sixteen 32 kHz clock cycles. Note that default value for all program memory registers is
0000h, which is Go-to-Start command.
Table 13. Go-to-Start Command Bits
Go-to-Start command
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Branch
When branch command is executed, the 'step number' value is loaded to PC, and program execution continues
from this location. Looping is done by the number defined in loop count parameter. Nested looping is supported
(loop inside loop). The number of nested loops is not limited. Command takes sixteen 32 kHz clock cycles.
Table 14. Branch Command
(1)
Branch command
15
14
13
1
0
1
(1)
12
11
10
9
8
7
Loop count
6
5
4
X
X
X
3
2
1
0
Step number
X means do not care whether 1 or 0
Table 15. Branch Command Bits
Name
Value(d)
loop count
0-63
Description
The number of loops to be done. 0 means infinite loop.
step number
0-15
The step number to be loaded to program counter.
End
End program execution resets the program counter and sets the corresponding EXEC register to 00b (hold).
Command takes sixteen 32 kHz clock cycles.
Table 16. End Command
(1)
End command
(1)
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
1
1
0
int
reset
X
X
X
X
X
X
X
X
X
X
X
X means do not care whether 1 or 0.
Table 17. End Command Bits
Name
int
20
Value
Description
0
No interrupt will be sent.
1
Send interrupt by setting corresponding status register bit high to
notify that program has ended. Interrupt can only be cleared by
reading interrupt status register 0Ch.
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Table 17. End Command Bits (continued)
Name
Value
reset
Description
0
Keep the current PWM value.
1
Set PWM value to 0.
Trigger
Wait or send triggers can be used to synchronize operation between different engines. The send-trigger
command takes sixteen 32 kHz clock cycles; the wait-for-trigger command takes at least sixteen 32 kHz clock
cycles. The receiving engine stores sent triggers. Received triggers are cleared by wait for trigger command if
received triggers match to engines defined in the command. Engine waits until all defined triggers have been
received.
Table 18. Trigger Command (1)
15
14
13
12
11
10
1
1
1
X
X
X
9
ENG3
(1)
8
7
wait trigger
ENG2
6
5
4
3
1
0
X
X
X
send trigger
X
ENG1
ENG3
2
ENG2
ENG1
X means do not care whether 1 or 0.
Table 19. Trigger Command Bits
Name
Value(d)
Description
wait
trigger
0-7
Wait for trigger for the engine(s) defined. Several triggers can be
defined in the same command. Bit 0 is engine 1, bit 1 is engine2, bit
2 is engine 3.
send
trigger
0-7
Send trigger for the engine(s) defined. Several triggers can be
defined in the same command. Bit 0 is engine 1, bit 1 is engine2, bit
2 is engine 3.
Program Load and Execution Example
• Start up device and configure device to SRAM write mode
– Supply 3.6V to VDD
– Supply 1.8V to EN
– Wait 1 ms
– Generate 32 kHz clock to CLK_32K pin
– Write to address 00h 0100 0000b (enable device)
– Wait 500 μs (startup delay)
– Write to address 01h 0001 0000b (configure engine 1 into 'Load program to SRAM' mode)
• Program load to SRAM
– Write to address 10h 0000 0011b (1st ramp command 8MSB)
– Write to address 11h 0111 1111b (1st ramp command 8 LSB)
– Write to address 12h 0100 1101b (1st wait command 8 MSB)
– Write to address 13h 0000 0000b (1st wait command 8 LSB)
– Write to address 14h 0000 0011b (2nd ramp command 8 MSB)
– Write to address 15h 1111 1111b (2nd ramp command 8 LSB)
– Write to address 16h 0110 0000b (2nd wait command 8 MSB)
– Write to address 17h 0000 0000b (2nd wait command 8 LSB)
• Enable Power Save and use external 32 kHz clock
– Write to address 08h 0010 0000b (enable powersave, use external clock)
• Run program
– Write to address 01h 0010 0000b (Configure LED controller operation mode to "Run program" in engine 1)
– Write to address 00h 0110 0000b (Configure program execution mode from "Hold" to "Run" in engine 1)
The LP5562 will generate a 1100 ms long LED pattern which will be repeated infinitely. The LED pattern is
illustrated in the figure below.
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PWM value
255
LED PWM mapped
to Engine1
127
Time (ms)
100
200
300
400
500
600
Engine1 program:
ramp up to PWM value 128 in 200 ms
wait 200 ms
ramp down to PWM value 0 in 200 ms
wait 500 ms
700
800
900 1000 1100 1200 1300 1400 1500 1600 1700
Engine1 program as binary code:
0000001101111111
0100110100000000
0000001111111111
0110000000000000
SVA-30197408
Figure 19. LED Lighting Pattern and Code for Program Load and Execution Example
SRAM Memory
In the LP5562 there is a SRAM memory reserved for storing the LED lighting programs. Each engine has its own
section of the memory so that engine 1 has registers 10h to 2Fh, engine 2 has registers 30h to 4Fh, and engine
3 has registers 50h to 6Fh. For each engine 16 engine commands (16-bit) can be stored. Each 16-bit command
takes up two I2C registers.
Table 20. SRAM Memory Registers
Address
Register
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
10h
Prog mem
ENG1
COMMAND1_ENG1[15:8]
11h
Prog mem
ENG1
COMMAND1_ENG1[7:0]
2Eh
Prog mem
ENG1
COMMAND16_ENG1[15:8]
2Fh
Prog mem
ENG1
COMMAND16_ENG1[7:0]
30h
Prog mem
ENG2
COMMAND1_ENG2[15:8]
31h
Prog mem
ENG2
COMMAND1_ENG2[7:0]
4Eh
Prog mem
ENG2
COMMAND16_ENG2[15:8]
4Fh
Prog mem
ENG2
COMMAND16_ENG2[7:0]
50h
Prog mem
ENG3
COMMAND1_ENG3[15:8]
51h
Prog mem
ENG3
COMMAND1_ENG3[7:0]
6Eh
Prog mem
ENG3
COMMAND16_ENG3[15:8]
6Fh
Prog mem
ENG3
COMMAND16_ENG3[7:0]
Bit1
Bit0
...
...
...
22
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When downloading a program to the SRAM engine modes need to be set to Load mode (see Table 6). While
loading sequential I2C writing can be used (repeated start see Figure 25). However, please note that sequential
read of the SRAM is not possible.
Power Save Mode
Automatic power save mode is enabled when the PS_EN bit in register address 08h is 1. Almost all analog
blocks are powered down in power save, if an external clock is used. However, if an internal clock has been
selected, only the LED drivers are disabled during power save since the digital part of the LED controller need to
remain active. During program execution the LP5562 can enter power-save mode if there is no PWM activity in
engine controlled outputs. To prevent short power-save sequences during program execution, the LP5562 has a
command look-ahead filter. In each instruction cycle every engine commands are analyzed, and if there is
sufficient time left with no PWM activity, the device will enter power save. In power save program execution
continues uninterruptedly. When a command that requires PWM activity is executed, fast internal startup
sequence will be started automatically. The following tables describe commands and conditions that can activate
power save. All engines need to meet power-save conditions in order to enable power save.
Table 21. Engine Operation Mode and Power Save
Engine operation mode
Power save condition
00b
Disabled mode enables power save
01b
Load program to SRAM mode prevents power save.
10b
Run program mode enables power save if there is no PWM activity and
command look-ahead filter condition is met.
11b
Direct control mode enables power save if there is no PWM activity.
Table 22. Engine Commands and Power Save
Command
Wait
Power save condition
No PWM activity and current command wait time longer than 50 ms. If
prescale = 1 then wait time needs to be longer than 80 ms.
Ramp
Ramp Command PWM value reaches minimum 0 and current command
execution time left more than 50 ms. If prescale = 1 then time left needs to be
more than 80 ms.
Trigger
No PWM activity during wait for trigger command execution.
End
Set PWM
Other commands
No PWM activity or Reset bit = 1.
Enables power save if PWM set to 0 and next command generates at least 50
ms wait.
No effect to power save.
External Clock
The presence of an external clock can be detected by the LP5562. Program execution is clocked with an internal
32 kHz clock or with an external clock. Clocking is controlled with register address 08h bits, INT_CLK_EN, and
CLK_DET_EN as seen in Table 23.
An external clock can be used if clock is present at the CLK_32K pin. The external clock frequency must be 32
kHz for the program execution PWM timing to be as specified. If higher or lower frequency is used, it will affect
the program engine execution speed. If a clock frequency other than 32kHz is used, the program execution
timings must be scaled accordingly.
LP5562 has automatic external clock detection. The external clock detector block only detects too low clock
frequency (
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