MCT8316Z
ZHCSNP1A – MARCH 2021 – REVISED OCTOBER 2021
MCT8316Z 含传感器梯形集成式 FET BLDC 电机驱动器
1 特性
3 说明
• 集成含传感器梯形控制的三相 BLDC 电机驱动器
– 基于霍尔传感器的梯形 (120°) 换向
– 支持模拟或数字霍尔输入
– 可配置 PWM 调制:同步/异步
– 逐周期电流限制,可限制相位电流
– 支持高达 200kHz 的 PWM 频率
– 主动消磁支持减少功率损耗
• 4.5V 至 35V 工作电压(绝对最大值 40V)
• 高输出电流能力:8A 峰值
• 低 MOSFET 导通状态电阻
– TA = 25°C 时,RDS(ON) (HS + LS) 为 95mΩ
• 低功耗睡眠模式
– 1.5µA(VVM = 24V,TA = 25°C)
• 集成内置电流检测
– 无需外部电流检测电阻器
• 灵活的器件配置选项
– MCT8316ZR:用于器件配置和故障状态的
5MHz 16 位 SPI 接口
– MCT8316ZT:基于硬件引脚的配置
• 支持 1.8V、3.3V 和 5V 逻辑输入
• 内置 3.3V (5%)、30mA LDO 稳压器
• 内置 3.3V/5V、200mA 降压稳压器
• 延迟补偿减少占空比失真
• 整套集成保护特性
– 电源欠压锁定 (UVLO)
– 电荷泵欠压 (CPUV)
– 过流保护 (OCP)
– 电机锁定保护
– 热警告和热关断 (OTW/OTSD)
– 故障条件指示引脚 (nFAULT)
– 可选择通过 SPI 接口进行故障诊断
MCT8316Z 为要驱动 12V 至 24V 有刷直流电机的客户
提供了一种单芯片无代码含传感器梯形解决方案。
MCT8316Z 集成了三个 1/2 H 桥,具有 40V 的绝对最
大电压和 95mΩ 的超低 RDS(ON)(高侧和低侧相结
合),可提供大功率驱动能力。电流通过集成电流检测
功能检测,无需再使用外部功率检测电阻器。可调降压
稳压器和 LDO 的电源管理系列能够为器件生成必要的
电压轨,可用于为外部电路供电。
MCT8316Z 集成多种保护特性,旨在出现故障事件时
保护该器件、电机和系统。
有关器件使用的设计考虑因素和建议,请参考
Application Information。
器件信息(1)
器件型号
VQFN (40)
7.00mm x 5.00mm
MCT8316ZT
VQFN (40)
7.00mm × 5.00mm
(1)
(2)
如需了解所有可用封装,请参阅数据表末尾的可订购产品附
录。
器件为预发布状态。
Buck/LDO out
无刷直流 (BLDC) 电机模块
小型家用电器
HVAC 电机
办公自动化设备
工厂自动化和机器人
4.5V to 35V (40V abs max)
8-A peak output current,
typically 12- to 24-V,
3.3 or 5.0 V, up to
200mA
MCT8316Z
A
SPEED
Buck/LDO out
PWM input
DIRECTION
BRAKE
•
•
•
•
•
封装尺寸(标称值)
封装
MCT8316ZR(2)
Sensored
Trap
Control
MOSFETs
2 应用
MCT8316Z 在固定功能状态机中实现含传感器梯形控
制,因此无需外部微控制器即可使无刷直流电机转动。
该器件集成了三个用于位置感应的模拟霍尔比较器,以
实现含传感器梯形 BLDC 电机控制。该控制方案具有
高度可配置性,可通过硬件引脚或寄存器设置进行配
置,范围涵盖从电机电流限制行为到故障响应。速度可
以通过 PWM 输入进行控制。
FGOUT
Speed feecback
nFAULT
B
H
H
C
Buck/LDO Regulator
H
SPI
Only on SPI
variant
Integrated Current Sensing
Hall inputs support:
Differen al Hall elements
Differen al analog output Hall-effect sensors
Digital output Hall-effect sensors
Single-ended analog output Hall-effect sensors
简化版原理图
本文档旨在为方便起见,提供有关 TI 产品中文版本的信息,以确认产品的概要。有关适用的官方英文版本的最新信息,请访问
www.ti.com,其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前,请务必参考最新版本的英文版本。
English Data Sheet: SLVSF18
MCT8316Z
www.ti.com.cn
ZHCSNP1A – MARCH 2021 – REVISED OCTOBER 2021
Table of Contents
1 特性................................................................................... 1
2 应用................................................................................... 1
3 说明................................................................................... 1
4 Revision History.............................................................. 2
5 Device Comparison Table ..............................................3
6 Pin Configuration and Functions...................................4
Pin Functions.................................................................... 5
7 Specifications.................................................................. 7
7.1 Absolute Maximum Ratings ....................................... 7
7.2 ESD Ratings .............................................................. 7
7.3 Recommended Operating Conditions ........................7
7.4 Thermal Information ...................................................8
7.5 Electrical Characteristics ............................................8
7.6 SPI Timing Requirements ........................................ 15
7.7 SPI Secondary Mode Timings...................................16
7.8 Typical Characteristics.............................................. 16
8 Detailed Description......................................................18
8.1 Overview................................................................... 18
8.2 Functional Block Diagram......................................... 19
8.3 Feature Description...................................................21
8.4 Device Functional Modes..........................................59
8.5 SPI Communication.................................................. 60
8.6 Register Map.............................................................63
9 Application and Implementation.................................. 78
9.1 Application Information............................................. 78
9.2 Hall Sensor Configuration and Connection...............79
9.3 Typical Applications.................................................. 83
10 Power Supply Recommendations..............................88
10.1 Bulk Capacitance.................................................... 88
11 Layout........................................................................... 89
11.1 Layout Guidelines................................................... 89
11.2 Layout Example...................................................... 90
11.3 Thermal Considerations.......................................... 91
12 Device and Documentation Support..........................92
12.1 支持资源..................................................................92
12.2 Trademarks............................................................. 92
12.3 Electrostatic Discharge Caution..............................92
12.4 术语表..................................................................... 92
4 Revision History
Changes from , to , (from Revision * (March 2021) to Revision A (October 2021))
Page
• 将器件状态更新为“量产数据”。......................................................................................................................1
2
Submit Document Feedback
Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: MCT8316Z
MCT8316Z
www.ti.com.cn
ZHCSNP1A – MARCH 2021 – REVISED OCTOBER 2021
5 Device Comparison Table
DEVICE
PACKAGES
INTERFACE
BUCK REGULATOR
MCT8316ZR(1)
40-pin VQFN (7x5 mm)
SPI
Yes
MCT8316ZT
(1)
Hardware
Device available for preview only.
表 5-1. MCT8316ZR (SPI variant) vs. MCT8316ZT (Hardware variant) configuration comparison
Parameters
MCT8316ZR (SPI variant)
MCT8316ZT (Hardware variant)
PWM control mode settings
PWM_MODE (4 settings)
MODE pin (7 settings)
Slew rate settings
SLEW (4 settings)
SLEW pin (4 settings)
Direction settings
DIR (2 settings)
DIR pin (2 settings)
DRVOFF pin configuration
DRV_OFF (2 settings)
Enabled
Current limit threshold
ILIMIT pin: AVDD/2 to AVDD/2-0.4V
ILIMIT pin: AVDD/2 to AVDD/2-0.4V
Current limit configuration
ILIM_RECIR (2 settings),
PWM_100_DUTY_SEL
Recirculation fixed to Brake mode and PWM
frequency for 100% duty fixed to 20 kHz
CSA GAIN
CSA_GAIN (4 settings)
Fixed to 0.15 V/A
Lead angle settings
ADVANCE_LVL (8 settings)
ADVANCE pin (7 settings)
Buck enable
BUCK_DIS (2 settings)
Enabled
BUCK_SEL(4 settings)
VSEL_BK pin (4 settings)
Buck threshold
Buck configuration: power sequencing,
current limit and slew rate
BUCK_PS_DIS (2 settings) and BUCK_CL(2 Power sequencing enabled, current limit: 600
settings)
mA and slew rate: 1000 V/us
FGOUT configuration
FGOUT_SEL (4 settings)
Fixed to commutation frequency
Motor lock configuration: mode, detection
and retry timing
MTR_LOCK_MODE (4 settings),
MTR_LOCK_TDET (4 settings),
MTR_LOCK_RETRY (2 settings)
Enabled with latched shutdown mode and
detection time of 1000 ms
Active demagnetization
EN_AAR (2 settings) and EN_ASR (2
settings)
MODE pin (7 settings)
OCP configuration: Mode,
OCP_MODE (4 settings) , OCP_LVL (4
settings) ,OCP_DEG (4 settings) and
OCP_RETRY (2 settings)
Enabled with latched shutdown mode, level is
fixed to 16A with 0.6 us deglitch time
Overvoltage protection configuration
OVP_EN (2 settings) , OVP_SEL (2 settings)
Enabled and level is fixed to 34V (typ)
Driver delay compensation configuration
DLYCMP_EN (2 settings), DLY_TARGET (16
settings)
Disabled
SDO pin configuration
SDO_MODE (2 settings)
NA
SPI fault configuration
SPI_PARITY(2 settings), SPI_SCLK_FLT(2
settings), SPI_ADDR_FLT(2 settings)
NA
Submit Document Feedback
Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: MCT8316Z
3
MCT8316Z
www.ti.com.cn
ZHCSNP1A – MARCH 2021 – REVISED OCTOBER 2021
5
CPL
6
CPH
7
MCT8316ZR
(Thermal PAD)
28
HNA
27
HPA
26
AGND
CP
8
25
AVDD
VM
9
24
NC
18
19
20
OUTC
OUTC
DRVOFF
PGND
21
17
12
OUTB
PGND
16
nFAULT
15
22
OUTB
11
PGND
VM
13
nSLEEP
14
23
OUTA
10
OUTA
VM
图 6-1. MCT8316ZR 40-Pin VQFN With Exposed
Thermal Pad Top View
4
ILIM
DIR
ADVANCE
SLEW
MODE
36
35
34
33
BRAKE
38
37
PWM
39
3
30
HNB
4
29
HPB
SW_BK
5
28
HNA
27
HPA
26
AGND
CPL
6
CPH
7
MCT8316ZT
(Thermal Pad)
CP
8
25
AVDD
VM
9
24
VSEL_BK
VM
10
23
nSLEEP
VM
11
22
nFAULT
PGND
12
21
DRVOFF
20
SW_BK
FB_BK
GND_BK
OUTC
HPB
19
29
18
4
OUTC
GND_BK
PGND
HNB
HNC
HPC
17
30
32
31
OUTB
3
1
2
OUTB
FB_BK
NC
AGND
16
HPC
15
SDO
33
31
PGND
SDI
34
2
FGOUT
SCLK
35
AGND
40
nSCS
36
HNC
13
ILIM
37
32
14
BRAKE
38
1
OUTA
PWM
NC
OUTA
FGOUT
40
39
6 Pin Configuration and Functions
图 6-2. MCT8316ZT 40-Pin VQFN With Exposed
Thermal Pad Top View
Submit Document Feedback
Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: MCT8316Z
MCT8316Z
www.ti.com.cn
ZHCSNP1A – MARCH 2021 – REVISED OCTOBER 2021
Pin Functions
PIN
40-pin Package
TYPE(1)
DESCRIPTION
NAME
MCT8316ZR
MCT8316ZT
ADVANCE
—
35
I
AGND
2, 26
2, 26
GND
AVDD
25
25
PWR O
BRAKE
38
38
I
CP
8
8
PWR O
CPH
7
7
PWR
CPL
6
6
PWR
DIR
—
36
I
Direction pin for setting the direction of the motor rotation to clockwise or
counterclockwise.
DRVOFF
21
21
I
When this pin is pulled high the six MOSFETs in the power stage are turned
OFF making all outputs Hi-Z.
FB_BK
3
3
PWR I
FGOUT
40
40
O
GND_BK
4
4
GND
HPA
27
27
I
Phase A hall element positive input. Noise filter capacitors may be desirable,
connected between the positive and negative hall inputs.
HPB
29
29
I
Phase B hall element positive input. Noise filter capacitors may be desirable,
connected between the positive and negative hall inputs.
HPC
31
31
I
Phase C hall element positive input. Noise filter capacitors may be desirable,
connected between the positive and negative hall inputs.
HNA
28
28
I
Phase A hall element negative input. Noise filter capacitors may be desirable,
connected between the positive and negative hall inputs.
HNB
30
30
I
Phase B hall element negative input. Noise filter capacitors may be desirable,
connected between the positive and negative hall inputs.
HNC
32
32
I
Phase C hall element negative input. Noise filter capacitors may be desirable,
connected between the positive and negative hall inputs.
ILIM
37
37
I
Set the threshold for phase current used in cycle by cycle current limit.
MODE
—
33
I
PWM input mode setting. This pin is a 7-level input pin set by an external
resistor.
1, 24
1
—
No connection, open
nFAULT
22
22
O
Fault indicator. Pulled logic-low with fault condition; Open-drain output requires
an external pull-up resistor to 1.8V to 5.0V. If external supply is used to pull up
nFAULT, ensure that it is pulled to >2.2V on power up or the device will enter
test mode
nSCS
36
—
I
Serial chip select. A logic low on this pin enables serial interface
communication.
nSLEEP
23
23
I
Driver nSLEEP. When this pin is logic low, the device goes into a low-power
sleep mode. An 20 to 40-µs low pulse can be used to reset fault conditions
without entering sleep mode.
OUTA
13, 14
13, 14
PWR O
Half bridge output A
OUTB
16, 17
16, 17
PWR O
Half bridge output B
NC
Advance angle level setting. This pin is a 7-level input pin set by an external
resistor.
Device analog ground. Refer Layout Guidelines for connections
recommendation.
3.3-V internal regulator output. Connect an X5R or X7R, 1-µF, 6.3-V ceramic
capacitor between the AVDD and AGND pins. This regulator can source up to
30 mA externally.
High → Brake the motor when High by turning all low side MOSFETs ON
Low → normal operation
Charge pump output. Connect a X5R or X7R, 1-µF, 16-V ceramic capacitor
between the CP and VM pins.
Charge pump switching node. Connect a X5R or X7R, 47-nF, ceramic
capacitor between the CPH and CPL pins. TI recommends a capacitor voltage
rating at least twice the normal operating voltage of the device.
Feedback for buck regulator. Connect to buck regulator output after the
inductor/resistor.
Motor Speed indicator output. Open-drain output requires an external pull-up
resistor to 1.8V to 5.0V. It can be set to different division factor of Hall signals
(see FGOUT Signal)
Buck regulator ground. Refer Layout Guidelines for connections
recommendation.
Submit Document Feedback
Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: MCT8316Z
5
MCT8316Z
www.ti.com.cn
ZHCSNP1A – MARCH 2021 – REVISED OCTOBER 2021
PIN
NAME
40-pin Package
DESCRIPTION
MCT8316ZT
OUTC
19, 20
19, 20
PWR O
PGND
12, 15, 18
12, 15, 18
GND
PWM
39
39
I
PWM input for motor control. Set the duty cycle and switching frequency of the
phase voltage of the motor.
SCLK
35
—
I
Serial clock input. Serial data is shifted out and captured on the corresponding
rising and falling edge on this pin (SPI devices).
SDI
34
—
I
Serial data input. Data is captured on the falling edge of the SCLK pin (SPI
devices).
SDO
33
—
O
Serial data output. Data is shifted out on the rising edge of the SCLK pin. This
pin requires an external pullup resistor (SPI devices).
SLEW
—
34
I
Slew rate control setting. This pin is a 4-level input pin set by an external
resistor (Hardware devices).
SW_BK
5
5
PWR O
Buck switch node. Connect this pin to an inductor or resistor.
Power supply. Connect to motor supply voltage; bypass to PGND with two 0.1µF capacitors (for each pin) plus one bulk capacitor rated for VM. TI
recommends a capacitor voltage rating at least twice the normal operating
voltage of the device.
VM
VSEL_BK
9, 10, 11
9, 10, 11
PWR I
—
24
I
Thermal
pad
(1)
6
TYPE(1)
MCT8316ZR
GND
Half bridge output C
Device power ground. Refer Layout Guidelines for connections
recommendation.
Buck output voltage setting. This pin is a 4-level input pin set by an external
resistor.
Must be connected to analog ground.
I = input, O = output, GND = ground pin, PWR = power, NC = no connect
Submit Document Feedback
Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: MCT8316Z
MCT8316Z
www.ti.com.cn
ZHCSNP1A – MARCH 2021 – REVISED OCTOBER 2021
7 Specifications
7.1 Absolute Maximum Ratings
over operating ambient temperature range (unless otherwise noted)(1)
Power supply pin voltage (VM)
MIN
MAX
–0.3
40
V
4
V/µs
Power supply voltage ramp (VM)
Voltage difference between ground pins (GND_BK, PGND, AGND)
–0.3
Charge pump voltage (CPH, CP)
UNIT
0.3
V
–0.3
VM + 6
V
Charge pump negative switching pin voltage (CPL)
–0.3
VM + 0.3
V
Switching regulator pin voltage (FB_BK)
–0.3
5.75
V
Switching node pin voltage (SW_BK)
–0.3
VM + 0.3
V
Analog regulators pin voltage (AVDD)
–0.3
4
V
Logic pin input voltage (DRVOFF, PWM, nSCS, nSLEEP, SCLK, SDI)
–0.3
5.75
V
Logic pin output voltage (nFAULT, SDO)
–0.3
5.75
V
Output pin voltage (OUTA, OUTB, OUTC)
–1
VM + 1
V
Ambient temperature, TA
–40
125
°C
Junction temperature, TJ
–40
150
°C
Storage tempertaure, Tstg
–65
150
°C
(1)
Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply
functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions. If
used outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not be fully
functional, and this may affect device reliability, functionality, performance, and shorten the device lifetime.
7.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic
discharge
Human body model (HBM), per ANSI/ESDA/JEDEC
JS-001(1)
UNIT
±2000
Charged device model (CDM), per ANSI/ESDA/JEDEC JS-002(2)
V
±500
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
7.3 Recommended Operating Conditions
over operating ambient temperature range (unless otherwise noted)
MIN
NOM
MAX
4.5
24
35
V
OUTA, OUTB, OUTC
200
kHz
OUTA, OUTB, OUTC
8
A
–0.1
5.5
V
–0.1
5.5
V
2.2
5.5
V
2.8
AVDD
V
Operating ambient temperature
–40
125
°C
Operating Junction temperature
–40
150
°C
VVM
Power supply voltage
VVM
fPWM
Output PWM frequency
IOUT (1)
Peak output winding current
VIN
Logic input voltage
DRVOFF, INHx, INLx, nSCS, nSLEEP,
SCLK, SDI
VOD
Open drain pullup voltage
nFAULT, SDO
VSDO
Push-pull voltage
SDO
IOD
Open drain output current
nFAULT, SDO
VVREF
Voltage reference pin voltage
VREF
TA
TJ
(1)
5
UNIT
mA
Power dissipation and thermal limits must be observed
Submit Document Feedback
Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: MCT8316Z
7
MCT8316Z
www.ti.com.cn
ZHCSNP1A – MARCH 2021 – REVISED OCTOBER 2021
7.4 Thermal Information
MCT8316ZT,
MCT8316ZR
THERMAL METRIC(1)
UNIT
VQFN (RGF)
40 Pins
RθJA
Junction-to-ambient thermal resistance
25.7
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
15.2
°C/W
RθJB
Junction-to-board thermal resistance
7.3
°C/W
ΨJT
Junction-to-top characterization parameter
0.2
°C/W
ΨJB
Junction-to-board characterization parameter
7.2
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
2.0
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
7.5 Electrical Characteristics
TJ = –40°C to +150°C, VVM = 4.5 to 35 V (unless otherwise noted). Typical limits apply for TA = 25°C, VVM = 24 V
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
POWER SUPPLIES
IVMQ
VM sleep mode current
IVMS
VM standby mode current
(Buck regulator disabled)
VM standby mode current
(Buck regulator enabled)
IVMS
VM operating mode current
(Buck regulator disabled)
IVM
VM operating mode current
(Buck regulator enabled)
IVM
8
VAVDD
Analog regulator voltage
IAVDD
External analog regulator load
VVCP
Charge pump regulator voltage
fCP
Charge pump switching frequency
VVM > 6 V, nSLEEP = 0, TA = 25 °C
1.5
2.5
µA
nSLEEP = 0
2.5
5
µA
nSLEEP = 1, PWM = 0, SPI =
'OFF', BUCK_DIS = 1;
4
10
mA
VVM > 6 V, nSLEEP = 1, PWM = 0, SPI =
'OFF', TA = 25 °C, BUCK_DIS = 1;
4
5
mA
VVM > 6 V, nSLEEP = 1, PWM = 0, SPI =
'OFF', IBK = 0, TA = 25 °C, BUCK_DIS =
0;
5
6
mA
nSLEEP = 1, PWM = 0, SPI = 'OFF', IBK
= 0, BUCK_DIS = 0;
6
10
mA
VVM > 6 V, nSLEEP = 1, fPWM = 25 kHz,
TA = 25 °C, BUCK_DIS = 1
10
13
mA
VVM > 6 V, nSLEEP = 1, fPWM = 200 kHz,
TA = 25 °C, BUCK_DIS = 1
18
21
mA
nSLEEP =1, fPWM = 25 kHz, BUCK_DIS
=1
11
15
mA
nSLEEP =1, fPWM = 200 kHz,
BUCK_DIS = 1
17
24
mA
VVM > 6 V, nSLEEP = 1, fPWM = 25 kHz,
TA = 25 °C, BUCK_DIS =
0; BUCK_PS_DIS = 0
11
13
mA
VVM > 6 V, nSLEEP = 1, fPWM = 200 kHz,
TA = 25 °C, BUCK_DIS =
0; BUCK_PS_DIS = 0
19
22
mA
nSLEEP =1, fPWM = 25 kHz, BUCK_DIS
= 0; BUCK_PS_DIS = 0
12
16
mA
nSLEEP =1, fPWM = 200 kHz,
BUCK_DIS = 0; BUCK_PS_DIS = 0
18
27
mA
3.3
3.465
0 mA ≤ IAVDD ≤ 30 mA; BUCK_PS_DIS
=0
3.1
30
VCP with respect to VM
3.6
4.7
400
Submit Document Feedback
5.2
V
mA
V
kHz
Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: MCT8316Z
MCT8316Z
www.ti.com.cn
ZHCSNP1A – MARCH 2021 – REVISED OCTOBER 2021
TJ = –40°C to +150°C, VVM = 4.5 to 35 V (unless otherwise noted). Typical limits apply for TA = 25°C, VVM = 24 V
PARAMETER
TEST CONDITIONS
MIN
tPWM_LOW
PWM low time required for motor lock
detection
tWAKE
Wakeup time
VVM > VUVLO, nSLEEP = 1 to outputs
ready and nFAULT released
tSLEEP
Sleep Pulse time
nSLEEP = 0 period to enter sleep mode
tRST
Reset Pulse time
nSLEEP = 0 period to reset faults
20
VVM > 6 V, 0 mA ≤ IBK ≤ 200 mA,
BUCK_SEL = 00b
3.1
VVM > 6 V, 0 mA ≤ IBK ≤ 200 mA,
BUCK_SEL = 01b
TYP
MAX UNIT
200
ms
1
120
ms
µs
40
µs
3.3
3.5
V
4.6
5.0
5.4
V
VVM > 6 V, 0 mA ≤ IBK ≤ 200 mA,
BUCK_SEL = 10b
3.7
4.0
4.3
V
VVM > 6.7 V, 0 mA ≤ IBK ≤ 200 mA,
BUCK_SEL = 11b
5.2
5.7
6.2
V
BUCK REGULATOR
VBK
Buck regulator average voltage
(LBK = 47 µH, CBK = 22 µF)
(SPI Device)
VVM < 6.0 V (BUCK_SEL = 00b, 01b,
10b) or VVM < 6.0 V (BUCK_SEL = 11b),
0 mA ≤ IBK ≤ 200 mA
VBK
Buck regulator average voltage
(LBK = 22 µH, CBK = 22 µF)
(SPI Device)
VVM–
IBK*(RLBK+
2)(1)
VVM > 6 V, 0 mA ≤ IBK ≤ 50 mA,
BUCK_SEL = 00b
3.1
3.3
3.5
V
VVM > 6 V, 0 mA ≤ IBK ≤ 50 mA,
BUCK_SEL = 01b
4.6
5.0
5.4
V
VVM > 6 V, 0 mA ≤ IBK ≤ 50 mA,
BUCK_SEL = 10b
3.7
4.0
4.3
V
VVM > 6.7 V, 0 mA ≤ IBK ≤ 50 mA,
BUCK_SEL = 11b
5.2
5.7
6.2
V
VVM < 6.0 V (BUCK_SEL = 00b, 01b,
10b) or VVM < 6.0 V (BUCK_SEL = 11b),
0 mA ≤ IBK ≤ 50 mA
VBK
Buck regulator average voltage
(RBK = 22 Ω, CBK = 22 µF)
(SPI Device)
VVM–
IBK*(RLBK+
2) (1)
VBK
V
VVM > 6 V, 0 mA ≤ IBK ≤ 40 mA,
BUCK_SEL = 00b
3.1
3.3
3.5
V
VVM > 6 V, 0 mA ≤ IBK ≤ 40 mA,
BUCK_SEL = 01b
4.6
5.0
5.4
V
VVM > 6 V, 0 mA ≤ IBK ≤ 40 mA,
BUCK_SEL = 10b
3.7
4.0
4.3
V
VVM > 6.7 V, 0 mA ≤ IBK ≤ 40 mA,
BUCK_SEL = 11b
5.2
5.7
6.2
V
VVM < 6.0 V (BUCK_SEL = 00b, 01b,
10b) or VVM < 6.0 V (BUCK_SEL = 11b),
0 mA ≤ IBK ≤ 40 mA
Buck regulator average voltage
(LBK = 47 µH, CBK = 22 µF)
(HW Device)
V
VVM–
IBK*(RBK+2
)(1)
V
VVM > 6 V, 0 mA ≤ IBK ≤ 200 mA,
VSEL_BK pin tied to AGND
3.1
3.3
3.5
VVM > 6 V, 0 mA ≤ IBK ≤ 200
mA, VSEL_BK pin to Hi-Z
4.6
5.0
5.4
VVM > 6 V, 0 mA ≤ IBK ≤ 200
mA, VSEL_BK pin to 47 kΩ +/- 5% tied
to AVDD
3.7
4.0
4.3
VVM > 6.7 V, 0 mA ≤ IBK ≤ 200 mA,
VSEL_BK pin to AGND
5.2
5.7
6.2
VVM < 6.0 V, 0 mA ≤ IBK ≤ 200 mA
VVM–
IBK*(RLBK+
2)(1)
V
V
Submit Document Feedback
Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: MCT8316Z
9
MCT8316Z
www.ti.com.cn
ZHCSNP1A – MARCH 2021 – REVISED OCTOBER 2021
TJ = –40°C to +150°C, VVM = 4.5 to 35 V (unless otherwise noted). Typical limits apply for TA = 25°C, VVM = 24 V
PARAMETER
Buck regulator average voltage
(LBK = 22 µH, CBK = 22 µF)
(HW Device)
VBK
MIN
TYP
VVM > 6 V, 0 mA ≤ IBK ≤ 50 mA,
VSEL_BK pin tied to AGND
TEST CONDITIONS
3.1
3.3
3.5
V
VVM > 6 V, 0 mA ≤ IBK ≤ 50
mA, VSEL_BK pin to Hi-Z
4.6
5.0
5.4
V
VVM > 6 V, 0 mA ≤ IBK ≤ 50
mA, VSEL_BK pin to 47 kΩ +/- 5% tied
to AVDD
3.7
4.0
4.3
V
VVM > 6.7 V, 0 mA ≤ IBK ≤ 50 mA,
VSEL_BK pin to AGND
5.2
5.7
6.2
V
VVM–
IBK*(RLBK+
2)(1)
VVM < 6.0 V, 0 mA ≤ IBK ≤ 50 mA
Buck regulator average voltage
(RBK = 22 Ω, CBK = 22 µF)
(HW Device)
VBK
IBK
Buck regulator ripple voltage
External buck regulator load
3.1
3.3
3.5
V
VVM > 6 V, 0 mA ≤ IBK ≤ 40
mA, VSEL_BK pin to Hi-Z
4.6
5.0
5.4
V
VVM > 6 V, 0 mA ≤ IBK ≤ 40
mA, VSEL_BK pin to 47 kΩ +/- 5% tied
to AVDD
3.7
4.0
4.3
V
VVM > 6.7 V, 0 mA ≤ IBK ≤ 40 mA,
VSEL_BK pin to AGND
5.2
5.7
6.2
V
VVM–
IBK*(RBK+2
)(1)
–100
100
mV
VVM > 6 V, 0 mA ≤ IBK ≤ 50 mA, Buck
regulator with inductor, LBK = 22 uH, CBK
= 22 µF
–100
100
mV
VVM > 6 V, 0 mA ≤ IBK ≤ 50 mA, Buck
regulator with resistor; RBK = 22 Ω, CBK
= 22 µF
–100
100
mV
LBK = 47 uH, CBK = 22 µF,
BUCK_PS_DIS = 1b
200
mA
LBK = 47 uH, CBK = 22 µF,
BUCK_PS_DIS = 0b
200 –
IAVDD
mA
50
mA
50 –
IAVDD
mA
40
mA
40 –
IAVDD
mA
LBK = 22 uH, CBK =
22 µF, BUCK_PS_DIS = 1b
LBK = 22 uH, CBK = 22 µF,
BUCK_PS_DIS = 0b
RBK = 22 Ω, CBK = 22 µF,
BUCK_PS_DIS = 0b
10
Buck regulator switching frequency
V
VVM > 6 V, 0 mA ≤ IBK ≤ 200 mA, Buck
regulator with inductor, LBK = 47 uH, CBK
= 22 µF
RBK = 22 Ω, CBK =
22 µF, BUCK_PS_DIS = 1b
fSW_BK
V
VVM > 6 V, 0 mA ≤ IBK ≤ 40 mA,
VSEL_BK pin tied to AGND
VVM < 6.0 V, 0 mA ≤ IBK ≤ 40 mA
VBK_RIP
MAX UNIT
Regulation Mode
20
535
kHz
Linear Mode
20
535
kHz
Submit Document Feedback
Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: MCT8316Z
MCT8316Z
www.ti.com.cn
ZHCSNP1A – MARCH 2021 – REVISED OCTOBER 2021
TJ = –40°C to +150°C, VVM = 4.5 to 35 V (unless otherwise noted). Typical limits apply for TA = 25°C, VVM = 24 V
PARAMETER
VBK_UV
Buck regulator undervoltage lockout
(SPI Device)
MIN
TYP
VBK rising, BUCK_SEL = 00b
TEST CONDITIONS
2.7
2.8
VBK falling, BUCK_SEL = 00b
2.5
VBK rising, BUCK_SEL = 01b
4.2
VBK falling, BUCK_SEL = 01b
VBK rising, BUCK_SEL = 10b
2.9
V
2.6
2.7
V
4.4
4.55
V
4.0
4.2
4.35
V
2.7
2.8
2.9
V
VBK falling, BUCK_SEL = 10b
2.5
2.6
2.7
V
VBK rising, BUCK_SEL = 11b
4.2
4.4
4.55
V
VBK falling, BUCK_SEL = 11b
VBK_UV
Buck regulator undervoltage lockout
(HW Device)
MAX UNIT
4
4.2
4.35
V
VBK rising, VSEL_BK pin tied to AGND
2.7
2.8
2.9
V
VBK falling, VSEL_BK pin tied to AGND
2.5
2.6
2.7
V
VBK rising, VSEL_BK pin to 47 kΩ +/5% tied to AVDD
4.3
4.4
4.5
V
VBK falling, VSEL_BK pin to 47 kΩ +/5% tied to AVDD
4.1
4.2
4.3
V
VBK rising, VSEL_BK pin to Hi-Z
2.7
2.8
2.9
V
VBK falling, VSEL_BK pin to Hi-Z
2.5
2.6
2.7
V
VBK rising, VSEL_BK pin tied to AVDD
4.2
4.4
4.55
V
VBK falling, VSEL_BK pin tied to AVDD
4.0
4.2
4.35
V
Rising to falling threshold
90
200
320
mV
BUCK_CL = 0b
360
600
900
mA
BUCK_CL = 1b
VBK_UV_HYS
Buck regulator undervoltage lockout
hysteresis
IBK_CL
Buck regulator Current limit threshold
(SPI Device)
80
150
250
mA
IBK_CL
Buck regulator Current limit threshold
(HW Device)
360
600
900
mA
IBK_OCP
Buck regulator Overcurrent protection
trip point
2
3
4
tBK_RETRY
Overcurrent protection retry time
0.7
1
1.3
ms
0
0.6
V
1.5
5.5
V
A
LOGIC-LEVEL INPUTS (BRAKE, DIR, DRVOFF, nSLEEP, PWM, SCLK, SDI)
VIL
VIH
Input logic low voltage
Input logic high voltage
VHYS
Input logic hysteresis
IIL
Input logic low current
IIH
Input logic high current
RPD
Input pulldown resistance
CID
Input capacitance
Other Pins
nSLEEP
1.6
5.5
V
Other PIns
180
300
420
mV
95
250
nSLEEP
420
mV
–1
1
µA
nSLEEP, VPIN (Pin Voltage) = 5 V
10
30
µA
Other pins, VPIN (Pin Voltage) = 5 V
30
75
µA
VPIN (Pin Voltage) = 0 V
nSLEEP
Other pins
150
200
300
kΩ
70
100
130
kΩ
30
pF
LOGIC-LEVEL INPUTS (nSCS)
VIL
Input logic low voltage
0
VIH
Input logic high voltage
1.5
VHYS
Input logic hysteresis
180
IIL
Input logic low current
VPIN (Pin Voltage) = 0 V
IIH
Input logic high current
VPIN (Pin Voltage) = 5 V
RPU
Input pullup resistance
CID
Input capacitance
0.6
300
–1
80
100
30
V
5.5
V
420
mV
75
µA
25
µA
130
kΩ
pF
Submit Document Feedback
Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: MCT8316Z
11
MCT8316Z
www.ti.com.cn
ZHCSNP1A – MARCH 2021 – REVISED OCTOBER 2021
TJ = –40°C to +150°C, VVM = 4.5 to 35 V (unless otherwise noted). Typical limits apply for TA = 25°C, VVM = 24 V
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
FOUR-LEVEL INPUTS (SLEW, VSEL_BK)
0.2*AVD
D
V
0.545*AV
DD
V
47 kΩ +/- 5% tied to AVDD
0.606*AV 0.757*AVD 0.909*AV
DD
D
DD
V
Input mode 4 voltage
Tied to AVDD
0.945*AV
DD
V
RPU
Input pullup resistance
To AVDD
70
100
130
kΩ
RPD
Input pulldown resistance
To AGND
70
100
130
kΩ
VL1
Input mode 1 voltage
Tied to AGND
VL2
Input mode 2 voltage
Hi-Z
VL3
Input mode 3 voltage
VL4
0
0.27*AV
DD
0.5*AVDD
AVDD
FOUR-LEVEL INPUTS (OCP/SR)
0.09*AV
DD
V
22 kΩ ± 5% to AGND
0.12*AV
0.2*AVD
0.15*AVDD
DD
D
V
Input mode 3 voltage
100 kΩ ± 5% to AGND
0.27*AV
0.4*AVD
0.33*AVDD
DD
D
V
VL4
Input mode 4 voltage
Hi-Z
0.45*AV
DD
0.5*AVDD
0.55*AV
DD
V
VL5
Input mode 5 voltage
100 kΩ ± 5% to AVDD
0.6*AVD
0.66*AVDD
D
0.73*AV
DD
V
VL6
Input mode 6 voltage
22 kΩ ± 5% to AVDD
0.77*AV
0.9*AVD
0.85*AVDD
DD
D
V
VL7
Input mode 7 voltage
Tied to AVDD
0.94*AV
DD
V
RPU
Input pullup resistance
To AVDD
80
100
120
kΩ
RPD
Input pulldown resistance
To AGND
80
100
120
kΩ
0.4
V
VL1
Input mode 1 voltage
Tied to AGND
VL2
Input mode 2 voltage
VL3
0
AVDD
OPEN-DRAIN OUTPUTS (FGOUT, nFAULT)
VOL
Output logic low voltage
IOD = 5 mA
IOH
Output logic high current
VOD = 5 V
COD
Output capacitance
–1
1
µA
30
pF
V
PUSH-PULL OUTPUTS (SDO)
VOL
Output logic low voltage
IOP = 5 mA
0
0.4
VOH
Output logic high voltage
IOP = 5 mA
2.2
5.5
V
IOL
Output logic low leakage current
VOP = 0 V
–1
1
µA
IOH
Output logic high leakage current
VOP = 5 V
–1
1
µA
COD
Output capacitance
30
pF
DRIVER OUTPUTS
RDS(ON)
12
Total MOSFET on resistance (High-side
+ Low-side)
VVM > 6 V, IOUT = 1 A, TA = 25°C
95
120
mΩ
VVM < 6 V, IOUT = 1 A, TA = 25°C
105
130
mΩ
VVM > 6 V, IOUT = 1 A, TJ = 150 °C
140
185
mΩ
VVM < 6 V, IOUT = 1 A, TJ = 150 °C
145
190
mΩ
Submit Document Feedback
Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: MCT8316Z
MCT8316Z
www.ti.com.cn
ZHCSNP1A – MARCH 2021 – REVISED OCTOBER 2021
TJ = –40°C to +150°C, VVM = 4.5 to 35 V (unless otherwise noted). Typical limits apply for TA = 25°C, VVM = 24 V
PARAMETER
TEST CONDITIONS
MIN
TYP
14
25
45
V/us
30
50
80
V/us
80
125
185
V/us
VVM = 24 V, SLEW = 11b or SLEW pin
tied to AVDD
130
200
280
V/us
VVM = 24 V, SLEW = 00b or SLEW pin
tied to AGND
14
25
45
V/us
30
50
80
V/us
80
125
185
V/us
110
200
280
V/us
VVM = 24 V, SLEW = 00b or SLEW pin
tied to AGND
SR
SR
VVM = 24 V, SLEW = 01b or SLEW pin to
Phase pin slew rate switching low to high Hi-Z
(Rising from 20 % to 80 %)
VVM = 24 V, SLEW = 10b or SLEW pin to
47 kΩ +/- 5% to AVDD
VVM = 24 V, SLEW = 01b or SLEW pin to
Phase pin slew rate switching high to low Hi-Z
(Falling from 80 % to 20 %
VVM = 24 V, SLEW = 10b or SLEW pin to
47 kΩ +/- 5% to AVDD
VVM = 24 V, SLEW = 11b or SLEW pin
tied to AVDD
ILEAK
tDEAD
tPD
tMIN_PULSE
MAX UNIT
Leakage current on OUTx
VOUTx = VVM, nSLEEP = 1
5
mA
Leakage current on OUTx
VOUTx = 0 V, nSLEEP = 1
1
µA
Output dead time (high to low / low to
high)
Propagation delay (high-side / low-side
ON/OFF)
Minimum output pulse width
VVM = 24 V, SR = 25 V/µs, HS driver ON
to LS driver OFF
1800
3400
ns
VVM = 24 V, SR = 50 V/µs, HS driver ON
to LS driver OFF
1100
1550
ns
VVM = 24 V, SR = 125 V/µs, HS driver
ON to LS driver OFF
650
1000
ns
VVM = 24 V, SR = 200 V/µs, HS driver
ON to LS driver OFF
500
750
ns
VVM = 24 V, PWM = 1 to OUTx
transisition, SR = 25 V/µs
2000
4550
ns
VVM = 24 V, PWM = 1 to OUTx
transisition, SR = 50V/µs
1200
2150
ns
VVM = 24 V, PWM = 1 to OUTx
transisition, SR = 125 V/µs
800
1350
ns
VVM = 24 V, PWM = 1 to OUTx
transisition, SR = 200 V/µs
650
1050
ns
SR = 200 V/µs
600
ns
HALL COMPARATORS
VICM
VHYS
Input Common Mode Voltage (Hall)
Voltage hysteresis (SPI Device)
Hall comparator hysteresis difference
VH(MIN)
Minimum Hall Differential Voltage
II
Input leakage current
tHDG
Hall deglitch time
tHEDG
Hall Enable deglitch time
V
HALL_HYS = 0
1.5
5
8
mV
HALL_HYS = 1
35
50
75
mV
1.5
5
8
mV
8
mV
Voltage hysteresis (HW Device)
ΔVHYS
AVDD –
1.2
0.5
Between Hall A, Hall B and Hall C
comparator
–8
40
HPX = HNX = 0 V
mV
–1
0.7
During Power up
1.15
1
μA
1.7
μs
1.4
μs
PULSE-BY-PULSE CURRENT LIMIT
VLIM
Voltage on VLIM pin for cycle by cycle
current limit
AVDD/2
AVDD/2
–0.4
V
Submit Document Feedback
Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: MCT8316Z
13
MCT8316Z
www.ti.com.cn
ZHCSNP1A – MARCH 2021 – REVISED OCTOBER 2021
TJ = –40°C to +150°C, VVM = 4.5 to 35 V (unless otherwise noted). Typical limits apply for TA = 25°C, VVM = 24 V
PARAMETER
ILIMIT
Current limit corresponding to VLIM pin
voltage range
ILIM_AC
Current limit accuracy
tBLANK
Cycle by cycle current limit blank time
TEST CONDITIONS
MIN
TYP
MAX UNIT
0
8
A
–10
10
%
5
µs
ADVANCE_LVL = 000 b
0
°
ADVANCE_LVL = 001 b
4
°
ADVANCE_LVL = 010 b
7
°
ADVANCE_LVL = 011 b
11
°
ADVANCE_LVL = 100 b
15
°
ADVANCE_LVL = 101 b
20
°
ADVANCE_LVL = 110 b
25
°
ADVANCE_LVL = 111 b
30
°
Advance pin tied to AGND
0
°
Advance pin tied to 22 kΩ ± 5% to
AGND
4
°
Advance pin tied to 100 kΩ ± 5% to
AGND
11
°
Advance pin tied to Hi-Z
15
°
Advance pin tied to 100 kΩ ± 5% to
AVDD
20
°
Advance pin tied to 22 kΩ ± 5% to AVDD
25
°
Advance pin tied to Tied to AVDD
30
°
ADVANCE ANGLE
Advance Angle Setting
(SPI Device)
θADV
Advance Angle Setting
(HW Device)
θADV
PROTECTION CIRCUITS
VUVLO
Supply undervoltage lockout (UVLO)
VUVLO_HYS
Supply undervoltage lockout hysteresis
tUVLO
Supply undervoltage deglitch time
Supply overvoltage protection (OVP)
(SPI Device)
VOVP
VM rising
4.3
4.4
4.5
V
VM falling
4.1
4.2
4.3
V
Rising to falling threshold
140
200
350
mV
3
5
7
µs
Supply rising, OVP_EN = 1, OVP_SEL =
0
32.5
34
35
V
Supply falling, OVP_EN = 1, OVP_SEL
=0
31.8
33
34.3
V
Supply rising, OVP_EN = 1, OVP_SEL =
1
20
22
23
V
Supply falling, OVP_EN = 1, OVP_SEL
=1
19
21
22
V
Rising to falling threshold, OVP_SEL = 1
0.9
1
1.1
V
Rising to falling threshold, OVP_SEL = 0
0.7
0.8
0.9
V
2.5
5
7
µs
VOVP_HYS
Supply overvoltage protection (OVP)
(SPI Device)
tOVP
Supply overvoltage deglitch time
VCPUV
Charge pump undervoltage lockout
(above VM)
Supply rising
2.3
2.5
2.7
V
Supply falling
2.2
2.4
2.6
V
VCPUV_HYS
Charge pump UVLO hysteresis
Rising to falling threshold
75
100
140
mV
Supply rising
2.7
2.85
3
V
Supply falling
2.5
2.65
2.8
V
Rising to falling threshold
180
200
240
mV
VAVDD_UV
Analog regulator undervoltage lockout
VAVDD_
Analog regulator undervoltage lockout
hysteresis
UV_HYS
14
Submit Document Feedback
Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: MCT8316Z
MCT8316Z
www.ti.com.cn
ZHCSNP1A – MARCH 2021 – REVISED OCTOBER 2021
TJ = –40°C to +150°C, VVM = 4.5 to 35 V (unless otherwise noted). Typical limits apply for TA = 25°C, VVM = 24 V
PARAMETER
IOCP
MIN
TYP
Overcurrent protection trip point (SPI
Device)
OCP_LVL = 0b
10
16
OCP_LVL = 1b
15
Overcurrent protection trip point (HW
Device)
OCP pin tied to AGND
10
Overcurrent protection deglitch time
(SPI Device)
tOCP
TEST CONDITIONS
OCP pin tied to AVDD
Overcurrent protection retry time
(SPI Device)
tRETRY
Overcurrent protection retry time
(HW Device)
tMTR_ LOCK
tMTR_ LOCK
Motor lock detection time
(SPI Device)
tMTR_LOCK_R Motor lock retry time
(SPI Device)
A
24
28
A
16
21.5
A
15
24
31
A
0.06
0.3
0.6
µs
OCP_DEG = 01b
0.3
0.6
1.1
µs
OCP_DEG = 10b
0.7
1.25
1.8
µs
OCP_DEG = 11b
1.1
1.6
2.5
µs
0.06
0.3
0.6
µs
OCP_RETRY = 0
4
5
6
ms
OCP_RETRY = 1
450
500
560
ms
4
5
6
ms
MOTOR_LOCK_TDET = 00b
270
300
330
ms
MOTOR_LOCK_TDET = 01b
450
500
550
ms
MOTOR_LOCK_TDET = 10b
900
1000
1100
ms
MOTOR_LOCK_TDET = 11b
4500
5000
5500
ms
900
1000
1100
ms
Motor lock detection time
(HW Device)
ETRY
20
OCP_DEG = 00b
Overcurrent protection deglitch time
(HW Device)
tRETRY
MAX UNIT
MOTOR_LOCK_RETRY = 0b
450
500
550
ms
MOTOR_LOCK_RETRY = 1b
4500
5000
5500
ms
450
500
550
ms
tMTR_LOCK_R Motor lock retry time
(HW Device)
ETRY
TOTW
Thermal warning temperature (FET)
Die temperature (TJ)
160
170
180
°C
TOTW_HYS
Thermal warning hysteresis (FET)
Die temperature (TJ)
25
30
35
°C
TTSD
Thermal shutdown temperature
Die temperature (TJ)
175
185
195
°C
TTSD_HYS
Thermal shutdown hysteresis
Die temperature (TJ)
25
30
35
°C
TTSD
Thermal shutdown temperature (FET)
Die temperature (TJ)
170
180
190
°C
TTSD_HYS
Thermal shutdown hysteresis (FET)
Die temperature (TJ)
25
30
35
°C
(1)
RLBK is resistance of inductor LBK
7.6 SPI Timing Requirements
MIN
tREADY
SPI ready after power up
tHI_nSCS
nSCS minimum high time
tSU_nSCS
tHD_nSCS
tSCLK
SCLK minimum period
tSCLKH
SCLK minimum high time
tSCLKL
tSU_SDI
NOM
MAX
1
UNIT
ms
300
ns
nSCS input setup time
25
ns
nSCS input hold time
25
ns
100
ns
50
ns
SCLK minimum low time
50
ns
SDI input data setup time
25
ns
tHD_SDI
SDI input data hold time
25
tDLY_SDO
SDO output data delay time
25
ns
tEN_SDO
SDO enable delay time
50
ns
ns
Submit Document Feedback
Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: MCT8316Z
15
MCT8316Z
www.ti.com.cn
ZHCSNP1A – MARCH 2021 – REVISED OCTOBER 2021
MIN
tDIS_SDO
NOM
MAX
SDO disable delay time
50
UNIT
ns
7.7 SPI Secondary Mode Timings
tHI_nSCS
tHD_nSCS
tSU_nSCS
tSCLK
tSCLKH
X
tSCLKL
MSB
LSB
tSU_SDI
Z
X
tDIS_SDO
tDLY_SDO
tHD_SDI
MSB
LSB
Z
tEN_SDO
图 7-1. SPI Secondary Mode Timing Diagram
7.8 Typical Characteristics
17
160
16
150
140
FPWM = 200 kHz
14
13
130
TJ = -40 C
TJ = 25 C
TJ = 150 C
12
11
120
110
100
90
10
9
80
FPWM = 25 kHz
70
8
7
6
9
12
15
18
21
24
27
Supply Voltage (V)
30
33
图 7-2. Supply current over supply voltage
16
RDS(ON) (m)
Active Current (mA)
15
36
60
-40
-20
0
20
40
60
80
100
Junction Temperature (V)
120
140
图 7-3. RDS(ON) (high and low side combined) for
MOSFETs over temperature
Submit Document Feedback
Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: MCT8316Z
MCT8316Z
www.ti.com.cn
ZHCSNP1A – MARCH 2021 – REVISED OCTOBER 2021
100
5.5
5.25
Buck Output Voltage (V)
95
Buck Efficiency (%)
5.75
TJ = -40 C
TJ = 25 C
TJ = -150 C
97.5
92.5
90
87.5
85
82.5
80
5
4.75
BUCK_SEL
BUCK_SEL
BUCK_SEL
BUCK_SEL
4.5
4.25
4
=
=
=
=
00b
01b
10b
11b
3.75
3.5
77.5
3.25
3
75
4
8
12
16
20
24
Supply Voltage (V)
28
32
图 7-4. Buck regulator efficiency over supply
voltage
36
0
0.02 0.04 0.06 0.08 0.1 0.12 0.14 0.16 0.18
Buck Output Load Current (A)
0.2
图 7-5. Buck regulator output voltage over load
current
Submit Document Feedback
Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: MCT8316Z
17
MCT8316Z
www.ti.com.cn
ZHCSNP1A – MARCH 2021 – REVISED OCTOBER 2021
8 Detailed Description
8.1 Overview
The MCT8316Z device is an integrated 100-mΩ (combined high-side and low-side MOSFET's on-state
resistance) driver for 3-phase motor-drive applications. The device reduces system component count, cost, and
complexity by integrating three half-bridge MOSFETs, gate drivers, charge pump, linear regulator for the external
load and buck regulator. A standard serial peripheral interface (SPI) provides a simple method for configuring the
various device settings and reading fault diagnostic information through an external controller. Alternatively, a
hardware interface (H/W) option allows for configuring the most commonly used settings through fixed external
resistors.
The architecture uses an internal state machine to protect against short-circuit events, and protect against dv/dt
parasitic turnon of the internal power MOSFET.
The MCT8316Z device integrates three-phase sensored trapezoidal commutation using analog or digital hall
sensors for position detection.
In addition to the high level of device integration, the MCT8316Z device provides a wide range of integrated
protection features. These features include power-supply undervoltage lockout (UVLO), charge-pump
undervoltage lockout (CPUV), overcurrent protection (OCP), AVDD undervoltage lockout (AVDD_UV), buck
regulator ULVO for MCT8316ZR/T and overtemperature shutdown (OTW and OTSD). Fault events are indicated
by the nFAULT pin with detailed information available in the SPI registers on the SPI device version.
The MCT8316ZT and MCT8316ZR device are available in 0.5-mm pin pitch, VQFN surface-mount packages.
The VQFN package size is 7 mm × 5 mm.
18
Submit Document Feedback
Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: MCT8316Z
MCT8316Z
www.ti.com.cn
ZHCSNP1A – MARCH 2021 – REVISED OCTOBER 2021
8.2 Functional Block Diagram
VVM
CPH
CVM1
CCP
CFLY
CPL
CP
CVM2
+
Replace Inductor (LBK)
with Resistor (RBK) for
larger external load
or to reduce power
dissipaon
VM
To AVDD and
Buck Regulator
Regulators
Ext.
Load
AVDD
VVM
Charge Pump
AVDD Linear Regulator
CAVDD1
AGND
LBK
SW_BK
RBK
I/O Control
Ext.
Load
CBK
GND_BK
VVM
Buck Regulator
FB_BK
nSLEEP
Protection
Differential Comparators
HPC
PWM
Overcurrent
Protection
Input
Control
+
-
HNC
Thermal Warning
HPB
To
Digital
Control
Thermal Shutdown
(Optional)
+
-
HNB
BRAKE
(Optional)
HPA
+
-
HNA
(Optional)
AVDD
Predriver Stage
Output
RnFAULT
Power Stage
VM
VCP
nFAULT
HS Predriver
AVDD
RFGOUT
OUTA
VLS
FGOUT
LS Predriver
PGND
Digital Control
Interface
Predriver Stage
SCLK
Power Stage
ISEN_A
VM
VCP
SPI
SDI
Current
Sense for
Phase - A
AVDD or
Buck Output
HS Predriver
AVDD
Hall A
OUTB
SDO**
VLS
Hall B
Hall C
AVDD
LS Predriver
nSCS
PGND
ILIM
ISEN_A
Power Stage
Predriver Stage
+
-
Current
Sense for
Phase - B
ISEN_B
VM
VCP
AV
SOA
ISEN_B
AV
Output
Offset
Bias
HS Predriver
SOB
OUTC
VLS
SOC
ISEN_C
LS Predriver
AV
AVDD
PGND
Current
Sense for
Phase - C
Current Sense and Current Limit
ISEN_C
** SDO can be configured to open drain or push
pull configura on
TPAD
PGND
PGND
PGND
图 8-1. MCT8316ZR Block Diagram
Submit Document Feedback
Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: MCT8316Z
19
MCT8316Z
www.ti.com.cn
ZHCSNP1A – MARCH 2021 – REVISED OCTOBER 2021
VVM
CPH
CVM1
CCP
CFLY
CPL
CP
CVM2
+
Replace Inductor (LBK)
with Resistor (RBK) for
larger external load
or to reduce power
dissipa on
VM
To AVDD and
Buck Regulator
Regulators
Ext.
Load
AVDD
VVM
Charge Pump
AVDD Linear Regulator
CAVDD1
AGND
LBK
SW_BK
RBK
I/O Control
Ext.
Load
CBK
GND_BK
VVM
Buck Regulator
FB_BK
nSLEEP
Protection
Differential Comparators
PWM
HPC
Overcurrent
Protection
DIR
+
-
HNC
Thermal Warning
To
Digital
Control
Thermal Shutdown
(Optional)
HPB
+
-
HNB
BRAKE
(Optional)
HPA
+
-
Input
Control
Predriver Stage
HNA
(Optional)
Power Stage
VM
VCP
ADVANCE
HS Predriver
MODE
OUTA
VLS
SLEW
LS Predriver
VSEL_BK
PGND
Current
Sense for
Phase - A
Digital Control
AVDD
RnFAULT
Predriver Stage
Output
Power Stage
ISEN_A
VM
VCP
AVDD or
Buck Output
HS Predriver
nFAULT
AVDD
Hall A
OUTB
RFGOUT
VLS
Hall B
Hall C
FGOUT
LS Predriver
PGND
ILIM
ISEN_A
Power Stage
Predriver Stage
+
-
Current
Sense for
Phase - B
ISEN_B
VM
VCP
AV
SOA
ISEN_B
AV
Output
Offset
Bias
HS Predriver
SOB
OUTC
VLS
SOC
ISEN_C
LS Predriver
AV
AVDD
PGND
Current
Sense for
Phase - C
Current Sense and Current Limit
ISEN_C
TPAD
PGND
PGND
PGND
图 8-2. MCT8316ZT Block Diagram
20
Submit Document Feedback
Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: MCT8316Z
MCT8316Z
www.ti.com.cn
ZHCSNP1A – MARCH 2021 – REVISED OCTOBER 2021
8.3 Feature Description
表 8-1 lists the recommended values of the external components for the driver.
Note
TI recommends to connect pull up on nFAULT even if it is not used to avoid undesirable entry into
internal test mode. If external supply is used to pull up nFAULT, ensure that it is pulled to >2.2V on
power up or the device will enter internal test mode.
表 8-1. MCT8316Z External Components
COMPONENTS
PIN 1
PIN 2
RECOMMENDED
CVM1
VM
PGND
X5R or X7R, 0.1-µF, TI recommends a capacitor
voltage rating at least twice the normal operating
voltage of the device
CVM2
VM
PGND
≥ 10-µF, TI recommends a capacitor voltage rating at
least twice the normal operating voltage of the device
CCP
CP
VM
X5R or X7R, 16-V, 1-µF capacitor
CFLY
CPH
CPL
X5R or X7R, 47-nF, TI recommends a capacitor
voltage rating at least twice the normal operating
voltage of the pin
CAVDD
AVDD
AGND
X5R or X7R, 1-µF, ≥ 6.3-V. In order for AVDD to
accurately regulate output voltage, capacitor should
have effective capacitance between 0.7-µF to 1.3-µF
at 3.3-V across operating temperature.
CBK
SW_BK
GND_BK
X5R or X7R, 22-µF, buck-output rated capacitor. TI
recommends a capacitor voltage rating at least twice
the normal operating voltage of the pin
LBK
SW_BK
FB_BK
Output inductor
RnFAULT
VCC
nFAULT
5.1-kΩ, Pullup resistor
RMODE
MODE
AGND or AVDD
MCT8316Z hardware interface
RSLEW
SLEW
AGND or AVDD
MCT8316Z hardware interface
RADVANCE
ADVANCE
AGND or AVDD
MCT8316Z hardware interface
RVSEL_BK
VSEL_BK
AGND or AVDD
MCT8316Z hardware interface
CILIM
ILIM
AGND
X5R or X7R, 0.1-µF, AVDD-rated capacitor (Optional)
8.3.1 Output Stage
The MCT8316Z device consists of an integrated 100-mΩ (combined high-side and low-side FET's on-state
resistance) NMOS FETs connected in a three-phase bridge configuration. A doubler charge pump provides the
proper gate-bias voltage to the high-side NMOS FET's across a wide operating-voltage range in addition to
providing 100% duty-cycle support. An internal linear regulator provides the gate-bias voltage for the low-side
MOSFETs. The device has three VM motor power-supply pins which are to be connected together to the motorsupply voltage.
8.3.2 PWM Control Mode (1x PWM Mode)
The MCT8316Z family of devices provides seven different control modes to support various commutation and
control methods. The MCT8316Z device provides a 1x PWM control mode for driving the BLDC motor in
trapezoidal current-control mode. The MCT8316Z device uses 6-step block commutation tables that are stored
internally. This feature lets a three-phase BLDC motor be controlled using a single PWM sourced from a simple
controller. The PWM is applied on the PWM pin and determines the output frequency and duty cycle of the halfbridges.
The MCT8316Z family of devices supports both analog and digital hall inputs by changing mode input setting.
Differential hall inputs should be connected to HPx and HNx pins (see 图 8-3). Digital hall inputs should be
connected to the HPx pins while keeping the HNx pins floating (see 图 8-4).
Submit Document Feedback
Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: MCT8316Z
21
MCT8316Z
www.ti.com.cn
ZHCSNP1A – MARCH 2021 – REVISED OCTOBER 2021
The half-bridge output states are managed by the HPA, HNA, HPB, HNB, HPC and HNC pins in analog mode
and HPA, HPB, HPC in digital mode which are used as state logic inputs. The state inputs are the position
feedback of the BLDC motor. The 1x PWM mode usually operates with synchronous rectification (low-side
MOSFET recirculation); however, the mode can be configured to use asynchronous rectification (MOSFET body
diode freewheeling) as shown below
表 8-2. PWM_MODE Configuration
MODE Type
MODE Pin (Hardware
Variant)
Hall Configuration
Modulation
ASR and AAR Mode
Mode 1
Connected to AGND
Analog Hall Input
Asynchronous
ASR and AAR Disabled
Mode 2
Connected to AGND with
RMODE1
Digital Hall Input
Asynchronous
ASR and AAR Disabled
Mode 3
Connected to AGND with
RMODE2
Analog Hall Input
Synchronous
ASR and AAR Disabled
Mode 4
Hi-Z
Digital Hall Input
Synchronous
ASR and AAR Disabled
Mode 5
Connected to AVDD with
RMODE2
Analog Hall Input
Synchronous
ASR and AAR Enabled
Mode 6
Connected to AVDD with
RMODE1
Digital Hall Input
Synchronous
ASR and AAR Enabled
Mode 7
Connected to AVDD
Note
Texas Instruments does not recommend changing the MODE pin or PWM_MODE register during
operation of the power MOSFETs. Set PWM to a low level before changing the MODE pin or
PWM_MODE register.
8.3.2.1 Analog Hall Input Configuration
图 8-3 shows the connection of Analog Hall inputs to the driver. Analog hall elements are fed to the hall
comparators, which zero crossing is used to generate the commutation logic.
22
Submit Document Feedback
Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: MCT8316Z
MCT8316Z
www.ti.com.cn
ZHCSNP1A – MARCH 2021 – REVISED OCTOBER 2021
MCT8316Z
HPC
(Optional)
HNC
HPB
Analog Hall
Comparator Input
(Optional)
HNB
HPA
PWM
MCU_PWM
(Optional)
HNA
MCU_GPIO
DIR
MCU_GPIO
BRAKE
OUTA
Hall A
OUTB
Hall B
Hall C
OUTC
图 8-3. 1x PWM Mode with Analog Hall Input
Note
Texas Instruments recommends motor direction (DIR) change when the motor is stationary.
Submit Document Feedback
Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: MCT8316Z
23
MCT8316Z
www.ti.com.cn
ZHCSNP1A – MARCH 2021 – REVISED OCTOBER 2021
8.3.2.2 Digital Hall Input Configuration
图 8-4 shows the connection of Digital Hall inputs to the driver.
MCT8316Z
HPC
X
HNC
HPB
Digital Inputs
X
HNB
HPA
PWM
MCU_PWM
X
HNA
MCU_GPIO
DIR
MCU_GPIO
BRAKE
OUTA
Hall A
Hall B
OUTB
Hall C
OUTC
图 8-4. 1x PWM Mode with Digital Hall Input
8.3.2.3 Asynchronous Modulation
The DIR pin controls the direction of BLDC motor in either clockwise or counter-clockwise direction. Tie the DIR
pin low if this feature is not required.
The BRAKE input halts the motor by turning off all high-side MOSFETs and turning on all low-side MOSFETs
when it is pulled high. This brake is independent of the states of the other input pins. Tie the BRAKE pin low if
this feature is not required.
表 8-3 shows the configuration in 1x PWM mode with asynchronous modulation.
表 8-3. Asynchronous Modulation
HALL INPUTS
DRIVER OUTPUTS
DIR = 0
STATE
24
DIR = 1
PHASE A
HALL_A HALL_B HALL_C HALL_A HALL_B HALL_C
/HPA
/HPB
/HPC
/HPA
/HPB
/HPC
PHASE B
High
Side
Low
Side
High
Side
PHASE C
Low
Side
High
Side
Low
Side
DESCRIPTION
Stop
0
0
0
0
0
0
L
L
L
L
L
L
Stop
Align
1
1
1
1
1
1
PWM
L
L
H
L
H
Align
1
1
1
0
0
0
1
L
L
PWM
L
L
H
B→C
2
1
0
0
0
1
1
PWM
L
L
L
L
H
A→C
3
1
0
1
0
1
0
PWM
L
L
H
L
L
A→B
4
0
0
1
1
1
0
L
L
L
H
PWM
L
C→B
5
0
1
1
1
0
0
L
H
L
L
PWM
L
C→A
6
0
1
0
1
0
1
L
H
PWM
L
L
L
B→A
Submit Document Feedback
Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: MCT8316Z
MCT8316Z
www.ti.com.cn
ZHCSNP1A – MARCH 2021 – REVISED OCTOBER 2021
8.3.2.4 Synchronous Modulation
表 8-4 shows the configuration in 1x PWM mode with synchronous modulation.
表 8-4. Synchronous Modulation
HALL INPUTS
DRIVER OUTPUTS
DIR = 0
STATE
DIR = 1
PHASE A
HALL_A HALL_B HALL_C HALL_A HALL_B HALL_C
/HPA
/HPB
/HPC
/HPA
/HPB
/HPC
High
Side
PHASE B
Low
Side
High
Side
PHASE C
Low
Side
High
Side
DESCRIPTION
Low
Side
Stop
0
0
0
0
0
0
L
L
L
L
L
L
Stop
Align
1
1
1
1
1
1
PWM
!PWM
L
H
L
H
Align
1
1
1
0
0
0
1
L
L
PWM
!PWM
L
H
B→C
2
1
0
0
0
1
1
PWM
!PWM
L
L
L
H
A→C
3
1
0
1
0
1
0
PWM
!PWM
L
H
L
L
A→B
4
0
0
1
1
1
0
L
L
L
H
PWM
!PWM
C→B
5
0
1
1
1
0
0
L
H
L
L
PWM
!PWM
C→A
6
0
1
0
1
0
1
L
H
PWM
!PWM
L
L
B→A
8.3.2.5 Motor Operation
图 8-5 and 图 8-6 shows the BLDC motor commutation with direction setting (DIR) as 0 and 1 respectively.
Hall A
Hall A
&t
Hall B
&t
Hall B
&t
&t
Hall C
Hall C
&t
&t
Idc
Van
ia
Idc
Van
ia
0
0
Vbn
Vbn
ib
ib
0
&t
2Œ/3
&t
2Œ/3
0
2Œ/3
&t
&t
2Œ/3
Vcn
Vcn
ic
ic
0
0
2Œ/3
HA, LB
HA, LC
HB, LC
HB, LA
HC, LA
2Œ
HC, LB
HB, LA
HC, LA
HC, LB
HA, LB
2Œ
&t
图 8-5. BLDC Motor Commutation with DIR = 0
&t
2Œ/3
&t
HA, LC
HB, LC
&t
图 8-6. BLDC Motor Commutation with DIR = 1
Submit Document Feedback
Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: MCT8316Z
25
MCT8316Z
www.ti.com.cn
ZHCSNP1A – MARCH 2021 – REVISED OCTOBER 2021
8.3.3 Device Interface Modes
The MCT8316Z family of devices supports two different interface modes (SPI and hardware) to let the end
application design for either flexibility or simplicity. The two interface modes share the same four pins, allowing
the different versions to be pin-to-pin compatible. This compatibility lets application designers evaluate with one
interface version and potentially switch to another with minimal modifications to their design.
8.3.3.1 Serial Peripheral Interface (SPI)
The SPI devices support a serial communication bus that lets an external controller send and receive data with
the MCT8316Z. This support lets the external controller configure device settings and read detailed fault
information. The interface is a four wire interface using the SCLK, SDI, SDO, and nSCS pins which are
described as follows:
• The SCLK pin is an input that accepts a clock signal to determine when data is captured and propagated on
the SDI and SDO pins.
• The SDI pin is the data input.
• The SDO pin is the data output. The SDO pin can be configured to either open-drain or push-pull through
SDO_MODE.
• The nSCS pin is the chip select input. A logic low signal on this pin enables SPI communication with the
MCT8316Z.
For more information on the SPI, see the 节 8.5 section.
8.3.3.2 Hardware Interface
Hardware interface devices convert the four SPI pins into four resistor-configurable inputs which are ADVANCE,
MODE, SLEW and VSEL_BK.
This conversion lets the application designer configure the most common device settings by tying the pin logic
high or logic low, or with a simple pullup or pulldown resistor. This removes the requirement for an SPI bus from
the external controller. General fault information can still be obtained through the nFAULT pin.
•
•
•
•
The MODE pin configures the PWM control mode.
The SLEW pin configures the slew rate of the output voltage.
The ADVANCE pin configures the lead angle of the output with respect to hall signals.
The VSEL_BK pin is used to configure the buck regulator voltage.
For more information on the hardware interface, see the 节 8.3.10 section.
AVDD
RSLEW
SCLK
AVDD
SLEW
AVDD
SPI
Interface
SDI
AVDD
MODE
VCC
RPU
AVDD
SDO
Hardware
Interface
ADVANCE
AVDD
AVDD
nSCS
GAIN
RGAIN
图 8-7. MCT8316ZR SPI Interface
26
图 8-8. MCT8316ZT Hardware Interface
Submit Document Feedback
Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: MCT8316Z
MCT8316Z
www.ti.com.cn
ZHCSNP1A – MARCH 2021 – REVISED OCTOBER 2021
8.3.4 Step-Down Mixed-Mode Buck Regulator
The MCT8316ZR and MCT8316ZT has an integrated mixed-mode buck regulator in conjunction with AVDD to
supply regulated 3.3 V or 5.0 V power for an external controller or system voltage rail. Additionally, the buck
output can also be configured to 4.0 V or 5.7 V for supporting the extra headroom for external LDO for
generating a 3.3 V or 5.0 V supplies. The output voltage of the buck is set by the VSEL_BK pin in the
MCT8316ZT device (hardware variant) and BUCK_SEL bits in the MCT8316ZR device (SPI variant).
TThe buck regulator has a low quiescent current of ~1-2 mA during light loads to prolong battery life. The device
improves performance during line and load transients by implementing a pulse-frequency current-mode control
scheme which requires less output capacitance and simplifies frequency compensation design.
To disable the buck regulator, set the BUCK_DIS bit in the MCT8316ZR (SPI variant). The buck regulator cannot
be disabled in the MCT8316ZT (hardware variant).
Note
If the buck regulator is unused, the buck pins SW_BK, GND_BK, and FB_BK cannot be left floating or
connected to ground. The buck regulator components LBK/RBK and CBK must be connected in
hardware.
表 8-5. Recommended settings for Buck Regulator
Buck Mode
Buck output voltage Max output current
from AVDD (IAVDD)
Max output current
from Buck (IBK)
Buck current limit
AVDD power
sequencing
Inductor - 47 μH
3.3 V or 4.0 V
30 mA
200 mA - IAVDD
600 mA (BUCK_CL = Not supported
0b)
(BUCK_PS_DIS = 1)
Inductor - 47 μH
5.0 V or 5.7 V
30 mA
200 mA - IAVDD
600 mA (BUCK_CL = Supported
0b)
(BUCK_PS_DIS = 0)
Inductor - 22 μH
5.0 V or 5.7 V
30 mA
50 mA - IAVDD
150 mA (BUCK_CL = Not supported
1b)
(BUCK_PS_DIS = 1)
Inductor - 22 μH
3.3 V or 4.0 V
30 mA
50 mA - IAVDD
150 mA (BUCK_CL = Supported
1b)
(BUCK_PS_DIS = 0)
Resistor - 22 μH
5.0 V or 5.7 V
30 mA
40 mA - IAVDD
150 mA (BUCK_CL = Not supported
1b)
(BUCK_PS_DIS = 1)
Resistor - 22 μH
3.3 V or 4.0 V
30 mA
40 mA - IAVDD
150 mA (BUCK_CL = Supported
1b)
(BUCK_PS_DIS = 0)
Submit Document Feedback
Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: MCT8316Z
27
MCT8316Z
www.ti.com.cn
ZHCSNP1A – MARCH 2021 – REVISED OCTOBER 2021
8.3.4.1 Buck in Inductor Mode
The buck regulator in MCT8316Z device is primarily designed to support low inductance of 47µH and 22µH
inductors. The 47µH inductor allows the buck regulator to operate up to 200 mA load current support, whereas
the 22µH inductor limits the load current to 50 mA.
图 8-9 shows the connection of buck regulator in inductor mode.
VM
SW_BK
Ext. Load
VBK
LBK
Control
CBK
GND_BK
FB_BK
图 8-9. Buck (Inductor Mode)
8.3.4.2 Buck in Resistor mode
If the external load requirements is less than 40mA, the inductor can be replaced with a resistor. In resistor mode
the power is dissipated across the external resistor and the efficiency is lower than buck in inductor mode.
图 8-10 shows the connection of buck regulator in resistor mode.
VM
SW_BK
Control
Ext. Load
VBK
RBK
CBK
GND_BK
FB_BK
图 8-10. Buck (Resistor Mode)
28
Submit Document Feedback
Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: MCT8316Z
MCT8316Z
www.ti.com.cn
ZHCSNP1A – MARCH 2021 – REVISED OCTOBER 2021
8.3.4.3 Buck Regulator with External LDO
The buck regulator also supports the voltage requirement to fed to external LDO to generate standard 3.3 V or
5.0 V output rail with higher accuracies. The buck output voltage should be configured to 4 V or 5.5 V to provide
for a extra headroom to support the external LDO for generating 3.3 V or 5 V rail as shown in 图 8-11.
This allows for a lower-voltage LDO design to save cost and better thermal management due to low drop-out
voltage.
VM
SW_BK
VBK
(4V / 5.7V)
VLDO
(3.3V / 5V)
VIN
VLDO
LBK
Control
CBK
3.3V / 5V
LDO
Ext. Load
CLDO
GND_BK
GND
FB_BK
GND
External LDO
图 8-11. Buck Regulator with External LDO
8.3.4.4 AVDD Power Sequencing on Buck Regulator
The AVDD LDO has an option of using the power supply from mixed mode buck regulator to reduce power
dissipation internally. The power sequencing mode allows on-the-fly changeover of LDO power supply from DC
mains (VM) to buck output (VBK) as shown in 图 8-12. This sequencing can be configured through the
BUCK_PS_DIS bit . Power sequencing is supported only when buck output voltage is set to 5.0 V or 5.7 V.
Submit Document Feedback
Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: MCT8316Z
29
MCT8316Z
www.ti.com.cn
ZHCSNP1A – MARCH 2021 – REVISED OCTOBER 2021
VM
SW_BK
Ext. Load
VBK
LBK
Control
CBK
GND_BK
FB_BK
BUCK_PS_DIS
VBK
VM
REF
+
–
AVDD
External Load
CAVDD
AGND
图 8-12. AVDD Power Sequencing on mixed mode Buck Regulator
30
Submit Document Feedback
Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: MCT8316Z
MCT8316Z
www.ti.com.cn
ZHCSNP1A – MARCH 2021 – REVISED OCTOBER 2021
8.3.4.5 Mixed mode Buck Operation and Control
The buck regulator implements a pulse frequency modulation (PFM) architecture with peak current mode control.
The output voltage of the buck regulator is compared with the internal reference voltage (VBK_REF) which is
internally generated depending on the buck-output voltage setting (BUCK_SEL) which constitutes an outer
voltage control loop. Depending on the comparator output going high (VBK < VBK_REF) or low (VBK > VBK_REF),
the high-side power FET of the buck turns on and turna off respectively. An independent current control loop
monitors the current in high-side power FET (IBK) and turns off the high-side FET when the current becomes
higher than the buck current limit (IBK_CL). This implements a current limit control for the buck regulator. 图 8-13
shows the architecture of the buck and various control/protection loops.
SW_BK
IBK
VM
Ext. Load
VBK
LBK
PWM Control
and Driver
CBK
GND_BK
+
Current Limit
_
+
OC Protection
_
+
UV Protection
_
VM
+
Voltage Control
IBK
IBK_CL
IBK
IBK_OCP
FB_BK
VBK
VBK_UVLO
VBK
VBK_REF
_
Buck
Reference
Voltage
Generator
Buck Control
BUCK_SEL
图 8-13. Buck Operation and Control Loops
Submit Document Feedback
Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: MCT8316Z
31
MCT8316Z
www.ti.com.cn
ZHCSNP1A – MARCH 2021 – REVISED OCTOBER 2021
8.3.5 AVDD Linear Voltage Regulator
A 3.3-V, linear regulator is integrated into the MCT8316Z family of devices and is available for use by external
circuitry. The AVDD regulator is used for powering up the internal digital circuitry of the device and additionally,
this regulator can also provide the supply voltage for a low-power MCU or other circuitry supporting low current
(up to 30 mA). The output of the AVDD regulator should be bypassed near the AVDD pin with a X5R or X7R, 1µF, 6.3-V ceramic capacitor routed directly back to the adjacent AGND ground pin.
The AVDD nominal, no-load output voltage is 3.3V.
FB_BK
BUCK_PS_DIS
VBK
VM
REF
+
–
AVDD
External Load
CAVDD
AGND
图 8-14. AVDD Linear Regulator Block Diagram
Use 方程式 1 to calculate the power dissipated in the device by the AVDD linear regulator with VM as supply
(BUCK_PD_DIS = 1)
2 = (88/ F 8#8&& ) × +#8&&
(1)
For example, at a VVM of 24 V, drawing 20 mA out of AVDD results in a power dissipation as shown in 方程式 2.
P
24 V 3.3 V u 20 mA
414 mW
(2)
Use 方程式 3 to calculate the power dissipated in the device by the AVDD linear regulator with buck output as
supply (BUCK_PD_DIS = 0)
P = VFB_BK − VAVDD × IAVDD
32
(3)
Submit Document Feedback
Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: MCT8316Z
MCT8316Z
www.ti.com.cn
ZHCSNP1A – MARCH 2021 – REVISED OCTOBER 2021
8.3.6 Charge Pump
Because the output stages use N-channel FETs, the device requires a gate-drive voltage higher than the VM
power supply to enhance the high-side FETs fully. The MCT8316Z integrates a charge-pump circuit that
generates a voltage above the VM supply for this purpose.
The charge pump requires two external capacitors for operation. See the block diagram, pin descriptions and
see section (节 8.3 ) for details on these capacitors (value, connection, and so forth).
The charge pump shuts down when nSLEEP is low.
VM
VM
CCP
CP
CPH
VM
CFLY
Charge
Pump
Control
CPL
图 8-15. MCT8316Z Charge Pump
Submit Document Feedback
Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: MCT8316Z
33
MCT8316Z
www.ti.com.cn
ZHCSNP1A – MARCH 2021 – REVISED OCTOBER 2021
8.3.7 Slew Rate Control
An adjustable gate-drive current control to the MOSFETs of half-bridges is implemented to achieve the slew rate
control. The MOSFET VDS slew rates are a critical factor for optimizing radiated emissions, energy and duration
of diode recovery spikes, and switching voltage transients related to parasitics. These slew rates are
predominantly determined by the rate of gate charge to internal MOSFETs as shown in 图 8-16.
VM
VCP (Internal)
Slew Rate
Control
OUTx
VCP (Internal)
Slew Rate
Control
GND
图 8-16. Slew Rate Circuit Implementation
The slew rate of each half-bridge can be adjusted by the SLEW pin in hardware device variant or by using the
SLEW bits in SPI device variant. Each half-bridge can be selected to either of a slew rate setting of 25-V/µs, 50V/µs, 125-V/µs or 200-V/µs. The slew rate is calculated by the rise time and fall time of the voltage on OUTx pin
as shown in 图 8-17.
VOUTx
VM
VM
80%
80%
20%
20%
0
Time
trise
tfall
图 8-17. Slew Rate Timings
34
Submit Document Feedback
Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: MCT8316Z
MCT8316Z
www.ti.com.cn
ZHCSNP1A – MARCH 2021 – REVISED OCTOBER 2021
8.3.8 Cross Conduction (Dead Time)
The device is fully protected for any cross conduction of MOSFETs. In half-bridge configuration, the operation of
high-side and low-side MOSFETs are ensured to avoid any shoot-through currents by inserting a dead time
(tdead). This is implemented by sensing the gate-source voltage (VGS) of the high-side and low-side MOSFETs
and ensuring that VGS of high-side MOSFET has reached below turn-off levels before switching on the low-side
MOSFET of same half-bridge as shown in 图 8-18 and 图 8-19.
VM
Gate
Control
+
VGS
HS
±
OUTx
LS
Gate
Control
GND
+
VGS
±
图 8-18. Cross Conduction Protection
OUTx HS
OUTx
Gate
(VGS_HS)
10%
tDEAD
OUTx
Gate
(VHS_LS)
OUTx LS
10%
Time
图 8-19. Dead Time
Submit Document Feedback
Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: MCT8316Z
35
MCT8316Z
www.ti.com.cn
ZHCSNP1A – MARCH 2021 – REVISED OCTOBER 2021
8.3.9 Propagation Delay
The propagation delay time (tpd) is measured as the time between an input logic edge to change in gate driver
voltage. This time has three parts consisting of the digital input deglitcher delay, analog driver, and comparator
delay.
The input deglitcher prevents high-frequency noise on the input pins from affecting the output state of the gate
drivers. To support multiple control modes, a small digital delay is added as the input command propagates
through the device.
PWM
OUTx High
tPD
OUTx
1V
OUTx Low
Time
图 8-20. Propagation Delay Timing
8.3.9.1 Driver Delay Compensation
MCT8316Z monitors the prorogation delay internally and adds a variable delay on top of it to provide fixed delay
as shown in 图 8-21 and 图 8-22. Delay compensation feature reduces uncertainty caused in timing of current
measurement and also reduces duty cycle distortion caused due to propagation delay.
The fixed delay is summation of propagation delay (tPD) caused to internal driver delay and variable delay (tVAR)
added to compensate for uncertainty. The fixed delay can be configured through DLY_TARGET register. Refer
表 8-6 for recommendation on configuration for DLY_TARGET for different slew rate settings.
Delay compensation is only available in SPI variant MCT8316ZR and can be enabled by configuring
DLYCMP_EN and DLY_TARGET. It is disabled in hardware variant MCT8316ZT
PWM
PWM
1V
1V
1V
1V
OUTx
OUTx
Time
Time
tPD
tVAR
DLY_TARGET
tPD
tVAR
DLY_TARGET
DLY_TARGET
图 8-21. Delay Compensation with current flowing
out of phase
36
tPD
tVAR
tPD
tVAR
DLY_TARGET
图 8-22. Delay Compensation with current flowing
into the phase
Submit Document Feedback
Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: MCT8316Z
MCT8316Z
www.ti.com.cn
ZHCSNP1A – MARCH 2021 – REVISED OCTOBER 2021
表 8-6. Delay Target Recommendation
SLEW RATE
DLY_TARGET
200 V/μs
DLY_TARGET = 0x5 (1.2 μs)
125 V/μs
DLY_TARGET = 0x8 (1.8 μs)
50 V/μs
DLY_TARGET = 0xB (2.4 μs)
25 V/μs
DLY_TARGET = 0xF (3.2 μs)
8.3.10 Pin Diagrams
This section presents the I/O structure of all digital input and output pins.
8.3.10.1 Logic Level Input Pin (Internal Pulldown)
图 8-23 shows the input structure for the logic level pins, BRAKE, DIR, DRVOFF, nSLEEP, PWM, SCLK and
SDI. The input can be with a voltage or external resistor. It is recommended to put these pins low in device sleep
mode to reduce leakage current through internal pull-down resistors.
AVDD
STATE
CONNECTION
INPUT
VIH
Tied to AVDD
Logic High
VIL
Tied to GND
Logic Low
RPD
ESD
图 8-23. Logic-Level Input Pin Structure
8.3.10.2 Logic Level Input Pin (Internal Pullup)
图 8-24 shows the input structure for the logic level pin, nSCS. The input can be driven with a voltage or external
resistor.
AVDD
STATE
AVDD
INPUT
CONNECTION
VIH
Tied to AVDD
VIL
Tied to GND
RPU
Logic High
Logic Low
ESD
图 8-24. Logic nSCC
8.3.10.3 Open Drain Pin
图 8-25 shows the structure of the open-drain output pins, nFAULT, FGOUT and SDO in open drain mode. The
open-drain output requires an external pullup resistor to function properly.
Submit Document Feedback
Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: MCT8316Z
37
MCT8316Z
www.ti.com.cn
ZHCSNP1A – MARCH 2021 – REVISED OCTOBER 2021
AVDD
STATE
STATUS
No Fault
Pulled-Up
Fault
Pulled-Down
RPU
OUTPUT
Inactive
ESD
Active
图 8-25. Open Drain
8.3.10.4 Push Pull Pin
图 8-26 shows the structure of SDO in push-pull mode.
AVDD
STATE
STATUS
VOH
Pulled-Up
VOL
Pulled-Down
OUTPUT
ESD
Logic High
Logic Low
图 8-26. Push Pull
8.3.10.5 Four Level Input Pin
图 8-27 shows the structure of the four level input pins, SLEW and VSEL_BK on hardware interface devices. The
input can be set with an external resistor.
CONTROL
AVDD
STATE
AVDD
RESISTANCE
VL1
Tied to AGND
VL2
Hi-Z (>2000 kŸ WR
AGND)
Setting-1
+
RPU
VL3
47 NŸ “5%
to AVDD
VL4
Tied to AVDD
±
Setting-2
RPD
+
±
Setting-3
+
±
Setting-4
图 8-27. Four Level Input Pin Structure
38
Submit Document Feedback
Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: MCT8316Z
MCT8316Z
www.ti.com.cn
ZHCSNP1A – MARCH 2021 – REVISED OCTOBER 2021
8.3.10.6 Seven Level Input Pin
图 8-28 shows the structure of the seven level input pins, ADVANCE and MODE, on hardware interface devices.
The input can be set with an external resistor.
CONTROL
Setting-1
+
STATE
RESISTANCE
VL1
Tied to AGND
VL2
22 k ± 5%
to AGND
VL3
100 k ± 5%
to AGND
VL4
Hi-Z (>2000 kŸ
to AGND)
VL5
100 k ± 5%
to AVDD
VL6
22 NŸ “5%
to AVDD
VL7
Tied to AVDD
±
Setting-2
AVDD
AVDD
+
±
Setting-3
RPU
+
±
Setting-4
RPD
Latch
+
±
Setting-5
+
±
Setting-6
+
±
Setting-7
图 8-28. Seven Level Input Pin Structure
Submit Document Feedback
Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: MCT8316Z
39
MCT8316Z
www.ti.com.cn
ZHCSNP1A – MARCH 2021 – REVISED OCTOBER 2021
8.3.11 Active Demagnetization
MCT8316Z family of devices has smart rectification features (active demagnetization) which decreases power
losses in the device by reducing diode conduction losses. When this feature is enabled, the device automatically
turns ON the corresponding MOSFET whenever it detects diode conduction. This feature can be configured with
the MODE pins in hardware variants. In SPI device variants this can be configured through EN_ASR and
EN_AAR bits. The smart rectification is classified into two categories of automatic synchronous rectification
(ASR) mode and automatic asynchronous rectification (AAR) mode which are described in sections below.
Note
In SPI device variants both bits, EN_ASR and EN_AAR needs to set to 1 to enable active
demagnetization.
The MCT8316Z device includes a high-side (AD_HS) and low-side (AD_LS) comparator which detects the
negative flow of current in the device on each half-bridge. The AD_HS comparator compares the sense-FET
output with the supply voltage (VM) threshold, whereas the AD_LS comparator compares with the ground (0-V)
threshold. Depending upon the flow of current from OUTx to VM or PGND to OUTx, the AD_HS or the AD_LS
comparator trips. This comparator provides a reference point for the operation of active demagnetization feature.
VM
AD_HS
Comparator
+
-
(To Digital)
Sense
FET
OUTX
VM
+
-
(To Digital)
AD_LS
Comparator
Sense
FET
0V (GND)
PGND
VREF
I/V Converter
SOX
GAIN
图 8-29. Active Demagnetization Operation
表 8-7 shows the configuration of ASR and AAR mode in the MCT8316Z device.
表 8-7. PWM_MODE Configuration
40
MODE Type
MODE Pin
(Hardware Variant)
ASR and AAR
configuration
Hall Configuration
Modulation
ASR and AAR Mode
Mode 1
Connected to AGND
EN_ASR = 0,
EN_AAR = 0
Analog Hall Input
Asynchronous
ASR and AAR
Disabled
Mode 2
Connected to AGND
with RMODE1
EN_ASR = 0,
EN_AAR = 0
Digital Hall Input
Asynchronous
ASR and AAR
Disabled
Mode 3
Connected to AGND
with RMODE2
EN_ASR = 0,
EN_AAR = 0
Analog Hall Input
Synchronous
ASR and AAR
Disabled
Mode 4
Hi-Z
EN_ASR = 0,
EN_AAR = 0
Digital Hall Input
Synchronous
ASR and AAR
Disabled
Mode 5
Connected to AVDD
with RMODE2
EN_ASR = 1,
EN_AAR = 1
Analog Hall Input
Synchronous
ASR and AAR
Enabled
Submit Document Feedback
Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: MCT8316Z
MCT8316Z
www.ti.com.cn
ZHCSNP1A – MARCH 2021 – REVISED OCTOBER 2021
表 8-7. PWM_MODE Configuration (continued)
MODE Type
MODE Pin
(Hardware Variant)
Mode 6
Connected to AVDD
with RMODE1
Mode 7
Connected to AVDD
ASR and AAR
configuration
Hall Configuration
Modulation
ASR and AAR Mode
EN_ASR = 1,
EN_AAR = 1
Digital Hall Input
Synchronous
ASR and AAR
Enabled
8.3.11.1 Automatic Synchronous Rectification Mode (ASR Mode)
The automatic synchronous rectification (ASR) mode is divided into two categories of ASR during commutation
and ASR during PWM mode.
8.3.11.1.1 Automatic Synchronous Rectification in Commutation
图 8-30 shows the operation of active demagnetization during the BLDC motor commutation. As shown in 图
8-30 (a), the current is flowing from HA to LC in one commutation state. During the commutation changeover as
shown in 图 8-30 (b), the HC switch is turned on, whereas the commutation current (due to motor inductance) in
OUTA flows through the body diode of LA. This incorporates a higher diode loss depending on the commutation
current. This commutation loss is reduced by turning on the LA for the commutation time as shown in 图 8-30 (c).
Similarly the operation of high-side FET is realized in 图 8-30 (d), (e) and (f).
Submit Document Feedback
Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: MCT8316Z
41
MCT8316Z
www.ti.com.cn
ZHCSNP1A – MARCH 2021 – REVISED OCTOBER 2021
VM
VM
HA
HB
HA
HC
HB
HC
OUTA
OUTA
OUTB
OUTB
OUTC
OUTC
LA
LA
LC
LB
(a) Current flowing from HA to LC
LC
LB
(d) Current flowing from HC to LA
VM
VM
Decay Current
Decay Current
HA
HC
HB
HA
OUTA
HC
HB
OUTA
OUTB
OUTB
OUTC
LA
OUTC
LC
LB
LA
LC
LB
(e) Decay current with AD disabled
(b) Decay current with AD disabled
VM
VM
Decay Current
HA
HB
HC
Decay Current
HA
OUTA
OUTA
OUTB
HC
HB
OUTB
OUTC
LA
LB
LC
(c) Decay current with AD enabled
OUTC
LA
LB
LC
(f) Decay current with AD enabled
图 8-30. ASR in BLDC Motor Commutation
42
Submit Document Feedback
Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: MCT8316Z
MCT8316Z
www.ti.com.cn
ZHCSNP1A – MARCH 2021 – REVISED OCTOBER 2021
图 8-31 (a) shows the BLDC motor phase current waveforms for automatic synchronous rectification mode in
BLDC motor operating with trapezoidal commutation. This figure shows the operation of various switches in a
single commutation cycle.
图 8-31 (b) shows the zoomed waveform of commutation cycle with details on the ASR mode start with margin
time (tmargin) and ASR mode early stop due to active demag. comparator threshold and delays.
Current Limit
3KDVH µ$¶
Current
LA
HA, LB
HA
HB, LC
HA, LC
HB, LA
HC, LA
HC, LB
(a) &RPPXWDWLRQ FXUUHQW RI 3KDVH ³$´
tmargin
tdead
HA Conducts
LA Body Diode
Conducts
HA Body Diode
Conducts
3KDVH µ$¶
Current
LA Conducts
tdead
HA, LC
HB, LC
HC, LA
HC, LB
(b) Zoomed waveform of Active Demagnetization
图 8-31. Current Waveforms for ASR in BLDC Motor Commutation
Submit Document Feedback
Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: MCT8316Z
43
MCT8316Z
www.ti.com.cn
ZHCSNP1A – MARCH 2021 – REVISED OCTOBER 2021
8.3.11.1.2 Automatic Synchronous Rectification in PWM Mode
图 8-32 shows the operation of ASR in PWM mode. As shown in this figure, a PWM is applied only on the highside FET, whereas the low-side FET is always off. During the PWM off time, current decays from the low-side
FET which results in higher power losses. Therefore, this mode supports turning on the low-side FET during the
low-side diode conduction.
PWM_HS
(Applied)
&t
PWM_LS
(Applied)
&t
PWM_HS
(Actual)
&t
PWM_LS
(Actual)
&t
Ia
&t
ASR Mode Disabled
ASR Mode Enabled
图 8-32. ASR in PWM Mode
44
Submit Document Feedback
Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: MCT8316Z
MCT8316Z
www.ti.com.cn
ZHCSNP1A – MARCH 2021 – REVISED OCTOBER 2021
8.3.11.2 Automatic Asynchronous Rectification Mode (AAR Mode)
图 8-33 shows the operation of AAR in PWM mode. As shown in this figure, a PWM is applied in a synchronous
rectification to the high-side and low-side FETs. During the low-side FET conduction, for lower inductance
motors, the current can decay to zero and becomes negative since low side FET is in on-state. This creates a
negative torque on the BLDC motor operation. When AAR mode is enabled, the current during the decay is
monitored and the low-side FET is turned off as soon as the current reaches near to zero. This saves the
negative current building in the BLDC motor which results in better noise performance and better thermal
management.
PWM_HS
(Applied)
&t
PWM_LS
(Applied)
&t
PWM_HS
(Actual)
&t
PWM_LS
(Actual)
&t
Ia
&t
AAR Mode Disabled
AAR Mode Enabled
图 8-33. AAR in PWM Mode
Submit Document Feedback
Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: MCT8316Z
45
MCT8316Z
www.ti.com.cn
ZHCSNP1A – MARCH 2021 – REVISED OCTOBER 2021
8.3.12 Cycle-by-Cycle Current Limit
The current-limit circuit activates if the current flowing through the low-side MOSFET exceeds the ILIMIT current.
This feature restricts motor current to less than the ILIMIT.
The current-limit circuitry utilizes the current sense amplifier output of the three phases compared with the
voltage at ILIM pin. 图 8-34 shows the implementation of current limit circuitry. As shown in this figure, the output
of current sense amplifiers is combined with star connected resistive network. This measured voltage VMEAS is
compared with the external reference voltage e VILIM pin to realize the current limit implementation. The relation
between current sensed on OUTX pin and VMEAS threshold is given as:
8
8/'#5 = @ #8&& W2A F k:+176# + +176$ + +176% ; × )#+0¤3o
(4)
where
• AVDD is 3.3-V LDO output
• OUTX is current flowing into the low-side MOSFET
• GAIN is the CSA_GAIN setting
The ILIMIT threshold can be adjusted by configuring ILIM pin between AVDD/2 to (AVDD/2 - 0.4) V. AVDD/2 is
minimum value and when it is applied on ILIM pin cycle by cycle current limit is disabled, whereas maximum
threshold of 8A can be configured by applying (AVDD/2 - 0.4) V on ILIM pin.
VM
AVDD
GAIN
I/V Converter
OUTA
Sense
FET
PGND
SOB
SOA
To PWM
Controller
VMEAS
+
-
VILIM
ILIM
SOC
图 8-34. Current Limit Implementation
When then the current limit activates, the high-side FET is disabled until the beginning of the next PWM cycle as
shown in 图 8-35. The low-side FETs can operate in brake mode or high-Z mode by configuring the ILIM_RECIR
bit in the SPI device variant.
46
Submit Document Feedback
Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: MCT8316Z
MCT8316Z
www.ti.com.cn
ZHCSNP1A – MARCH 2021 – REVISED OCTOBER 2021
PWM
OUTx
ILIMIT
Bridge Operating in
Brake Mode
IBRIDGE
Time
图 8-35. Cycle-by-Cycle Current-Limit Operation
Submit Document Feedback
Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: MCT8316Z
47
MCT8316Z
www.ti.com.cn
ZHCSNP1A – MARCH 2021 – REVISED OCTOBER 2021
In the MCT8316Z device, when the current limit activates in synchronous rectification mode, the current
recirculates through the low-side FETs while the high-side FETs are disabled as shown in 图 8-36
Moreover, when the current limit activates in asynchronous rectification mode, the current recirculates through
the body diodes of the low-side FETs while the high-side FETs are disabled as shown in 图 8-37
VM
VM
HA
X X X
HB
HC
HA
X X X
HB
HC
OUTA
OUTA
OUTB
OUTB
OUTC
OUTC
LA
LB
LC
LA
X X X
LB
图 8-36. Brake State
LC
图 8-37. Coast State
Note
The current-limit circuit is ignored immediately after the PWM signal goes active for a short blanking
time to prevent false trips of the current-limit circuit.
Note
During the brake operation, a high-current can flow through the low-side FETs which can eventually
trigger the over current protection circuit. This allows the body-diode of the high-side FET to conduct
and pump brake energy to the VM supply rail.
48
Submit Document Feedback
Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: MCT8316Z
MCT8316Z
www.ti.com.cn
ZHCSNP1A – MARCH 2021 – REVISED OCTOBER 2021
8.3.12.1 Cycle by Cycle Current Limit with 100% Duty Cycle Input
In case of 100% duty cycle applied on PWM input, there is no edge available to turn high-side FET back on. To
overcome this problem, MCT8316Z has built in internal PWM clock which is used to turn high-side FET back on
once it is disabled after exceeding ILIMIT threshold. In SPI variant MCT8316ZR, this internal PWM clock can be
configured to either 20 kHz or 40 kHz through PWM_100_DUTY_SEL. In H/W variant MCT8316ZT PWM
internal clock is set to 20 kHz. 图 8-38 shows operation with 100 % duty cycle.
PWM
Internal
PWM
OUTx
ILIMIT
Bridge Operating in
Brake Mode
Time
图 8-38. Cycle-by-Cycle Current-Limit Operation with 100% PWM Duty Cycle
Submit Document Feedback
Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: MCT8316Z
49
MCT8316Z
www.ti.com.cn
ZHCSNP1A – MARCH 2021 – REVISED OCTOBER 2021
8.3.13 Hall Comparators (Analog Hall Inputs)
Three comparators are provided to process the raw signals from the Hall-effect sensors to commutate the motor.
The Hall comparators sense the zero crossings of the differential inputs and pass the information to digital logic.
The Hall comparators have hysteresis, and their detect threshold is centered at 0. The hysteresis is defined as
shown in 图 8-39.
In addition to the hysteresis, the Hall inputs are deglitched with a circuit that ignores any extra Hall transitions for
a period of tHDEG after sensing a valid transition. Ignoring these transitions for the tHDEG time prevents PWM
noise from being coupled into the Hall inputs, which can result in erroneous commutation.
If excessive noise is still coupled into the Hall comparator inputs, adding capacitors between the positive and
negative inputs of the Hall comparators may be required. The ESD protection circuitry on the Hall inputs
implements a diode to the AVDD pin. Because of this diode, the voltage on the Hall inputs should not exceed the
AVDD voltage.
Because the AVDD pin is disabled in sleep mode (nSLEEP inactive), the Hall inputs should not be driven by
external voltages in sleep mode. If the Hall sensors are powered externally, the supply to the Hall sensors should
be disabled if the MCT8316Z device is put into sleep mode. In addition, the Hall sensors' power supply should
be powered up after enabling the motor otherwise an invalid Hall state may cause a delay in motor operation.
VHYS/2
Hall Differential
Voltage (VID/2)
Hall Comparator
Common Mode
Voltage (VCM)
Hall Comparator
Output
tHDEG (Hall
Deglitch Time)
Time
图 8-39. Hall Comparators Operation
50
Submit Document Feedback
Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: MCT8316Z
MCT8316Z
www.ti.com.cn
ZHCSNP1A – MARCH 2021 – REVISED OCTOBER 2021
8.3.14 Advance Angle
The MCT8316Z includes device an advance angle feature to advance the commutation by a specified electrical
angle based on the voltage on the ADVANCE pin (in H/W device variant) or the ADVANCE bits (in SPI device
variant). 图 8-40 shows the operation of advance angle feature.
Hall A
&t
Hall B
&t
Hall C
&t
Before Advance
After Advance
Van
ia
0
&t
Advance
Angle
Vbn
ib
0
&t
2Œ/3
Vcn
ic
0
2Œ/3
HA, LB
HA, LC
HB, LC
HB, LA
HC, LA
2Œ
&t
HC, LB
&t
图 8-40. Advance Angle
Submit Document Feedback
Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: MCT8316Z
51
MCT8316Z
www.ti.com.cn
ZHCSNP1A – MARCH 2021 – REVISED OCTOBER 2021
8.3.15 FGOUT Signal
The MCT8316Z device also has an open-drain FGOUT signal that can be used for closed-loop speed control of
a BLDC motor. This signal includes the information of all three Hall-elements inputs as shown in 节 8.3.15. In the
MCT8316ZR (SPI variant), FGOUT can be configured to be a different division factor of Hall signals as shown in
节 8.3.15. In the MCT8316ZT (Hardware variant), the default mode is FGOUT = 00b.
Hall Input
(HPA, HNA)
Hall Input
(HPB, HNB)
Hall Input
(HPC, HNC)
Hall Comparator
Output (HA) /
Digital Hall Input
Hall Comparator
Output (HB) /
Digital Hall Input
Hall Comparator
Output (HC) /
Digital Hall Input
FGOUT
(FGOUT_SEL =
00b)
FGOUT
(FGOUT_SEL =
01b)
FGOUT
(FGOUT_SEL =
10b)
FGOUT
(FGOUT_SEL =
11b)
Time
图 8-41. FGOUT Signal
52
Submit Document Feedback
Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: MCT8316Z
MCT8316Z
www.ti.com.cn
ZHCSNP1A – MARCH 2021 – REVISED OCTOBER 2021
8.3.16 Protections
The MCT8316Z family of devices is protected against VM undervoltage, charge pump undervoltage, and
overcurrent events. 表 8-8 summarizes various faults details.
表 8-8. Fault Action and Response (SPI Devices)
FAULT
CONDITION
CONFIGURATION
REPORT
H-BRIDGE
LOGIC
RECOVERY
VM undervoltage
(NPOR)
VVM < VUVLO
—
—
Hi-Z
Disabled
Automatic:
VVM > VUVLO_R
CLR_FLT, nSLEEP Reset Pulse (NPOR
bit)
AVDD undervoltage
(NPOR)
VAVDD < VAVDD_UV
—
—
Hi-Z
Disabled
Automatic:
VAVDD > VAVDD_UV_R
CLR_FLT, nSLEEP Reset Pulse (NPOR
bit)
Buck undervoltage
(BUCK_UV)
VFB_BK < VBK_UV
—
nFAULT
Active
Active
Automatic:
VFB_BK > VBUCK_UV_R
CLR_FLT, nSLEEP Reset Pulse
(BUCK_UV bit)
Charge pump
undervoltage
(VCP_UV)
VCP < VCPUV
—
nFAULT
Hi-Z
Active
Automatic:
VVCP > VCPUV
CLR_FLT, nSLEEP Reset Pulse
(VCP_UV bit)
OverVoltage
Protection
(OVP)
OVP_EN = 0b
None
Active
Active
No action (OVP Disabled)
VVM > VOVP
OVP_EN = 1b
FAULT
Hi-Z
Active
Automatic:
VVM < VOVP
CLR_FLT, nSLEEP Reset Pulse (OVP bit)
OCP_MODE = 00b
nFAULT
Hi-Z
Active
Latched:
CLR_FLT, nSLEEP Reset Pulse (OCP
bits)
OCP_MODE = 01b
nFAULT
Hi-Z
Active
Retry:
tRETRY
OCP_MODE = 10b
nFAULT
Active
Active
Automatic:
CLR_FLT, nSLEEP Reset Pulse (OCP
bits)
OCP_MODE = 11b
None
Active
Active
No action
Overcurrent
Protection
(OCP)
IPHASE > IOCP
Buck Overcurrent
Protection
(BUCK_OCP)
IBK > IBK_OC
—
nFAULT
Active
Active
Retry:
tRETRY
SPI Error
(SPI_FLT)
SCLK fault and ADDR
fault
SPI_FLT_REP = 0b
nFAULT
Active
Active
Automatic:
CLR_FLT, nSLEEP Reset Pulse
(SPI_FLT bit)
SPI_FLT_REP = 1b
None
Active
Active
No action
OTP Error
(OTP_ERR)
OTP reading is erroneous
—
nFAULT
Hi-Z
Active
Latched:
Power Cycle, nSLEEP Reset Pulse
MTR_LOCK_MODE = 00b
nFAULT
Hi-Z
Active
Latched:
CLR_FLT, nSLEEP Pulse (MTR_LOCK
bit)
MTR_LOCK_MODE = 01b
nFAULT
Hi-Z
Active
Retry:
tMTR_LOCK_RETRY
MTR_LOCK_MODE = 10b
nFAULT
Active
Active
Automatic:
CLR_FLT, nSLEEP Reset Pulse (OCP
bits)
MTR_LOCK_MODE = 11b
None
Active
Active
No action
OTW_REP = 0b
None
Active
Active
No action
Motor Lock
(MTR_LOCK)
No Hall Signals >
tMTR_LOCK_TDET
Thermal warning
(OTW)
TJ > TOTW
Thermal shutdown
(OTSD)
TJ > TOTSD
OTW_REP = 1b
nFAULT
Active
Active
Automatic:
TJ < TOTW – THYS
CLR_FLT, nSLEEP Pulse (OTW bit)
—
nFAULT
Hi-Z
Active
Automatic:
TJ < TOTSD – THYS
CLR_FLT, nSLEEP Pulse (OTS bit)
Submit Document Feedback
Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: MCT8316Z
53
MCT8316Z
www.ti.com.cn
ZHCSNP1A – MARCH 2021 – REVISED OCTOBER 2021
8.3.16.1 VM Supply Undervoltage Lockout (NPOR)
If at any time the input supply voltage on the VM pin falls lower than the VUVLO threshold (VM UVLO falling
threshold), all of the integrated FETs, driver charge-pump and digital logic controller are disabled as shown in 图
8-42. Normal operation resumes (driver operation) when the VM undervoltage condition is removed. The NPOR
bit is reset and latched low in the IC status (IC_STAT) register once the device presumes VM. The NPOR bit
remains in reset condition until cleared through the CLR_FLT bit or an nSLEEP pin reset pulse (tRST).
VUVLO (max) rising
VUVLO (min) rising
VUVLO (max) falling
VUVLO (min) falling
VVM
DEVICE OFF
DEVICE ON
DEVICE ON
Time
图 8-42. VM Supply Undervoltage Lockout
8.3.16.2 AVDD Undervoltage Lockout (AVDD_UV)
If at any time the voltage on AVDD pin falls lower than the VAVDD_UV threshold, all of the integrated FETs, driver
charge-pump and digital logic controller are disabled. Normal operation resumes (driver operation) when the
AVDD undervoltage condition is removed. The NPOR bit is reset and latched low in the IC status (IC_STAT)
register once the device presumes VM. The NPOR bit remains in reset condition until cleared through the
CLR_FLT bit or an nSLEEP pin reset pulse (tRST).
8.3.16.3 BUCK Undervoltage Lockout (BUCK_UV)
If at any time the voltage on VFB_BK pin falls lower than the VBK_UV threshold, the integrated FETs of the buck
regulator are disabled while the driver FETs, charge pump, and digital logic control continue to operate normally.
The nFAULT pin is driven low in the event of a buck undervoltage fault, and the BK_FLT bit in IC_STAT register
is set in SPI devices. The FAULT and BUCK_UV bits are also latched high in the registers on SPI devices.
Normal operation starts again (buck regulator operation and the nFAULT pin is released) when the BUCK
undervoltage condition clears. The BK_FLT and BUCK_UV bits stay set until cleared through the CLR_FLT bit or
an nSLEEP pin reset pulse (tRST).
8.3.16.4 VCP Charge Pump Undervoltage Lockout (CPUV)
If at any time the voltage on the VCP pin (charge pump) falls lower than the VCPUV threshold voltage of the
charge pump, all of the integrated FETs are disabled and the nFAULT pin is driven low. The FAULT and VCP_UV
bits are also latched high in the registers on SPI devices. Normal operation starts again (driver operation and the
nFAULT pin is released) when the VCP undervoltage condition clears. The CPUV bit stays set until cleared
through the CLR_FLT bit or an nSLEEP pin reset pulse (tRST). The CPUV protection is always enabled in both
hardware and SPI device varaints.
8.3.16.5 Overvoltage Protections (OV)
If at any time input supply voltage on the VM pins rises higher lower than the VOVP threshold voltage, all of the
integrated FETs are disabled and the nFAULT pin is driven low. The FAULT and OVP bits are also latched high
in the registers on SPI devices. Normal operation starts again (driver operation and the nFAULT pin is released)
when the OVP condition clears. The OVP bit stays set until cleared through the CLR_FLT bit or an nSLEEP pin
54
Submit Document Feedback
Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: MCT8316Z
MCT8316Z
www.ti.com.cn
ZHCSNP1A – MARCH 2021 – REVISED OCTOBER 2021
reset pulse (tRST). Setting the OVP_EN bit high on the SPI devices enables this protection feature. On hardware
interface devices, the OVP protection is always enabled and set to a 34-V threshold.
The OVP threshold is also programmable on the SPI device variant. The OVP threshold can be set to 20-V or
32-V based on the OVP_SEL bit.
VVM
VOVP (max) rising
VOVP (min) rising
VOVP (max) falling
VOVP (min) falling
DEVICE OFF
DEVICE ON
DEVICE ON
nFAULT
Time
图 8-43. Over Voltage Protection
8.3.16.6 Overcurrent Protection (OCP)
A MOSFET overcurrent event is sensed by monitoring the current flowing through FETs. If the current across a
FET exceeds the IOCP threshold for longer than the tOCP deglitch time, an OCP event is recognized and action is
done according to the OCP_MODE bit. On hardware interface devices, the IOCP threshold is fixed at 16-A
threshold, the tOCP_DEG is fixed at 0.6-µs, and the OCP_MODE bit is configured for latched shutdown. On SPI
devices, the IOCP threshold is set through the OCP_LVL SPI register, the tOCP_DEG is set through the OCP_DEG
SPI register, and the OCP_MODE bit can operate in four different modes: OCP latched shutdown, OCP
automatic retry, OCP report only, and OCP disabled.
8.3.16.6.1 OCP Latched Shutdown (OCP_MODE = 00b)
After a OCP event in this mode, all MOSFETs are disabled and the nFAULT pin is driven low. The FAULT, OCP,
and corresponding FET's OCP bits are latched high in the SPI registers. Normal operation starts again (driver
operation and the nFAULT pin is released) when the OCP condition clears and a clear faults command is issued
either through the CLR_FLT bit or an nSLEEP reset pulse (tRST).
Submit Document Feedback
Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: MCT8316Z
55
MCT8316Z
www.ti.com.cn
ZHCSNP1A – MARCH 2021 – REVISED OCTOBER 2021
Peak Current due
to deglitch time
IOCP
IOUTx
tOCP
nFAULT Pulled High
nFAULT Released
Fault Condition
nFAULT
Clear Fault
Time
图 8-44. Overcurrent Protection - Latched Shutdown Mode
8.3.16.6.2 OCP Automatic Retry (OCP_MODE = 01b)
After a OCP event in this mode, all the FETs are disabled and the nFAULT pin is driven low. The FAULT, OCP,
and corresponding FET's OCP bits are latched high in the SPI registers. Normal operation starts again
automatically (driver operation and the nFAULT pin is released) after the tRETRY time elapses. After the tRETRY
time elapses, the FAULT, OCP, and corresponding FET's OCP bits stay latched until a clear faults command is
issued either through the CLR_FLT bit or an nSLEEP reset pulse (tRST).
Peak Current due
to deglitch time
IOCP
IOUTx
tRETRY
tOCP
nFAULT Pulled High
nFAULT Released
Fault Condition
nFAULT
Time
图 8-45. Overcurrent Protection - Automatic Retry Mode
8.3.16.6.3 OCP Report Only (OCP_MODE = 10b)
No protective action occurs after a OCP event in this mode. The overcurrent event is reported by driving the
nFAULT pin low and latching the FAULT, OCP, and corresponding FET's OCP bits high in the SPI registers. The
MCT8316Z continues to operate as usual. The external controller manages the overcurrent condition by acting
56
Submit Document Feedback
Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: MCT8316Z
MCT8316Z
www.ti.com.cn
ZHCSNP1A – MARCH 2021 – REVISED OCTOBER 2021
appropriately. The reporting clears (nFAULT pin is released) when the OCP condition clears and a clear faults
command is issued either through the CLR_FLT bit or an nSLEEP reset pulse (tRST).
8.3.16.6.4 OCP Disabled (OCP_MODE = 11b)
No action occurs after a OCP event in this mode.
8.3.16.7 Buck Overcurrent Protection
A buck overcurrent event is sensed by monitoring the current flowing through buck regulator’s FETs. If the
current across the buck regulator FET exceeds the IBK_OCP threshold for longer than the tBK_OCP deglitch time,
an OCP event is recognized. The buck OCP mode is configured in automatic retry setting. In this setting, after a
buck OCP event is detected, all the buck regulator’s FETs are disabled and the nFAULT pin is driven low. The
FAULT, BK_FLT, and BUCK_OCP bits are latched high in the SPI registers. Normal operation starts again
automatically (driver operation and the nFAULT pin is released) after the tBK_RETRY time elapses. The FAULT,
BK_FLT, and BUCK_OCP bits stay latched until the tRETRY period expires.
8.3.16.8 Motor Lock (MTR_LOCK)
During motor is in lock condition the hall signals will be not available, so a Motor Lock event is sensed by
monitoring the hall signals. If the hall signals are not present for for longer than the tMTR_LOCK, a MTR_LCK event
is recognized and action is done according to the MTR_LOCK_MODE bits. On hardware interface devices, the
tMTR_LOCK threshold is set to 1000-ms, and the MTR_LOCK_MODE bit is configured for latched shutdown. On
SPI devices, the tMTR_LOCK threshold is set through the MTR_LOCK_TDET register and the MTR_LOCK_MODE
bit can operate in four different modes: MTR_LOCK latched shutdown, MTR_LOCK automatic retry, MTR_LOCK
report only, and MTR_LOCK disabled.
8.3.16.8.1 MTR_LOCK Latched Shutdown (MTR_LOCK_MODE = 00b)
After a motor lock event in this mode, all FETs are disabled and the nFAULT pin is driven low. The FAULT and
MTR_LOCK bits are latched high in the SPI registers. Normal operation starts again (driver operation and the
nFAULT pin is released) when a clear faults command is issued either through the CLR_FLT bit or an nSLEEP
reset pulse (tRST).
8.3.16.8.2 MTR_LOCK Automatic Retry (MTR_LOCK_MODE = 01b)
After a motor lock event in this mode, all the external MOSFETs are disabled and the nFAULT pin is driven low.
The FAULT and MTR_LOCK bits are latched high in the SPI registers. Normal operation starts again
automatically (driver operation and the nFAULT pin is released) after the tMTR_LOCK_RETRY time elapses. The
FAULT and MTR_LOCK bits stay latched until the tMTR_LOCK_RETRY period expires.
8.3.16.8.3 MTR_LOCK Report Only (MTR_LOCK_MODE= 10b)
No protective action occurs after a MTR_LOCK event in this mode. The motor lock event is reported by driving
the nFAULT pin low and latching the FAULT and MTR_LOCK bits high in the SPI registers. The MCT8316Z
continues to operate as usual. The external controller manages the motor lock condition by acting appropriately.
The reporting clears (nFAULT pin is released) when a clear faults command is issued either through the
CLR_FLT bit or an nSLEEP reset pulse (tRST).
8.3.16.8.4 MTR_LOCK Disabled (MTR_LOCK_MODE = 11b)
No action occurs after a MTR_LOCK event in this mode.
8.3.16.8.5
Note
The motor lock detection scheme requires the PWM off-time (tPWM_OFF) to be lower than the motor
lock detection time (tMTR_LOCK)
8.3.16.9 Thermal Warning (OTW)
If the die temperature exceeds the trip point of the thermal warning (TOTW), the OT bit in the IC status (IC_STAT)
register and OTW bit in the status register is set. The reporting of OTW on the nFAULT pin can be enabled by
Submit Document Feedback
Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: MCT8316Z
57
MCT8316Z
www.ti.com.cn
ZHCSNP1A – MARCH 2021 – REVISED OCTOBER 2021
setting the over-temperature warning reporting (OTW_REP) bit in the configuration control register. The device
performs no additional action and continues to function. In this case, the nFAULT pin releases when the die
temperature decreases below the hysteresis point of the thermal warning (TOTW_HYS). The OTW bit remains set
until cleared through the CLR_FLT bit or an nSLEEP reset pulse (tRST) and the die temperature is lower than
thermal warning trip (TOTW).
Note
Over temperature warning is not reported on nFAULT pin by default.
8.3.16.10 Thermal Shutdown (OTS)
If the die temperature exceeds the trip point of the thermal shutdown limit (TOTS), all the FETs are disabled, the
charge pump is shut down, and the nFAULT pin is driven low. In addition, the FAULT and OT bit in the IC status
(IC_STAT) register and OTS bit in the status register is set. Normal operation starts again (driver operation and
the nFAULT pin is released) when the overtemperature condition clears. The OTS bit stays latched high
indicating that a thermal event occurred until a clear fault command is issued either through the CLR_FLT bit or
an nSLEEP reset pulse (tRST). This protection feature cannot be disabled.
58
Submit Document Feedback
Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: MCT8316Z
MCT8316Z
www.ti.com.cn
ZHCSNP1A – MARCH 2021 – REVISED OCTOBER 2021
8.4 Device Functional Modes
8.4.1 Functional Modes
8.4.1.1 Sleep Mode
The nSLEEP pin manages the state of the MCT8316Z family of devices. When the nSLEEP pin is low, the
device goes to a low-power sleep mode. In sleep mode, all FETs are disabled, sense amplifiers are disabled,
buck regulator (if present) is disabled, the charge pump is disabled, the AVDD regulator is disabled, and the SPI
bus is disabled. The tSLEEP time must elapse after a falling edge on the nSLEEP pin before the device goes to
sleep mode. The device comes out of sleep mode automatically if the nSLEEP pin is pulled high. The tWAKE time
must elapse before the device is ready for inputs.
In sleep mode and when VVM < VUVLO, all MOSFETs are disabled.
Note
During power up and power down of the device through the nSLEEP pin, the nFAULT pin is held low
as the internal regulators are enabled or disabled. After the regulators have enabled or disabled, the
nFAULT pin is automatically released. The duration that the nFAULT pin is low does not exceed the
tSLEEP or tWAKE time.
Note
TI recommends to connect pull up on nFAULT even if it is not used to avoid undesirable entry into
internal test mode. If external supply is used to pull up nFAULT, ensure that it is pulled to >2.2V on
power up or the device will enter internal test mode.
8.4.1.2 Operating Mode
When the nSLEEP pin is high and the VVM voltage is greater than the VUVLO voltage, the device goes to
operating mode. The tWAKE time must elapse before the device is ready for inputs. In this mode the charge
pump, AVDD regulator, buck regulator, and SPI bus are active.
8.4.1.3 Fault Reset (CLR_FLT or nSLEEP Reset Pulse)
In the case of device latched faults, the MCT8316Z family of devices goes to a partial shutdown state to help
protect the power MOSFETs and system.
When the fault condition clears, the device can go to the operating state again by either setting the CLR_FLT
SPI bit on SPI devices or issuing a reset pulse to the nSLEEP pin on either interface variant. The nSLEEP reset
pulse (tRST) consists of a high-to-low-to-high transition on the nSLEEP pin. The low period of the sequence
should fall with the tRST time window or else the device will start the complete shutdown sequence. The reset
pulse has no effect on any of the regulators, device settings, or other functional blocks.
8.4.2 DRVOFF functionality
When DRVOFF pin is pulled high, all six MOSFETs are disabled. If nSLEEP is high when the DRVOFF pin is
high, the charge pump, AVDD regulator, buck regulator, and SPI bus are active and any driver-related faults
such as OCP will be inactive. DRVOFF pin independently disables MOSFETs which will stop motor commutation
irrespective of status of PWM input pin.
Note
Since DRVOFF pin independently disables MOSFET, it can trigger fault condition resulting in nFAULT
getting pulled low.
Submit Document Feedback
Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: MCT8316Z
59
MCT8316Z
www.ti.com.cn
ZHCSNP1A – MARCH 2021 – REVISED OCTOBER 2021
8.5 SPI Communication
8.5.1 Programming
On MCT8316Z SPI devices, an SPI bus is used to set device configurations, operating parameters, and read out
diagnostic information. The SPI operates in secondary mode and connects to a controller. The SPI input data
(SDI) word consists of a 16-bit word, with a 6-bit address and 8 bits of data. The SPI output consists of 16 bit
word, with a 8 bits of status information (STAT register) and 8-bit register data.
A valid frame must meet the following conditions:
• The SCLK pin should be low when the nSCS pin transitions from high to low and from low to high.
• The nSCS pin should be pulled high for at least 400 ns between words.
• When the nSCS pin is pulled high, any signals at the SCLK and SDI pins are ignored and the SDO pin is
placed in the Hi-Z state.
• Data is captured on the falling edge of the SCLK pin and data is propagated on the rising edge of the SCLK
pin.
• The most significant bit (MSB) is shifted in and out first.
• A full 16 SCLK cycles must occur for transaction to be valid.
• If the data word sent to the SDI pin is less than or more than 16 bits, a frame error occurs and the data word
is ignored.
• For a write command, the existing data in the register being written to is shifted out on the SDO pin following
the 8-bit status data.
The SPI registers are reset to the default settings on power up and when the device is enters sleep mode
8.5.1.1 SPI Format
The SDI input data word is 16 bits long and consists of the following format:
•
•
•
•
1 read or write bit, W (bit B15)
6 address bits, A (bits B14 through B9)
Parity bit, P (bit B8). Parity bit is set such that the SDI input data word has even number of 1s and 0s
8 data bits, D (bits B7 through B0)
The SDO output data word is 16 bits long and the first 8 bits are status bits. The data word is the content of the
register being accessed.
For a write command (W0 = 0), the response word on the SDO pin is the data currently in the register being
written to.
For a read command (W0 = 1), the response word is the data currently in the register being read.
nSCS
A1
D1
S1
R1
SDI
SDO
图 8-46.
60
Submit Document Feedback
Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: MCT8316Z
MCT8316Z
www.ti.com.cn
ZHCSNP1A – MARCH 2021 – REVISED OCTOBER 2021
Master Controller
Device
MCLK
SCLK
SDI
MO
SPI
Communication
SDO
MI
SPI
Communication
nSCS
CS
图 8-47.
表 8-9. SDI Input Data Word Format
R/W
ADDRESS
Parity
DATA
B15
B14
B13
B12
B11
B10
B9
B8
B7
B6
B5
B4
B3
B2
B1
B0
W0
A5
A4
A3
A2
A1
A0
P
D7
D6
D5
D4
D3
D2
D1
D0
表 8-10. SDO Output Data Word Format
STATUS
DATA
B15
B14
B13
B12
B11
B10
B9
B8
B7
B6
B5
B4
B3
B2
B1
B0
S7
S6
S5
S4
S3
S2
S1
S0
D7
D6
D5
D4
D3
D2
D1
D0
nSCS
SCLK
SDI
X
MSB
LSB
X
SDO
Z
MSB
LSB
Z
Capture
Point
Propagate
Point
图 8-48. SPI Secondary Timing Diagram
SPI Error Handling
SPI Frame Error (SPI_SCLK_FLT: If the nSCS gets deasserted before the end of 16-bit frame, SPI frame error
is detected and SPI_SCLK_FLT bit is set in STAT2. The SPI_SCLK_FLT status bit is latched and can be cleared
when a clear faults command is issued either through the CLR_FLT bit or an nSLEEP reset pulse
Submit Document Feedback
Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: MCT8316Z
61
MCT8316Z
www.ti.com.cn
ZHCSNP1A – MARCH 2021 – REVISED OCTOBER 2021
SPI Address Error (SPI_ADDR_FLT): If an invalid address is provided in the ADDR field of the input SPI data
on SDI, SPI address error is detected and SPI_ADDR_FLT bit in STAT2 is set. Invalid address is any address
that is not defined in Register Map i.e. address not falling in the range of address 0x0 to 0xC. The
SPI_ADDR_FLT status bit is latched and can be cleared when a clear faults command is issued either through
the CLR_FLT bit or an nSLEEP reset pulse
62
Submit Document Feedback
Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: MCT8316Z
MCT8316Z
www.ti.com.cn
ZHCSNP1A – MARCH 2021 – REVISED OCTOBER 2021
8.6 Register Map
8.6.1 STATUS Registers
STATUS Registers lists the memory-mapped registers for the STATUS registers. All register offset addresses not
listed in STATUS Registers should be considered as reserved locations and the register contents should not be
modified.
表 8-11. STATUS Registers
Offset
Acronym
Register Name
0h
IC_Status_Register
IC Status Register
Section
节 8.6.1.1
1h
Status_Register_1
Status Register 1
节 8.6.1.2
2h
Status_Register_2
Status Register 2
节 8.6.1.3
Complex bit access types are encoded to fit into small table cells. STATUS Access Type Codes shows the codes
that are used for access types in this section.
表 8-12. STATUS Access Type Codes
Access Type
Code
Description
R
R
Read
R-0
R
-0
Read
Returns 0s
Read Type
Reset or Default Value
-n
Value after reset or the default
value
Submit Document Feedback
Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: MCT8316Z
63
MCT8316Z
www.ti.com.cn
ZHCSNP1A – MARCH 2021 – REVISED OCTOBER 2021
8.6.1.1 IC_Status_Register Register (Offset = 0h) [Reset = 00h]
IC_Status_Register is shown in IC_Status_Register Register and described in IC_Status_Register Register Field
Descriptions.
Return to the STATUS Registers.
图 8-49. IC_Status_Register Register
7
6
5
4
3
2
1
0
MTR_LOCK
BK_FLT
SPI_FLT
OCP
NPOR
OVP
OT
FAULT
R-0h
R-0h
R-0h
R-0h
R-0h
R-0h
R-0h
R-0h
表 8-13. IC_Status_Register Register Field Descriptions
Bit
7
Field
Type
Reset
Description
MTR_LOCK
R
0h
Motor Lock Staus Bit
0h = No motor lock is detected
1h = Motor lock is detected
64
6
BK_FLT
R
0h
Buck Fault Bit
0h = No buck regulator fault condition is detected
1h = Buck regulator fault condition is detected
5
SPI_FLT
R
0h
SPI Fault Bit
0h = No SPI fault condition is detected
1h = SPI Fault condition is detected
4
OCP
R
0h
Over Current Protection Status Bit
0h = No overcurrent condition is detected
1h = Overcurrent condition is detected
3
NPOR
R
0h
Supply Power On Reset Bit
0h = Power on reset condition is detected on VM
1h = No power-on-reset condition is detected on VM
2
OVP
R
0h
Supply Overvoltage Protection Status Bit
0h = No overvoltage condition is detected on VM
1h = Overvoltage condition is detected on VM
1
OT
R
0h
Overtemperature Fault Status Bit
0h = No overtemperature warning / shutdown is detected
1h = Overtemperature warning / shutdown is detected
0
FAULT
R
0h
Device Fault Bit
0h = No fault condition is detected
1h = Fault condition is detected
Submit Document Feedback
Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: MCT8316Z
MCT8316Z
www.ti.com.cn
ZHCSNP1A – MARCH 2021 – REVISED OCTOBER 2021
8.6.1.2 Status_Register_1 Register (Offset = 1h) [Reset = 00h]
Status_Register_1 is shown in Status_Register_1 Register and described in Status_Register_1 Register Field
Descriptions.
Return to the STATUS Registers.
图 8-50. Status_Register_1 Register
7
6
5
4
3
2
1
0
OTW
OTS
OCP_HC
OCL_LC
OCP_HB
OCP_LB
OCP_HA
OCP_LA
R-0h
R-0h
R-0h
R-0h
R-0h
R-0h
R-0h
R-0h
表 8-14. Status_Register_1 Register Field Descriptions
Bit
Field
Type
Reset
Description
7
OTW
R
0h
Overtemperature Warning Status Bit
0h = No overtemperature warning is detected
1h = Overtemperature warning is detected
6
OTS
R
0h
Overtemperature Shutdown Status Bit
0h = No overtemperature shutdown is detected
1h = Overtemperature shutdown is detected
5
OCP_HC
R
0h
Overcurrent Status on High-side switch of OUTC
0h = No overcurrent detected on high-side switch of OUTC
1h = Overcurrent detected on high-side switch of OUTC
4
OCL_LC
R
0h
Overcurrent Status on Low-side switch of OUTC
0h = No overcurrent detected on low-side switch of OUTC
1h = Overcurrent detected on low-side switch of OUTC
3
OCP_HB
R
0h
Overcurrent Status on High-side switch of OUTB
0h = No overcurrent detected on high-side switch of OUTB
1h = Overcurrent detected on high-side switch of OUTB
2
OCP_LB
R
0h
Overcurrent Status on Low-side switch of OUTB
0h = No overcurrent detected on low-side switch of OUTB
1h = Overcurrent detected on low-side switch of OUTB
1
OCP_HA
R
0h
Overcurrent Status on High-side switch of OUTA
0h = No overcurrent detected on high-side switch of OUTA
1h = Overcurrent detected on high-side switch of OUTA
0
OCP_LA
R
0h
Overcurrent Status on Low-side switch of OUTA
0h = No overcurrent detected on low-side switch of OUTA
1h = Overcurrent detected on low-side switch of OUTA
Submit Document Feedback
Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: MCT8316Z
65
MCT8316Z
www.ti.com.cn
ZHCSNP1A – MARCH 2021 – REVISED OCTOBER 2021
8.6.1.3 Status_Register_2 Register (Offset = 2h) [Reset = 00h]
Status_Register_2 is shown in Status_Register_2 Register and described in Status_Register_2 Register Field
Descriptions.
Return to the STATUS Registers.
图 8-51. Status_Register_2 Register
7
6
5
4
3
2
RESERVED
OTP_ERR
BUCK_OCP
BUCK_UV
VCP_UV
SPI_PARITY
1
R-0-0h
R-0h
R-0h
R-0h
R-0h
R-0-0h
0
SPI_SCLK_FLT SPI_ADDR_FL
T
R-0h
R-0h
表 8-15. Status_Register_2 Register Field Descriptions
Bit
66
Field
Type
Reset
Description
7
RESERVED
R-0
0h
Reserved
6
OTP_ERR
R
0h
One Time Programmabilty Error
0h = No OTP error is detected
1h = OTP Error is detected
5
BUCK_OCP
R
0h
Buck Regulator Overcurrent Staus Bit
0h = No buck regulator overcurrent is detected
1h = Buck regulator overcurrent is detected
4
BUCK_UV
R
0h
Buck Regulator Undervoltage Staus Bit
0h = No buck regulator undervoltage is detected
1h = Buck regulator undervoltage is detected
3
VCP_UV
R
0h
Charge Pump Undervoltage Status Bit
0h = No charge pump undervoltage is detected
1h = Charge pump undervoltage is detected
2
SPI_PARITY
R-0
0h
SPI Parity Error Bit
0h = No SPI parity error is detected
1h = SPI parity error is detected
1
SPI_SCLK_FLT
R
0h
SPI Clock Framing Error Bit
0h = No SPI clock framing error is detected
1h = SPI clock framing error is detected
0
SPI_ADDR_FLT
R
0h
SPI Address Error Bit
0h = No SPI address fault is detected (due to accessing non-user
register)
1h = SPI address fault is detected
Submit Document Feedback
Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: MCT8316Z
MCT8316Z
www.ti.com.cn
ZHCSNP1A – MARCH 2021 – REVISED OCTOBER 2021
8.6.2 CONTROL Registers
CONTROL Registers lists the memory-mapped registers for the CONTROL registers. All register offset
addresses not listed in CONTROL Registers should be considered as reserved locations and the register
contents should not be modified.
表 8-16. CONTROL Registers
Offset
Acronym
Register Name
3h
Control_Register_1
Control Register 1
节 8.6.2.1
Section
4h
Control_Register_2A
Control Register 2A
节 8.6.2.2
5h
Control_Register_3
Control Register 3
节 8.6.2.3
6h
Control_Register_4
Control Register 4
节 8.6.2.4
7h
Control_Register_5
Control Register 5
节 8.6.2.5
8h
Control_Register_6
Control Register 6
节 8.6.2.6
9h
Control_Register_7
Control Register 7
节 8.6.2.7
Ah
Control_Register_8
Control Register 8
节 8.6.2.8
Bh
Control_Register_9
Control Register 9
节 8.6.2.9
Ch
Control_Register_10
Control Register 10
节 8.6.2.10
Complex bit access types are encoded to fit into small table cells. CONTROL Access Type Codes shows the
codes that are used for access types in this section.
表 8-17. CONTROL Access Type Codes
Access Type
Code
Description
R
R
Read
R-0
R
-0
Read
Returns 0s
W
W
Write
W1C
W
1C
Write
1 to clear
WAPU
W
APU
Write
Atomic write with password
unlock
Read Type
Write Type
Reset or Default Value
-n
Value after reset or the default
value
Submit Document Feedback
Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: MCT8316Z
67
MCT8316Z
www.ti.com.cn
ZHCSNP1A – MARCH 2021 – REVISED OCTOBER 2021
8.6.2.1 Control_Register_1 Register (Offset = 3h) [Reset = 00h]
Control_Register_1 is shown in Control_Register_1 Register and described in Control_Register_1 Register Field
Descriptions.
Return to the CONTROL Registers.
图 8-52. Control_Register_1 Register
7
6
5
4
3
2
1
RESERVED
REG_LOCK
R-0-0h
R/WAPU-0h
0
表 8-18. Control_Register_1 Register Field Descriptions
68
Bit
Field
Type
Reset
Description
7-3
RESERVED
R-0
0h
Reserved
2-0
REG_LOCK
R/WAPU
0h
Register Lock Bits
0h = No effect unless locked or unlocked
1h = No effect unless locked or unlocked
2h = No effect unless locked or unlocked
3h = Write 011b to this register to unlock all registers
4h = No effect unless locked or unlocked
5h = No effect unless locked or unlocked
6h = Write 110b to lock the settings by ignoring further register writes
except to these bits and address 0x03h bits 2-0.
7h = No effect unless locked or unlocked
Submit Document Feedback
Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: MCT8316Z
MCT8316Z
www.ti.com.cn
ZHCSNP1A – MARCH 2021 – REVISED OCTOBER 2021
8.6.2.2 Control_Register_2A Register (Offset = 4h) [Reset = 60h]
Control_Register_2A is shown in Control_Register_2A Register and described in Control_Register_2A Register
Field Descriptions.
Return to the CONTROL Registers.
图 8-53. Control_Register_2A Register
7
6
5
4
3
2
1
0
RESERVED
SDO_MODE
SLEW
PWM_MODE
CLR_FLT
R/W-1h
R/W-1h
R/W-0h
R/W-0h
W1C-0h
表 8-19. Control_Register_2A Register Field Descriptions
Bit
Field
Type
Reset
Description
7-6
RESERVED
R/W
1h
Reserved
5
SDO_MODE
R/W
1h
SDO Mode Setting
0h = SDO IO in Open Drain Mode
1h = SDO IO in Push Pull Mode
4-3
SLEW
R/W
0h
Slew Rate Settings
0h = Slew rate is 25 V/µs
1h = Slew rate is 50 V/µs
2h = Slew rate is 125 V/µs
3h = Slew rate is 200 V/µs
2-1
PWM_MODE
R/W
0h
Device Mode Selection
0h = Asynchronous rectification with analog Hall
1h = Asynchronous rectification with digital Hall
2h = Synchronous rectification with analog Hall
3h = Synchronous rectification with digital Hall
CLR_FLT
W1C
0h
Clear Fault
0h = No clear fault command is issued
1h = To clear the latched fault bits. This bit automatically resets after
being written.
0
Submit Document Feedback
Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: MCT8316Z
69
MCT8316Z
www.ti.com.cn
ZHCSNP1A – MARCH 2021 – REVISED OCTOBER 2021
8.6.2.3 Control_Register_3 Register (Offset = 5h) [Reset = 46h]
Control_Register_3 is shown in Control_Register_3 Register and described in Control_Register_3 Register Field
Descriptions.
Return to the CONTROL Registers.
图 8-54. Control_Register_3 Register
7
6
5
4
3
2
1
0
RESERVED
RESERVED
RESERVED
PWM_100_DU
TY_SEL
OVP_SEL
OVP_EN
RESERVED
OTW_REP
R-0-0h
R/W-1h
R/W-0h
R/W-0h
R/W-0h
R/W-1h
R/W-1h
R/W-0h
表 8-20. Control_Register_3 Register Field Descriptions
Bit
70
Field
Type
Reset
Description
7
RESERVED
R-0
0h
Reserved
6
RESERVED
R/W
1h
Reserved
5
RESERVED
R/W
0h
Reserved
4
PWM_100_DUTY_SEL
R/W
0h
Freqency of PWM at 100% Duty Cycle
0h = 20KHz
1h = 40KHz
3
OVP_SEL
R/W
0h
Overvoltage Level Setting
0h = VM overvoltage level is 34-V
1h = VM overvoltage level is 22-V
2
OVP_EN
R/W
1h
Overvoltage Enable Bit
0h = Overvoltage protection is disabled
1h = Overvoltage protection is enabled
1
RESERVED
R/W
1h
Reserved
0
OTW_REP
R/W
0h
Overtemperature Warning Reporting Bit
0h = Over temperature reporting on nFAULT is disabled
1h = Over temperature reporting on nFAULT is enabled
Submit Document Feedback
Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: MCT8316Z
MCT8316Z
www.ti.com.cn
ZHCSNP1A – MARCH 2021 – REVISED OCTOBER 2021
8.6.2.4 Control_Register_4 Register (Offset = 6h) [Reset = 10h]
Control_Register_4 is shown in Control_Register_4 Register and described in Control_Register_4 Register Field
Descriptions.
Return to the CONTROL Registers.
图 8-55. Control_Register_4 Register
7
6
3
2
DRV_OFF
OCP_CBC
5
OCP_DEG
4
OCP_RETRY
OCP_LVL
1
OCP_MODE
0
R/W-0h
R/W-0h
R/W-1h
R/W-0h
R/W-0h
R/W-0h
表 8-21. Control_Register_4 Register Field Descriptions
Bit
Field
Type
Reset
Description
7
DRV_OFF
R/W
0h
Driver OFF Bit
0h = No Action
1h = Enter Low Power Standby Mode
6
OCP_CBC
R/W
0h
OCP PWM Cycle Operation Bit
0h = OCP clearing in PWM input cycle change is disabled
1h = OCP clearing in PWM input cycle change is enabled
5-4
OCP_DEG
R/W
1h
OCP Deglitch Time Settings
0h = OCP deglitch time is 0.2 µs
1h = OCP deglitch time is 0.6 µs
2h = OCP deglitch time is 1.25 µs
3h = OCP deglitch time is 1.6 µs
3
OCP_RETRY
R/W
0h
OCP Retry Time Settings
0h = OCP retry time is 5 ms
1h = OCP retry time is 500 ms
2
OCP_LVL
R/W
0h
Overcurrent Level Setting
0h = OCP level is 16 A
1h = OCP level is 24 A
OCP_MODE
R/W
0h
OCP Fault Options
0h = Overcurrent causes a latched fault
1h = Overcurrent causes an automatic retrying fault
2h = Overcurrent is report only but no action is taken
3h = Overcurrent is not reported and no action is taken
1-0
Submit Document Feedback
Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: MCT8316Z
71
MCT8316Z
www.ti.com.cn
ZHCSNP1A – MARCH 2021 – REVISED OCTOBER 2021
8.6.2.5 Control_Register_5 Register (Offset = 7h) [Reset = 00h]
Control_Register_5 is shown in Control_Register_5 Register and described in Control_Register_5 Register Field
Descriptions.
Return to the CONTROL Registers.
图 8-56. Control_Register_5 Register
7
6
5
4
3
2
RESERVED
ILIM_RECIR
RESERVED
RESERVED
EN_AAR
EN_ASR
1
CSA_GAIN
0
R/W-0h
R/W-0h
R/W-0h
R/W-0h
R/W-0h
R/W-0h
R/W-0h
表 8-22. Control_Register_5 Register Field Descriptions
Bit
Field
Type
Reset
Description
7
RESERVED
R/W
0h
Reserved
6
ILIM_RECIR
R/W
0h
Current Limit Recirculation Settings
0h = Current recirculation through FETs (Brake Mode)
1h = Current recirculation through diodes (Coast Mode)
5
RESERVED
R/W
0h
Reserved
4
RESERVED
R/W
0h
Reserved
3
EN_AAR
R/W
0h
Active Asynshronous Rectification Enable Bit
0h = AAR mode is disabled
1h = AAR mode is enabled
2
EN_ASR
R/W
0h
Active Synchronous Rectification Enable Bit
0h = ASR mode is disabled
1h = ASR mode is enabled
CSA_GAIN
R/W
0h
Current Sense Amplifier's Gain Settings
0h = CSA gain is 0.15 V/A
1h = CSA gain is 0.3 V/A
2h = CSA gain is 0.6 V/A
3h = CSA gain is 1.2 V/A
1-0
72
Submit Document Feedback
Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: MCT8316Z
MCT8316Z
www.ti.com.cn
ZHCSNP1A – MARCH 2021 – REVISED OCTOBER 2021
8.6.2.6 Control_Register_6 Register (Offset = 8h) [Reset = 00h]
Control_Register_6 is shown in Control_Register_6 Register and described in Control_Register_6 Register Field
Descriptions.
Return to the CONTROL Registers.
图 8-57. Control_Register_6 Register
7
5
4
3
RESERVED
6
RESERVED
BUCK_PS_DIS
BUCK_CL
2
BUCK_SEL
1
BUCK_DIS
0
R-0-0h
R/W-0h
R/W-0h
R/W-0h
R/W-0h
R/W-0h
表 8-23. Control_Register_6 Register Field Descriptions
Bit
Field
Type
Reset
Description
7-6
RESERVED
R-0
0h
Reserved
5
RESERVED
R/W
0h
Reserved
4
BUCK_PS_DIS
R/W
0h
Buck Power Sequencing Disable Bit
0h = Buck power sequencing is enabled
1h = Buck power sequencing is disabled
3
BUCK_CL
R/W
0h
Buck Current Limit Setting
0h = Buck regulator current limit is set to 600 mA
1h = Buck regulator current limit is set to 150 mA
2-1
BUCK_SEL
R/W
0h
Buck Voltage Selection
0h = Buck voltage is 3.3 V
1h = Buck voltage is 5.0 V
2h = Buck voltage is 4.0 V
3h = Buck voltage is 5.7 V
0
BUCK_DIS
R/W
0h
Buck Disable Bit
0h = Buck regulator is enabled
1h = Buck regulator is disabled
Submit Document Feedback
Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: MCT8316Z
73
MCT8316Z
www.ti.com.cn
ZHCSNP1A – MARCH 2021 – REVISED OCTOBER 2021
8.6.2.7 Control_Register_7 Register (Offset = 9h) [Reset = 01h]
Control_Register_7 is shown in Control_Register_7 Register and described in Control_Register_7 Register Field
Descriptions.
Return to the CONTROL Registers.
图 8-58. Control_Register_7 Register
7
4
3
2
1
0
RESERVED
6
5
HALL_HYS
BRAKE_MODE
COAST
BRAKE
DIR
R-0-0h
R/W-0h
R/W-0h
R/W-0h
R/W-0h
R/W-1h
表 8-24. Control_Register_7 Register Field Descriptions
74
Bit
Field
Type
Reset
Description
7-5
RESERVED
R-0
0h
Reserved
4
HALL_HYS
R/W
0h
Hall Comparator Hysteresis Settings
0h = 5 mV
1h = 50 mV
3
BRAKE_MODE
R/W
0h
Brake Mode Setting
0h = Device operation is braking in brake mode
1h = Device operation is coasting in brake mode
2
COAST
R/W
0h
Coast Bit
0h = Device coast mode is disabled
1h = Device coast mode is enabled
1
BRAKE
R/W
0h
Brake Bit
0h = Device brake mode is disabled
1h = Device brake mode is enabled
0
DIR
R/W
1h
Direction Bit
0h = Motor direction is set to clockwise direction
1h = Motor direction is set to anti-clockwise direction
Submit Document Feedback
Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: MCT8316Z
MCT8316Z
www.ti.com.cn
ZHCSNP1A – MARCH 2021 – REVISED OCTOBER 2021
8.6.2.8 Control_Register_8 Register (Offset = Ah) [Reset = 41h]
Control_Register_8 is shown in Control_Register_8 Register and described in Control_Register_8 Register Field
Descriptions.
Return to the CONTROL Registers.
图 8-59. Control_Register_8 Register
7
5
4
FG_MODE
6
RESERVED
MTR_LOCK_R
ETRY
MTR_LOCK_TDET
3
2
MTR_LOCK_MODE
1
0
R/W-1h
R-0-0h
R/W-0h
R/W-0h
R/W-1h
表 8-25. Control_Register_8 Register Field Descriptions
Bit
Field
Type
Reset
Description
7-6
FG_MODE
R/W
1h
Electrical Frequency Generation Output Mode Bits
0h = FGOUT frequency is commutation frequency
1h = FGOUT frequency is 1/2 of commutation frequency
2h = FGOUT frequency is 1/4 of commutation frequency
3h = FGOUT frequency is 1/8 of commutation frequency
5
RESERVED
R-0
0h
Reserved
4
MTR_LOCK_RETRY
R/W
0h
Motor Lock Retry Time Settings
0h = 500 ms
1h = 5000 ms
3-2
MTR_LOCK_TDET
R/W
0h
Motor Lock Detection Time Settings
0h = 300 ms
1h = 500 ms
2h = 1000 ms
3h = 5000 ms
1-0
MTR_LOCK_MODE
R/W
1h
Motor Lock Fault Options
0h = Motor lock causes a latched fault
1h = Motor lock causes an automatic retrying fault
2h = Motor lock is report only but no action is taken
3h = Motor lock is not reported and no action is taken
Submit Document Feedback
Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: MCT8316Z
75
MCT8316Z
www.ti.com.cn
ZHCSNP1A – MARCH 2021 – REVISED OCTOBER 2021
8.6.2.9 Control_Register_9 Register (Offset = Bh) [Reset = 00h]
Control_Register_9 is shown in Control_Register_9 Register and described in Control_Register_9 Register Field
Descriptions.
Return to the CONTROL Registers.
图 8-60. Control_Register_9 Register
7
6
5
4
3
2
1
RESERVED
ADVANCE_LVL
R-0-0h
R/W-0h
0
表 8-26. Control_Register_9 Register Field Descriptions
76
Bit
Field
Type
Reset
Description
7-3
RESERVED
R-0
0h
Reserved
2-0
ADVANCE_LVL
R/W
0h
Phase Advance Setting
0h = 0°
1h = 4°
2h = 7°
3h = 11°
4h = 15°
5h = 20°
6h = 25°
7h = 30°
Submit Document Feedback
Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: MCT8316Z
MCT8316Z
www.ti.com.cn
ZHCSNP1A – MARCH 2021 – REVISED OCTOBER 2021
8.6.2.10 Control_Register_10 Register (Offset = Ch) [Reset = 00h]
Control_Register_10 is shown in Control_Register_10 Register and described in Control_Register_10 Register
Field Descriptions.
Return to the CONTROL Registers.
图 8-61. Control_Register_10 Register
7
6
5
4
3
2
1
RESERVED
DLYCMP_EN
DLY_TARGET
R-0-0h
R/W-0h
R/W-0h
0
表 8-27. Control_Register_10 Register Field Descriptions
Bit
Field
Type
Reset
Description
7-5
RESERVED
R-0
0h
Reserved
4
DLYCMP_EN
R/W
0h
Driver Delay Compensation enable
0h = Disable
1h = Enable
3-0
DLY_TARGET
R/W
0h
Delay Target for Driver Delay Compensation
0h = 0 us
1h = 0.4 us
2h = 0.6 us
3h = 0.8 us
4h = 1 us
5h = 1.2 us
6h = 1.4 us
7h = 1.6 us
8h = 1.8 us
9h = 2 us
Ah = 2.2 us
Bh = 2.4 us
Ch = 2.6 us
Dh = 2.8 us
Eh = 3 us
Fh = 3.2 us
Submit Document Feedback
Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: MCT8316Z
77
MCT8316Z
www.ti.com.cn
ZHCSNP1A – MARCH 2021 – REVISED OCTOBER 2021
9 Application and Implementation
Note
以下应用部分中的信息不属于 TI 器件规格的范围,TI 不担保其准确性和完整性。TI 的客 户应负责确定
器件是否适用于其应用。客户应验证并测试其设计,以确保系统功能。
9.1 Application Information
The MCT8316Z can be used to drive Brushless-DC motors. The following design procedure can be used to
configure the MCT8316Z.
VVM
1 µF
10 nF
0.1 µF
CPL
CPH
VCC
CP
+
0.1 µF
10 µF
VM
RCL1
ILIM
AVDD
Microcontroller
RCL2
CAVDD
AGND
Replace Inductor (LBK) with Resistor
(RBK) for larger external load or to
LBK reduce power dissipa on
RPU1
SW_BK
RPU2
PWM
Control
Module
RBK
nFAULT
GP-I
Driver
Control
External
Load
FGOUT
GP-I
GP-O
nSLEEP
GP-O
DRVOFF
GP-O
PWM
GP-O
DIR
GP-O
BRAKE
MCT8316ZT
CBK
GND_BK
FB_BK
PWM
Control
Input
OUTA
Hall
Sensors
AVDD
Hall A
SLEW
MODE
Hall B
OUTB
ADVANCE
Hall C
Hardware
interface
OUTC
VSEL_BK
PGND
HPA HNA
HPB HNB
HPC HNC
(Optional)
图 9-1. Primary Application Schematics for MCT8316ZT (hardware variant)
78
Submit Document Feedback
Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: MCT8316Z
MCT8316Z
www.ti.com.cn
ZHCSNP1A – MARCH 2021 – REVISED OCTOBER 2021
VVM
1 µF
47 nF
0.1 µF
CPL
CPH
VCC
CP
+
0.1 µF
10 µF
VM
RCL1
ILIM
AVDD
Microcontroller
RCL2
CAVDD
AGND
Replace Inductor (LBK) with Resistor
(RBK) for larger external load or to
LBK reduce power dissipa on
RPU1
SW_BK
RPU2
GP-I
Driver
Control
PWM
Control
Module
External
Load
FGOUT
GP-I
RBK
nFAULT
GP-O
nSLEEP
GP-O
DRVOFF
GP-O
PWM
GP-O
DIR
GP-O
BRAKE
MCT8316ZR
CBK
GND_BK
FB_BK
PWM
Control
Input
OUTA
Hall
Sensors
Hall A
GP-I
SPI
Hall B
OUTB
SDO
GP-O
nSCS
GP-O
SCLK
GP-O
SDI
Hall C
SPI
OUTC
PGND
HPA HNA
HPB HNB
HPC HNC
(Optional)
图 9-2. Primary Application Schematics for MCT8316ZR (SPIvariant)
9.2 Hall Sensor Configuration and Connection
The combinations of Hall sensor connections in this section are common connections.
9.2.1 Typical Configuration
The Hall sensor inputs on the MCT8316Z device can interface with a variety of Hall sensors. Typically, a Hall
element is used, which outputs a differential signal. To use this type of sensor, the AVDD regulator can be used
to power the Hall sensor. 图 9-3 shows the connections.
Submit Document Feedback
Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: MCT8316Z
79
MCT8316Z
www.ti.com.cn
ZHCSNP1A – MARCH 2021 – REVISED OCTOBER 2021
AVDD
INP
OUTN
Hall Sensor
OUTP
HPx
Hall
Comparator
+
-
INN
(Optional)
HNx
图 9-3. Typical Hall Sensor Configuration
Because the amplitude of the Hall-sensor output signal is very low, capacitors are often placed across the Hall
inputs to help reject noise coupled from the motor. Capacitors with a value of 1 nF to 100 nF are typically used.
9.2.2 Open Drain Configuration
Some motors use digital Hall sensors with open-drain outputs. These sensors can also be used with the
MCT8316Z device, with the addition of a few resistors as shown in 图 9-4.
AVDD
1 to
4.7 NŸ
VCC
1 to
4.7 NŸ
HPx
Hall Sensor
Hall
Comparator
OUT
+
-
GND
HNx
To Other
HNx Inputs
图 9-4. Open-Drain Hall Sensor Configuration
The negative (HNx) inputs are biased to AVDD / 2 by a pair of resistors between the AVDD pin and ground. For
open-collector Hall sensors, an additional pullup resistor to the VREG pin is required on the positive (HPx) input.
Again, the AVDD output can usually be used to supply power to the Hall sensors.
80
Submit Document Feedback
Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: MCT8316Z
MCT8316Z
www.ti.com.cn
ZHCSNP1A – MARCH 2021 – REVISED OCTOBER 2021
9.2.3 Series Configuration
Hall elements are also connected in series or parallel depending upon the Hall sensor current/voltage
requirement. 图 9-5 shows the series connection of Hall sensors powered via the MCT8316Z internal LDO
(AVDD). This configuration is used if the current requirement per Hall sensor is high (>10 mA)
RSE
AVDD
INP
Hall Sensor
OUTN
HPA
Hall
Comparator
OUTP
+
-
INN
HNA
INP
Hall Sensor
OUTN
HPB
Hall
Comparator
OUTP
+
-
INN
HNB
INP
Hall Sensor
OUTN
HPC
Hall
Comparator
OUTP
+
-
INN
GND
HNC
图 9-5. Hall Sensor Connected in Series Configuration
Submit Document Feedback
Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: MCT8316Z
81
MCT8316Z
www.ti.com.cn
ZHCSNP1A – MARCH 2021 – REVISED OCTOBER 2021
9.2.4 Parallel Configuration
图 9-6 shows the parallel connection of Hall sensors which is powered by the AVDD. This configuration can be
used if the current requirement per Hall sensor is low ( VM − VBK × IBK
(5)
PR_BK > 0.434W
(7)
PRBK > 24V − 3.3V × 20mA
(6)
9.3.1.1.5 Power Dissipation and Junction Temperature Losses
To calculate the junction temperature of the MCT8316Z from power losses, use 方程式 8. Note that the thermal
resistance θJA depends on PCB configurations such as the ambient temperature, numbers of PCB layers,
copper thickness on top and bottom layers, and the PCB area.
℃
T J ℃ = Ploss W × θ JA W
+ TA ℃
(8)
Submit Document Feedback
Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: MCT8316Z
85
MCT8316Z
www.ti.com.cn
ZHCSNP1A – MARCH 2021 – REVISED OCTOBER 2021
9.3.1.2 Application Curves
图 9-9. Device Powerup with VM
图 9-10. Device Powerup with nSLEEP
图 9-11. Driver PWM Operation
图 9-12. Driver PWM Operation with FGOUT
图 9-13. Power Management
86
图 9-14. Driver PWM with Active Demagnetization
(ASR and AAR)
Submit Document Feedback
Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: MCT8316Z
MCT8316Z
www.ti.com.cn
ZHCSNP1A – MARCH 2021 – REVISED OCTOBER 2021
图 9-15. Driver PWM Operation with Current Limit
图 9-16. Driver 100% Operation with Current
Chopping
Submit Document Feedback
Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: MCT8316Z
87
MCT8316Z
www.ti.com.cn
ZHCSNP1A – MARCH 2021 – REVISED OCTOBER 2021
10 Power Supply Recommendations
10.1 Bulk Capacitance
Having an appropriate local bulk capacitance is an important factor in motor drive system design. It is generally
beneficial to have more bulk capacitance, while the disadvantages are increased cost and physical size.
The amount of local capacitance needed depends on a variety of factors, including:
• The highest current required by the motor system
• The capacitance and current capability of the power supply
• The amount of parasitic inductance between the power supply and motor system
• The acceptable voltage ripple
• The type of motor used (brushed dc, brushless DC, stepper)
• The motor braking method
The inductance between the power supply and the motor drive system limits the rate current can change from
the power supply. If the local bulk capacitance is too small, the system responds to excessive current demands
or dumps from the motor with a change in voltage. When adequate bulk capacitance is used, the motor voltage
remains stable and high current can be quickly supplied.
The data sheet generally provides a recommended value, but system-level testing is required to determine the
appropriate sized bulk capacitor.
Parasitic Wire
Inductance
Motor Drive System
Power Supply
VM
+
+
Motor Driver
±
GND
Local
Bulk Capacitor
IC Bypass
Capacitor
图 10-1. Example Setup of Motor Drive System With External Power Supply
The voltage rating for bulk capacitors should be higher than the operating voltage, to provide margin for cases
when the motor transfers energy to the supply.
88
Submit Document Feedback
Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: MCT8316Z
MCT8316Z
www.ti.com.cn
ZHCSNP1A – MARCH 2021 – REVISED OCTOBER 2021
11 Layout
11.1 Layout Guidelines
The bulk capacitor should be placed to minimize the distance of the high-current path through the motor driver
device. The connecting metal trace widths should be as wide as possible, and numerous vias should be used
when connecting PCB layers. These practices minimize inductance and allow the bulk capacitor to deliver high
current.
Small-value capacitors such as the charge pump, AVDD, and VREF capacitors should be ceramic and placed
closely to device pins.
The high-current device outputs should use wide metal traces.
To reduce noise coupling and EMI interference from large transient currents into small-current signal paths,
grounding should be partitioned between PGND and AGND. TI recommends connecting all non-power stage
circuitry (including the thermal pad) to AGND to reduce parasitic effects and improve power dissipation from the
device. Optionally, GND_BK can be split. Ensure grounds are connected through net-ties or wide resistors to
reduce voltage offsets and maintain gate driver performance.
The device thermal pad should be soldered to the PCB top-layer ground plane. Multiple vias should be used to
connect to a large bottom-layer ground plane. The use of large metal planes and multiple vias helps dissipate
the I2 × RDS(on) heat that is generated in the device.
To improve thermal performance, maximize the ground area that is connected to the thermal pad ground across
all possible layers of the PCB. Using thick copper pours can lower the junction-to-air thermal resistance and
improve thermal dissipation from the die surface.
Separate the SW_BUCK and FB_BUCK traces with ground separation to reduce buck switching from coupling
as noise into the buck outer feedback loop. Widen the FB_BUCK trace as much as possible to allow for faster
load switching.
Recommended Layout Example for VQFN Package shows a layout example for the MCT8316Z.
Submit Document Feedback
Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: MCT8316Z
89
MCT8316Z
www.ti.com.cn
ZHCSNP1A – MARCH 2021 – REVISED OCTOBER 2021
11.2 Layout Example
Recommended Layout Example for VQFN Package
90
Submit Document Feedback
Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: MCT8316Z
MCT8316Z
www.ti.com.cn
ZHCSNP1A – MARCH 2021 – REVISED OCTOBER 2021
11.3 Thermal Considerations
The MCT8316Z has thermal shutdown (TSD) as previously described. A die temperature in excess of 150°C
(minimally) disables the device until the temperature drops to a safe level.
Any tendency of the device to enter thermal shutdown is an indication of excessive power dissipation, insufficient
heatsinking, or too high an ambient temperature.
11.3.1 Power Dissipation
The power dissipated in the output FET resistance, or RDS(on) dominates power dissipation in the MCT8316Z.
At start-up and fault conditions, this current is much higher than normal running current; remember to take these
peak currents and their duration into consideration.
The total device dissipation is the power dissipated in each of the three half-H-bridges added together.
The maximum amount of power that the device can dissipate depends on ambient temperature and heatsinking.
Note that RDS(on) increases with temperature, so as the device heats, the power dissipation increases. Take this
into consideration when sizing the heatsink.
A summary of equations for calculating each loss is shown below for trapezoidal control.
表 11-1. MCT8316Z Power Losses for Trapezoidal Control
Loss type
Trapezoidal
Standby power
Pstandby = VM x IVM_TA
LDO (from VM)
PLDO = (VM-VAVDD) x IAVDD
FET conduction
PCON = 2 x IRMS(trap) x Rds,on(TA)
FET switching
PSW = IPK(trap) x VPK(trap) x trise/fall x fPWM
Diode
Pdiode = IRMS(trap) x Vdiode
X tdiode x fPWM
Buck
PBK = 0.97 x VBK x IBK
Submit Document Feedback
Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: MCT8316Z
91
MCT8316Z
www.ti.com.cn
ZHCSNP1A – MARCH 2021 – REVISED OCTOBER 2021
12 Device and Documentation Support
12.1 支持资源
TI E2E™ 支持论坛是工程师的重要参考资料,可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解
答或提出自己的问题可获得所需的快速设计帮助。
链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范,并且不一定反映 TI 的观点;请参阅
TI 的《使用条款》。
12.2 Trademarks
TI E2E™ is a trademark of Texas Instruments.
所有商标均为其各自所有者的财产。
12.3 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
12.4 术语表
TI 术语表
92
本术语表列出并解释了术语、首字母缩略词和定义。
Submit Document Feedback
Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: MCT8316Z
PACKAGE OUTLINE
VQFN - 1 mm max height
RGF0040E
PLASTIC QUAD FLAT PACK- NO LEAD
A
5.1
4.9
B
PIN 1 INDEX AREA
7.1
6.9
1 MAX
C
SEATING PLANE
3.7±0.1
0.05
0.00
0.08 C
3.5
SYMM
(0.1) TYP
20
13
36X 0.5
21
12
SYMM
41
5.5
5.7±0.1
1
PIN 1 ID
(OPTIONAL)
32
33
40
40X 0.5
0.3
40X 0.3
0.2
0.1
0.05
C A B
C
4224999/A 06/2019
NOTES:
1.
2.
3.
All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
This drawing is subject to change without notice.
The package thermal pad must be soldered to the printed circuit board for optimal thermal and mechanical performance.
www.ti.com
EXAMPLE BOARD LAYOUT
VQFN - 1 mm max height
RGF0040E
PLASTIC QUAD FLAT PACK- NO LEAD
(3.7)
(3.5)
36X (0.5)
SYMM
33
40
40X (0.6)
40X (0.25)
1
32
(Ø0.2) VIA
TYP
(5.7)
SYMM
41
(5.5)
(1.35)
(1.25)
21
12
20
13
(R0.05) TYP
(0.625)
(0.975)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 12X
0.07 MAX
ALL AROUND
0.07 MIN
METAL ALL AROUND
SOLDER MASK
OPENING
EXPOSED METAL
EXPOSED METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
SOLDER MASK
DEFINED
NON- SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4224999/A 06/2019
NOTES: (continued)
4.
5.
This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271) .
Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
www.ti.com
EXAMPLE STENCIL DESIGN
VQFN - 1 mm max height
RGF0040E
PLASTIC QUAD FLAT PACK- NO LEAD
(3.5)
36X (0.5)
SYMM
33
40
40X (0.6)
40X (0.25)
41
1
32
(Ø0.2) VIA
TYP
SYMM
(5.5)
(0.675)
(1.35)
21
12
12X (1.15)
20
13
12X (1.05)
(R0.05) TYP
(1.25)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD
69% PRINTED COVERAGE BY AREA
SCALE: 12X
4224999/A 06/2019
NOTES: (continued)
6.
Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
PACKAGE OPTION ADDENDUM
www.ti.com
20-Jan-2022
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
MCT8316Z0RRGFR
ACTIVE
VQFN
RGF
40
3000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
MCT
8316ZR
MCT8316Z0TRGFR
ACTIVE
VQFN
RGF
40
3000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
MCT
8316ZT
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of