ONET3301PARGTTG4

    
    SLLS603 − MARCH 2004 features D Multi-Rate Operation from 155 Mbps Up to D D D D D D D D 3.3 Gbps 106-mW Power Consumption Input Offset Cancellation High Input Dynamic Range Output Disable Output Polarity Select CML Data Outputs Receive Signals Strength Indicator (RSSI) Loss of Signal Detection D Single 3.3-V Supply D Surface Mount Small Footprint 3 mm × 3 mm 16-Pin QFN Package applications D SONET/SDH Transmission Systems at OC3, D D OC12, OC24, OC48 1.0625-Gbps and 2.125-Gbps Fibre Channel Receivers Gigabit Ethernet Receivers description The ONET3301PA is a versatile high-speed limiting amplifier for multiple fiber optic applications with data rates up to 3.3 Gbps. This device provides a gain of about 50 dB, which ensures a fully differential output swing for input signals as low as 3 mVp−p. The high input signal dynamic range ensures low jitter output signals even when overdriven with input signal swings as high as 1200 mVp−p. The ONET3301PA comprises a loss of signals detection as well as a received signal strength indicator. The part is available in a small footprint 3 mm × 3 mm 16-pin QFN package and requires a single 3.3-V supply. This power efficient limiting amplifier dissipates less than 106 mW typical. It is characterized for operation from –40°C to 85°C. available options TA −40°C to 85°C PACKAGED DEVICE ONET3301PARGT FEATURES 3.3-Gbps limiting amplifier with LOS and RSSI Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Copyright  2004, Texas Instruments Incorporated 

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    SLLS603 − MARCH 2004 block diagram A simplified block diagram of the ONET3301PA is shown in Figure 1. These compact, low power 3.3-Gbps limiting amplifier consists of a high-speed data path with offset cancellation block, a loss of signal and RSSI detection block, and a bandgap voltage reference and bias current generation block. The limiting amplifier requires a single 3.3-V supply voltage. All circuit parts are described in detail below. COC2 COC1 VCC Offset Cancellation GND OUTPOL VCCO DIN+ DIN− + + − + + Gain Stage Gain Stage + DOUT+ − Input Buffer DOUT− Gain Stage CML Output Buffer DISABLE Bandgap Voltage Reference and Bias Current Generation Loss of Signal and RSSI Detection LOS RSSI TH Figure 1. Block Diagram high-speed data path The high-speed data signal is applied to the data path by means of the input signal pins DIN+/DIN–. The data path consists of the input stage with 2 × 50-Ω on-chip line termination to VCC, three gain stages, which provide the required typical gain of about 50 dB, and a CML output stage. The amplified data output signal is available at the output pins DOUT+/DOUT–, which provide 2 × 50-Ω back-termination to VCCO. The output stage also includes a data polarity switching function, which is controlled by the OUTPOL input and a disable function, controlled by the signal applied to the DISABLE input pin. An offset cancellation compensates inevitable internal offset voltages and thus ensures proper operation even for small input data signals. The low frequency cutoff is as low as 45 kHz with the built-in filter capacitor. For applications, which require even lower cutoff frequencies, an additional external filter capacitor may be connected to the COC1/COC2 pins. loss of signal and RSSI detection The output signal of the input buffer is monitored by the loss of signal and RSSI detection circuitry. In this block a signal is generated, which is linear proportional to the input amplitude over a wide input voltage range. This signal is available at the RSSI output pin. Furthermore, this circuit block compares the input signal to a threshold, which can be programmed by means of an external resistor connected to the TH pin. If the input signal falls below the specified threshold, a loss of signal is indicated at the LOS pin. 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 
    
    SLLS603 − MARCH 2004 bandgap voltage and bias generation The ONET3301PA limiting amplifier is supplied by a single 3.3-V ±10% supply voltage connected to the VCC and VCCO pins. This voltage is referred to ground (GND). An on-chip bandgap voltage circuitry generates a supply voltage independent reference from which all other internally required voltages and bias currents are derived. package RSSI COC1 COC2 GND For the ONET3301PA a small footprint 3 mm × 3 mm 16-pin QFN package is used, with a lead pitch of 0,5 mm. The pin out is shown in Figure 2. VCC VCCO DIN+ DOUT+ DIN− VCC DOUT− GND DISABLE LOS TH OUTPOL Figure 2. Pinout of ONET3301PA in a 3 mm y 3 mm 16-Pin QFN Package terminal functions The following table shows a pin description for the ONET3301PA in a 3 mm x 3 mm 16-pin QFN package. TERMINAL NAME NO. TYPE DESCRIPTION 3.3-V ±10% supply voltage VCC 1, 4 Supply DIN+ 2 Analog in Noninverted data input. On-chip 50-Ω terminated to VCC DIN– 3 Analog in Inverted data input. On-chip 50-Ω terminated to VCC TH 5 Analog in LOS threshold adjustment with resistor to GND. DISABLE 6 CMOS in Disables CML output stage when set to high level. LOS 7 CMOS out GND 8, 16, EP Supply OUTPOL 9 CMOS in Output data signal polarity select (internally pulled up): Setting to high level or leaving pin open selects normal polarity. Low level selects inverted polarity. High level indicates that the input signal amplitude is below the programmed threshold level. Circuit ground. Exposed die pad (EP) must be grounded. DOUT– 10 CML out Inverted data output. On-chip 50-Ω back-terminated to VCCO DOUT+ 11 CML out Noninverted data output. On-chip 50-Ω back-terminated to VCCO VCCO 12 Supply RSSI 13 Analog out COC1 14 Analog Offset cancellation filter capacitor terminal 1. Connect an additional filter capacitor between this pin and COC2 (pin 15). To disable the offset cancellation loop connect COC1 and COC2 (pins 14 and 15). COC2 15 Analog Offset cancellation filter capacitor terminal 2. Connect an additional filter capacitor between this pin and COC1 (pin 14). To disable the offset cancellation loop connect COC1 and COC2 (pins 14 and 15). 3.3-V ±10% supply voltage for output stage Analog output voltage proportional to the input data amplitude. Indicates the strength of the received signal (RSSI). POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3 
    
    SLLS603 − MARCH 2004 absolute maximum ratings over operating free-air temperature range unless otherwise noted† VALUE UNIT –0.3 to 4 V 0.5 to 4 V –0.3 to 4 V ±1 V VCC, VCCO VDIN+, VDIN− Supply voltage, See Note 1 VTH,VDISABLE,VLOS,VOUTPOL,VDOUT+, VDOUT−, VRSSI, VCOC1, VCOC2 Voltage at TH, DISABLE, LOS, OUTPOL, DOUT+, DOUT–, RSSI, COC1, and COC2, See Note 1 VCOC_DIFF VDIN_DIFF Differential voltage between COC1 and COC2 ILOS IDIN+, IDIN−, IDOUT+, IDOUT– Current into LOS ESD ESD rating at all pins TJ(max) Tstg Maximum junction temperature Storage temperature range TA TL Characterized free-air operating temperature range −40 to 85 °C 260 °C Voltage at DIN+, DIN–, See Note 1 Differential voltage between DIN+ and DIN– Continuous current at inputs and outputs Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds ±2.5 V –1 to 9 mA –25 to 25 mA 2 kV (HBM) 125 °C −65 to 85 °C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE 1: All voltage values are with respect to network ground terminal. recommended operating conditions Supply voltage, VCC, VCCO Operating free-air temperature, TA MIN TYP MAX 3 3.3 3.6 V 85 °C −40 UNIT dc electrical characteristics over recommended operating conditions (unless otherwise noted) PARAMETER TEST CONDITIONS VCC,VCCO ICC Supply voltage VOD Differential data output voltage swing rIN, rOUT Data input/output resistance MIN 3 Supply current DISABLE = low (excludes CML output current) DISABLE = high V(IN_MIN) V(IN_MAX) DISABLE = low 600 Single ended TYP 3.6 V 32 40 mA 0.25 10 780 1200 mVp−p mVp−p 100 RSSI output voltage Input = 80 mVp−p, RRSSI ≥ 10 kΩ 2800 RSSI linearity 20−dB input signal, VIN ≤ 80 mVpp BER < 10–10 ±3% ±8% 3 5 Data input overload 2.1 LOS hysteresis LOS assert threshold range 223−1 PRBS (at 2.5 Gbps and 155 Mbps) Power supply noise rejection f < 2 MHz LOS low voltage POST OFFICE BOX 655303 2.4 • DALLAS, TEXAS 75265 4.5 2−40 26 V V 0.4 2.5 mVp−p mVp−p V 0.6 ISINK = –30 µA ISOURCE = 1 mA 223−1 PRBS (at 2.5 Gbps and 155 Mbps) LOS high voltage mV 1200 CMOS input low voltage 4 Ω Input = 2 mVp−p, RRSSI ≥ 10 kΩ Data input sensitivity UNIT 3.3 50 CMOS input high voltage VTH PSNR MAX V dB mVp−p dB 
    
    SLLS603 − MARCH 2004 ac electrical characteristics over recommended operating conditions (unless otherwise noted) typical operating condition is at VCC = 3.3 V and TA = 25°C PARAMETER TEST CONDITIONS MIN COC = open COC = 2.2 nF Low frequency −3-dB bandwidth DJ MAX 45 kHz 3.3 Input referred noise Gb/s µVRMS 180 Deterministic jitter, See Note 2 UNIT 70 0.8 Data rate vNI TYP K28.5 pattern at 3.3 Gbps 8.5 25 223−1 PRBS equivalent pattern at 2.7 Gbps 9.3 30 K28.5 pattern at 2.1 Gbps 7.8 25 223−1 PRBS equivalent pattern at 155 Mbps 25 50 Input = 5 mVpp 6.5 psp−p RJ Random jitter tr tf Output rise time 20% to 80% 60 85 ps Output fall time 20% to 80% 60 85 ps tDIS tLOS Disable response time Input = 10 mVpp psRMS 3 20 LOS assert/deassert time 2 ns 100 µs NOTE 2: Deterministic jitter does not include pulse-width distortion due to residual small output offset voltage. APPLICATION INFORMATION Figure 3 shows the ONET3301PA connected with an ac-coupled interface to the data signal source as well as to the output load. Besides the ac-coupling capacitors C1 through C4 in the input and output data signal lines, the only required external component is the LOS threshold setting resistor RTH. In addition, an optional external filter capacitor (COC) may be used if a low cutoff frequency is desired. RSSI RSSI COC1 GND COC2 COC Optional VCC C2 DIN+ DIN− ONET3301PA DOUT+ 16 Pin QFN DOUT− TH VCC OUTPOL VCC C3 C4 DOUT+ DOUT− OUTPOL GND DIN− VCCO LOS C1 DISABLE DIN+ DISABLE LOS RTH Figure 3. Basic Application Circuit With AC-Coupled I/Os POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All products are sold subject to TI’s terms and conditions of sale supplied at the time of order acknowledgment. TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI’s standard warranty. Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty. Except where mandated by government requirements, testing of all parameters of each product is not necessarily performed. TI assumes no liability for applications assistance or customer product design. Customers are responsible for their products and applications using TI components. To minimize the risks associated with customer products and applications, customers should provide adequate design and operating safeguards. TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right, copyright, mask work right, or other TI intellectual property right relating to any combination, machine, or process in which TI products or services are used. Information published by TI regarding third-party products or services does not constitute a license from TI to use such products or services or a warranty or endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual property of the third party, or a license from TI under the patents or other intellectual property of TI. Reproduction of information in TI data books or data sheets is permissible only if reproduction is without alteration and is accompanied by all associated warranties, conditions, limitations, and notices. Reproduction of this information with alteration is an unfair and deceptive business practice. TI is not responsible or liable for such altered documentation. Resale of TI products or services with statements different from or beyond the parameters stated by TI for that product or service voids all express and any implied warranties for the associated TI product or service and is an unfair and deceptive business practice. TI is not responsible or liable for any such statements. Following are URLs where you can obtain information on other Texas Instruments products and application solutions: Products Applications Amplifiers amplifier.ti.com Audio www.ti.com/audio Data Converters dataconverter.ti.com Automotive www.ti.com/automotive DSP dsp.ti.com Broadband www.ti.com/broadband Interface interface.ti.com Digital Control www.ti.com/digitalcontrol Logic logic.ti.com Military www.ti.com/military Power Mgmt power.ti.com Optical Networking www.ti.com/opticalnetwork Microcontrollers microcontroller.ti.com Security www.ti.com/security Telephony www.ti.com/telephony Video & Imaging www.ti.com/video Wireless www.ti.com/wireless Mailing Address: Texas Instruments Post Office Box 655303 Dallas, Texas 75265 Copyright  2004, Texas Instruments Incorporated