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OPA314, OPA2314, OPA4314
SBOS563G – MAY 2011 – REVISED JUNE 2015
OPAx314 3-MHz, Low-Power, Low-Noise, RRIO, 1.8-V CMOS
Operational Amplifier
1 Features
3 Description
•
•
•
•
•
•
•
•
•
The OPA314 family of single-, dual-, and quadchannel operational amplifiers represents a new
generation of low-power, general-purpose CMOS
amplifiers. Rail-to-rail input and output swings, low
quiescent current (150 μA typically at 5 VS) combined
with a wide bandwidth of 3 MHz, and very low noise
(14 nV/√Hz at 1 kHz) make this family very attractive
for a variety of battery-powered applications that
require a good balance between cost and
performance. The low input bias current supports
applications with MΩ source impedances.
1
Low IQ: 150 µA/ch
Wide Supply Range: 1.8 V to 5.5 V
Low Noise: 14 nV/√Hz at 1 kHz
Gain Bandwidth: 3 MHz
Low Input Bias Current: 0.2 pA
Low Offset Voltage: 0.5 mV
Unity-Gain Stable
Internal RF/EMI Filter
Extended Temperature Range:
–40°C to 125°C
The robust design of the OPA314 devices provides
ease-of-use to the circuit designer: unity-gain stability
with capacitive loads of up to 300 pF, an integrated
RF/EMI rejection filter, no phase reversal in overdrive
conditions, and high electrostatic discharge (ESD)
protection (4-kV HBM).
2 Applications
•
•
•
•
•
•
Battery-Powered Instruments:
– Consumer, Industrial, Medical
– Notebooks, Portable Media Players
Photodiode Amplifiers
Active Filters
Remote Sensing
Wireless Metering
Handheld Test Equipment
These devices are optimized for low-voltage
operation as low as 1.8 V (±0.9 V) and up to 5.5 V
(±2.75 V), and are specified over the full extended
temperature range of –40°C to 125°C.
The OPA314 (single) is available in both SC70-5 and
SOT23-5 packages. The OPA2314 (dual) is offered in
SO-8, MSOP-8, and DFN-8 packages. The quadchannel OPA4314 is offered in a TSSOP-14 package.
EMIRR vs Frequency
Device Information(1)
120
110
PART NUMBER
EMIRR IN+ (dB)
100
90
OPA314
80
70
60
OPA2314
50
40
OPA4314
30
20
10
0
10M
PACKAGE
BODY SIZE (NOM)
SOT-23 (5)
2.90 mm × 1.60 mm
SC70 (5)
2.00 mm × 1.25 mm
VSSOP (8)
3.00 mm × 3.00 mm
SOIC (8)
4.90 mm × 3.91 mm
VSON (8)
3.00 mm × 3.00 mm
TSSOP (14)
5.00 mm × 4.40 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
100M
1G
Frequency (Hz)
10G
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
OPA314, OPA2314, OPA4314
SBOS563G – MAY 2011 – REVISED JUNE 2015
www.ti.com
Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
4
6
6.1
6.2
6.3
6.4
6.5
6.6
6.7
6.8
6
6
6
6
7
7
7
9
Absolute Maximum Ratings .....................................
ESD Ratings..............................................................
Recommended Operating Conditions.......................
Thermal Information: OPA314 ..................................
Thermal Information: OPA2314 ................................
Thermal Information: OPA4314 ................................
Electrical Characteristics...........................................
Typical Characteristics ..............................................
Detailed Description ............................................ 16
7.1 Overview ................................................................. 16
7.2 Functional Block Diagram ....................................... 16
7.3 Feature Description................................................. 16
7.4 Device Functional Modes........................................ 19
8
Application and Implementation ........................ 20
8.1 Application Information............................................ 20
8.2 Typical Application .................................................. 22
9 Power Supply Recommendations...................... 24
10 Layout................................................................... 25
10.1 Layout Guidelines ................................................. 25
10.2 Layout Example .................................................... 25
11 Device and Documentation Support ................. 26
11.1
11.2
11.3
11.4
11.5
11.6
Device Support......................................................
Related Links ........................................................
Community Resource............................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
26
26
26
26
26
27
12 Mechanical, Packaging, and Orderable
Information ........................................................... 27
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision F (April 2013) to Revision G
Page
•
Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation
section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and
Mechanical, Packaging, and Orderable Information section ................................................................................................. 1
•
Moved revision history to the second page ............................................................................................................................ 1
Changes from Revision E (September 2012) to Revision F
•
Page
Changed document title (removed "Value Line Series") ........................................................................................................ 1
Changes from Revision D (March 2012) to Revision E
•
Page
Added "Value Line Series" to title........................................................................................................................................... 1
Changes from Revision C (February 2012) to Revision D
Page
•
Changed product status from mixed status to production data.............................................................................................. 1
•
Deleted shading and footnote 2 from Package Information table .......................................................................................... 1
Changes from Revision B (December 2011) to Revision C
Page
•
Changed first Features bullet ................................................................................................................................................. 1
•
Deleted shading from OPA314 SOT23-5 row (DBV package) in Package Information table................................................ 1
•
Added OPA2314, OPA4314 to first two Power Supply, Quiescent current per amplifier parameter rows in Electrical
Characteristics table .............................................................................................................................................................. 8
•
Added OPA314 Power Supply, Quiescent current per amplifier parameter row to Electrical Characteristics table .............. 8
2
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SBOS563G – MAY 2011 – REVISED JUNE 2015
Changes from Revision A (August 2011) to Revision B
•
Page
Deleted shading from OPA2314 MSOP-8 row in Package Information table ........................................................................ 1
Copyright © 2011–2015, Texas Instruments Incorporated
Product Folder Links: OPA314 OPA2314 OPA4314
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3
OPA314, OPA2314, OPA4314
SBOS563G – MAY 2011 – REVISED JUNE 2015
www.ti.com
5 Pin Configuration and Functions
DCK Package
5-Pin SC70
Top View
+IN
1
V-
2
-IN
3
DBV Package
5-Pin SOT23
Top View
5
4
V+
OUT
1
V-
2
+IN
3
1
-IN A
2
+IN A
3
V-
4
Exposed
Thermal
Die Pad
on
Underside(2)
V+
4
-IN
OUT
DRB Package(1)
8-Pin DFN
Top View
OUT A
5
D or DGK Package
8-Pin SOIC or VSSOP
Top View
8
V+
7
OUT B
6
-IN B
5
+IN B
OUT A
1
8
V+
-IN A
2
7
OUT B
+IN A
3
6
-IN B
V-
4
5
+IN B
PW Package
14-Pin TSSOP
Top View
14
OUT D
13
-IN D
3
12
+IN D
V+
4
11
V-
+IN B
5
10
+IN C
-IN B
6
9
-IN C
OUT B
7
8
OUT C
OUT A
1
-IN A
2
+IN A
A
B
(1)
Pitch: 0.65 mm.
(2)
Connect thermal pad to V–. Pad size: 1.8 mm × 1.5 mm.
D
C
Pin Functions: OPA314
PIN
NAME
DBV
DCK
+IN
3
1
–IN
4
OUT
1
V+
V–
4
I/O
DESCRIPTION
I
Noninverting input
3
I
Inverting input
4
O
Output
5
5
—
Positive (highest) supply
2
2
—
Negative (lowest) supply
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Product Folder Links: OPA314 OPA2314 OPA4314
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www.ti.com
SBOS563G – MAY 2011 – REVISED JUNE 2015
Pin Functions: OPA2314
PIN
I/O
DESCRIPTION
NAME
DRB
DGK
D
+IN A
3
3
3
I
Noninverting input
+IN B
5
5
5
I
Noninverting input
–IN A
2
2
2
I
Inverting input
–IN B
6
6
6
I
Inverting input
OUT A
1
1
1
O
Output
OUT B
7
7
7
O
Output
V+
8
8
8
—
Positive (highest) supply
V–
4
4
4
—
Negative (lowest) supply
Pin Functions: OPA4314
PIN
I/O
DESCRIPTION
NAME
NO.
+IN A
3
I
Noninverting input
+IN B
5
I
Noninverting input
+IN C
10
I
Noninverting input
+IN D
12
I
Noninverting input
–IN A
2
I
Inverting input
–IN B
6
I
Inverting input
–IN C
9
I
Inverting input
–IN D
13
I
Inverting input
OUT A
1
O
Output
OUT B
7
O
Output
OUT C
8
O
Output
OUT D
14
O
Output
V+
4
—
Positive (highest) supply
V–
11
—
Negative (lowest) supply
Copyright © 2011–2015, Texas Instruments Incorporated
Product Folder Links: OPA314 OPA2314 OPA4314
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OPA314, OPA2314, OPA4314
SBOS563G – MAY 2011 – REVISED JUNE 2015
www.ti.com
6 Specifications
6.1 Absolute Maximum Ratings
Over operating free-air temperature range, unless otherwise noted. (1)
MIN
MAX
UNIT
7
V
Supply voltage
Voltage
Signal input terminals
(2)
(V–) – 0.5
(V+) + 0.5
V
–10
10
mA
Current (2)
Output short-circuit (3)
Continuous
Operating temperature, TA
mA
–40
150
–65
150
°C
Junction temperature, TJ
°C
Storage temperature, Tstg
(1)
(2)
(3)
°C
Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may
degrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyond
those specified is not supported.
Input terminals are diode-clamped to the power-supply rails. Input signals that can swing more than 0.5 V beyond the supply rails should
be current limited to 10 mA or less.
Short-circuit to ground, one amplifier per package.
6.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1)
±4000
Charged-device model (CDM), per JEDEC specification JESD22C101 (2)
±1000
Machine model (MM)
±200
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
VS
Supply voltage
TA
Ambient operating temperature
NOM
MAX
UNIT
1.8 (±0.9)
5.5 (±2.75)
V
–40
125
°C
6.4 Thermal Information: OPA314
OPA314
THERMAL METRIC (1)
DBV (SOT23)
DCK (SC70)
DRL (SOT553)
5 PINS
5 PINS
5 PINS
UNIT
RθJA
Junction-to-ambient thermal resistance
228.5
281.4
208.1
°C/W
RθJC(top)
Junction-to-case(top) thermal resistance
99.1
91.6
0.1
°C/W
RθJB
Junction-to-board thermal resistance
54.6
59.6
42.4
°C/W
ψJT
Junction-to-top characterization parameter
7.7
1.5
0.5
°C/W
ψJB
Junction-to-board characterization parameter
53.8
58.8
42.2
°C/W
(1)
6
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
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SBOS563G – MAY 2011 – REVISED JUNE 2015
6.5 Thermal Information: OPA2314
OPA2314
THERMAL METRIC (1)
D (SO)
DGK (MSOP)
DRB (DFN)
8 PINS
8 PINS
8 PINS
UNIT
191.2
53.8
°C/W
RθJA
Junction-to-ambient thermal resistance
138.4
RθJC(top)
Junction-to-case(top) thermal resistance
89.5
61.9
69.2
°C/W
RθJB
Junction-to-board thermal resistance
78.6
111.9
20.1
°C/W
ψJT
Junction-to-top characterization parameter
29.9
5.1
3.8
°C/W
ψJB
Junction-to-board characterization parameter
78.1
110.2
11.6
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
6.6 Thermal Information: OPA4314
OPA4314
THERMAL METRIC (1)
D (SOIC)
PW (TSSOP)
14 PINS
14 PINS
UNIT
RθJA
Junction-to-ambient thermal resistance
93.2
121
°C/W
RθJC(top)
Junction-to-case(top) thermal resistance
51.8
49.4
°C/W
RθJB
Junction-to-board thermal resistance
49.4
62.8
°C/W
ψJT
Junction-to-top characterization parameter
13.5
5.9
°C/W
ψJB
Junction-to-board characterization parameter
42.2
62.2
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
6.7 Electrical Characteristics
VS = 1.8 V to 5.5 V; At TA = 25 °C, RL = 10 kΩ connected to VS/2, VCM = VS/2, and VOUT = VS/2, unless otherwise noted. (1)
PARAMETER
TEST CONDITIONS
TA = 25 °C
MIN
TA = –40°C to 125°C
TYP
MAX
0.5
2.5
MIN
TYP
MAX
UNIT
OFFSET VOLTAGE
VOS
Input offset voltage
dVOS/dT
vs Temperature
PSRR
vs power supply
VCM = (VS+) – 1.3 V
VCM = (VS+) – 1.3 V
78
92
dB
Over temperature
Channel separation, DC
mV
μV/°C
1
74
At DC
dB
10
µV/V
INPUT VOLTAGE RANGE
VCM
Common-mode voltage
range
CMRR
Common-mode rejection
ratio
Over temperature
(V–) –
0.2
VS = 1.8 V to 5.5 V, (VS–) – 0.2 V < VCM <
(VS+) – 1.3 V
VS = 5.5 V, VCM = –0.2 V to 5.7 V
(2)
(V+) +
0.2
75
96
66
80
V
dB
dB
VS = 1.8 V, (VS–) – 0.2 V < VCM < (VS+) – 1.3 V
70
86
dB
VS = 5.5 V, (VS–) – 0.2 V < VCM < (VS+) – 1.3 V
73
90
dB
VS = 5.5 V, VCM = –0.2 V to 5.7 V (2)
60
dB
INPUT BIAS CURRENT
IB
Input bias current
±0.2
±10
Over temperature
IOS
pA
±600
Input offset current
±0.2
Over temperature
±10
pA
pA
±600
pA
NOISE
Input voltage noise
(peak-to-peak)
(1)
(2)
f = 0.1 Hz to 10 Hz
μVPP
5
Parameters with minimum or maximum specification limits are 100% production tested at +25ºC, unless otherwise noted. Over
temperature limits are based on characterization and statistical analysis.
Specified by design and characterization; not production tested.
Copyright © 2011–2015, Texas Instruments Incorporated
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OPA314, OPA2314, OPA4314
SBOS563G – MAY 2011 – REVISED JUNE 2015
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Electrical Characteristics (continued)
VS = 1.8 V to 5.5 V; At TA = 25 °C, RL = 10 kΩ connected to VS/2, VCM = VS/2, and VOUT = VS/2, unless otherwise noted.(1)
PARAMETER
TEST CONDITIONS
TA = 25 °C
MIN
TYP
TA = –40°C to 125°C
MAX
MIN
TYP
MAX
UNIT
f = 10 kHz
13
nV/√Hz
f = 1 kHz
14
nV/√Hz
f = 1 kHz
5
fA/√Hz
Differential
VS = 5 V
1
pF
Common-mode
VS = 5 V
5
pF
en
Input voltage noise
density
in
Input current noise
density
INPUT CAPACITANCE
CIN
OPEN-LOOP GAIN
AOL
Open-loop voltage gain
Over temperature
VS = 1.8 V, 0.2 V < VO < (V+) – 0.2 V, RL = 10
kΩ
90
115
dB
VS = 5.5 V, 0.2 V < VO < (V+) – 0.2 V, RL = 10
kΩ
100
128
dB
VS = 1.8 V, 0.5 V < VO < (V+) – 0.5 V, RL = 2
kΩ (2)
90
100
dB
VS = 5.5 V, 0.5 V < VO < (V+) – 0.5 V, RL = 2
kΩ (2)
94
110
dB
VS = 5.5 V, 0.2 V < VO < (V+) – 0.2 V, RL = 10
kΩ
90
VS = 5.5 V, 0.5 V < VO < (V+) – 0.2 V, RL = 2 kΩ
Phase margin
110
dB
100
dB
VS = 5 V, G = 1, RL = 10 kΩ
65
°
VS = 1.8 V, RL = 10 kΩ, CL = 10 pF
2.7
MHz
3
MHz
VS = 5 V, G = 1
1.5
V/μs
To 0.1%, VS = 5 V, 2-V step , G = 1
2.3
μs
To 0.01%, VS = 5 V, 2-V step , G = 1
3.1
μs
Overload recovery time
VS = 5 V, VIN × Gain > VS
5.2
μs
Total harmonic distortion
+ noise (4)
VS = 5 V, VO = 1 VRMS, G = +1, f = 1 kHz, RL =
10 kΩ
FREQUENCY RESPONSE
GBW
Gain-bandwidth product
SR
Slew rate (3)
tS
Settling time
THD+N
VS = 5 V, RL = 10 kΩ, CL = 10 pF
0.001%
OUTPUT
VO
Voltage output swing
from supply rails
Over temperature
VS = 1.8 V, RL = 10 kΩ
5
15
mV
VS = 5.5 V, RL = 10 kΩ
5
20
mV
VS = 1.8 V, RL = 2 kΩ
15
30
mV
VS = 5.5 V, RL = 2 kΩ
22
40
mV
VS = 5.5 V, RL = 10 kΩ
30
VS = 5.5 V, RL = 2 kΩ
60
mV
mV
ISC
Short-circuit current
VS = 5 V
±20
mA
RO
Open-loop output
impedance
VS = 5.5 V, f = 100 Hz
570
Ω
POWER SUPPLY
VS
IQ
Specified voltage range
Quiescent current per
amplifier
Over temperature
Power-on time
1.8
5.5
V
130
180
µA
OPA2314, OPA4314, VS = 5 V, IO = 0 mA
150
190
µA
OPA314, VS = 5 V, IO = 0 mA
150
210
OPA314, OPA2314, OPA4314, VS = 1.8 V, IO =
0 mA
VS = 5 V, IO = 0 mA
µA
220
VS = 0 V to 5 V, to 90% IQ level
44
µA
µs
TEMPERATURE
(3)
(4)
8
Specified range
–40
125
°C
Operating range
–40
150
°C
Signifies the slower value of the positive or negative slew rate.
Third-order filter; bandwidth = 80 kHz at –3 dB.
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SBOS563G – MAY 2011 – REVISED JUNE 2015
Electrical Characteristics (continued)
VS = 1.8 V to 5.5 V; At TA = 25 °C, RL = 10 kΩ connected to VS/2, VCM = VS/2, and VOUT = VS/2, unless otherwise noted.(1)
PARAMETER
TEST CONDITIONS
Storage range
TA = 25 °C
MIN
TYP
–65
TA = –40°C to 125°C
MAX
MIN
TYP
MAX
150
UNIT
°C
6.8 Typical Characteristics
Table 1. Characteristic Performance Measurements
TITLE
FIGURE
Open-Loop Gain and Phase vs Frequency
Figure 1
Open-Loop Gain vs Temperature
Figure 2
Quiescent Current vs Supply Voltage
Figure 3
Quiescent Current vs Temperature
Figure 4
Offset Voltage Production Distribution
Figure 5
Offset Voltage Drift Distribution
Figure 6
Offset Voltage vs Common-Mode Voltage (Maximum Supply)
Figure 7
Offset Voltage vs Temperature
Figure 8
CMRR and PSRR vs Frequency (RTI)
Figure 9
CMRR and PSRR vs Temperature
Figure 10
0.1-Hz to 10-Hz Input Voltage Noise (5.5 V)
Figure 11
Input Voltage Noise Spectral Density vs Frequency (1.8 V, 5.5 V)
Figure 12
Input Voltage Noise vs Common-Mode Voltage (5.5 V)
Figure 13
Input Bias and Offset Current vs Temperature
Figure 14
Open-Loop Output Impedance vs Frequency
Figure 15
Maximum Output Voltage vs Frequency and Supply Voltage
Figure 16
Output Voltage Swing vs Output Current (over Temperature)
Figure 17
Closed-Loop Gain vs Frequency, G = 1, –1, 10 (1.8 V)
Figure 18
Closed-Loop Gain vs Frequency, G = 1, –1, 10 (5.5 V)
Figure 19
Small-Signal Overshoot vs Load Capacitance
Figure 20
Small-Signal Step Response, Noninverting (1.8 V)
Figure 21
Small-Signal Step Response, Noninverting ( 5.5 V)
Figure 22
Large-Signal Step Response, Noninverting (1.8 V)
Figure 23
Large-Signal Step Response, Noninverting ( 5.5 V)
Figure 24
Positive Overload Recovery
Figure 25
Negative Overload Recovery
Figure 26
No Phase Reversal
Figure 27
Channel Separation vs Frequency (Dual)
Figure 28
THD+N vs Amplitude (G = 1, 2 kΩ, 10 kΩ)
Figure 29
THD+N vs Amplitude (G = –1, 2 kΩ, 10 kΩ)
Figure 30
THD+N vs Frequency (0.5 VRMS, G = +1, 2 kΩ, 10 kΩ)
Figure 31
EMIRR
Figure 32
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At TA = 25°C, RL = 10 kΩ connected to VS/2, VCM = VS/2, and VOUT = VS/2, unless otherwise noted.
RL = 10 kW/10 pF
VS = ±2.5 V
140
-20
10 kW, 5.5 V
100
-40
80
-60
60
-80
40
-100
20
-120
0
-140
-20
1
10
100
1k
10k
100k
1M
Phase (°)
Gain (dB)
120
0
Open-Loop Gain (dB)
140
-160
10M
130
2 kW, 5.5 V
120
10 kW, 1.8 V
110
100
-50
0
-25
Frequency (Hz)
160
170
155
160
150
140
130
120
110
100
100
125
VS = 5.5 V
150
145
140
135
130
VS = 1.8 V
125
90
80
120
1.5
2
2.5
3
3.5
4
4.5
5
5.5
6
-50
0
-25
Supply Voltage (V)
10
25
Percent of Amplifiers (%)
30
6
4
2
75
50
100
125
Figure 4. Quiescent Current vs Temperature
12
8
25
Temperature (°C)
Figure 3. Quiescent Current vs Supply
Percent of Amplifiers (%)
75
50
Figure 2. Open-Loop Gain vs Temperature
180
Quiescent Current (mA/Ch)
Quiescent Current (mA/Ch)
Figure 1. Open-Loop Gain and Phase vs Frequency
20
15
10
5
-1.4
-1.3
-1.2
-1.1
-1.0
-0.9
-0.8
-0.7
-0.6
-0.5
-0.4
-0.3
-0.2
-0.1
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
1.1
1.2
1.3
1.4
0
0
0.2
0.4
0.6
Offset Voltage (mV)
Figure 5. Offset Voltage Production Distribution
10
25
Temperature (°C)
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0.8
1
1.2
1.4
1.6
1.8
2
Offset Voltage Drift (mV/°C)
Figure 6. Offset Voltage Drift Distribution
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At TA = 25°C, RL = 10 kΩ connected to VS/2, VCM = VS/2, and VOUT = VS/2, unless otherwise noted.
1000
1500
800
1000
Offset Voltage (mV)
Offset Voltage (mV)
600
400
200
0
-200
-400
-600
-800
-2
0
-500
-1000
Typical Units
VS = ±2.75 V
-1000
-2.75
500
Typical Units
VS = ±2.75 V
-1500
-1.25
-0.5
0
0.5
1.25
2
2.75
-40 -25 -10
5
20
Common-Mode Voltage (V)
Figure 7. Offset Voltage vs Common-Mode Voltage
Common-Mode Rejection Ratio (dB),
Power-Supply Rejection Ratio (dB)
Common-Mode Rejection Ratio (dB),
Power-Supply Rejection Ratio (dB)
65
80
95
110 125
104
+PSRR
100
-PSRR
60
CMRR
40
20
0
50
Figure 8. Offset Voltage vs Temperature
120
80
35
Temperature (°C)
VS = ±2.75 V
102
100
98
CMRR
96
94
92
PSRR
90
88
86
84
10
100
1k
10k
100k
1M
-50
0
-25
Frequency (Hz)
25
50
75
100
125
Temperature (°C)
Figure 9. CMRR and PSRR vs Frequency (Referred-to-Input)
Figure 10. CMRR and PSRR vs Temperature
Voltage (0.5 mV/div)
Voltage Noise (nv/ÖHz)
100
VS = ±0.9 V
VS = ±2.75 V
10
Time (1 s/div)
10
100
1k
10k
100k
Frequency (Hz)
Figure 11. 0.1-Hz to 10-Hz Input Voltage Noise
Figure 12. Input Voltage Noise Spectral Density vs
Frequency
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At TA = 25°C, RL = 10 kΩ connected to VS/2, VCM = VS/2, and VOUT = VS/2, unless otherwise noted.
20
1000
900
18
800
Input Bias Current (pA)
Voltage Noise (nV/ÖHz)
VS = ±2.75 V
f = 1 kHz
16
14
12
700
IB
600
500
400
300
200
IOS
100
10
0
0
0.5
1
2
1.5
2.5
3
3.5
4
5
4.5
5.5
-50
-25
0
25
Common-Mode Input Voltage (V)
50
75
Figure 13. Voltage Noise vs Common-Mode Voltage
150
6
VIN = 5.5 V
VIN = 3.3 V
VIN = 1.8 V
5
10k
Voltage (VPP)
Output Impedance (W)
125
Figure 14. Input Bias and Offset Current vs Temperature
100k
VS = ±0.9 V
1k
4
3
2
1
RL = 10 kW
CL = 10 pF
VS = ±2.75 V
0
1
1
10
100
1k
10k
100k
1M
10M
10k
100k
Frequency (Hz)
1M
10M
Frequency (Hz)
Figure 15. Open-Loop Output Impedance vs Frequency
Figure 16. Maximum Output Voltage vs Frequency and
Supply Voltage
40
3
VS = 1.8 V
G = -1 V/V
G = +1 V/V
G = +10 V/V
2
20
1
Gain (dB)
Output Voltage Swing (V)
100
Temperature (°C)
+25°C
0
+125°C
-40°C
0
-1
-2
VS = ±2.75 V
-3
0
12
5
10
15
20
25
30
35
40
-20
10k
100k
1M
Output Current (mA)
Frequency (Hz)
Figure 17. Output Voltage Swing vs Output Current (Over
Temperature)
Figure 18. Closed-Loop Gain vs Frequency
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10M
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At TA = 25°C, RL = 10 kΩ connected to VS/2, VCM = VS/2, and VOUT = VS/2, unless otherwise noted.
40
70
VS = 5.5 V
G = -1 V/V
G = +1 V/V
G = +10 V/V
60
50
Gain (dB)
Overshoot (%)
20
0
40
30
20
VS = ±2.75 V
Gain = +1 V/V
RL = 10 kW
10
-20
0
10k
100k
1M
0
800
1000
1200
Figure 20. Small-Signal Overshoot vs Load Capacitance
Gain = +1
VS = ±2.75 V
RF = 10 kW
VIN
Voltage (25 mV/div)
Gain = +1
VS = ±0.9 V
RF = 10 kW
ZL = 10 pF + 10 kW
ZL = 100 pF + 10 kW
ZL = 10 pF + 10 kW
ZL = 100 pF + 10 kW
Time (1 ms/div)
Time (1 ms/div)
Figure 22. Small-Signal Pulse Response (Inverting)
2
Gain = +1
VS = ±0.9 V
RL = 10 kW
VIN
0.5
0.25
0
VOUT
1
VIN
0.5
0
-0.5
-0.5
-1
-0.75
-1.5
-1
Gain = +1
VS = ±2.75 V
RL = 10 kW
1.5
Voltage (V)
Voltage (V)
600
Figure 19. Closed-Loop Gain vs Frequency
1
-0.25
400
Capacitive Load (pF)
Figure 21. Small-Signal Pulse Response (Noninverting)
0.75
200
Frequency (Hz)
VIN
Voltage (25 mV/div)
10M
VOUT
-2
Time (1 ms/div)
Figure 23. Large-Signal Pulse Response (Noninverting)
Time (1 ms/div)
Figure 24. Large-Signal Pulse Response (Inverting)
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At TA = 25°C, RL = 10 kΩ connected to VS/2, VCM = VS/2, and VOUT = VS/2, unless otherwise noted.
3
1
0.5
Output
2
Voltage (0.5 V/div)
Voltage (0.5 V/div)
2.5
1.5
1
0.5
0
Input
0
-0.5
-1
-1.5
-2
Output
Input
-0.5
-2.5
-1
-3
0
4
2
6
8
10
12
14
0
6
8
10
Figure 25. Positive Overload Recovery
Figure 26. Negative Overload Recovery
-60
Channel Separation (dB)
VIN
VOUT
3
12
Time (2 ms/div)
4
2
Voltage (1 V/div)
4
2
Time (2 ms/div)
1
0
-1
-2
14
VS = ±2.75 V
-80
-100
-120
-3
-4
-140
0
250
500
750
1000
100
1k
Figure 27. No Phase Reversal
Total Harmonic Distortion + Noise (%)
Total Harmonic Distortion + Noise (%)
1M
10M
0.1
VS = ±2.5 V
f = 1 kHz
BW = 80 kHz
G = +1 V/V
0.01
Load = 2 kW
0.001
Load = 10 kW
0.1
1
10
0.01
Load = 2 kW
0.001
VS = ±2.5 V
f = 1 kHz
BW = 80 kHz
G = -1 V/V
0.0001
0.01
Figure 29. THD+N vs Output Amplitude (G = 1 V/V)
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Load = 10 kW
0.1
Output Amplitude (VRMS)
14
100k
Figure 28. Channel Separation vs Frequency OPA2314
0.1
0.0001
0.01
10k
Frequency (Hz)
Time (125 ms/div)
1
10
Output Amplitude (VRMS)
Figure 30. THD+N vs Output Amplitude (G = –1 V/V)
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At TA = 25°C, RL = 10 kΩ connected to VS/2, VCM = VS/2, and VOUT = VS/2, unless otherwise noted.
120
110
VS = ±2.5 V
VOUT = 0.5 VRMS
BW = 80 kHz
G = +1 V/V
0.01
Load = 2 kW
0.001
Load = 10 kW
0.0001
10
100
1k
10k
100k
EMIRR IN+ (dB)
Total Harmonic Distortion + Noise (%)
0.1
100
90
80
70
60
50
40
30
20
10
0
10M
Frequency (Hz)
Figure 31. THD+N vs Frequency
PRF = −10 dBm
VS = ±2.5 V
VCM = 0 V
100M
1G
Frequency (Hz)
10G
G001
Figure 32. Electromagnetic Interference Rejection Ratio
Referred to Noninverting Input (EMIRR IN+) vs Frequency
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7 Detailed Description
7.1 Overview
The OPA314 is a family of low-power, rail-to-rail input and output operational amplifiers specifically designed for
portable applications. These devices operate from 1.8 V to 5.5 V, are unity-gain stable, and suitable for a wide
range of general-purpose applications. The class AB output stage is capable of driving ≤ 10-kΩ loads connected
to any point between V+ and ground. The input common-mode voltage range includes both rails, and allows the
OPA314 series to be used in virtually any single-supply application. Rail-to-rail input and output swing
significantly increases dynamic range, especially in low-supply applications, and makes them ideal for driving
sampling analog-to-digital converters (ADCs).
The OPA314 features 3-MHz bandwidth and 1.5-V/μs slew rate with only 150-μA supply current per channel,
providing good AC performance at very low power consumption. DC applications are also well served with a very
low input noise voltage of 14 nV/√Hz at 1 kHz, low input bias current (0.2 pA), and an input offset voltage of
0.5 mV (typical).
7.2 Functional Block Diagram
V+
Reference
Current
VIN+
VINVBIAS1
Class AB
Control
Circuitry
VO
VBIAS2
V(Ground)
7.3 Feature Description
7.3.1 Operating Voltage
The OPA314 series operational amplifiers are fully specified and ensured for operation from 1.8 V to 5.5 V. In
addition, many specifications apply from –40°C to 125°C. Parameters that vary significantly with operating
voltages or temperature are shown in the Typical Characteristics graphs. Power-supply pins should be bypassed
with 0.01-μF ceramic capacitors.
16
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Feature Description (continued)
7.3.2 Rail-to-Rail Input
The input common-mode voltage range of the OPA314 series extends 200 mV beyond the supply rails. This
performance is achieved with a complementary input stage: an N-channel input differential pair in parallel with a
P-channel differential pair, as shown in Figure 33. The N-channel pair is active for input voltages close to the
positive rail, typically (V+) – 1.3 V to 200 mV above the positive supply, while the P-channel pair is on for inputs
from 200 mV below the negative supply to approximately (V+) – 1.3 V. There is a small transition region, typically
(V+) – 1.4 V to (V+) – 1.2 V, in which both pairs are on. This 200-mV transition region can vary up to 300 mV
with process variation. Thus, the transition region (both stages on) can range from (V+) – 1.7 V to (V+) – 1.5 V
on the low end, up to (V+) – 1.1 V to (V+) – 0.9 V on the high end. Within this transition region, PSRR, CMRR,
offset voltage, offset drift, and THD may be degraded compared to device operation outside this region.
V+
Reference
Current
VIN+
VINVBIAS1
Class AB
Control
Circuitry
VO
VBIAS2
V(Ground)
Figure 33. Simplified Schematic
7.3.3 Input and ESD Protection
The OPA314 family incorporates internal electrostatic discharge (ESD) protection circuits on all pins. In the case
of input and output pins, this protection primarily consists of current-steering diodes connected between the input
and power-supply pins. These ESD protection diodes also provide in-circuit, input overdrive protection, as long
as the current is limited to 10 mA as stated in the Absolute Maximum Ratings . Figure 34 shows how a series
input resistor may be added to the driven input to limit the input current. The added resistor contributes thermal
noise at the amplifier input and its value should be kept to a minimum in noise-sensitive applications.
V+
IOVERLOAD
10-mA max
Device
VOUT
VIN
5 kW
Figure 34. Input Current Protection
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Feature Description (continued)
7.3.4 Common-Mode Rejection Ratio (CMRR)
CMRR for the OPA314 is specified in several ways so the best match for a given application may be used; see
the Electrical Characteristics. First, the CMRR of the device in the common-mode range below the transition
region [VCM < (V+) – 1.3 V] is given. This specification is the best indicator of the capability of the device when
the application requires use of one of the differential input pairs. Second, the CMRR over the entire commonmode range is specified at (VCM = –0.2 V to 5.7 V). This last value includes the variations seen through the
transition region (see Figure 7).
7.3.5 EMI Susceptibility and Input Filtering
Operational amplifiers vary with regard to the susceptibility of the device to electromagnetic interference (EMI). If
conducted EMI enters the operational amplifier, the DC offset observed at the amplifier output may shift from its
nominal value while EMI is present. This shift is a result of signal rectification associated with the internal
semiconductor junctions. While all operational amplifier pin functions can be affected by EMI, the signal input
pins are likely to be the most susceptible. The OPA314 operational amplifier family incorporate an internal input
low-pass filter that reduces the amplifiers response to EMI. Both common-mode and differential mode filtering
are provided by this filter. The filter is designed for a cutoff frequency of approximately 80 MHz (–3 dB), with a
roll-off of 20 dB per decade.
Texas Instruments has developed the ability to accurately measure and quantify the immunity of an operational
amplifier over a broad frequency spectrum extending from 10 MHz to 6 GHz. The EMI rejection ratio (EMIRR)
metric allows operational amplifiers to be directly compared by the EMI immunity. Figure 32 illustrates the results
of this testing on the OPAx314. Detailed information can also be found in the application report, EMI Rejection
Ratio of Operational Amplifiers (SBOA128), available for download from www.ti.com.
7.3.6 Rail-to-Rail Output
Designed as a micro-power, low-noise operational amplifier, the OPA314 delivers a robust output drive capability.
A class AB output stage with common-source transistors is used to achieve full rail-to-rail output swing capability.
For resistive loads up to 10 kΩ, the output swings typically to within 5 mV of either supply rail regardless of the
power-supply voltage applied. Different load conditions change the ability of the amplifier to swing close to the
rails; refer to Figure 17.
7.3.7 Capacitive Load and Stability
The OPA314 is designed to be used in applications where driving a capacitive load is required. As with all
operational amplifiers, there may be specific instances where the OPA314 can become unstable. The particular
operational amplifiers circuit configuration, layout, gain, and output loading are some of the factors to consider
when establishing whether or not an amplifier is stable in operation. An operational amplifier in the unity-gain (+1V/V) buffer configuration that drives a capacitive load exhibits a greater tendency to be unstable than an amplifier
operated at a higher noise gain. The capacitive load, in conjunction with the operational amplifier output
resistance, creates a pole within the feedback loop that degrades the phase margin. The degradation of the
phase margin increases as the capacitive loading increases. When operating in the unity-gain configuration, the
OPA314 remains stable with a pure capacitive load up to approximately 1 nF. The equivalent series resistance
(ESR) of some very large capacitors (CL greater than 1 μF) is sufficient to alter the phase characteristics in the
feedback loop such that the amplifier remains stable. Increasing the amplifier closed-loop gain allows the
amplifier to drive increasingly larger capacitance. This increased capability is evident when observing the
overshoot response of the amplifier at higher voltage gains. See Figure 20.
One technique for increasing the capacitive load drive capability of the amplifier operating in a unity-gain
configuration is to insert a small resistor, typically 10 Ω to 20 Ω, in series with the output, as shown in Figure 35.
This resistor significantly reduces the overshoot and ringing associated with large capacitive loads. One possible
problem with this technique, however, is that a voltage divider is created with the added series resistor and any
resistor connected in parallel with the capacitive load. The voltage divider introduces a gain error at the output
that reduces the output swing.
18
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Feature Description (continued)
V+
RS
VOUT
Device
10 W to
20 W
VIN
RL
CL
Figure 35. Improving Capacitive Load Drive
7.4 Device Functional Modes
The OPA2314 device is powered on when the supply is connected. The device can be operated as a singlesupply operational amplifier or a dual-supply amplifier, depending on the application.
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8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The OPA2314 device is a low-power, rail-to-rail input and output operational amplifier specifically designed for
portable applications. The device operates from 1.8 V to 5.5 V, is unity-gain stable, and suitable for a wide range
of general-purpose applications. The class AB output stage is capable of driving ≤ 10-kΩ loads connected to any
point between V+ and ground. The input common-mode voltage range includes both rails, and allows the
OPA2314 device to be used in virtually any single-supply application. Rail-to-rail input and output swing
significantly increases dynamic range, especially in low-supply applications, and makes the device ideal for
driving sampling analog-to-digital converters (ADCs).
The OPA2314 device features a 3-MHz bandwidth and 1.5-V/μs slew rate with only 150-μA supply current per
channel, providing good AC performance at very low power consumption. DC applications are also well served
with a very-low input noise voltage of 14 nV/√Hz at 1 kHz, low-input bias current (0.2 pA), and an input offset
voltage of 0.5 mV (typical).
8.1.1 General Configurations
When receiving low-level signals, limiting the bandwidth of the incoming signals into the system is often required.
The simplest way to establish this limited bandwidth is to place an RC filter at the noninverting terminal of the
amplifier, as Figure 36 shows.
RG
RF
R1
VOUT
VIN
C1
f-3 dB =
(
RF
VOUT
= 1+
RG
VIN
((
1
1 + sR1C1
1
2pR1C1
(
Figure 36. Single-Pole Low-Pass Filter
If even more attenuation is needed, a multiple pole filter is required. The Sallen-Key filter can be used for this
task, as Figure 37 shows. For best results, the amplifier should have a bandwidth that is eight to 10 times the
filter frequency bandwidth. Failure to follow this guideline can result in phase shift of the amplifier.
20
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Application Information (continued)
C1
R1
R1 = R2 = R
C1 = C2 = C
Q = Peaking factor
(Butterworth Q = 0.707)
R2
VIN
VOUT
C2
1
2pRC
f-3 dB =
RF
RF
RG =
RG
(
2-
1
Q
(
Figure 37. Two-Pole Low-Pass Sallen-Key Filter
8.1.2 Capacitive Load and Stability
The OPA2314 device is designed to be used in applications where driving a capacitive load is required. As with
all op-amps, specific instances can occur where the OPA2314 device can become unstable. The particular opamp circuit configuration, layout, gain, and output loading are some of the factors to consider when establishing
whether or not an amplifier is stable in operation. An op-amp in the unity-gain (1 V/V) buffer configuration that
drives a capacitive load exhibits a greater tendency to be unstable than an amplifier operated at a higher noise
gain. The capacitive load, in conjunction with the op-amp output resistance, creates a pole within the feedback
loop that degrades the phase margin. The degradation of the phase margin increases as the capacitive loading
increases. When operating in the unity-gain configuration, the OPA2314 device remains stable with a pure
capacitive load up to approximately 1 nF. The equivalent series resistance (ESR) of some very large capacitors
(CL greater than 1 μF) is sufficient to alter the phase characteristics in the feedback loop such that the amplifier
remains stable. Increasing the amplifier closed-loop gain allows the amplifier to drive increasingly larger
capacitance. This increased capability is evident when observing the overshoot response of the amplifier at
higher voltage gains. See the graph, Figure 20.
One technique for increasing the capacitive load drive capability of the amplifier operating in a unity-gain
configuration is to insert a small resistor, typically 10 Ω to 20 Ω, in series with the output, as shown in Figure 38.
This resistor significantly reduces the overshoot and ringing associated with large capacitive loads. One possible
problem with this technique, however, is that a voltage divider is created with the added series resistor and any
resistor connected in parallel with the capacitive load. The voltage divider introduces a gain error at the output
that reduces the output swing.
V+
RS
VOUT
Device
10 W to
20 W
VIN
RL
CL
Figure 38. Improving Capacitive Load Drive
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8.2 Typical Application
Some applications require differential signals. Figure 39 shows a simple circuit to convert a single-ended input of
0.1 V to 2.4 V into a differential output of ±2.3 V on a single 2.7-V supply. The output range is intentionally limited
to maximize linearity. The circuit is composed of two amplifiers. One amplifier functions as a buffer and creates a
voltage, VOUT+. The second amplifier inverts the input and adds a reference voltage to generate VOUT–. Both
VOUT+ and VOUT– range from 0.1 V to 2.4 V. The difference, VDIFF, is the difference between VOUT+ and VOUT–.
This makes the differential output voltage range 2.3 V.
R2
2.7 V
R1
±
VOUT±
+
Device
R3
+
VREF
2.5 V
R4
V
VDIFF
+
2.7 V
±
VOUT+
+
Device
+
+
VIN
Figure 39. Schematic for a Single-Ended Input to Differential Output Conversion
8.2.1 Design Requirements
The design requirements are as follows:
• Supply voltage: 2.7 V
• Reference voltage: 2.5 V
• Input: 0.1 V to 2.4 V
• Output differential: ±2.3 V
• Output common-mode voltage: 1.25 V
• Small-signal bandwidth: 1 MHz
8.2.2 Detailed Design Procedure
The circuit in Figure 39 takes a single-ended input signal, VIN, and generates two output signals, VOUT+ and
VOUT– using two amplifiers and a reference voltage, VREF. VOUT+ is the output of the first amplifier and is a
buffered version of the input signal, VIN (as shown in Equation 1). VOUT– is the output of the second amplifier
which uses VREF to add an offset voltage to VIN and feedback to add inverting gain. The transfer function for
VOUT– is given in Equation 2.
VOUT VIN
(1)
V287±
22
§ R 4 · § R2 ·
R2
V5() u ¨
¸ u ¨1
¸ V,1 u
R1 ¹
R1
© R3 R4 ¹ ©
Submit Documentation Feedback
(2)
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SBOS563G – MAY 2011 – REVISED JUNE 2015
Typical Application (continued)
The differential output signal, VDIFF, is the difference between the two single-ended output signals, VOUT+ and
VOUT–. Equation 3 shows the transfer function for VDIFF. By applying the conditions that R1 = R2 and R3 = R4, the
transfer function is simplified into Equation 6. Using this configuration, the maximum input signal is equal to the
reference voltage and the maximum output of each amplifier is equal to VREF. The differential output range is 2 ×
VREF. Furthermore, the common-mode voltage is one half of VREF (see Equation 7).
V287 V287±
V',))
§ R 4 · § R2 ·
§ R ·
V,1 u ¨ 1 2 ¸ V5() u ¨
¸ u ¨1
¸
R1 ¹
R1 ¹
©
© R3 R 4 ¹ ©
(3)
VOUT
VIN
(4)
V287±
V5() V,1
(5)
VDIFF
2 u VIN VREF
VCM
§ V287 V287± ·
¨
¸
2
©
¹
(6)
1
VREF
2
(7)
8.2.2.1 Amplifier Selection
Linearity over the input range is key for good dc accuracy. The common-mode input range and output swing
limitations determine the linearity. In general, an amplifier with rail-to-rail input and output swing is required.
Bandwidth is a key concern for this design, so the OPA2314-Q1 device is selected because its bandwidth is
greater than the target of 1 MHz. The bandwidth and power ratio makes this device power efficient and the low
offset and drift ensure good accuracy for moderate precision applications.
8.2.2.2 Passive Component Selection
Because the transfer function of Vout– is heavily reliant on resistors (R1, R2, R3, and R4), use resistors with low
tolerances to maximize performance and minimize error. This design uses resistors with resistance values of
49.9 kΩ and tolerances of 0.1%. However, if the noise of the system is a key parameter, smaller resistance
values (6 kΩ or lower) can be selected to keep the overall system noise low. This ensures that the noise from the
resistors is lower than the amplifier noise.
2.50
2.50
2.00
2.00
1.50
1.50
Vout- (V)
Vout+ (V)
8.2.3 Application Curves
1.00
0.50
0.00
0.00
1.00
0.50
0.50
1.00
1.50
2.00
Input voltage (V)
Figure 40. VOUT+ vs Input Voltage
2.50
0.00
0.00
0.50
1.00
1.50
2.00
Input voltage (V)
C027
2.50
C027
Figure 41. VOUT– vs Input Voltage
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Typical Application (continued)
2.50
2.00
1.50
Vdiff (V)
1.00
0.50
0.00
-0.50
-1.00
-1.50
-2.00
-2.50
0.00
0.50
1.00
1.50
2.00
Input voltage (V)
2.50
C027
Figure 42. VDIFF vs Input Voltage
9 Power Supply Recommendations
The OPA2314-Q1 device is specified for operation from 1.8 V to 5.5 V (±0.9 V to ±2.75 V); many specifications
apply from –40°C to 125°C. The Typical Characteristics presents parameters that can exhibit significant variance
with regard to operating voltage or temperature.
CAUTION
Supply voltages larger than 7 V can permanently damage the device (see the Absolute
Maximum Ratings ).
Place 0.1-μF bypass capacitors close to the power-supply pins to reduce errors coupling in from noisy or highimpedance power supplies. For more detailed information on bypass capacitor placement, refer to the Layout
Guidelines section.
24
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SBOS563G – MAY 2011 – REVISED JUNE 2015
10 Layout
10.1 Layout Guidelines
For best operational performance of the device, use good PCB layout practices, including:
• Noise can propagate into analog circuitry through the power pins of the circuit as a whole and the
operational amplifier. Bypass capacitors are used to reduce the coupled noise by providing lowimpedance power sources local to the analog circuitry.
– Connect low-ESR, 0.1-µF ceramic bypass capacitors between each supply pin and ground, placed as
close to the device as possible. A single bypass capacitor from V+ to ground is applicable for singlesupply applications.
• Separate grounding for analog and digital portions of the circuitry is one of the simplest and most
effective methods of noise suppression. One or more layers on multilayer PCBs are usually devoted to
ground planes. A ground plane helps distribute heat and reduces EMI noise pickup. Make sure to
physically separate digital and analog grounds, paying attention to the flow of the ground current. For
more detailed information, refer to Circuit Board Layout Techniques, SLOA089.
• To reduce parasitic coupling, run the input traces as far away from the supply or output traces as
possible. If these traces cannot be kept separate, crossing the sensitive trace perpendicularly is much
better than crossing in parallel with the noisy trace.
• Place the external components as close to the device as possible. Keeping RF and RG close to the
inverting input minimizes parasitic capacitance, as shown in Figure 43.
• Keep the length of input traces as short as possible. Always remember that the input traces are the most
sensitive part of the circuit.
• Consider a driven, low-impedance guard ring around the critical traces. A guard ring can significantly
reduce leakage currents from nearby traces that are at different potentials.
10.2 Layout Example
RIN
+
VIN
VOUT
RG
RF
(Schematic Representation)
Run the input traces
as far away from
the supply lines
as possible
Place components
close to device and to
each other to reduce
parasitic errors
VS+
RF
NC
NC
±IN
V+
+IN
OUT
V±
NC
RG
GND
VIN
GND
RIN
Only needed for
dual-supply
operation
GND
VS±
(or GND for single supply)
Use low-ESR, ceramic
bypass capacitor
VOUT
Ground (GND) plane on another layer
Figure 43. Operational Amplifier Board Layout for Noninverting Configuration
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11 Device and Documentation Support
11.1 Device Support
11.1.1 Device Nomenclature
11.1.1.1 DFN Package
The OPA2314 (dual version) uses the DFN style package (also known as SON); this package is a QFN with
contacts on only two sides of the package bottom. This leadless package maximizes printed circuit board (PCB)
space and offers enhanced thermal and electrical characteristics through an exposed pad. One of the primary
advantages of the DFN package is its low, 0.9-mm height. DFN packages are physically small, have a smaller
routing area, improved thermal performance, reduced electrical parasitics, and use a pinout scheme that is
consistent with other commonly-used packages, such as SO and MSOP. Additionally, the absence of external
leads eliminates bent-lead issues.
The DFN package can easily be mounted using standard PCB assembly techniques. See Application Note,
QFN/SON PCB Attachment (SLUA271) and Application Report, Quad Flatpack No-Lead Logic Packages
(SCBA017), both available for download from www.ti.com.
NOTE
The exposed leadframe die pad on the bottom of the DFN package should be connected
to the most negative potential (V–).
11.2 Related Links
The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to sample or buy.
Table 2. Related Links
PARTS
PRODUCT FOLDER
SAMPLE & BUY
TECHNICAL
DOCUMENTS
TOOLS &
SOFTWARE
SUPPORT &
COMMUNITY
OPA314
Click here
Click here
Click here
Click here
Click here
OPA2314
Click here
Click here
Click here
Click here
Click here
OPA4314
Click here
Click here
Click here
Click here
Click here
11.3 Community Resource
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
11.4 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
11.5 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
26
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SBOS563G – MAY 2011 – REVISED JUNE 2015
11.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
Copyright © 2011–2015, Texas Instruments Incorporated
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PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
OPA2314AID
ACTIVE
SOIC
D
8
75
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
O2314
OPA2314AIDGK
ACTIVE
VSSOP
DGK
8
80
RoHS & Green
NIPDAUAG
Level-2-260C-1 YEAR
-40 to 125
OCPQ
OPA2314AIDGKR
ACTIVE
VSSOP
DGK
8
2500
RoHS & Green
NIPDAUAG
Level-2-260C-1 YEAR
-40 to 125
OCPQ
OPA2314AIDR
ACTIVE
SOIC
D
8
2500
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
O2314
OPA2314AIDRBR
ACTIVE
SON
DRB
8
3000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
QXY
OPA2314AIDRBT
ACTIVE
SON
DRB
8
250
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
QXY
OPA314AIDBVR
ACTIVE
SOT-23
DBV
5
3000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
RAZ
OPA314AIDBVT
ACTIVE
SOT-23
DBV
5
250
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
RAZ
OPA314AIDCKR
ACTIVE
SC70
DCK
5
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
SAA
OPA314AIDCKT
ACTIVE
SC70
DCK
5
250
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
SAA
OPA4314AIPW
ACTIVE
TSSOP
PW
14
90
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
OPA4314
OPA4314AIPWR
ACTIVE
TSSOP
PW
14
2000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
OPA4314
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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