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OPA2356-EP
SBOS955 – FEBRUARY 2019
OPA2356-EP 200-MHz, CMOS operational amplifier
1 Features
3 Description
•
•
•
•
•
The OPA2356-EP high-speed, voltage-feedback
CMOS operational amplifier is designed for video and
other applications requiring wide bandwidth. The
OPA2356-EP is unity-gain stable and can drive large
output currents. Differential gain is 0.02% and
differential phase is 0.05°. Quiescent current is only
8.3 mA per channel.
1
•
•
•
•
•
•
•
Unity-gain bandwidth: 450 MHz
Wide bandwidth: 200-MHz GBW
High slew rate: 360 V/µs
Low noise: 5.8 nV/√Hz
Excellent video performance:
– Differential gain: 0.02%
– Differential phase: 0.05°
– 0.1-dB gain flatness: 75 MHz
Input range includes ground
Rail-to-rail output (within 100 mV)
Low input bias current: 3 pA
Thermal shutdown
Single-supply operating range: 2.5 V to 5.5 V
Microsize packages
Supports defense, aerospace, and medical
applications:
– Controlled baseline
– Available in military (–55°C to 125°C)
temperature range
– Extended product life cycle
– Extended product-change notification
– Product traceability
The OPA2356-EP is optimized for operation on single
or dual supplies as low as 2.5 V (±1.25 V) and up to
5.5 V (±2.75 V). The common-mode input range for
the OPA2356-EP extends 100 mV below ground and
up to 1.5 V from V+. The output swing is within 100
mV of the rails, supporting wide dynamic range.
The OPA2356-EP is available in dual (VSSOP-8)
versions. These versions feature completely
independent circuitry for lowest crosstalk and
freedom from interaction. The OPA2356-EP are
specified over the extended –55°C to 125°C range.
Device Information(1)
PART NUMBER
OPA2356MDGKREP
OPA2356MDGKTEP
Video processing
Optical networking, tunable lasers
Photodiode transimpedance amplifiers
Active filters
High-speed integrators
Analog-to-digital converter (ADC) input buffers
Digital-to-analog converter (DAC) output amplifiers
Communications
VSSOP (8)
BODY SIZE (NOM)
3.00 mm × 3.00 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Simplified Schematic
2 Applications
•
•
•
•
•
•
•
•
PACKAGE
V+
–VIN
Device
Out
+VIN
V–
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
OPA2356-EP
SBOS955 – FEBRUARY 2019
www.ti.com
Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
4
6.1
6.2
6.3
6.4
6.5
6.6
4
4
4
4
5
7
Absolute Maximum Ratings ......................................
ESD Ratings..............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics...........................................
Typical Characteristics ..............................................
7.4 Device Functional Modes........................................ 13
8
Application and Implementation ........................ 14
8.1 Application Information............................................ 14
8.2 Typical Applications ................................................ 14
9 Power Supply Recommendations...................... 19
10 Layout................................................................... 20
10.1 Layout Guidelines ................................................. 20
10.2 Layout Example .................................................... 20
11 Device and Documentation Support ................. 21
11.1
11.2
11.3
11.4
11.5
11.6
Detailed Description ............................................ 12
7.1 Overview ................................................................. 12
7.2 Functional Block Diagram ....................................... 12
7.3 Feature Description................................................. 13
Documentation Support ........................................
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
21
21
21
21
21
21
12 Mechanical, Packaging, and Orderable
Information ........................................................... 22
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
2
DATE
REVISION
NOTES
February 2019
*
Initial release.
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5 Pin Configuration and Functions
DGK Package
8-Pin VSSOP
Top View
Out A 1
-In A 2
8
V+
7
Out B
6
-In B
5
+In B
A
+In A 3
B
V-
4
NOTE: NC means no internal connection.
Pin Functions
PIN
NAME
NO.
I/O
DESCRIPTION
–In A
2
I
Inverting input pin, channel A.
–In B
6
I
Inverting input pin, channel B.
+In A
3
I
Noninverting input pin, channel A.
+In B
5
I
Noninverting input pin, channel B.
Out A
1
O
Output pin, channel A.
Out B
7
O
Output pin, channel B.
V–
4
—
Negative power supply.
V+
8
—
Positive power supply.
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SBOS955 – FEBRUARY 2019
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
MIN
VS
MAX
UNIT
7.5
V
Supply voltage, V+ to V–
Signal input pins, voltage
(2)
(V–) – 0.5
(V+) + 0.5
V
10
mA
150
°C
160
°C
150
°C
Signal input pins, current (2)
Output short-circuit (3)
TA
Operating temperature
TJ
Junction temperature
Tstg
Storage temperature
(1)
(2)
(3)
Continuous
–55
–65
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
Input terminals are diode-clamped to the power-supply rails. Input signals that can swing more than 0.5 V beyond the supply rails should
be current limited to 10 mA or less.
Short-circuit to ground one amplifier per package.
6.2 ESD Ratings
VALUE
V(ESD)
(1)
Electrostatic discharge
Human-body model (HBM), per AEC Q100-002 (1)
±2000
Charged-device model (CDM), per AEC Q100-011
±1500
UNIT
V
AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
MAX
VS
Supply voltage, V– to V+
2.7
5.5
UNIT
V
TA
Operating free-air temperature
–55
125
°C
6.4 Thermal Information
OPA2356-EP
THERMAL METRIC (1)
DGK (VSSOP)
UNIT
8 PINS
RθJA
171.4
°C/W
RθJC(top) Junction-to-case (top) thermal resistance
60.2
°C/W
RθJB
Junction-to-board thermal resistance
92.5
°C/W
ψJT
Junction-to-top characterization parameter
7.3
°C/W
ψJB
Junction-to-board characterization parameter
90.9
°C/W
(1)
4
Junction-to-ambient thermal resistance
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
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SBOS955 – FEBRUARY 2019
6.5 Electrical Characteristics
at TA = –55°C to 125°C, RF = 604 Ω, and RL = 150 Ω connected to VS / 2 (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
OFFSET VOLTAGE
VS = 5 V
±2
±9
VOS
Input offset voltage
ΔVOS/ΔT
Offset voltage drift over temperature
TA = –55°C to 125°C
±7
Offset voltage drift vs power supply
VS = 2.7 V to 5.5 V,
VCM = VS / 2 – 0.15 V
±80
±350
µV/V
3
±50
pA
±1
±50
pA
PSRR
TA = –55°C to 125°C
mV
±15
µV/°C
INPUT BIAS CURRENT
IB
Input bias current
IOS
Input offset current
NOISE
Vn
Input voltage noise density
f = 1 MHz
5.8
nV/√Hz
In
Current noise density
f = 1 MHz
50
fA/√Hz
INPUT VOLTAGE RANGE
VCM
CMRR
Input common-mode voltage range
Input common-mode rejection ratio
(V–) – 0.1
VS = 5.5 V, –0.1 V < VCM < 4 V
66
TA = –55°C to 125°C
66
(V+) – 1.5
V
80
dB
INPUT IMPEDANCE
Differential input impedance
1013 || 1.5
Ω || pF
Common-mode input impedance
1013 || 1.5
Ω || pF
OPEN-LOOP GAIN
VS = 5 V, 0.4 V < VO < 4.6 V, TA = –55°C
to 125°C
Open-loop gain
80
dB
FREQUENCY RESPONSE
G = 1, VO = 100 mVp-p, RF = 0 Ω
450
G = 2, VO = 100 mVp-p, RL = 50 Ω
100
G = 2, VO = 100 mVp-p, RL = 150 Ω
170
f–3dB
Small-signal bandwidth
G = 2, VO = 100 mVp-p, RL = 1 kΩ
200
GBW
Gain-bandwidth product
G = 10, RL = 1 kΩ
200
MHz
f0.1dB
Bandwidth for 0.1-dB gain flatness
G = 2, VO = 100 mVp-p, RF = 560 Ω
75
MHz
SR
Slew rate
VS = 5 V, G = 2, 4-V output step
G = 2, VO = 200 mVp-p, 10% to 90%
Rise and fall times
Settling time
G = 2, VO = 2 Vp-p, 10% to 90%
0.1%
0.01%
Overload recovery time
Harmonic distortion
VS = 5 V, G = 2, 2-V output step
VIN × Gain = VS
Second
harmonic
Third harmonic
G = 2, f = 1 MHz, VO = 2 Vp-p,
RL = 200 Ω
MHz
300
–360
2.4
8
30
120
8
–81
V/µs
ns
ns
ns
dBc
–93
Differential gain error
NTSC, RL = 150 Ω
0.02%
Differential phase error
NTSC, RL = 150 Ω
0.05
°
Channel-to-channel crosstalk
f = 5 MHz
–90
dB
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Electrical Characteristics (continued)
at TA = –55°C to 125°C, RF = 604 Ω, and RL = 150 Ω connected to VS / 2 (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
VS = 5 V, RL = 150 Ω, AOL > 84 dB
0.2
0.3
VS = 5 V, RL = 1 kΩ
0.1
IO = ±100 mA
0.8
UNIT
OUTPUT
Voltage output swing from rail
IO
IO
Continuous output current (1)
Peak output current (1)
V
1
±60
VS = 5 V
VS = 3 V
mA
±100
mA
±80
250
Short-circuit current
mA
–200
Closed-loop output impedance
Ω
0.02
POWER SUPPLY
IQ
Quiescent current (per amplifier)
VS = 5 V, IO = 0 V
8.3
TA = –55°C to 125°C
11
14
mA
THERMAL SHUTDOWN
Junction temperature
(1)
6
Shutdown
160
Reset from shutdown
140
°C
See Figure 20.
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6.6 Typical Characteristics
at TA = –55°C to 125°C, VS = 5 V, G = 2, RF = 604 Ω, and RL = 150 Ω connected to VS / 2 (unless otherwise noted)
3
6
VO = 0.1 Vp-p
0
Normalized Gain (dB)
3
Normalized Gain (dB)
VO = 0.1 Vp-p
G = +1
RF = 0
0
-3
G = +2
-6
G = +5
-9
G = -1
-3
G = -5
G = -2
-6
G = -10
-9
G = +10
-12
-12
-15
100k
1M
10M
Frequency (Hz)
100M
-15
100k
1G
Figure 1. Noninverting Small-Signal Frequency Response
100M
1G
Output Voltage (500 mV/div)
G = +2
Time (20 ns/div)
Time (20 ns/div)
Figure 3. Noninverting Small-Signal Step Response
Figure 4. Noninverting Large-Signal Step Response
0.5
VO = 0.1 Vp-p
CL = 0 pF
RF = 604 W
0.3
0.2
0.1
0
-0.1
RF = 560 W
-0.2
-0.3
RF = 500 W
-0.4
Harmonic Distortion (dBc)
–50
0.4
Normalized Gain (dB)
10M
Frequency (Hz)
Figure 2. Inverting Small-Signal Frequency Response
G = +2
Output Voltage (50 mV/div)
1M
f = 1 MHz
RL = 200 Ω
–60
–70
2nd Harmonic
–80
3rd Harmonic
–90
–100
-0.5
1
10
Frequency (MHz)
Figure 5. 0.1-dB Gain Flatness for Various RF
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100
0
1
2
Output Voltage (Vp-p)
3
4
Figure 6. Harmonic Distortion vs Output Voltage
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Typical Characteristics (continued)
at TA = –55°C to 125°C, VS = 5 V, G = 2, RF = 604 Ω, and RL = 150 Ω connected to VS / 2 (unless otherwise noted)
-50
VO = 2 Vp-p
f = 1 MHz
RL = 200 W
-60
Harmonic Distortion (dBc)
Harmonic Distortion (dBc)
-50
-70
2nd Harmonic
-80
3rd Harmonic
-90
-100
VO = 2 Vp-p
f = 1 MHz
RL = 200 W
-60
-70
2nd Harmonic
-80
3rd Harmonic
-90
-100
1
10
1
10
Gain (V/V)
Gain (V/V)
Figure 7. Harmonic Distortion vs Noninverting Gain
Figure 8. Harmonic Distortion vs Inverting Gain
-50
-50
VO = 2 Vp-p
f = 1 MHz
-60
Harmonic Distortion (dBc)
Harmonic Distortion (dBc)
VO = 2 Vp-p
RL = 200 W
2nd Harmonic
-70
-80
3rd Harmonic
-90
-60
-70
-80
2nd Harmonic
-90
3rd Harmonic
-100
100k
-100
1M
Frequency (Hz)
10M
100
1k
RL (W)
Figure 9. Harmonic Distortion vs Frequency
Figure 10. Harmonic Distortion vs Load Resistance
3
10k
RL = 10 kΩ
1k
Normalized Gain (dB)
Voltage Noise (nV/√Hz),
Current Noise (fA/√Hz)
0
Current Noise
Voltage Noise
100
10
CL = 0 pF
VO = 0.1 Vp-p
-3
RL = 50 Ω
-6
RL = 150 Ω
-9
RL = 1 kΩ
-12
1
10
100
1k
10k
100k
1M
10M
Frequency (Hz)
Figure 11. Input Voltage and Current Noise
Spectral Density vs Frequency
8
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100M
-15
100k
1M
10M
Frequency (Hz)
100M
1G
Figure 12. Frequency Response for Various RL
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Typical Characteristics (continued)
at TA = –55°C to 125°C, VS = 5 V, G = 2, RF = 604 Ω, and RL = 150 Ω connected to VS / 2 (unless otherwise noted)
9
120
CL = 100 pF
RS = 0 Ω
VO = 0.1 Vp-p
6
Normalized Gain (dB)
100
CL = 47 pF
3
RS (Ω)
0
-3
80
60
VIN
CL = 5.6 pF
RS
VO
Device
-6
40
CL
1 kΩ
604 Ω
-9
20
0
-15
100k
1M
10M
Frequency (Hz)
100M
1G
1
Figure 13. Frequency Response for Various CL
3
RS
Device
-9
604 Ω
VO
CL
+PSRR
70
60
CMRR
50
40
30
20
(1 kΩ is
Optional)
604 Ω
-12
CL = 47 pF
RS = 36 Ω
1 kΩ
-PSRR
80
CMRR, PSRR (dB)
Normalized Gain (dB)
90
-3
VIN
10
0
-15
1M
10M
100M
Frequency (Hz)
1G
10k
Figure 15. Frequency Response vs Capacitive Load
100k
1M
10M
Frequency (Hz)
100M
1G
Figure 16. Common-Mode Rejection Ratio and
Power-Supply Rejection Ratio vs Frequency
0.40
180
160
0.35
RL = 1k Ω
140
120
dG/dP (%/degrees)
Open-Loop Phase (degrees)
Open-Loop Gain (dB)
100
Figure 14. Recommended RS vs Capacitive Load
CL = 5.6 pF
RS = 80 Ω
CL = 100 pF
RS = 24 Ω
-6
10
Capacitive Load (pF)
100
G = +2
VO = 0.1 Vp-p
0
(1 kΩ is
Optional)
604 Ω
-12
Phase
100
80
60
RL = 150 Ω
40
Gain
20
0.30
0.25
0.20
dP
0.15
0.10
dG
0.05
0
0
-20
1k
10k
100k
1M
10M
Frequency (Hz)
100M
Figure 17. Open-Loop Gain and Phase
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1G
1
2
3
Number of 150 Loads
4
Figure 18. Composite Video Differential Gain and Phase
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Typical Characteristics (continued)
at TA = –55°C to 125°C, VS = 5 V, G = 2, RF = 604 Ω, and RL = 150 Ω connected to VS / 2 (unless otherwise noted)
10n
3
-55ºC
Output Voltage (V)
Input Bias Current (pA)
25ºC
1n
100
10
2
125ºC
Continuous currents above
60 mA are not recommended.
125ºC
1
-55ºC
25ºC
1
0
-55
-35
-15
5
25
45
65
Temperature (ºC)
85
105 125 135
0
30
60
90
Output Current (mA)
120
150
VS = 3 V
Figure 19. Input Bias Current vs Temperature
Figure 20. Output Voltage Swing vs Output Current
14
5
25°C
–55°C
12
4
10
Output Voltage (V)
Supply Current (mA)
VS = 5.5 V
8
6
VS = 3 V
VS = 2.5 V
4
VS = 5 V
125°C
3
Continuous currents above
60 mA are not recommended.
2
125°C
1
2
–55°C
25°C
0
0
–55
–35
–15
5
25
45
65
Temperature (°C)
85
105 125 135
0
50
100
150
Output Current (mA)
200
250
VS = 5 V
Figure 21. Supply Current vs Temperature
Figure 22. Output Voltage Swing vs Output Current
6
100
10
Output Voltage (Vp-p)
Output Impedance (Ω)
VS = 5.5 V
5
1
Device
0.1
604 Ω
ZO
0.01
3
VS = 2.7 V
2
1
604 Ω
0
0.001
10k
100k
1M
10M
Frequency (Hz)
100M
1G
Figure 23. Closed-Loop Output Impedance vs Frequency
10
Maximum Output
Voltage Without
Slew-Rate
Induced Distortion
4
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1
10
Frequency (MHz)
100
Figure 24. Maximum Output Voltage vs Frequency
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Typical Characteristics (continued)
at TA = –55°C to 125°C, VS = 5 V, G = 2, RF = 604 Ω, and RL = 150 Ω connected to VS / 2 (unless otherwise noted)
0.2
110
VO = 2 Vp-p
RL = 1 kΩ
100
Open-Loop Gain (dB)
Output Error (%)
0.1
0
–0.1
–0.2
90
RL = 150 Ω
80
70
–0.3
–0.4
60
0
5
10
15
20
25
30
Time (ns)
35
40
45
50
–55
Figure 25. Output Settling Time to 0.1%
–35
–15
25
45
65
Temperature (°C)
85
105 125 135
Figure 26. Open-Loop Gain vs Temperature
20
100
18
Power-Supply Rejection Ratio
16
90
CMRR, PSRR (dB)
Percent of Amplifiers (%)
5
14
12
10
8
6
4
80
Common-Mode Rejection Ratio
70
60
2
0
50
–9 –8 –7 –6 –5 –4 –3 –2 –1 0 1 2 3 4 5 6 7 8 9
Offset Voltage (mV)
–55
Figure 27. Offset Voltage Production Distribution
–35
–15
5
25
45
65
Temperature (°C)
85
105 125 135
Figure 28. Common-Mode Rejection Ratio and
Power-Supply Rejection Ratio vs Temperature
Crosstalk, Input-Referred (dB)
0
-20
-40
-60
-80
OPA2356-EP
-100
-120
100k
1M
10M
100M
Frequency (Hz)
Figure 29. Channel-to-Channel Crosstalk
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7 Detailed Description
7.1 Overview
The OPA2356-EP is a CMOS, high-speed, voltage feedback, operational amplifier designed for video and other
general-purpose applications. The OPA2356-EP is available as a dual op amp.
The amplifier features a 200-MHz gain bandwidth and 360-V/µs slew rate, but is unity-gain stable and can be
operated as a 1-V/V voltage follower.
The OPA2356-EP input common-mode voltage range includes ground, allowing the amplifier to be used in
virtually any single-supply application up to a supply voltage of 5.5 V.
7.2 Functional Block Diagram
V+
Reference
Current
VIN+
VIN±
VBIAS1
Class AB
Control
Circuitry
VO
VBIAS2
V±
(Ground)
12
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7.3 Feature Description
7.3.1 Operating Voltage
The OPA2356-EP is specified over a power-supply range of 2.7 V to 5.5 V (±1.35 V to ±2.75 V). However, the
supply voltage may range from 2.5 V to 5.5 V (±1.25 V to ±2.75 V). Supply voltages higher than 7.5 V (absolute
maximum) can permanently damage the amplifier.
Parameters that vary significantly over supply voltage or temperature are shown in the Typical Characteristics
section of this data sheet.
7.3.2 Output Drive
The output stage of the OPA2356-EP is capable of driving a standard back-terminated 75-Ω video cable. A backterminated transmission line does not exhibit a capacitive load to its driver. A properly back-terminated 75-Ω
cable does not appear as capacitance; the cable presents only a 150-Ω resistive load to the OPA2356-EP
output.
The output stage can supply high short-circuit current (typically over 200 mA). Therefore, an on-chip thermal
shutdown circuit is provided to protect the OPA2356-EP from dangerously high junction temperatures. At 160°C,
the protection circuit shuts down the amplifier. Normal operation resumes when the junction temperature cools to
below 140°C.
NOTE
TI does not recommend running a continuous dc current in excess of ±60 mA. See
Figure 20 in the Typical Characteristics section.
7.4 Device Functional Modes
The OPA2356-EP is powered on when the supply is connected. The device can operate as a single-supply
operational amplifier or dual-supply amplifier depending on the application. The device can also be used with
asymmetrical supplies as long as the differential voltage (V– to V+) is at least 1.8 V and no greater than 5.5 V
(for example, V– is set to –3.5 V and V+ is set to 1.5 V).
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8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The OPA2356-EP is a CMOS, high-speed, voltage-feedback, operational amplifier (op amp) designed for
general-purpose applications.
The amplifier features a 200-MHz gain bandwidth and 300-V/μs slew rate, but the device is unity-gain stable and
operates as a 1-V/V voltage follower.
The input common-mode voltage range of the device includes ground, which allows the OPA2356-EP to be used
in virtually any single-supply application up to a supply voltage of 5.5 V.
8.2 Typical Applications
8.2.1 Transimpedance Amplifier
Wide gain bandwidth, low input bias current, low input voltage, and current noise make the OPA2356-EP a
preferred wideband photodiode transimpedance amplifier. Low-voltage noise is important because photodiode
capacitance causes the effective noise gain of the circuit to increase at high frequency.
The key elements to a transimpedance design, as shown in Figure 30, are the expected diode capacitance
(C(D)), which must include the parasitic input common-mode and differential-mode input capacitance (4 pF + 5
pF), the desired transimpedance gain (R(FB)), and the gain-bandwidth (GBW) for the OPA2356-EP (20 MHz).
With these three variables set, the feedback capacitor value (C(FB)) is set to control the frequency response. C(FB)
includes the stray capacitance of R(FB), which is 0.2 pF for a typical surface-mount resistor.
C
(1)
(F)
< 1 pF
R (F)
10 M
V(V+)
l
C
(D)
V
(1)
V
Device
O
(V±)
C(FB) is optional to prevent gain peaking. C(FB) includes the stray capacitance of R(FB).
Figure 30. Dual-Supply Transimpedance Amplifier
8.2.1.1 Design Requirements
PARAMETER
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VALUE
Supply voltage V(V+)
2.5 V
Supply voltage V(V–)
–2.5 V
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8.2.1.2 Detailed Design Procedure
8.2.1.2.1 Custom Design With WEBENCH® Tools
Click here to create a custom design using the OPA2356 device with the WEBENCH® Power Designer.
1. Start by entering the input voltage (VIN), output voltage (VOUT), and output current (IOUT) requirements.
2. Optimize the design for key parameters such as efficiency, footprint, and cost using the optimizer dial.
3. Compare the generated design with other possible solutions from Texas Instruments.
The WEBENCH Power Designer provides a customized schematic along with a list of materials with real-time
pricing and component availability.
In most cases, these actions are available:
• Run electrical simulations to see important waveforms and circuit performance
• Run thermal simulations to understand board thermal performance
• Export customized schematic and layout into popular CAD formats
• Print PDF reports for the design, and share the design with colleagues
Get more information about WEBENCH tools at www.ti.com/WEBENCH.
8.2.1.2.2 OPA2356-EP Design Procedure
To achieve a maximally-flat, second-order Butterworth frequency response, the feedback pole must be set to:
1
=
2 ´ p ´ R(FB) ´ C(FB)
GBW
4 ´ p ´ R(FB) ´ C(D)
(1)
Use Equation 2 to calculate the bandwidth.
ƒ(–3 dB) =
GBW
2 ´ p ´ R(FB) ´ C(D)
(2)
For single-supply applications, the +INx input can be biased with a positive DC voltage to allow the output to
reach true zero when the photodiode is not exposed to any light, and respond without the added delay that
results from coming out of the negative rail; this configuration is shown in Figure 31. This bias voltage appears
across the photodiode, providing a reverse bias for faster operation.
0.5 pF
100 k
±
Device
VOUT
+
13.7 k
SFH213
1 F
280
5V
Figure 31. Single-Supply Transimpedance Amplifier
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For additional information, see the Compensate transimpedance amplifiers intuitively application report.
8.2.1.2.2.1 Optimizing the Transimpedance Circuit
To achieve the best performance, select components according to the following guidelines:
1. For lowest noise, select R(FB) to create the total required gain. Using a lower value for R(FB) and adding gain
after the transimpedance amplifier generally produces poorer noise performance. The noise produced by
R(FB) increases with the square-root of R(FB), whereas the signal increases linearly. Therefore, signal-to-noise
ratio improves when all the required gain is placed in the transimpedance stage.
2. Minimize photodiode capacitance and stray capacitance at the summing junction (inverting input). This
capacitance causes the voltage noise of the op amp to amplify (increasing amplification at high frequency).
Using a low-noise voltage source to reverse-bias a photodiode can significantly reduce the capacitance.
Smaller photodiodes have lower capacitance. Use optics to concentrate light on a small photodiode.
3. Noise increases with increased bandwidth. Limit the circuit bandwidth to only that required. Use a capacitor
across the R(FB) to limit bandwidth, even if not required for stability.
4. Circuit board leakage can degrade the performance of an otherwise well-designed amplifier. Clean the circuit
board carefully. A circuit board guard trace that encircles the summing junction and is driven at the same
voltage can help control leakage.
For additional information, see the Noise analysis of FET transimpedance amplifiers and Noise analysis for highspeed op amps application reports.
8.2.1.3 Application Curve
105
100
Gain (dB, V/A)
95
90
85
80
75
70
65
60
1000
10000
100000
1000000
Frequency (Hz)
1E+7
5E+7
D001
–3-dB bandwidth is 4.56 MHz
Figure 32. AC Transfer Function
8.2.2 High-Impedance Sensor Interface
Many sensors have high source impedances that may range up to 10 MΩ, or even higher. The output signal of
sensors often must be amplified or otherwise conditioned by means of an amplifier. The input bias current of this
amplifier can load the sensor output and cause a voltage drop across the source resistance, as shown in
Figure 33, where (V(+INx) = VS – I(BIAS) × R(S)). The last term, I(BIAS) × R(S), shows the voltage drop across R(S). To
prevent errors introduced to the system as a result of this voltage, an op amp with very low input bias current
must be used with high impedance sensors. This low current keeps the error contribution by I(BIAS) × R(S) less
than the input voltage noise of the amplifier, so that the input voltage noise does not become the dominant noise
factor. The OPA2356-EP op amp features very low input bias current (typically 200 fA) and is therefore a
preferred choice for such applications.
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R(S)
100 kΩ
IIB
V(+INx)
V(V+)
Device
V(V–)
VO
R(F)
R(G)
Figure 33. Noise as a Result of I(BIAS)
8.2.3 Driving ADCs
The OPA2356-EP op amps are designed for driving sampling analog-to-digital converters (ADCs) with sampling
speeds up to 1 MSPS. The zero-crossover distortion input stage topology allows the OPA2356-EP to drive ADCs
without degradation of differential linearity and THD.
The OPA2356-EP can be used to buffer the ADC switched input capacitance and resulting charge injection while
providing signal gain. Figure 34 shows the OPA2356-EP configured to drive the ADS8326.
5V
C1
100 nF
V
5V
(1)
R1
100
(V+)
+INx
OPA2356-EP
(1)
V
V
C3
1 nF
(V±)
±INx
ADS8326
16-Bit
250 kSPS
I
0 V to 4.096 V
REF IN
(2)
5V
Optional
R2
50 k
SD1
BAS40
±5 V
C2
100 nF
REF3240
4.096 V
C4
100 nF
(1)
Suggested value; may require adjustment based on specific application.
(2)
Single-supply applications lose a small number of ADC codes near ground as a result of op amp output swing
limitation. If a negative power supply is available, this simple circuit creates a –0.3-V supply to allow output swing to
true ground potential.
Figure 34. Driving the ADS8326
8.2.4 Active Filter
The OPA2356-EP is designed for active filter applications that require a wide bandwidth, fast slew rate, lownoise, single-supply operational amplifier. Figure 35 depicts a 500-kHz, second-order, low-pass filter using the
multiple-feedback (MFB) topology. The components are selected to provide a maximally-flat Butterworth
response. Beyond the cutoff frequency, roll-off is –40 dB/dec. The Butterworth response is preferred for
applications requiring predictable gain characteristics, such as the anti-aliasing filter used in front of an ADC.
One point to observe when considering the MFB filter is that the output is inverted, relative to the input. If this
inversion is not required, or not desired, a noninverting output can be achieved through one of the following
options:
1. Adding an inverting amplifier,
2. Adding an additional second-order MFB stage,
3. Using a noninverting filter topology, such as the Sallen-Key (see Figure 36).
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MFB and Sallen-Key, low-pass and high-pass filter synthesis is quickly accomplished using TI’s FilterPro™
program. This software is available as a free download at www.ti.com.
R3
549 Ω
C2
150 pF
R1
549 Ω
R2
1.24 kΩ
V(V+)
VI
VO
Device
C1
1 nF
V(V–)
Figure 35. Second-Order Butterworth 500-kHz Low-Pass Filter
220 pF
1.8 kΩ
19.5 kΩ
V(V+)
150 kΩ
VI = 1 VRMS
3.3 nF
47 pF
Device
VO
V(V–)
Figure 36. OPA2356-EP Configured as a Three-Pole, 20-kHz, Sallen-Key Filter
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9 Power Supply Recommendations
The OPA2356-EP is specified for operation from 2.7 to 5.5 V (±1.35 to ±2.75 V); many specifications apply from
–55°C to 125°C. Parameters that can exhibit significant variance with regard to operating voltage or temperature
are shown in the Typical Characteristics section.
Place 0.1-μF bypass capacitors close to the power-supply pins to reduce errors coupling in from noisy or highimpedance power supplies. For more detailed information on bypass capacitor placement, see the Layout
Guidelines section.
Power dissipation depends on power-supply voltage, signal, and load conditions. With DC signals, power
dissipation is equal to the product of output current times the voltage across the conducting output transistor,
VS – VO. Minimize power dissipation by using the lowest possible power-supply voltage required to ensure the
required output voltage swing.
For resistive loads, the maximum power dissipation occurs at a DC output voltage of one-half the power-supply
voltage. Dissipation with AC signals is lower.
Any tendency to activate the thermal protection circuit indicates excessive power dissipation or an inadequate
heat sink. For reliable operation, limit junction temperature to 150°C maximum. To estimate the margin of safety
in a complete design, increase the ambient temperature to trigger the thermal protection at 160°C. The thermal
protection must trigger more than 35°C above the maximum expected ambient condition of the application.
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10 Layout
10.1 Layout Guidelines
Good high-frequency PC board layout techniques should be employed for the OPA2356-EP. Generous use of
ground planes, short direct signal traces, and a suitable bypass capacitor located at the V+ pin assure clean,
stable operation. Large areas of copper also provide a means of dissipating heat that is generated within the
amplifier in normal operation.
Sockets are not recommended for use with any high-speed amplifier.
A 10-µF ceramic bypass capacitor is the minimum recommended value; adding a 1-µF or larger tantalum
capacitor in parallel can be beneficial when driving a low-resistance load. Providing adequate bypass
capacitance is essential to achieving very low harmonic and intermodulation distortion.
10.2 Layout Example
Place output resistors close
to output pins (pin 1 and 7) to
minimize parasitic capacitance.
1
Place bypass capacitors
close to power pins.
8
2
7
Place an input resistor close to pin 2
and 6 to minimize stray capacitance.
A
3
6
B
4
5
Noninverting inputs (pin 3 and 5)
terminated in 50 Ÿ.
Place feedback resistor on the bottom of
PCB between positive supply pin (8) and
inverting input pins (2, 6).
Place bypass capacitors
close to power pins.
Remove GND and power plane
under pins 1, 2, 7, and 6 to
minimize stray PCB capacitance.
Ground and power plane exist on inner layers.
Ground and power plane removed from inner layers.
Figure 37. Example Layout
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11 Device and Documentation Support
11.1 Documentation Support
11.1.1 Related Documentation
For related documentation see the following:
• Texas Instruments, Compensate transimpedance amplifiers intuitively application report
• Texas Instruments, Noise analysis of FET transimpedance amplifiers application report
• Texas Instruments, Noise analysis for high-speed op amps application report
• Texas Instruments, FilterPro™ user's guide
11.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
11.3 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
11.4 Trademarks
E2E is a trademark of Texas Instruments.
FilterPro is a trademark of Texas Instruments Incorporated.
All other trademarks are the property of their respective owners.
11.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
11.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
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12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
OPA2356MDGKREP
ACTIVE
VSSOP
DGK
8
2500
RoHS & Green
NIPDAUAG
Level-3-260C-168 HR
-55 to 125
AYIH
OPA2356MDGKTEP
ACTIVE
VSSOP
DGK
8
250
RoHS & Green
NIPDAUAG
Level-3-260C-168 HR
-55 to 125
AYIH
V62/18609-01XE
ACTIVE
VSSOP
DGK
8
250
RoHS & Green
NIPDAUAG
Level-3-260C-168 HR
-55 to 125
AYIH
V62/18609-01XE-R
ACTIVE
VSSOP
DGK
8
2500
RoHS & Green
NIPDAUAG
Level-3-260C-168 HR
-55 to 125
AYIH
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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