OPA2613IDTJR

OPA2613 SBOS249H − JUNE 2003 − REVISED AUGUST 2008 Dual, Wideband, High Output Current, Operational Amplifier with Current Limit FEATURES D D D D D D D APPLICATIONS D D D D D D D LOW INPUT NOISE VOLTAGE: 1.8nV/√Hz HIGH UNITY-GAIN BANDWIDTH: 230MHz HIGH GAIN BANDWIDTH PRODUCT: 125MHz HIGH OUTPUT CURRENT: 350mA LOW INPUT OFFSET VOLTAGE: ±0.2mV FLEXIBLE SUPPLY RANGE: Single +5V to +12V Operation Dual ±2.5V to ±6V Operation LOW SUPPLY CURRENT: 6.0mA/ch xDSL DIFFERENTIAL LINE DRIVERS 16-BIT ADC DRIVER LOW NOISE PLL INTEGRATORS TRANSIMPEDANCE AMPLIFIERS PRECISION BASEBAND I/Q AMPLIFIERS ACTIVE FILTERS TS613 IMPROVED REPLACEMENT OPA2613 RELATED PRODUCTS DESCRIPTION FEATURES The OPA2613 offers very low 1.8nV√Hz input noise in a wideband, unity-gain stable, voltage-feedback architecture. Intended for xDSL driver applications, the OPA2613 also supports this low input noise with exceptionally low harmonic distortion, particularly in differential configurations. Adequate output current is provided to drive the potentially heavy load of a twisted-pair line. Harmonic distortion for a 2VPP differential output operating from +5V to +12V supplies is ≤ −95dBc through 1MHz input frequencies. Operating on a low 6.0mA/ch supply current, the OPA2613 can satisfy most xDSL driver requirements over a wide range of possible supply voltagefrom a single +5V condition, to ±5V, on up to a single +12V design. General-purpose applications on a single +5V supply will benefit from the high input and output voltage swing available on this reduced supply voltage. Low-cost precision integrators for PLLs will also benefit from the low voltage noise and offset voltage. Baseband I/Q receiver channels can achieve almost perfect channel match with noise and distortion to support signals through 5MHz with > 14-bit dynamic range. SINGLES DUALS TRIPLES High Gain Stable  OPA2614  High Slew Rate VFB OPA690 OPA2690 OPA3690 R/R Input/Output VFB OPA353 OPA2353  Current-Feedback OPA691 OPA2691 OPA3691 Current-Feedback  OPA2677  OPA2613 RO n:1 xDSL D river RO 500Ω 1kΩ 500Ω OP A2822 500Ω 1kΩ xDSL Receiver OP A2822 500Ω Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. All trademarks are the property of their respective owners. Copyright  2003−2008, Texas Instruments Incorporated
          
             
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"#$% www.ti.com SBOS249H − JUNE 2003 − REVISED AUGUST 2008 ELECTROSTATIC DISCHARGE SENSITIVITY ABSOLUTE MAXIMUM RATINGS(1) Supply Voltage (−40°C to +85°C) . . . . . . . . . . . . . . . . . . . . . . ±6.5V Supply Voltage (0°C to +70°C) . . . . . . . . . . . . . . . . . . . . . . . ±6.65V Internal Power Dissipation . . . . . . . . . See Thermal Characteristics Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±1.2V Input Voltage Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±VS Storage Temperature Range . . . . . . . . . . . . . . . . . . −65°C to +125°C Lead Temperature (SO-8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . +260°C Junction Temperature (TJ) . . . . . . . . . . . . . . . . . . . . . . . . . . . +150°C ESD Rating (Human Body Model) . . . . . . . . . . . . . . . . . . . . 2000V (Machine Model) . . . . . . . . . . . . . . . . . . . . . . . . . . 200V (Charge Device Model) . . . . . . . . . . . . . . . . . . . 1500V This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. (1) Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may degrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those specified is not supported. PACKAGE/ORDERING INFORMATION(1) PRODUCT PACKAGE-LEAD PACKAGE DESIGNATOR OPA2613 SO-8 D SPECIFIED TEMPERATURE RANGE PACKAGE MARKING ORDERING NUMBER TRANSPORT MEDIA, QUANTITY −40°C to +85°C OPA2613 OPA2613ID OPA2613IDR Rails, 100 Tape and Reel, 2500 (1) For the most current package and ordering information see the Package Option Addendum at the end of this document, or see the TI web site at www.ti.com. PIN CONFIGURATION SO Top View OPA2613 2 Out A 1 8 +VS −In A 2 7 Out B +In A 3 6 −In B −VS 4 5 +In B 
"#$% www.ti.com SBOS249H − JUNE 2003 − REVISED AUGUST 2008 ELECTRICAL CHARACTERISTICS: VS = ±6V Boldface limits are tested at +25°C. RF = 402Ω, RL = 100Ω, and G = +2, unless otherwise noted. See Figure 1 for AC performance only. OPA2613ID TYP PARAMETER AC Performance (see Figure 1) Small-Signal Bandwidth Gain-Bandwidth Product Bandwidth for 0.1dB Gain Flatness Peaking at a Gain of +1 Large-Signal Bandwidth Slew Rate Rise-and-Fall Time Settling Time to 0.02% 0.1% Harmonic Distortion 2nd-Harmonic 3rd-Harmonic Input Voltage Noise Input Current Noise Differential Gain Differential Phase Channel-to-Channel Crosstalk MIN/MAX OVER TEMPERATURE +25°C(1) 0°C to +70°C(2) −40°C to +85°C(2) 80 10 95 75 9 80 70 9 75 56 4.8 68 51 51 5.4 71 53 50 5.5 72 54 −70 −95 −84 −97 1.8 1.7 0.02 0.03 −80 −63 −90 −80 −92 2.0 2.1 −61 −88 −78 −90 2.1 2.2 97 ±0.2 92 ±1.0 −6 −12 ±50 ±300 TEST CONDITIONS +25°C G = +1, VO = 0.1VPP, RF = 0Ω G = +2, VO = 0.1VPP G = +10, VO = 0.1VPP G ≥ 20 G = +2, VO < 0.1VPP VO < 0.1VPP G = +2, VO = 2VPP G = +2, 4V Step G = +2, VO = 0.2V Step G = +2, VO = 2V Step G = +2, VO = 2V Step G = +2, f = 1MHz, VO = 2VPP RL = 20Ω RL ≥ 500Ω RL = 20Ω RL ≥ 500Ω f > 10kHz f > 10kHz G = +2, PAL, VO = 1.4VPP, RL = 150Ω G = +2, PAL, VO = 1.4VPP, RL = 150Ω f = 1MHz, Input-Referred 230 110 13 125 5 1 22 70 3.6 55 40 TEST LEVEL UNITS MIN/ MAX MHz MHz MHz MHz MHz dB MHz V/µs ns ns ns typ min min min typ typ typ min typ typ typ C B B B C C C B C C C −60 −87 −77 −89 2.3 2.4 dBc dBc dBc dBc nV/√Hz pA/√Hz % deg dBc max max max max max max typ typ typ B B B B B B C C C 92 ±1.15 ±3.3 −13 −30 ±520 ±5 91 ±1.2 ±3.3 −14.5 −35 ±750 ±7 dB mV µV/°C µA nA/°C nA nA/°C min max max max max max max A A B A B A B (3) DC Performance(4) Open-Loop Gain (AOL) Input Offset Voltage Average Offset Voltage Drift Input Bias Current Average Bias Current Drift (Magnitude) Input Offset Current Average Offset Bias Current Drift VO = 0V, RL = 100Ω VCM = 0V VCM = 0V VCM = 0V VCM = 0V VCM = 0V VCM = 0V Input ±4.7 ±4.5 ±4.5 ±4.4 V min A VCM = ±1V 100 88 87 86 dB min A VCM = 0 VCM = 0 18 0.6 7 1 kΩ pF MΩ pF typ typ C C No Load 100Ω VO = 0, Linear Operation VO = 0, Linear Operation Output Shorted to Ground G = +2, f = 100kHz ±5.0 ±4.9 +350 −350 500 0.01 V V mA mA mA Ω min min min min typ typ A A A A C C Common-Mode Input Range (CMIR)(5) Common-Mode Rejection Ratio (CMRR) Input Impedance Differential-Mode Common-Mode Output Output Voltage Swing Current Output, Sourcing Current Output, Sinking Short-Circuit Current Closed-Loop Output Impedance ±4.8 ±4.7 +280 −280 ±4.8 ±4.7 +240 −240 ±4.7 ±4.6 +220 −220 (1) Junction temperature = ambient for +25°C tested specifications. (2) Junction temperature = ambient at low temperature limit; junction temperature = ambient +23°C at high temperature limit for over temperature tested specifications. (3) Test levels: (A) 100% tested at +25°C. Over temperature limits by characterization and simulation. (B) Limits set by characterization and simulation. (C) Typical value only for information. (4) Current is considered positive-out-of-node. VCM is the input common-mode voltage. (5) Tested < 3dB below minimum CMRR specification at ± CMIR limits. 3 
"#$% www.ti.com SBOS249H − JUNE 2003 − REVISED AUGUST 2008 ELECTRICAL CHARACTERISTICS: VS = ±6V (continued) Boldface limits are tested at +25°C. RF = 402Ω, RL = 100Ω, and G = +2, unless otherwise noted. See Figure 1 for AC performance only. OPA2613ID TYP PARAMETER Power Supply Specified Operating Voltage Maximum Operating Voltage Range Maximum Quiescent Current Minimum Quiescent Current Power-Supply Rejection Ratio (−PSRR) TEST CONDITIONS +25°C MIN/MAX OVER TEMPERATURE 0°C to +70°C(2) −40°C to +85°C(2) UNITS MIN/ MAX ±6.3 12.4 11.6 90 ±6.3 12.8 11.2 88 ±6.3 13 11 87 V V mA mA dB typ max max min min C A A A A °C typ C °C/W typ C ±6 VS = ±6V, Both Channels VS = ±6V, Both Channels Input-Referred 12 12 95 TEST LEVEL +25°C(1) (3) Thermal Characteristics Specified Operating Range D Package Thermal Resistance, qJA D SO-8 −40 to +85 Junction-to-Ambient 125 (1) Junction temperature = ambient for +25°C tested specifications. (2) Junction temperature = ambient at low temperature limit; junction temperature = ambient +23°C at high temperature limit for over temperature tested specifications. (3) Test levels: (A) 100% tested at +25°C. Over temperature limits by characterization and simulation. (B) Limits set by characterization and simulation. (C) Typical value only for information. (4) Current is considered positive-out-of-node. VCM is the input common-mode voltage. (5) Tested < 3dB below minimum CMRR specification at ± CMIR limits. 4 
"#$% www.ti.com SBOS249H − JUNE 2003 − REVISED AUGUST 2008 ELECTRICAL CHARACTERISTICS: VS = +5V Boldface limits are tested at +25°C. RF = 402Ω, RL = 100Ω, and G = +2, unless otherwise noted. See Figure 3 for AC performance only. OPA2613ID TYP MIN/MAX OVER TEMPERATURE +25°C(1) 0°C to +70°C(2) −40°C to +85°C(2) 75 10 93 69 8 78 68 8 76 47 5.0 78 62 46 5.6 80 64 46 5.7 81 64 −67 −82 −84 −94 1.9 1.7 −80 −60 −79 −78 −89 2.1 2.1 −58 −77 −76 −87 2.2 2.2 95 ±0.2 91 ±1.0 −6 −11 ±50 ±300 Least Positive Input Voltage 1.2 Most Positive Input Voltage 3.8 VCM = ±1V 95 VCM = 0 VCM = 0 15 1 5 1.3 Most Positive Output Voltage No Load 100Ω Load to 2.5V 4.0 3.95 3.85 3.8 3.8 3.75 Least Positive Output Voltage No Load 100Ω Load to 2.5V VO = 0, Linear Operation VO = 0, Linear Operation Output Shorted to Mid-Supply G = +2, f = 100kHz 1.0 1.05 +300 −300 ±400 0.01 1.15 1.20 1.2 1.25 PARAMETER AC Performance (see Figure 3) Small-Signal Bandwidth Gain-Bandwidth Product Bandwidth for 0.1dB Gain Flatness Peaking at a Gain of +1 Large-Signal Bandwidth Slew Rate Rise-and-Fall Time Settling Time to 0.02% 0.1% Harmonic Distortion 2nd-Harmonic 3rd-Harmonic Input Voltage Noise Input Current Noise Channel-to-Channel Crosstalk TEST CONDITIONS +25°C G = +1, VO = 0.1VPP, RF = 0Ω G = +2, VO = 0.1VPP G = +10, VO = 0.1VPP G ≥ 20 G = +2, VO < 0.1VPP VO < 0.1VPP G = +2, VO = 2VPP G = +2, 2V Step G = +2, VO = 0.2V Step G = +2, VO = 2V Step G = +2, VO = 2V Step G = +2, f = 1MHz, VO = 2VPP RL = 20Ω to VS/2 RL ≥ 500Ω to VS/2 RL = 20Ω to VS/2 RL ≥ 500Ω to VS/2 f > 10kHz f > 10kHz f = 1MHz, Input-Referred 230 105 12 118 5 2.6 21 60 3.8 63 52 VO = 0V, RL = 100Ω VCM = 0V VCM = 0V VCM = 0V VCM = 0V VCM = 0V VCM = 0V TEST LEVEL UNITS MIN/ MAX MHz MHz MHz MHz MHz dB MHz V/µs ns ns ns typ min min min typ typ typ min typ typ typ C B B B C C C B B B B −57 −76 −75 −86 2.4 2.4 dBc dBc dBc dBc nV/√Hz pA/√Hz dBc max max max max max max typ B B B B B B C 89 ±1.15 ±3.3 −12 −35 ±520 ±5 88 ±1.2 ±3.3 −13.5 −35 ±750 ±7 dB mV µV/°C µA nA/°C nA nA/°C min max max max max max max A A B A B A B 1.4 1.4 1.5 V max A 3.6 3.6 3.5 V min A 85 84 83 dB min kΩ pF MΩ pF typ typ A A C C 3.75 3.7 V V min min A A 1.25 1.3 V V mA mA mA Ω min min typ typ typ typ A A C C C C (3) DC Performance(4) Open-Loop Gain (AOL) Input Offset Voltage Average Offset Voltage Drift Input Bias Current Average Bias Current Drift (Magnitude) Input Offset Current Average Offset Bias Current Drift Input Common-Mode Rejection Ratio (CMRR) Input Impedance Differential-Mode Common-Mode Output Current Output, Sourcing Current Output, Sinking Short-Circuit Current Closed-Loop Output Impedance (1) Junction temperature = ambient for +25°C tested specifications. (2) Junction temperature = ambient at low temperature limit; junction temperature = ambient +23°C at high temperature limit for over temperature tested specifications. (3) Test levels: (A) 100% tested at +25°C. Over temperature limits by characterization and simulation. (B) Limits set by characterization and simulation. (C) Typical value only for information. (4) Current is considered positive-out-of-node. VCM is the input common-mode voltage. (5) Tested < 3dB below minimum CMRR specification at ± CMIR limits. 5 
"#$% www.ti.com SBOS249H − JUNE 2003 − REVISED AUGUST 2008 ELECTRICAL CHARACTERISTICS: VS = +5V (continued) Boldface limits are tested at +25°C. RF = 402Ω, RL = 100Ω, and G = +2, unless otherwise noted. See Figure 3 for AC performance only. OPA2613ID TYP PARAMETER TEST CONDITIONS MIN/MAX OVER TEMPERATURE +25°C(1) 0°C to +70°C(2) −40°C to +85°C(2) 12.6 11.0 9.4 12.6 11.3 9.4 12.6 11.5 9.1 TEST LEVEL UNITS MIN/ MAX V V mA mA dB typ max max min typ C A A A C −40 to +85 °C typ C 125 °C/W typ C +25°C (3) Power Supply Specified Operating Voltage Maximum Operating Voltage Range Maximum Quiescent Current Minimum Quiescent Current Power-Supply Rejection Ratio (−PSRR) 5 VS = ±6V, Both Channels VS = ±6V, Both Channels Input-Referred 10.5 10.5 95 Thermal Characteristics Specified Operating Range D Package Thermal Resistance, qJA D SO-8 Junction-to-Ambient (1) Junction temperature = ambient for +25°C tested specifications. (2) Junction temperature = ambient at low temperature limit; junction temperature = ambient +23°C at high temperature limit for over temperature tested specifications. (3) Test levels: (A) 100% tested at +25°C. Over temperature limits by characterization and simulation. (B) Limits set by characterization and simulation. (C) Typical value only for information. (4) Current is considered positive-out-of-node. VCM is the input common-mode voltage. (5) Tested < 3dB below minimum CMRR specification at ± CMIR limits. 6 
"#$% www.ti.com SBOS249H − JUNE 2003 − REVISED AUGUST 2008 TYPICAL CHARACTERISTICS: VS = ±6V At TA = +25°C, G = +2, RF = 402Ω, and RL = 100Ω, unless otherwise noted. INVERTING SMALL−SIGNAL FREQUENCY RESPONSE NONINVERTING SMALL−SIGNAL FREQUENCY RESPONSE 6 6 VO = 100mVPP G = +1 3 3 Normalized Gain (dB) 0 −3 −6 −9 G = +8 −12 G = +4 −15 0 G = −1 −3 −6 G = −4 −9 G = −2 −12 G = −8 −15 See Figure 1 See Figure 2 −18 −18 1 10 100 1 500 10 100 Frequency (MHz) Frequency (MHz) NONINVERTING LARGE−SIGNAL FREQUENCY RESPONSE INVERTING LARGE−SIGNAL FREQUENCY RESPONSE 12 6 V O = 100mVP P VO = 100mV PP 9 3 0 6 3 Gain (dB) Gain (dB) V O = 500mVP P V O = 2V PP 0 VO = 1VP P −3 V O = 5V PP −6 VO = 500mV PP −3 VO = 2V PP −6 VO = 1V PP −9 V O = 5V PP −12 −9 −15 See Figure 1 −12 See Figure 2 −18 1 10 100 500 1 10 Frequency (MHz) Left Scale 200mVPP Small Signal −1 Right Scale 0.1 0 −0.1 −2 −0.2 2 Output Voltage (1V/div) 0.2 Output Voltage (100mV/div) Output Voltage (1V/div) G = +2V/V Large Signal 0 3 0.3 1 500 INVERTING PULSE RESPONSE NONINVERTING PULSE RESPONSE Left Scale 4V PP 100 Frequency (MHz) 3 2 500 4VPP 200mVPP Small Signal −1 0.3 0.2 Large Signal 1 0 G = −1V/V Right Scale 0.1 0 −0.1 −2 −0.2 Output Voltage (100mV/div) Normalized Gain (dB) G = +2 See Figure 2 See Figure 1 −3 −0.3 Time (50ns/div) −3 −0.3 Time (50ns/div) 7 
"#$% www.ti.com SBOS249H − JUNE 2003 − REVISED AUGUST 2008 TYPICAL CHARACTERISTICS: VS = ±6V (continued) At TA = +25°C, G = +2, RF = 402Ω, and RL = 100Ω, unless otherwise noted. HARMONIC DISTORTION vs FREQUENCY G = +2 RL = 100Ω −70 2nd−Harmonic −80 3rd−Harmonic −90 Single Channel (see Figure 1) −100 0.1 1 HARMONIC DISTORTION vs OUTPUT VOLTAGE −60 Harmonic Distortion (dBc) Harmonic Distortion (dBc) −60 G = +2 f = 1MHz RL = 100Ω −70 2nd−Harmonic −80 −90 Single Channel (see Figure 1) −100 0.1 10 1 HARMONIC DISTORTION vs NONINVERTING GAIN Harmonic Distortion (dBc) Harmonic Distortion (dBc) 2nd−Harmonic −80 3rd−Harmonic −90 VO = 2VPP f = 1MHz R L = 100Ω −70 2nd−Harmonic −80 3rd−Harmonic −90 Single Channel (see Figure 2) Single Channel (see Figure 1) −100 HARMONIC DISTORTION vs INVERTING GAIN −60 VO = 2VPP f = 1MHz RL = 100Ω −70 −100 1 10 1 10 Gain Magnitude (V/V) Gain Magnitude (V/V) HARMONIC DISTORTION vs LOAD RESISTANCE −60 Harmonic Distortion (dBc) VO = 2VPP f = 1MHz −70 2nd−Harmonic −80 3rd−Harmonic −90 Single Channel (see Figure 1) −100 10 8 10 Output Voltage (VPP) Frequency (MHz) −60 3rd−Harmonic 100 Load Resistance (Ω) 1000 
"#$% www.ti.com SBOS249H − JUNE 2003 − REVISED AUGUST 2008 TYPICAL CHARACTERISTICS: VS = ±6V (continued) At TA = +25°C, G = +2, RF = 402Ω, and RL = 100Ω, unless otherwise noted. MAXIMUM OUTPUT SWING vs LOAD RESISTANCE OUTPUT VOLTAGE AND CURRENT LIMITATIONS 5 6 5 4 3 4 RL = 100Ω 3 2 2 1 0 −1 VO (V) Output Voltage (V) 6 −2 −3 RL = 50Ω 1 0 −1 RL = 25Ω −2 −3 −4 −5 −4 −5 See Figure 1 −6 10 100 −6 −400 1000 1W Internal Power Single Channel −300 −200 −100 0 100 200 300 400 IO (mA) Load Resistance (Ω) INPUT VOLTAGE AND CURRENT NOISE DENSITY CHANNEL−TO−CHANNEL CROSSTALK −30 10 Voltage Noise 1.8nV/√Hz Crosstalk, Input Referred (dB) Voltage Noise (nV/√Hz) Current Noise (pA/√Hz) Input Referred −40 −50 −60 −70 −80 Current Noise 1.7pA/√Hz −90 1 102 103 104 105 106 107 1 10 RECOMMENDED RS vs CAPACITIVE LOAD FREQUENCY RESPONSE vs CAPACITIVE LOAD Normalized Gain to Capacitive Load (dB) 30 RS(Ω) 20 10 0 1 10 100 Capacitive Load (pF) 100 Frequency (MHz) Frequency (Hz) 1000 3 CL = 22pF 0 CL = 10pF CL = 100pF −3 CL = 47pF −6 −9 1/2 OPA2613 −12 402Ω −15 402Ω RS CL 1kΩ 1kΩ is optional. −18 1 10 100 500 Frequency (MHz) 9 
"#$% www.ti.com SBOS249H − JUNE 2003 − REVISED AUGUST 2008 TYPICAL CHARACTERISTICS: VS = ±6V (continued) At TA = +25°C, G = +2, RF = 402Ω, and RL = 100Ω, unless otherwise noted. OPEN−LOOP GAIN AND PHASE CMRR AND PSRR vs FREQUENCY 20 log (AOL) −PSRR 60 40 80 20 1k 10k 100k 1M 10M 60 −90 40 −120 20 −150 0 −180 −20 100 100M −210 1k 10k 100k CLOSED−LOOP OUTPUT IMPEDANCE vs FREQUENCY 10M 100M 1G VIDEO DIFFERENTIAL GAIN/DIFFERENTIAL PHASE 100 0.14 0.28 G = +2 VS = ±5V 0.12 10 Differential Gain (%) 1 0.1 0.01 dφ, Negative Video 0.24 0.10 0.20 dG , Positive Video 0.08 0.16 0.06 0.12 0.04 0.08 dφ, Positive Video 0.001 0.02 0.0001 0.04 dG, Negative Video 0 10k 100k 1M 10M 100M 1 2 3 4 5 Frequency (Hz) 4 2 2 1 0 0 −2 −1 −4 −2 −6 −8 −10 −3 G = +2 RL = 100Ω See Figure 1 −4 −5 Time (100ns/div) Output Voltage (2V/div) Output 4 Input 6 3 Input Voltage (1V/div) 6 8 0 9 10 INVERTING OVERDRIVE RECOVERY 8 5 Input 8 7 Video Loads NONINVERTING OVERDRIVE RECOVERY 10 6 G = −1 RL = 100Ω 8 6 4 4 2 2 0 0 −2 −2 −4 −4 −6 −8 −6 Output See Figure 2 Time (100ns/div) −8 Input Voltage (2V/div) Output Impedance Magnitude (Ω) 1M Frequency (Hz) Frequency (Hz) Output Voltage (2V/div) −60 ∠ AOL Differential Phase (_) 100 Open−Loop Phase (_ ) CMRR 0 10 −30 100 100 80 0 120 +PSRR Open−Loop Gain (dB) Common−Mode Rejection Ratio (dB) Power−Supply Rejection Ratio (dB) 120 
"#$% www.ti.com SBOS249H − JUNE 2003 − REVISED AUGUST 2008 TYPICAL CHARACTERISTICS: VS = ±6V (continued) At TA = +25°C, G = +2, RF = 402Ω, and RL = 100Ω, unless otherwise noted. SUPPLY AND OUTPUT CURRENT vs TEMPERATURE TYPICAL DC DRIFT OVER TEMPERATURE 0 0 Input Offset Voltage (VIO) −5 −0.5 Inverting Bias Current (IB) −25 0 25 50 75 100 −10 125 290 12.2 Left Scale 12.1 280 Supply Current Right Scale 270 12.0 260 11.9 250 −50 −25 0 Ambient Temperature (_C) 25 50 75 100 Supply Current (0.1mA/div) (10 Times Input Offset Current) 10 x IOS Sourcing and Sinking Current Output Current (10mA/div) 5 0.5 11.8 125 Ambient Temperature (_ C) COMMON−MODE INPUT RANGE AND OUTPUT SWING vs SUPPLY VOLTAGE 6 RL = 100Ω 5 Voltage Range (V) Input Offset Voltage (mV) Input Bias and Offset Current (µA) 10 1 −1 −50 12.3 300 −V Input Voltage 4 3 −Output Voltage 2 +V Input Voltage 1 +Output Voltage 0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6 Supply Voltage (±V) 11 
"#$% www.ti.com SBOS249H − JUNE 2003 − REVISED AUGUST 2008 TYPICAL CHARACTERISTICS: VS = ±6V, Differential Configuration At TA = +25°C, Differential Gain = 4, RF = 402Ω, and RL = 70Ω, unless otherwise noted. See Figure 5 for AC performance only. DIFFERENTIAL SMALL−SIGNAL FREQUENCY RESPONSE DIFFERENTIAL LARGE−SIGNAL FREQUENCY RESPONSE 15 3 R L = 70Ω R L = 70Ω G D = +4 GD = +1 0 12 GD = 2 V O = 0.2V PP Gain (dB) Normalized Gain (dB) VO = 200mV PP −3 −6 9 VO = 1VP P 6 V O = 2VP P 3 G D = +4 See Figure 5 0 10 1 100 200 1 10 Frequency (MHz) DIFFERENTIAL DISTORTION vs LOAD RESISTANCE Harmonic Distortion (dBc) Harmonic Distortion (dBc) DIFFERENTIAL DISTORTION vs FREQUENCY −55 GD = +4 f = 1MHz VO = 2VPP 3rd−Harmonic −90 2nd−Harmonic −95 GD = 4 RL = 70Ω VO = 2VPP −65 3rd−Harmonic −75 −85 2nd−Harmonic −95 −105 See Figure 5 See Figure 5 10 −115 100 1k 0.1 1 Resistance (Ω) Frequency (MHz) DIFFERENTIAL DISTORTION vs OUTPUT VOLTAGE −70 GD = 4 RL = 70Ω f = 1MHz Harmonic Distortion (dBc) −75 −80 3rd−Harmonic −85 −90 −95 2nd−Harmonic −100 See Figure 5 −105 0.1 1 Output Voltage Swing (VPP) 12 100 Frequency (MHz) −85 −100 V O = 5V PP See Figure 5 GD = +8 −9 10 20 10 
"#$% www.ti.com SBOS249H − JUNE 2003 − REVISED AUGUST 2008 TYPICAL CHARACTERISTICS: VS = +5V At TA = +25°C, G = +2, RF = 402Ω, and RL = 100Ω, unless otherwise noted. INVERTING SMALL−SIGNAL FREQUENCY RESPONSE NONINVERTING SMALL−SIGNAL FREQUENCY RESPONSE VO = 100mVPP RL = 100Ω to VS/2 3 G = +1 VO = 100mVPP RL = 100Ω to VS/2 Normalized Gain (dB) 0 G = +2 −3 −6 G = +8 See Figure 3 −9 1 G = −1 0 G = −2 −3 G = −4 −6 G = −8 G = +4 See Figure 4 −9 10 100 1 500 10 100 Frequency (MHz) Frequency (MHz) NONINVERTING LARGE−SIGNAL FREQUENCY RESPONSE INVERTING LARGE−SIGNAL FREQUENCY RESPONSE 9 3 G = +2 G = −1 R L = 100Ω to VS /2 VO = 0.1V PP R L = 100Ω to VS /2 6 VO = 0.1V P P 0 VO = 0.5V PP VO = 0.5V P P Gain (dB) Gain (dB) 3 0 VO = 1V PP −3 1 −3 −6 V O = 1V PP −9 V O = 2VP P See Figure 3 −6 10 100 300 1 10 2VPP Large Signal 3.3 2.9 2.5 200mVPP Small Signal 4.5 2.9 4.1 2.8 3.7 2.7 Right Scale 2.6 2.5 2.1 2.4 1.7 2.3 1.3 0.9 0.5 See Figure 3 Time (50ns/div) Output Voltage (mV) Output Voltage (1V/div) Left Scale 300 INVERTING PULSE RESPONSE 3.0 Output Voltage (mV) G = +2V/V RL = 100Ωto VS/2 4.1 100 Frequency (MHz) NONINVERTING PULSE RESPONSE 4.5 VO = 2VP P See Figure 4 −12 Frequency (MHz) 3.7 300 Left Scale 2.5 2VPP 200mVPP Small Signal 3.0 2.9 2.8 Large Signal 3.3 2.9 G = −1V/V RL = 100Ωto VS/2 2.7 Right Scale 2.6 2.5 2.1 2.4 1.7 2.3 2.2 1.3 2.2 2.1 0.9 2.0 0.5 Output Voltage (mV) Normalized Gain (dB) 3 2.1 See Figure 4 2.0 Time (50ns/div) 13 
"#$% www.ti.com SBOS249H − JUNE 2003 − REVISED AUGUST 2008 TYPICAL CHARACTERISTICS: VS = +5V (continued) At TA = +25°C, G = +2, RF = 402Ω, and RL = 100Ω, unless otherwise noted. HARMONIC DISTORTION vs FREQUENCY VO = 2VPP G = +2 RL = 100Ω to VS/2 −70 f = 1MHz RL = 100Ω to VS/2 2nd−Harmonic −80 3rd−Harmonic −90 Single Channel (see Figure 3) −100 0.1 HARMONIC DISTORTION vs OUTPUT VOLTAGE −70 Harmonic Distortion (dBc) Harmonic Distortion (dBc) −60 1 −80 2nd−Harmonic −90 3rd−Harmonic −100 −110 0.1 10 1 HARMONIC DISTORTION vs INVERTING GAIN HARMONIC DISTORTION vs NONINVERTING GAIN −50 VO = 2VPP f = 1MHz RL = 100Ωto VS/2 −60 Harmonic Distortion (dBc) Harmonic Distortion (dBc) −50 2nd−Harmonic −70 −80 3rd−Harmonic −90 Single Channel (see Figure 3) −100 1 VO = 2VPP f = 1MHz RL = 100Ω to VS/2 −60 2nd−Harmonic −70 −80 3rd−Harmonic −90 Single Channel (see Figure 4) −100 1 10 10 Gain Magnitude (V/V) Gain Magnitude (V/V) HARMONIC DISTORTION vs LOAD RESISTANCE −60 VO = 2VPP f = 1MHz G = +2 RL to VS/2 Harmonic Distortion (dBc) 2nd−Harmonic −70 −80 3rd−Harmonic −90 Single Channel (see Figure 3) −100 10 100 Load Resistance (Ω) 14 5 Output Voltage (VPP) Frequency (MHz) 1000 
"#$% www.ti.com SBOS249H − JUNE 2003 − REVISED AUGUST 2008 TYPICAL CHARACTERISTICS: VS = +5V, Differential Configuration At TA = +25°C, GD = 4, RF = 402Ω, and RL = 70Ω, unless otherwise noted. +5V DIFFERENTIAL SMALL−SIGNAL FREQUENCY RESPONSE 806Ω 3 RL = 70Ω 806Ω Normalized Gain (dB) 1/2 OPA2613 RF 402Ω 0.01µF RG VI RL RF 402Ω 0.01µF VI 0.01µF 806Ω GD = 1 0 GD = 2 −3 −6 GD = 4 1/2 OPA2613 806Ω GD = 8 −9 2RF GD = 1 + RG 1 10 100 200 Frequency (MHz) DIFFERENTIAL LARGE−SIGNAL FREQUENCY RESPONSE DIFFERENTIAL DISTORTION vs LOAD RESISTANCE −85 15 RL = 70Ω GD = 4 Harmonic Distortion (dBc) 12 Gain (dB) VO = 0.2VPP 9 VO = 1VPP 6 VO = 2VPP 3 VO = 5VPP −90 2nd−Harmonic −95 −100 0 1 10 100 10 200 100 DIFFERENTIAL DISTORTION vs FREQUENCY DIFFERENTIAL DISTORTION vs OUTPUT VOLTAGE −85 GD = 4V/V RL = 70Ω VO = 2VPP Harmonic Distortion (dBc) Harmonic Distortion (dBc) −85 1k Resistance (Ω) Frequency (MHz) −75 GD = +4 RL = 70Ω VO = 2VPP f = 1MHz 3rd−Harmonic 3rd−Harmonic −95 2nd−Harmonic −105 GD = 4V/V R L = 70Ω f = 1MHz 3rd−Harmonic 2nd−Harmonic −90 −95 −115 0.1 1 Frequency (MHz) 2 0.1 1 10 Output Voltage Swing (VPP ) 15 
"#$% www.ti.com SBOS249H − JUNE 2003 − REVISED AUGUST 2008 APPLICATION INFORMATION WIDEBAND VOLTAGE-FEEDBACK OPERATION The OPA2613 gives the exceptional AC performance of a wideband voltage-feedback op amp with a highly linear, high-power output stage. Requiring only 6mA/ch quiescent current, the OPA2613 swings to within 1.0V of either supply rail and delivers in excess of 280mA at room temperature. This low-output headroom requirement, along with supply voltage independent biasing, gives remarkable single (+5V) supply operation. The OPA2613 delivers greater than 20MHz bandwidth driving a 2VPP output into 100Ω on a single +5V supply. Previous boosted output stage amplifiers typically suffer from very poor crossover distortion as the output current goes through zero. The OPA2613 achieves exceptional power gain with much better linearity. Figure 1 shows the DC-coupled, gain of +2, dual power-supply circuit configuration used as the basis of the ±6V Electrical and Typical Characteristics. For test purposes, the input impedance is set to 50Ω with a resistor to ground; and the output impedance is set to 50Ω with a series output resistor. Voltage swings reported in the electrical characteristics are taken directly at the input and output pins, whereas load powers (dBm) are defined at a matched 50Ω load. For the circuit of Figure 1, the total effective load is 100Ω || 804Ω = 89Ω. 0.1µF +6V +VS 6.8µF + 50Ω Source VI 50Ω VO 1/2 OPA2613 50Ω 50Ω Load RF 402Ω RG 402Ω 6.8µF 0.1µF + −VS −6V Figure 1. DC-Coupled, G = +2, Bipolar Supply, Specification and Test Circuit 16 Figure 2 shows the DC-coupled, bipolar supply circuit configuration used as the basis for the Inverting Gain −1V/V Typical Characteristics. Key design considerations of the inverting configuration are developed in the Inverting Amplifier Operation section. +5V 208Ω 50Ω Source RF 402Ω Power−Supply decoupling not shown. 1/2 OPA2613 VO 50Ω 50ΩLoad −5V R F 402Ω VI RM 57.6Ω Figure 2. DC-Coupled, G = −1, Bipolar Supply, Specification and Test Circuit Figure 3 shows the AC-coupled, gain of +2, single-supply circuit configuration used as the basis of the +5V Electrical and Typical Characteristics. Though not a rail-to-rail design, the OPA2613 requires minimal input and output voltage headroom compared to other very wideband voltage-feedback op amps. It will deliver a 2.6VPP output swing on a single +5V supply with greater than 20MHz bandwidth. The key requirement of broadband singlesupply operation is to maintain input and output signal swings within the usable voltage ranges at both the input and the output. The circuit of Figure 3 establishes an input midpoint bias using a simple resistive divider from the +5V supply (two 806Ω resistors). The input signal is then AC-coupled into this midpoint voltage bias. The input voltage can swing to within 1.4V of either supply pin, giving a 2.2VPP input signal range centered between the supply pins. The input impedance matching resistor (57.6Ω) used for testing is adjusted to give a 50Ω input match when the parallel combination of the biasing divider network is included. The gain resistor (RG) is AC-coupled, giving the circuit a DC gain of +1which puts the input DC bias voltage (2.5V) on the output as well. Again, on a single +5V supply, the output voltage can swing to within 1.1V of either supply pin while delivering more than 100mA output current. A demanding 100Ω load to a midpoint bias is used in this characterization circuit. The new output stage used in the OPA2613 can deliver large bipolar output currents into this midpoint load with minimal crossover distortion, as shown by the +5V supply, harmonic distortion plots. 
"#$% www.ti.com SBOS249H − JUNE 2003 − REVISED AUGUST 2008 the OPA2613. Each has its advantages and disadvantages. Figure 5 shows a basic starting point for noninverting input differential I/O applications. +5V +VS + 0.1µF 6.8µF 806Ω +VCC 0.1µF VI 57.6Ω 806Ω 1/2 OPA2613 VO 100Ω 1/2 VS /2 O P A2613 RF 402Ω RF 402Ω RG 402Ω VI RG 268Ω 0.1µF Figure 3. AC-Coupled, G = +2, Single-Supply, Specification and Test Circuit The last configuration used as the basis of the +5V Electrical and Typical Characteristics is shown in Figure 4. Design considerations for this inverting, bipolar supply configuration are covered either in single-supply configuration (as shown in Figure 3) or in the Inverting Amplifier Operation section. +5V 0.1µF 806Ω 0.1µF RG 0.1µF 402Ω 806Ω 1/2 OPA2613 Power−Supply decoupling not shown. VO + 6.8µF RF 402Ω 1/2 O P A2613 −VCC Figure 5. Noninverting Differential I/O Amplifier This approach provides for a source termination impedance that is independent of the signal gain. For instance, simple differential filters may be included in the signal path right up to the noninverting inputs without interacting with the gain setting. The differential signal gain for the circuit of Figure 5 is: AD + 1 ) 2 100Ω VS /2 RF 402Ω VI RM 57.6Ω Figure 4. AC-Coupled, G = −1, Single-Supply, Specification and Test Circuit DIFFERENTIAL INTERFACE APPLICATIONS Dual op amps are particularly suitable to differential input to differential output applications. Typically, these fall into either Analog-to-Digital Converter (ADC) input interface or line driver applications. Two basic approaches to differential I/O are noninverting or inverting configurations. Since the output is differential, the signal polarity is somewhat meaningless—the noninverting and inverting terminology applies here to where the input is brought into VO RF RG (1) Since the OPA2613 is a voltage-feedback (VFB) amplifier, its bandwidth is principally controlled by the noise gain. The equivalent noise gain for Figure 5 is: 1)2 402W + 4VńV 268W (2) Various combinations of single-supply or AC-coupled gain can also be delivered using the basic circuit of Figure 5. Common-mode bias voltages on the two noninverting inputs pass on to the output with a gain of 1 since an equal DC voltage at each inverting node creates no current through RG. This circuit does show a common-mode gain of 1 from input to output. The source connection should either remove this common-mode signal if undesired (using an input transformer can provide this function), or the common-mode voltage at the inputs can be used to set the output common-mode bias. If the low common-mode rejection of this circuit is a problem, the output interface may also be used to reject that common-mode. For instance, most modern differential input ADCs reject common-mode signals very well, while a line driver application through a transformer will also remove the common-mode signal through to the line. 17 
"#$% www.ti.com SBOS249H − JUNE 2003 − REVISED AUGUST 2008 SINGLE-SUPPLY ADSL UPSTREAM DRIVER Figure 6 shows an example of a single-supply ADSL upstream driver. The dual OPA2613 is configured as a differential gain stage to provide signal drive to the primary of the transformer (here, a step-up transformer with a turns ratio of 1:2). The main advantage of this configuration is the cancellation of all even harmonic distortion products. Another important advantage for ADSL is that each amplifier needs only to swing half of the total output required driving the load. receiver. The value of these resistors (RM) is a function of the line impedance and the transformer turns ratio (n), given by the following equation: Z LINE 2n2 RM + (4) LINE DRIVER HEADROOM MODEL The first step in a transformer-coupled, twisted-pair driver design is to compute the peak-to-peak output voltage from the target specifications. This is done using the following equations: 2 P L + 10 +12V 1/2 OPA2613 AFE 2VPP Max Assumed +6.3V 0.1µF IP = 150mA RM 12.5Ω 1:n RF 1kΩ 1kΩ 1kΩ RG 308Ω V RMS + 15VPP RM 12.5Ω 1/2 OPA2613 V LPP + 2 IP = 150mA Figure 6. Single-Supply ADSL Upstream Driver The analog front-end (AFE) signal is AC-coupled to the driver, and the noninverting input of each amplifier is biased slightly above the mid-supply voltage (+6.3V in this case). In addition to providing the proper biasing to the amplifier, this approach also provides a high-pass filtering with a corner frequency, set here at 1.6kHz. As the upstream signal bandwidth starts at 26kHz, this high-pass filter does not generate any problems and has the advantage of filtering out unwanted lower frequencies. The input signal is amplified with a gain set by the following equation: 2 RF RG PL 10 10 V RMS + CF (6) V RMS (7) CF VRMS (8) The two back-termination resistors (12.5Ω each) added at each input of the transformer make the impedance of the modem match the impedance of the phone line, and also provide a means of detecting the received signal for the CF Ǹ(1mW) RL PL 10 10 (9) This VLPP is usually computed for a nominal line impedance and may be taken as a fixed design target. The next step for the driver is to compute the individual amplifier output voltage and currents as a function of VPP on the line and transformer turns ratio. As the turns ratio changes, the minimum allowed supply voltage changes along with it. The peak current in the amplifier output is given by: "I P + 1 2 2 V LPP n 1 4R M (10) With VLPP as defined in Equation 8, and RM as defined in Equation 4 and shown in Figure 7. RM (3) With RF = 1kΩ and RG = 308Ω, the gain for this differential amplifier is 7.5. This gain boosts the AFE signal, assumed to be a maximum of 2VPP, to a maximum of 15VPP. 18 RL with VLPP: peak-to-peak voltage at the load. Consolidating Equations 4 through 7 allows expressing the required peak-to-peak voltage at the load as a function of the crest factor, the load impedance, and the power at the load. Thus, V LPP + 2 GD + 1 ) (5) with VP peak voltage at the load and CF Crest Factor. 100Ω 1µF Ǹ(1mW) V P + Crest Factor ZLINE RF 1kΩ 20Ω VRMS (1mW) RL With PL power and VRMS voltage at the load, and RL load impedance, this gives the following: 20Ω 0.1µF log Vpp = 2VLpp n VLpp n 1:n RL VLpp RM Figure 7. Driver Peak Output Voltage 
"#$% www.ti.com SBOS249H − JUNE 2003 − REVISED AUGUST 2008 With the previous information available, it is now possible to select a supply voltage and the turns ratio desired for the transformer as well as calculate the headroom for the OPA2613. The model (shown in Figure 8) can be described with the following set of equations: 1. First, as available output swing: V PP + VCC * (V1 ) V2) * I P 2. OPA2613 holds a relatively constant quiescent current versus supply voltage—giving a power contribution that is simply the quiescent current times the supply voltage used (the supply voltage will be greater than the solution given in Equation 12). The total output stage power may be computed with reference to Figure 9. +VCC (R 1 ) R 2) (11) IAVG = IP CF Or as required supply voltage: V CC + VPP ) (V1 ) V2) ) I P (R 1 ) R 2) (12) RT The minimum supply voltage for a power and load requirement is given by Equation 11. +VCC Figure 9. Output Stage Power Model R1 V1 VO IP V2 R2 Figure 8. Line Driver Headroom Model V1, V2, R1, and R2 are given in Table 1 for both +12V and +5V operation. Table 1. Line Driver Headroom Model Values V1 R1 V2 R2 +5V 1.0V 2Ω 1.0V 5.5Ω +12V 1.0V 2Ω 1.0V 5.5Ω TOTAL DRIVER POWER FOR xDSL APPLICATIONS The total internal power dissipation for the OPA2613 in an xDSL line driver application will be the sum of the quiescent power and the output stage power. The The two output stages used to drive the load of Figure 7 can be seen as an H-Bridge in Figure 9. The average current drawn from the supply into this H-Bridge and load will be the peak current in the load given by Equation 10 divided by the crest factor (CF) for the xDSL modulation. This total power from the supply is then reduced by the power in RT to leave the power dissipated internal to the drivers in the four output stage transistors. That power is simply the target line power used in Equation 5 plus the power lost in the matching elements (RM). In the examples here, a perfect match is targeted giving the same power in the matching elements as in the load. The output stage power is then set by Equation 13. P OUT + IP CF V CC * 2P L (13) The total amplifier power is then: P TOT + I q VCC ) IP CF V CC * 2P L (14) For the ADSL CPE upstream driver design of Figure 6, the peak current is 150mA for a signal that requires a crest factor of 5.33 with a target line power of 13dBm into 100Ω (20mW). With a typical quiescent current of 12mA and a nominal supply voltage of +12V, the total internal power dissipation for the solution of Figure 6 will be: PTOT + 12mA(12V) ) 150mA (12V) * 2(20mW) + 400mW 5.33 (15) 19 
"#$% www.ti.com SBOS249H − JUNE 2003 − REVISED AUGUST 2008 DESIGN-IN TOOLS +6V DEMONSTRATION FIXTURE Power−supply decoupling not shown. A printed circuit board (PCB) is available to assist in the initial evaluation of circuit performance using the OPA2613. The fixture is offered free of charge as an unpopulated PCB, delivered with a user’s guide. The summary information for this fixture is shown in Table 2. Table 2. Demonstration Fixture PRODUCT PACKAGE ORDERING NUMBER OPA2613ID SO-8 DEM-OPA-SO-2A LITERATURE NUMBER SBOU003 The demonstration fixture can be requested at the Texas Instruments web site (www.ti.com) through the OPA2613 product folder. MACROMODELS AND APPLICATIONS SUPPORT Computer simulation of circuit performance using SPICE is often useful when analyzing the performance of analog circuits and systems. This is particularly true for video and RF amplifier circuits where parasitic capacitance and inductance can have a major effect on circuit performance. A SPICE model for the OPA2613 is available through the TI web site (www.ti.com). This model does a good job of predicting small-signal AC and transient performance under a wide variety of operating conditions, but does not do as well in predicting the harmonic distortion or video dG/dP characteristics. This model does not attempt to distinguish between the package types in small-signal AC performance, nor does it attempt to simulate channel-tochannel coupling. INVERTING AMPLIFIER OPERATION As the OPA2613 is a general-purpose, wideband voltage-feedback op amp, most of the familiar op amp application circuits are available to the designer. Wideband inverting operation is particularly suited to the OPA2613. Figure 10 shows a typical inverting configuration where the I/O impedances and signal gain from Figure 1 are retained in an inverting circuit configuration. 20 50Ω Load 1/2 OPA2613 50Ω Source RG 200Ω VO 50Ω RF 402Ω VI VO RM 66.7Ω VI =− RF RG = −2 − 6V Figure 10. Inverting Gain of −1 with Impedance Matching In the inverting configuration, two key design considerations must be noted. The first is that the gain resistor (RG) becomes part of the input impedance. If input impedance matching is desired (which is beneficial whenever the signal is coupled through a cable, twistedpair, long PC board trace, or other transmission line conductor), it is normally necessary to add an additional matching resistor to ground. RG, by itself, is not normally set to the required input impedance since its value, along with the desired gain, will determine an RF, which may be non-optimal from a frequency response standpoint. The total input impedance for the source becomes the parallel combination of RG and RM. The second major consideration, touched on in the previous paragraph, is that the signal source impedance becomes part of the noise gain equation and has an effect on the bandwidth. In the example of Figure 10, the RM value combines in parallel with the external 50Ω source impedance, yielding an effective driving impedance of 50Ω || 66.7Ω = 28.6Ω. This impedance is added in series with RG for calculating the noise gainwhich gives NG = 2.76. Note that the noninverting input in this bipolar supply inverting application is connected to ground through a 146Ω resistor. It is often suggested that an additional resistor be connected to ground on the noninverting input to achieve bias current error cancellation at the output. 
"#$% www.ti.com SBOS249H − JUNE 2003 − REVISED AUGUST 2008 OUTPUT CURRENT AND VOLTAGE The OPA2613 provides output voltage and current capabilities that are unsurpassed in a low-cost dual monolithic op amp. Under no-load conditions at 25°C, the output voltage typically swings closer than 1V to either supply rail; tested at +25°C, swing limit is within 1.1V of either rail. Into a 12Ω load (the minimum tested load), it delivers more than ±280mA continuous output current. The specifications described previously, though familiar in the industry, consider voltage and current limits separately. In many applications, it is the voltage times current (or V-I product) that is more relevant to circuit operation. Refer to the Output Voltage and Current Limitations plot in the Typical Characteristics. The X and Y axes of this graph show the zero-voltage output current limit and the zero-current output voltage limit, respectively. The four quadrants give a more detailed view of the OPA2613 output drive capabilities, noting that the graph is bounded by a safe operating area of 1W maximum internal power dissipation (in this case, for one channel only). Superimposing resistor load lines onto the plot shows that the OPA2613 can drive +4.8 and −4.1 into 25Ω without exceeding the output capabilities or the 1W dissipation limit. A 100Ω load line (the standard test circuit load) shows the full ±4.9V output swing capability, as shown in the Electrical Characteristics tables. The minimum specified output voltage and current over temperature are set by worst-case simulations at the cold temperature extreme. Only at cold startup will the output current and voltage decrease to the numbers shown in the Electrical Characteristics tables. As the output transistors deliver power, the junction temperatures increase, decreasing the VBEs (increasing the available output voltage swing), and increasing the current gains (increasing the available output current). In steady-state operation, the available output voltage and current will always be greater than that shown in the over-temperature specifications, since the output stage junction temperatures will be higher than the minimum specified operating ambient. DRIVING CAPACITIVE LOADS One of the most demanding and yet very common load conditions for an op amp is capacitive loading. Often, the capacitive load is the input of an ADCincluding additional external capacitance that may be recommended to improve the ADC linearity. A high-speed, high open-loop gain amplifier like the OPA2613 can be very susceptible to decreased stability and closed-loop response peaking when a capacitive load is placed directly on the output pin. When the amplifier open-loop output resistance is considered, this capacitive load introduces an additional pole in the signal path that can decrease the phase margin. Several external solutions to this problem have been suggested. When the primary considerations are frequency response flatness, pulse response fidelity, and/or distortion, the simplest and most effective solution is to isolate the capacitive load from the feedback loop by inserting a series isolation resistor between the amplifier output and the capacitive load. This does not eliminate the pole from the loop response, but rather shifts it and adds a zero at a higher frequency. The additional zero acts to cancel the phase lag from the capacitive load pole, thus increasing the phase margin and improving stability. The Typical Characteristics show the Recommended RS vs Capacitive Load and the resulting frequency response at the load. Parasitic capacitive loads greater than 2pF can begin to degrade the performance of the OPA2613. Long PCB traces, unmatched cables, and connections to multiple devices can easily cause this value to be exceeded. Always consider this effect carefully, and add the recommended series resistor as close as possible to the OPA2613 output pin (see the Board Layout Guidelines section). The very high output current and unity gain stability for the OPA2613 can be used to drive large capacitive loads with moderate slew rates. An example is shown in Figure 11 where a 5000pF load cap is driven with a 1MHz square wave to give a ±5V swing. The supplies were slightly increased to give more headroom for the charging current through the 2Ω isolation resistor. +6.2V VI ±2.5V 1MHz Square Wave Input 1/2 OPA2613 Supply decoupling not shown. 2Ω VO 5000pF 402Ω − 6.2V 402Ω Figure 11. Large Capacitive Load Driver 21 
"#$% www.ti.com SBOS249H − JUNE 2003 − REVISED AUGUST 2008 Figure 12 shows a comparison of 2 × Input voltage to the capacitor voltage. The transition time is set by the 70V/µs slew rate for the OPA2613. For this controlled dV/dT, the charging current into the 5000pF load will be given by: Slew Rate = IP/C Solving for IP gives: I P + 5000pF 70Vńms + 350mA peak current (16) Input and Output Voltage 6 5 Capacitor Voltage 4 3 2X Input Voltage 2 NOISE PERFORMANCE Wideband voltage-feedback op amps generally have a lower output noise than comparable current-feedback op amps. The OPA2613 offers an excellent balance between voltage and current noise terms to achieve low output noise. The input voltage noise (1.8nV/√Hz) is lower than most unity-gain stable, wideband voltage-feedback op amps. The op amp input voltage noise and the two input current noise terms combine to give low output noise under a wide variety of operating conditions. Figure 13 shows the op amp noise analysis model with all the noise terms included. In this model, all noise terms are taken to be noise voltage or current density terms in either nV/√Hz or pA/√Hz. 1 0 −1 70V/µs Slew Rate ENI −2 −3 −4 1/2 OPA2613 RS −5 −6 Time (100ns/div) ERS Figure 12. Large-Signal Capacitive Load Drive At these larger capacitive loads, very low series R will maintain stabilitybut some R is always required. The OPA2613 provides good distortion performance into a 100Ω load on ±6V supplies. Generally, until the fundamental signal reaches high frequency or power levels, the 2nd-harmonic dominates the distortion with a negligible 3rd-harmonic component. Focusing then on the 2nd-harmonic, increasing the load impedance improves distortion directly. Remember that the total load includes the feedback networkin the noninverting configuration (see Figure 1), this is the sum of RF + RG, whereas in the inverting configuration, it is just RF. Also, providing an additional supply decoupling capacitor (0.01µF) between the supply pins (for bipolar operation) improves the 2nd-order distortion slightly (3dB to 6dB). In most op amps, increasing the output voltage swing increases harmonic distortion directly. The Typical Characteristics show the 2nd-harmonic increasing at a little less than the expected 2x rate whereas the 3rd-harmonic increases at a little less than the expected 3x rate. Where the test power doubles, the difference between it and the 2nd-harmonic decreases less than the expected 6dB, whereas the difference between it and the 3rd-harmonic decreases by less than the expected 12dB. Operating differentially will suppress the 2nd-order harmonics below the 3rd. Operating as a differential I/O stage will also suppress the 2nd-harmonic distortion. 22 RF √4kTRS √4kTRF IBI RG 4kT RG DISTORTION PERFORMANCE EO IBN 4kT = 1.6E −20J at 290_K Figure 13. Op Amp Noise Analysis Model The total output spot noise voltage can be computed as the square root of the sum of all squared output noise voltage contributors. Equation 17 shows the general form for the output noise voltage using the terms given in Figure 13. EO + Ǹǒ E NI ) ǒI BN RSǓ ) 4kTRS 2 2 Ǔ NG 2 ) ǒI BI 2 RFǓ ) 4kTRFNG (17) Dividing this expression by the noise gain (NG = (1 + RF/RG)) gives the equivalent input-referred spot noise voltage at the noninverting input, as shown in Equation 18. EN + Ǹ ǒ 2 E NI ) I BN R Ǔ S 2 ) 4kTR ) S ǒ I BI Ǔ RF NG 2 ) 4kTR F NG (18) Evaluating these two equations for the OPA2613 circuit and component values (see Figure 1) gives a total output spot noise voltage of 6.34nV/√Hz and a total equivalent input spot noise voltage of 3.2nV/√Hz. This total input referred spot noise voltage is higher than the 1.8nV/√Hz specification for the op amp voltage noise alone. This reflects the noise added to the output by the inverting current noise times the feedback resistor. 
"#$% www.ti.com SBOS249H − JUNE 2003 − REVISED AUGUST 2008 DIFFERENTIAL NOISE PERFORMANCE As the OPA2613 is used as a differential driver in xDSL applications, it is important to analyze the noise in such a configuration. Figure 14 shows the op amp noise model for the differential configuration. IN Evaluating these equations for the OPA2613 ADSL circuit and component values of Figure 6 gives a total output spot noise voltage of 23.3nV/√Hz and a total equivalent input spot noise voltage of 3.2nV/√Hz. In order to minimize the output noise due to the noninverting input bias current noise, it is recommended to keep the noninverting source impedance as low as possible. DC ACCURACY AND OFFSET CONTROL Driver EN RS IN ERS √4kTRF RF √4kTRS RG EO2 √4kTRG √4kTRF RF IN EN RS IN ERS √4kTRS Figure 14. Differential Op Amp Noise Analysis Model The OPA2613 can provide excellent DC signal accuracy due to its high open-loop gain, high common-mode rejection, high power-supply rejection, and low input offset voltage and bias current offset errors. To take full advantage of the low input offset voltage (±1.0mV maximum at 25°C), careful attention to input bias current cancellation is also required. The high-speed input stage for the OPA2613 has relatively high input bias current (6µA typical into the pins) but with a very close match between the two input currents, typically 50nA input offset current. The total output offset voltage may be reduced considerably by matching the source impedances looking out of the two inputs. For example, one way to add bias current cancellation to the circuit of Figure 1 would be to insert a 175Ω series resistor into the noninverting input from the 50Ω terminating resistor. If the 50Ω source resistor is DC-coupled, this will increase the source impedance for the noninverting input bias current to 200Ω. Since this is now equal to the impedance looking out of the inverting input (RF || RG), the circuit will cancel the bias current effects, leaving only the offset current times the feedback resistor as a residual DC error term at the output. Evaluating the configuration of Figure 1 adding a 175Ω in series with the noninverting input pin, using worst-case +25°C input offset voltage and the two input bias currents, gives a worst-case output offset range equal to: VOFF = ± (NG × VOS(MAX)) ± (IOS × RF) As a reminder, the differential gain is expressed as: GD + 1 ) 2 where NG = noninverting signal gain = ± (2 × 1.0mV) ± (402Ω × 300nA) RF RG (19) VOFF = ±2.12mV The output noise can be expressed as shown below: (20) e O + Ǹ 2 G 2 D ǒ ǒ e 2) i N N R S Ǔ 2 ) 4kTR S Ǔ 2 ) 2ǒi R Ǔ ) 2ǒ4kTR G Ǔ I F F D Dividing this expression by the differential noise gain (G D = (1 + 2R F/R G)) gives the equivalent input referred spot noise voltage at the noninverting input, as shown in Equation 21. ei + Ǹ 2 (21) ǒ eN 2 ) ǒi N Ǔ ǒ Ǔ ǒ R SǓ ) 4kTR S ) 2 2 i IR F GD 2 )2 = ±2.0mV ± 0.12mV Ǔ 4kTR F GD THERMAL ANALYSIS Due to the high output power capability of the OPA2613, heat-sinking or forced airflow may be required under extreme operating conditions. Maximum desired junction temperature sets the maximum allowed internal power dissipation as described below. In no case should the maximum junction temperature be allowed to exceed 150°C. Operating junction temperature (TJ) is given by TA + PD × qJA. The total internal power dissipation (PD) is the sum of quiescent power (PDQ) and additional power dissipation in the output stage (PDL) to deliver load power. Quiescent power is the specified no-load supply current times the total supply voltage across the part. PDL depends 23 
"#$% www.ti.com SBOS249H − JUNE 2003 − REVISED AUGUST 2008 on the required output signal and load, but for a grounded resistive load, PDL is at a maximum when the output is fixed at a voltage equal to 1/2 of either supply voltage (for equal bipolar supplies). Under this condition, PDL = VS2/(4 × RL) where RL includes feedback network loading. Note that it is the power in the output stage and not into the load that determines internal power dissipation. As a worst-case example, compute the maximum TJ using an OPA2613 SO-8 in the circuit of Figure 1 operating at the maximum specified ambient temperature of +85°C with both outputs driving a grounded 20Ω load to +3.0V. PD = 12V × 13.0mA + 2 × [62/ (4 × (20Ω  804Ω))] = 1. 08W Maximum TJ = +85°C + (1.08W × 125°C/W) = 220°C This absolute worst-case condition exceeds specified maximum junction temperature. This extreme case is not normally encountered. Where high internal power dissipation is anticipated, consider the thermal slug package version. Under the same worst case conditions the junction temperature will drop to 139°C with the 50°C/W thermal impedance available using the PSO-8 package. BOARD LAYOUT GUIDELINES Achieving optimum performance with a high-frequency amplifier like the OPA2613 requires careful attention to board layout parasitic and external component types. Recommendations that optimize performance include: a) Minimize parasitic capacitance to any AC ground for all of the signal I/O pins. Parasitic capacitance on the output and inverting input pins can cause instability; on the noninverting input, it can react with the source impedance to cause unintentional band limiting. To reduce unwanted capacitance, a window around the signal I/O pins should be opened in all of the ground and power planes around those pins. Otherwise, ground and power planes should be unbroken elsewhere on the board. b) Minimize the distance (< 0.25″) from the power-supply pins to high-frequency 0.1µF decoupling capacitors. At the device pins, the ground and power plane layout should not be in close proximity to the signal I/O pins. Avoid narrow power and ground traces to minimize inductance between the pins and the decoupling capacitors. The power-supply connections (on pins 4 and 7) should always be decoupled with these capacitors. An optional supply decoupling capacitor across the two power supplies (for bipolar operation) improves 2nd-harmonic distortion performance. Larger (2.2µF to 6.8µF) decoupling capacitors, effective at a lower frequency, should also be used on the main supply pins. These can be placed somewhat farther from the device and may be shared among several devices in the same area of the PCB. 24 c) Careful selection and placement of external components preserve the high-frequency performance of the OPA2613. Resistors should be of a very low reactance type. Surface-mount resistors work best and allow a tighter overall layout. Metal film and carbon composition axially leaded resistors can also provide good high-frequency performance. Again, keep the leads and PC board trace length as short as possible. Never use wire-wound type resistors in a high-frequency application. Although the output pin and inverting input pin are the most sensitive to parasitic capacitance, always position the feedback and series output resistor, if any, as close as possible to the output pin. Other network components, such as noninverting input termination resistors, should also be placed close to the package. Where double-side component mounting is allowed, place the feedback resistor directly under the package on the other side of the board between the output and inverting input pins. The 402Ω feedback resistor used in the Typical Characteristics at a gain of +2 on ±6V supplies is a good starting point for design. d) Connections to other wideband devices on the board may be made with short direct traces or through onboard transmission lines. For short connections, consider the trace and the input to the next device as a lumped capacitive load. Relatively wide traces (50mils to 100mils) should be used, preferably with ground and power planes opened up around them. Estimate the total capacitive load and set RS from the plot of Recommended RS vs Capacitive Load. Low parasitic capacitive loads (< 5pF) may not need an RS because the OPA2613 is nominally compensated to operate with a 2pF parasitic load. If a long trace is required, and the 6dB signal loss intrinsic to a doubly-terminated transmission line is acceptable, implement a matched impedance transmission line using microstrip or stripline techniques (consult an ECL design handbook for microstrip and stripline layout techniques). A 50Ω environment is normally not necessary on board; in fact, a higher impedance environment improves distortion (see the distortion versus load plots). With a characteristic board trace impedance defined based on board material and trace dimensions, a matching series resistor into the trace from the output of the OPA2613 is used, as well as a terminating shunt resistor at the input of the destination device. Remember also that the terminating impedance is the parallel combination of the shunt resistor and the input impedance of the destination device. 
"#$% www.ti.com SBOS249H − JUNE 2003 − REVISED AUGUST 2008 This total effective impedance should be set to match the trace impedance. The high output voltage and current capability of the OPA2613 allows multiple destination devices to be handled as separate transmission lines, each with their own series and shunt terminations. If the 6dB attenuation of a doubly-terminated transmission line is unacceptable, a long trace can be series-terminated at the source end only. Treat the trace as a capacitive load in this case and set the series resistor value as shown in the plot of RS vs Capacitive Load. However, this does not preserve signal integrity as well as a doubly-terminated line. If the input impedance of the destination device is low, there is some signal attenuation due to the voltage divider formed by the series output into the terminating impedance. e) Socketing a high-speed part like the OPA2613 is not recommended. The additional lead length and pin-to-pin capacitance introduced by the socket can create an extremely troublesome parasitic network, which can make it almost impossible to achieve a smooth, stable frequency response. Best results are obtained by soldering the OPA2613 onto the board. INPUT AND ESD PROTECTION The OPA2613 is built using a high-speed complementary bipolar process. The internal junction breakdown voltages are relatively low for these very small geometry devices and are reflected in the absolute maximum ratings table. All device pins have limited ESD protection using internal diodes to the power supplies, as shown in Figure 15. These diodes provide moderate protection to input overdrive voltages above the supplies as well. The protection diodes can typically support 30mA continuous current. Where higher currents are possible (for example, in systems with ±15V supply parts driving into the OPA2613), current-limiting series resistors should be added into the two inputs. Keep these resistor values as low as possible, because high values degrade both noise performance and frequency response. +VCC External Pin Internal Circuitry −VCC Figure 15. Internal ESD Protection 25 www.ti.com SBOS249H − JUNE 2003 − REVISED AUGUST 2008 Revision History DATE REV PAGE SECTION 8/08 H 2 Absolute Maximum Ratings   9/07 G DESCRIPTION Changed Storage Temperature minimum value from −40°C to −65°C. Deleted all references to PSO−8 (OPA2613H) package. 1 Description Deleted last paragraph. 25 Board Layout Guidelines Deleted paragraph (F). NOTE: Page numbers for previous revisions may differ from page numbers in the current version. 26 PACKAGE OPTION ADDENDUM www.ti.com 14-Oct-2022 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) Samples (4/5) (6) OPA2613ID ACTIVE SOIC D 8 75 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 85 OPA 2613 Samples OPA2613IDR ACTIVE SOIC D 8 2500 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 85 OPA 2613 Samples (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of