OPA2673IRGVT

OPA2673 SBOS382G – JUNE 2008 – REVISED DECEMBER 2021 OPA2673 Dual, High Output Current Operational Amplifier With Active Off-Line Control 1 Features 3 Description • • • • • The OPA2673 provides the high output current and low distortion required for power-line modem driver and test and measurement applications. The OPA2673 operates on power-supplies ranging from 5.75 V to 13 V and consumes a low 16.5 mA/channel quiescent current to deliver a very high 700 mA output current. The OPA2673 can support the most demanding power-line modem requirements with 460 mA assured minimum output current drive (at 25 °C). • • • • • Wideband operation: 340 MHz (G = 4V/V) Unity-gain stable: 600 MHz (G = 1V/V) High output current: 700 mA Active off-line mode for TDMA Adjustable power modes: – Full-bias mode: 16.5 mA/channel – 75% bias mode: 12.5 mA/channel – 50% bias mode: 8.5 mA/channel – Off-Line mode: 2.4 mA/channel Bipolar-supply range: ±3.5 V to ±6.5 V Single-supply range: 5.75 V to 13 V High slew rate: 3500 V/µs Overtemperature protection circuit Output current limit (±1 A) Power control features are included to minimize system power consumption. Two logic control lines allow four quiescent power settings: full power, 75% bias power, 50% bias power and offline mode with active offline control to present a high impedance even with large signals present at the output pin. The two channels of OPA2673 can be used independently as individual opamps or can be configured as a differential-input to differential-output, high current line driver. 2 Applications • • • • • • Power-line modems Matched I/Q channel amplifiers Broadband video line drivers ARB line drivers High cap load drivers Ultrasonic-Piezo drivers Device Information(1) PART NUMBER OPA2673 (1) PACKAGE BODY SIZE (NOM) VQFN (16) 4.00 mm × 4.00 mm For all available packages, see the orderable addendum at the end of the data sheet. RG1 35.7 +12V RF1 250 +6 V 1/2 OPA2673 + 511W +6.0V 2kW 5W RSOURCE 50  1:1.4 U1 OPA2673 –6 V 50W 8VPP + 348W 511W 5W RG2 35.7  RS1 40.2  RT 30  1mF 2VPP 2kW RT1 100  50-
Transmission Line (TL2) RF2 250  +6 V VIN VOUT RLOAD 50  RS2 40.2 – 1/2 OPA2673 Single-Supply PLC Line Driver + RT2 100  U1 OPA2673 –6 V 50 Ω Transmission Line Driver An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. OPA2673 www.ti.com SBOS382G – JUNE 2008 – REVISED DECEMBER 2021 Table of Contents 1 Features............................................................................1 2 Applications..................................................................... 1 3 Description.......................................................................1 4 Revision History.............................................................. 2 5 Device Family Comparison Table.................................. 4 6 Pin Configuration and Functions...................................5 7 Specifications.................................................................. 6 7.1 Absolute Maximum Ratings........................................ 6 7.2 ESD Ratings............................................................... 6 7.3 Recommended Operating Conditions.........................6 7.4 Thermal Information....................................................7 7.5 Electrical Characteristics: Full Bias and Offline Mode VS = ±6 V.............................................................7 7.6 Electrical Characteristics: 75% Bias Mode VS = ±6 V............................................................................... 9 7.7 Electrical Characteristics: 50% Bias Mode VS = ±6 V............................................................................. 10 7.8 Typical Characteristics: VS = ±6 V, Full Bias............. 11 7.9 Typical Characteristics: VS = ±6 V Differential, Full Bias.......................................................................15 7.10 Typical Characteristics: VS = ±6 V, 75% Bias......... 17 7.11 Typical Characteristics: VS = ±6 V, 50% Bias..........18 8 Detailed Description......................................................19 8.1 Overview................................................................... 19 8.2 Functional Block Diagram......................................... 19 8.3 Feature Description...................................................19 8.4 Device Functional Modes..........................................25 9 Application and Implementation.................................. 26 9.1 Application Information............................................. 26 10 Power Supply Recommendations..............................28 10.1 Thermal Analysis.................................................... 28 10.2 Input and ESD Protection....................................... 28 11 Layout........................................................................... 29 11.1 Layout Guidelines................................................... 29 11.2 Layout Example...................................................... 30 12 Device and Documentation Support..........................31 12.1 Receiving Notification of Documentation Updates..31 12.2 Support Resources................................................. 31 12.3 Trademarks............................................................. 31 12.4 Electrostatic Discharge Caution..............................31 12.5 Glossary..................................................................31 13 Mechanical, Packaging, and Orderable Information.................................................................... 31 4 Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision F (April 2010) to Revision G (December 2021) Page • Added Device Information table, Pin Functions table, ESD Ratings table, Recommended Operating Conditions table, Thermal Information table, Overview section, Functional Block Diagram section, Feature Description section, Device Functional Modes section, Application and Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information section ..................................................................................................1 • Updated the numbering format for tables, figures, and cross-references throughout the document..................1 • Changed the title of the Related Products section to Device Family Comparison Table ................................... 4 • Deleted Package/Ordering Information table......................................................................................................4 • Changed the title of the Pin Configuration section to Pin Configuration and Functions .................................... 5 • Changed QFN to VQFN throughout the document.............................................................................................5 • Changed all input pin current limit from ±30 mA to ±10 mA............................................................................... 6 • Added new thermal metric table......................................................................................................................... 7 • Changed SSBW across temperaure at G = 4 V/V from 260 MHz to 300 MHz................................................... 7 • Changed SSBW across temperaure at G = 8 V/V from 260 MHz to 300 MHz................................................... 7 • Added new specifications for LSBW at gain of 9 V/V and 8 V/V........................................................................ 7 • Changed LSBW at G = 4 V/V from 300 MHz to 144 MHz ................................................................................. 7 • Changed Slew Rate specification from 3000 V/µs to 3500 V/µs........................................................................ 7 • Changed HD2 from -68 dBc to -70 dBc.............................................................................................................. 7 • Changed HD3 from -72 dBc to -73 dBc.............................................................................................................. 7 • Changed noninverting input current noise from 5.2 pA/√Hz to 3 pA/√Hz........................................................... 7 • Changed inverting input current noise from 35 pA/√Hz to 25 pA/√Hz................................................................ 7 • Changed crosstalk from -92 dBc to -85 dBc....................................................................................................... 7 • Changed typical noninverting input resistance from 1.5 MΩ to 3 MΩ.................................................................7 • Changed minimum inverting input resistance from 16Ω to 10Ω......................................................................... 7 • Changed typical short circuit current limit from ±800 mA to ±1000 mA.............................................................. 7 • Changed typical closed-loop output impedance from 10 mΩ to 0.4 mΩ............................................................ 7 2 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: OPA2673 OPA2673 www.ti.com • • • • • • • • • • SBOS382G – JUNE 2008 – REVISED DECEMBER 2021 Changed maximum quiescent current at full bias from 38 mA to 42 mA............................................................7 Changed maximum quiescent current across temperature at full bias from 42 mA to 46 mA ...........................7 Added +PSRR specification................................................................................................................................7 Added AC performance data at 75% Bias.......................................................................................................... 9 Changed HD3 spec at 75% bias from -66 dBc to -72 dBc..................................................................................9 Changed maximum quiescent current at 75% bias from 29 mA to 31 mA......................................................... 9 Added AC performance data at 50% Bias........................................................................................................ 10 Changed HD3 spec at 50% bias from -60 dBc to -70 dBc................................................................................10 Quiescent current at 75% and 50% bias condition at room temperature and across temperature increased by 2mA.................................................................................................................................................................. 10 Changed maximum quiescent current at full bias from 19 mA to 21 mA..........................................................10 Changes from Revision E (April 2010) to Revision F (May 2010) Page • Added minimum operating voltage (single supply) parameter............................................................................6 Changes from Revision D (January 2010) to Revision E (April 2010) Page • Revised Absolute Maximum Ratings table; deleted lead temperature specification, changed storage temperature range from -40°C to -65°C..............................................................................................................6 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: OPA2673 3 OPA2673 www.ti.com SBOS382G – JUNE 2008 – REVISED DECEMBER 2021 5 Device Family Comparison Table 4 SINGLES DUALS TRIPLES NOTES OPA691 OPA2691 OPA3691 Single +12 V capable — THS6042 — ±15 V capable — OPA2677 — Single +12 V capable — OPA2674 — Single +12 V capable, output current limit Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: OPA2673 OPA2673 www.ti.com SBOS382G – JUNE 2008 – REVISED DECEMBER 2021 (1) +VS OUT B 14 13 (1) NC 15 16 OUT A 6 Pin Configuration and Functions (1) 11 -IN B +IN A 3 10 + IN B GND 4 9 NC (1) 5 (1) NC 8 2 A0 -IN A 7 NC -VS 12 6 1 NC A1 Figure 6-2. RGV Package, 16-Pin VQFN (Bottom View) Figure 6-1. RGV Package, 16-Pin VQFN (Top View) Table 6-1. Pin Functions PIN NAME NO. A0 8 A1 GND TYPE(2) DESCRIPTION I Bias Mode Control 9 I Bias Mode Control 4 P Ground –IN A 2 I Amplifier A inverting input +IN A 3 I Amplifier A noninverting input –IN B 11 I Amplifier B inverting input +IN B 10 I Amplifier B noninverting input NC(1) 1, 5, 6, 12, 15 — Do not connect. OUT A 16 O Amplifier A output OUT B 13 O Amplifier B output –VS 7 P Negative power-supply connection +VS 14 P Positive power-supply connection Thermal Pad — Electrically connected to die substrate and VS–. Connect to VS– on the PCB for best performance. (1) (2) There is no internal connection. Typically GND is the recommended connection to a heat spreading plane. I = input, O = output, P = power, GND = ground, NC = no connect. Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: OPA2673 5 OPA2673 www.ti.com SBOS382G – JUNE 2008 – REVISED DECEMBER 2021 7 Specifications 7.1 Absolute Maximum Ratings over operating free-air temperature range (unless otherwise noted)(1) MIN MAX 0 VS- + 5 All pins except VS+, VS– and Bias control pins VS– VS+ GND Pin VS– VS+ Supply voltage, VS = (VS+) – (VS–)(2) 13 Bias control pin voltage, referenced to GND Voltage Output pin: Offline mode ±4.5 Inverting input pin: Offline mode ±1.1 Differential input voltage (each amplifier) Current ±10 139 condition)(3) 150 Storage, Tstg (1) (2) (3) mA See Thermal Information Continuous operating junction temperature(3) Maximum junction, TJ (under any V ±2 All input pins, current limit Continuous power dissipation Temperature UNIT –65 °C 150 Operation outside the Absolute Maximum Rating may cause permanent device damage. Absolute maximum ratings do not imply functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Condition. If briefly operating outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not sustain damage, but it may not be fully functional. Operating the device in this manner may affect device reliability, functionality, performance, and shorten the device lifetime. Refer to Breakdown Test. The absolute maximum junction temperature for continuous operation is limited by the package constraints. Operation above this temperature can result in reduced reliability and/or lifetime of the device. OPA2673 has thermal protection that shuts down the device at approximately 180°C junction temperature and recovery at approximately 160°C. 7.2 ESD Ratings VALUE V(ESD) (1) (2) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins(1) ±2000 Charged device model (CDM), per ANSI/ESDA/JEDEC JS-002, all pins(2) ±1500 UNIT V JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. 7.3 Recommended Operating Conditions over operating free-air temperature range (unless otherwise noted) MIN MAX VS Supply voltage, Dual Supply ±3.5 ±6.5 VS Supply voltage, Single Supply 5.75 13 GND GND pin voltage VS– TA Ambient operating air temperature –40 Thermal (1) 6 NOM Shutdown(1) UNIT V VS+ – 2.5 25 85 180 °C OPA2673 has thermal protection that shuts down the device at approximately 180°C junction temperature and recovery at approximately 160°C. Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: OPA2673 OPA2673 www.ti.com SBOS382G – JUNE 2008 – REVISED DECEMBER 2021 7.4 Thermal Information OPA2673A THERMAL METRIC(1) UNIT RGV (VQFN) 16 PINS RθJA Junction-to-ambient thermal resistance 43 °C/W RθJC(top) Junction-to-case (top) thermal resistance 43 °C/W RθJB Junction-to-board thermal resistance 18 °C/W ΨJT Junction-to-top characterization parameter 1.1 °C/W YJB Junction-to-board characterization parameter 18 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance 2.5 °C/W (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report. 7.5 Electrical Characteristics: Full Bias and Offline Mode VS = ±6 V At TA = +25°C, A0 = A1 = 0 (full power), G = + 4V/V, RF = 402 Ω, and RL = 100 Ω, CL = 1 pF, unless otherwise noted. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT AC PERFORMANCE(1) SSBW Small-signal bandwidth G = 1 V/V, RF = 511 Ω, VO = 0.5 VPP 600 G = 2 V/V, RF = 475 Ω, VO = 0.5 VPP 450 G = 4 V/V, RF = 402 Ω, VO = 0.5 VPP G = 8 V/V, RF = 250 Ω, VO = 0.5 VPP LSBW 270 340 Peaking at G = 1V/V G = 1V/V, RF = 511 Ω 1.5 dB Peaking at G = 4V/V G = 4V/V, RF = 402 Ω 0.1 dB Large-signal bandwidth G = 9 V/V, RF = 250 Ω, VO = 9 VPP 230 Large-signal bandwidth G = 8 V/V, RF = 250 Ω, VO = 5 VPP 330 Slew rate (20% to 80%) Rise and fall time (10% to 90%) HD MHz 300 300 ±0.1-dB bandwidth flatness HD 340 G = 8 V/V, TA = –40°C to 85°C Large-signal bandwidth SR 270 G = 4 V/V, TA = –40°C to 85°C 2nd-order harmonic distortion 3rd-order harmonic distortion 2nd-order harmonic distortion 3rd-order harmonic distortion en Input voltage noise in+ Noninverting input current noise in- Inverting input current noise en Input voltage noise in+ Noninverting input current noise in- Inverting input current noise Channel-to-channel crosstalk 70 VO = 5-V step TA = –40°C to 85°C 3500 1.2 ns –70 VO = 2 VPP, 20 MHz, RL = 50 Ω –73 dBc –63 –61 2.4 f ≥ 1 MHz, input-referred V/µs 2300 VO = 2-V Step VO = 2 VPP, 20 MHz, RL = 50 Ω, TA = –40°C to 85°C MHz 144 G = 4 V/V, VO = 5 VPP 2.62 nV/√Hz 3 4.6 25 30 pA/√Hz 4.2 nV/√Hz f ≥ 1 MHz, input-referred, TA = –40°C to 85°C 8.3 35 f ≥ 1 MHz, input-referred –85 pA/√Hz dBc Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: OPA2673 7 OPA2673 www.ti.com SBOS382G – JUNE 2008 – REVISED DECEMBER 2021 7.5 Electrical Characteristics: Full Bias and Offline Mode VS = ±6 V (continued) At TA = +25°C, A0 = A1 = 0 (full power), G = + 4V/V, RF = 402 Ω, and RL = 100 Ω, CL = 1 pF, unless otherwise noted. PARAMETER TEST CONDITIONS MIN TYP 60 90 MAX UNIT DC PERFORMANCE ZOL Open-loop transimpedance gain Input offset voltage (each amplifier) Input offset voltage mismatching Input offset voltage drift Noninverting input bias current Inverting input bias current Noninverting input bias current matching Inverting input bias current matching Noninverting input bias current drift Inverting input bias current drift TA= –40°C to 85°C kΩ 55 ±2 TA = –40°C to 85°C ±7 ±9 Amplifier A to B ±0.5 TA = –40°C to 85°C ±2.2 mV ±2.5 TA = –40°C to 85°C ±30 ±5 TA = –40°C to 85°C ±28 ±6 TA = –40°C to 85°C µV/°C ±25 ±48 µA ±55 ±0.5 ±5 ±6 ±25 TA = –40°C to 85°C ±7 TA = –40°C to 85°C µA ±30 ±47 TA = –40°C to 85°C ±110 nA/°C INPUT CHARACTERISTICS CMIR Common-mode input range CMRR Common-mode rejection ratio ±3.5 TA= –40°C to 85°C 50 TA = –40°C to 85°C V 56 dB 47 Noninverting input resistance 3 || 1.5 Inverting input resistance Shutdown Isolation,Offline Mode ±3.6 ±3.2 10 Input to Output Isolation at 1 MHz 24 85 MΩ || pF 40 Ω dB OUTPUT CHARACTERISTICS VO VO IO 8 Output voltage swing(2) Output voltage swing(2) Output current (sourcing and sinking) (2) No Load ±4.8 No Load, TA = –40°C to 85℃ ±4.7 RL = 100 Ω ±4.75 RL = 100 Ω, TA = –40°C to 85℃ ±4.65 RL = 25 Ω ±4.5 RL = 25 Ω, TA = –40°C to 85℃ ±4.4 RL = 4 Ω ±460 RL = 4 Ω, TA = –40°C to 85℃ ±425 Short-circuit output current Sourcing and Sinking ZOUT Closed-Loop output impedance f = 100 kHz ZO Open-Loop Output impedance f = 100 kHz, Offline Mode Submit Document Feedback ±4.9 V ±4.9 ±4.7 ±700 ±1000 0.4 25 || 4.5 V mA mA mΩ kΩ || pF Copyright © 2021 Texas Instruments Incorporated Product Folder Links: OPA2673 OPA2673 www.ti.com SBOS382G – JUNE 2008 – REVISED DECEMBER 2021 7.5 Electrical Characteristics: Full Bias and Offline Mode VS = ±6 V (continued) At TA = +25°C, A0 = A1 = 0 (full power), G = + 4V/V, RF = 402 Ω, and RL = 100 Ω, CL = 1 pF, unless otherwise noted. PARAMETER TEST CONDITIONS MIN TYP MAX 33 42 UNIT POWER SUPPLY Full bias (A0 = 0, A1 = 0) IQ Quiescent current, Total both channels Full bias, TA = –40°C to 85°C 46 Offline Mode (A0 = 1, A1 = 1) 5.5 Offline Mode, TA = –40°C to 85°C +PSRR Positive power-supply rejection ratio –PSRR Negative power-supply rejection ratio TA = –40°C to 85℃ 7.2 mA 9 57 60 47 55 dB BIAS CONTROL Bias control pin logic threshold Bias control pin current (1) (2) (3) Logic 1, with respect to GND 2 Logic 0, with respect to GND 0.8 A0, A1 = 0.5 V(3) , TA = –40°C to 85°C 30 A0, A1 = 3.3 V, TA = –40°C to 85°C 150 V µA Min/Max limits for AC performance set by design See Output Headroom vs Output Current for output voltage vs output current characteristics. Current flows into the pins. 7.6 Electrical Characteristics: 75% Bias Mode VS = ±6 V At TA = +25°C, A0 = 1, A1 = 0 (75% Bias ), G = + 4V/V, RF = 402 Ω, and RL = 100 Ω, CL = 1 pF, unless otherwise noted. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT AC PERFORMANCE SSBW Small-signal bandwidth G = 4 V/V, RF = 402 Ω, VO = 0.5 VPP 310 LSBW Large-signal bandwidth VO = 4 VPP 160 SR Slew rate (20% to 80%) VO = 5-V step HD2 2nd-order harmonic distortion HD3 3rd-order harmonic distortion en input voltage noise Input offset voltage (each amplifier) IO Output current (sourcing and sinking) Short-circuit output current 3000 V/µs -69 VO = 2 VPP, 20 MHz ,RL = 50 Ω dBc -72 f ≥ 1 MHz, input-referred 2.6 ±2 TA = –40°C to 85°C nV/√Hz ±7 ±9 RL = 4 Ω ±350 RL = 4 Ω, TA = –40°C to 85℃ ±300 Sourcing and Sinking MHz mV ±500 mA ±1000 POWER SUPPLY IQ Quiescent current, Total both channels 25 TA = –40°C to 85°C 31 34 mA Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: OPA2673 9 OPA2673 www.ti.com SBOS382G – JUNE 2008 – REVISED DECEMBER 2021 7.7 Electrical Characteristics: 50% Bias Mode VS = ±6 V At TA = +25°C, A0 = 0 , A1 = 1 (50% Bias ), G = + 4V/V, RF = 402 Ω, and RL = 100 Ω, CL = 1 pF, unless otherwise noted. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT AC PERFORMANCE SSBW Small-signal bandwidth G = 4 V/V, RF = 402 Ω, VO = 0.5 VPP 260 LSBW Large-signal bandwidth VO = 4 VPP 140 SR Slew rate (20% to 80%) VO = 5-V step HD2 2nd-order harmonic distortion HD3 3rd-order harmonic distortion en input voltage noise Input offset voltage (each amplifier) IO Output current (sourcing and sinking) Short-circuit output current 2700 V/µs -66 VO = 2 VPP, 20 MHz, RL = 50 Ω dBc -70 f ≥ 1 MHz, input-referred 3.2 ±2 TA = –40°C to 85°C nV/√Hz ±7 ±9 RL = 4 Ω ±120 RL = 4 Ω, TA = –40°C to 85℃ ±110 Sourcing and Sinking MHz mV ±180 mA ±1000 POWER SUPPLY IQ 10 Quiescent current, Total both channels 17 TA = –40°C to 85°C Submit Document Feedback 21 23 mA Copyright © 2021 Texas Instruments Incorporated Product Folder Links: OPA2673 OPA2673 www.ti.com SBOS382G – JUNE 2008 – REVISED DECEMBER 2021 7.8 Typical Characteristics: VS = ±6 V, Full Bias 3 3 0 0 Normalized Gain (dB) -3 -6 -12 10M G = 1 V/V, RF = 511  G = 2 V/V, RF = 475  G = 4 V/V, RF = 402  G = 8 V/V, RF = 250  -6 -9 100M Frequency (Hz) Full Bias 75% Bias 50% Bias -12 1G 0 VO = 500 mVPP Small Signal Output Voltage (mV) Normalized Gain (dB) 0 -3 -12 10M 600 VO = 1 VPP VO = 2 VPP VO = 5 VPP VO = 8 VPP VO = 5 VPP, G = 8 V/V VO = 9 VPP, G = 9 V/V 300 3 200 2 100 1 0 0 -100 -200 -300 100M Frequency (Hz) -1 Small Signal 200 mVPP Large Signal 5 VPP -2 -3 1G Time (5ns/div) . Full Bias Mode Figure 7-3. Large-Signal Frequency Response Figure 7-4. Small-Signal and Large-Signal Pulse Responses 3 300 3 200 2 200 2 100 1 100 1 0 0 0 0 -100 -200 -1 Small Signal 200 mVPP Large Signal 5 VPP -300 Time (5ns/div) Output Voltage (mV) 300 Output Voltage (V) Output Voltage (mV) 500 Figure 7-2. Small-Signal Frequency Response Over Power Settings 3 -9 200 300 400 Freqeuncy (MHz) VO = 500 mVPP Figure 7-1. Small-Signal Frequency Response -6 100 Large Signal Output Voltage (V) -9 -3 -100 -2 -200 -3 -300 -1 Small Signal 200 mVPP Large Signal 5 VPP Output Voltage (V) Normalized Gain (dB) At TA = +25°C, G = +4 V/V, RF = 402 Ω, and RL = 100 Ω, unless otherwise specified. -2 -3 Time (5ns/div) D010 75% Bias Mode 50% Bias Mode Figure 7-5. Small-Signal and Large-Signal Pulse Responses Figure 7-6. Small-Signal and Large-Signal Pulse Responses Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: OPA2673 11 OPA2673 www.ti.com SBOS382G – JUNE 2008 – REVISED DECEMBER 2021 7.8 Typical Characteristics: VS = ±6 V, Full Bias (continued) At TA = +25°C, G = +4 V/V, RF = 402 Ω, and RL = 100 Ω, unless otherwise specified. 30 -40 25 -50 20 15 Crosstalk (dB) Voltage (V) 10 5 0 -5 -10 -60 -70 -80 -15 -20 VIN  4 V/V VOUT -25 -30 -90 Channel 1 to Channel 2 Channel 2 to Channel 1 -100 1M 10M Frequency (Hz) Time, 50ns/div . Input-Referred Figure 7-8. Channel-to-Channel Crosstalk -60 -30 -65 -40 -70 -50 Harmonic Distortion (dBc) Harmonic Distortion (dBc) Figure 7-7. Overdrive Recovery -75 -80 -85 -90 -95 -100 10M Frequency (Hz) -60 -70 -80 -90 -100 HD2 HD3 -110 HD2 HD3 -105 -110 1M -120 0 100M 1 2 3 4 5 6 7 Output Voltage (V PP) -70 10 -60 HD2 HD3 -80 -85 -90 HD2 HD3 -65 Harmonic Distortion (dBc) -75 Harmonic Distortion (dBc) 9 Figure 7-10. Harmonic Distortion vs Output Voltage Figure 7-9. Harmonic Distortion vs Frequency -70 -75 -80 -85 -95 -90 100 1k 1 Resistance () 2 3 4 5 6 Gain (V/V) 7 8 9 10 VO = 2 VPP, f = 20 MHz VO = 2 VPP, f = 20 MHz Figure 7-11. Harmonic Distortion vs Load Resistance 12 8 f = 20 MHz VO = 2 VPP -100 50 100M Figure 7-12. Harmonic Distortion vs Noninverting Gain Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: OPA2673 OPA2673 www.ti.com SBOS382G – JUNE 2008 – REVISED DECEMBER 2021 7.8 Typical Characteristics: VS = ±6 V, Full Bias (continued) At TA = +25°C, G = +4 V/V, RF = 402 Ω, and RL = 100 Ω, unless otherwise specified. 80 -50 Harmonic Distortion (dBc) -55 -60 -65 -70 -75 -80 -85 -90 2.5 3 3.5 4 4.5 5 Supply Voltage (±Vs) 5.5 +PSRR −PSRR 70 Power-Supply Rejection Ratio (dB) HD2 HD3 60 50 40 30 20 10 0 1k 6 10k VO = 2 VPP, f = 20 MHz 120 -30 100 -60 80 -90 60 -120 40 -150 20 -180 -20 10k -210 100k 1M 10M Frequency (Hz) 100M 100M Figure 7-14. CMRR and PSRR vs Frequency 100 Voltage Noise Density (nV/Hz) Current Noise Density (pA/Hz) 0 Transimpedance Phase () Transimpedance Gain (dB) 140 Gain Phase 10M . Figure 7-13. Harmonic Distortion vs Supply Voltage 0 100k 1M Frequency (Hz) -240 1G Noninverting Current Noise Voltage Noise Inverting Current Noise 10 1 100 1k . 10k 100k Frequency (Hz) 1M 10M . Figure 7-15. Open-Loop Transimpedance Gain and Phase 10 Figure 7-16. Input Voltage and Current Noise Density 100k Open Loop Closed Loop, RF = 402 , G = 4 V/V Output Impedance () Impedance () 1 0.1 10m 10k 1k 1m 0.1m 10k 100k 1M Frequency (Hz) 10M 100M 100 10k . 100k 1M 10M Frequency (Hz) 100M 1G Single-Ended Figure 7-17. Closed-Loop Output Impedance vs Frequency Figure 7-18. Active Off-Line Impedance vs Frequency Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: OPA2673 13 OPA2673 www.ti.com SBOS382G – JUNE 2008 – REVISED DECEMBER 2021 7.8 Typical Characteristics: VS = ±6 V, Full Bias (continued) At TA = +25°C, G = +4 V/V, RF = 402 Ω, and RL = 100 Ω, unless otherwise specified. 2.25 Noninverting Bias Current Inverting Bias Current Input Offset Voltage 8 2 0 1.75 -0.5 1.5 -1 1.25 -1.5 1 -2 6 4 Voltage (V) 0.5 10 Input Offset Voltage (mV) Inverting Input Bias Current (PA) Noninverting Input Bias Current (PA) 1 2 0 -2 -4 A0, A1 OUT A OUT B OUT A - OUT B -6 0.75 -8 -2.5 -50 -25 0 25 50 Temperature (qC) 0.5 100 75 -10 Time (100ns/div) D027 . . Figure 7-19. Typical DC Drift Over Temperature Figure 7-20. Full Bias Mode to Offline Mode Transition Time 60 50 Full Bias 75% Bias 50% Bias Offline 40 Full Bias Mode Offline Mode 75% Bias Mode 50% Bias Mode 55 50 Quiescent Current (mA) Quiescent Current (mA) 45 35 30 25 20 15 10 45 40 35 30 25 20 15 10 5 5 0 5 6 7 8 9 10 11 Total Supply Voltage (VS) 12 13 0 -50 -25 . 25 50 Temperature (C) 75 100 . Figure 7-21. Supply Current vs Supply Voltage 14 0 Figure 7-22. Supply Current vs Temperature Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: OPA2673 OPA2673 www.ti.com SBOS382G – JUNE 2008 – REVISED DECEMBER 2021 7.9 Typical Characteristics: VS = ±6 V Differential, Full Bias At TA = +25°C, RF = 511 Ω, RL = 100 Ω Differential, GDIFF = +4 V/V, and GCM = +1 V/V, unless otherwise specified. 12 3 9 0 Normalized Gain (dB) Normalized Gain (dB) 6 3 0 -3 -6 -9 GDIFF = 1 V/V GDIFF = 2 V/V GDIFF = 4 V/V GDIFF = 8 V/V -12 -15 -18 10M -3 -6 -9 -12 VO = 0.5 VPP VO = 4 VPP VO = 8 VPP VO = 16 VPP -15 100M Frequency (Hz) -18 10M 1G 100M Frequency (MHz) VO = 500 mVPP . Figure 7-24. Large-Signal Frequency Response 1.2 4 0.8 2 0.4 0 0 -2 -60 HD2 HD3 -0.4 -0.8 Large Signal 8 VPP Small Signal 1 VPP -6 Harmonic Distortion (dBc) 6 Output Voltage (V) Output Voltage (V) Figure 7-23. Small-Signal Frequency Response -4 -1.2 -70 -80 -90 -100 -110 1M Time (10ns/div) 10M Frequency (MHz) D42_ . VO = 2 VPP Figure 7-25. Small-Signal and Large-Signal Pulse Responses Figure 7-26. Harmonic Distortion vs Frequency -60 -60 HD2 HD3 HD2 HD3 -70 Harmonic Distortion (dBc) Harmonic Distortion (dBc) 1G -80 -90 -100 -110 0 1 2 3 4 5 6 7 Output Voltage (V PP) 8 9 10 -70 -80 -90 -100 -110 50 100 1k Resistance () f = 20 MHz VO = 2 VPP, f = 20 MHz Figure 7-27. Harmonic Distortion vs Output Voltage Figure 7-28. Harmonic Distortion vs Load Resistance Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: OPA2673 15 OPA2673 www.ti.com SBOS382G – JUNE 2008 – REVISED DECEMBER 2021 7.9 Typical Characteristics: VS = ±6 V Differential, Full Bias (continued) At TA = +25°C, RF = 511 Ω, RL = 100 Ω Differential, GDIFF = +4 V/V, and GCM = +1 V/V, unless otherwise specified. -60 Harmonic Distortion (dBc) HD2 HD3 -70 -80 -90 -100 1 10 Gain (V/V) VO = 2 VPP, f = 20 MHz Figure 7-29. Harmonic Distortion vs Noninverting Gain 16 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: OPA2673 OPA2673 www.ti.com SBOS382G – JUNE 2008 – REVISED DECEMBER 2021 7.10 Typical Characteristics: VS = ±6 V, 75% Bias At TA = +25°C, G = +4 V/V, RF = 402 Ω, and RL = 100 Ω, unless otherwise specified. 3 Normalized Gain (dB) Normalized Gain (dB) 0 -3 -6 -9 -12 10M G = 1 V/V, RF = 511  G = 2 V/V, RF = 475  G = 4 V/V, RF = 402  G = 8 V/V, RF = 250  100M Frequency (Hz) 1G 3 2 1 0 -1 -2 -3 -4 -5 -6 -7 -8 -9 -10 -11 -12 10M VO = 1 VPP VO = 2 VPP VO = 5 VPP VO = 8 VPP 100M Frequency (Hz) VO = 500 mVPP . Figure 7-30. Small-Signal Frequency Response Figure 7-31. Large-Signal Frequency Response -40 -30 -40 Harmonic Distortion (dBc) Harmonic Distortion (dBc) -50 -60 -70 -80 -90 -100 HD2 HD3 -50 -60 -70 -80 -90 -100 HD2 HD3 -110 -120 -110 1M 10M Frequency (Hz) 0 100M 1 2 3 4 5 6 7 Output Voltage (V PP) 9 10 Figure 7-33. Harmonic Distortion vs Output Voltage -60 -65 HD2 HD3 -75 -80 -85 -90 HD2 HD3 -65 Harmonic Distortion (dBc) -70 Harmonic Distortion (dBc) 8 f = 20 MHz VO = 2 VPP Figure 7-32. Harmonic Distortion vs Frequency -70 -75 -80 -85 -95 -100 50 1G 100 1k Resistance () -90 1 VO = 2 VPP, f = 20 MHz 2 3 4 5 6 Gain (V/V) 7 8 9 10 VO = 2 VPP, f = 20 MHz Figure 7-34. Harmonic Distortion vs Load Resistance Figure 7-35. Harmonic Distortion vs Noninverting Gain Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: OPA2673 17 OPA2673 www.ti.com SBOS382G – JUNE 2008 – REVISED DECEMBER 2021 7.11 Typical Characteristics: VS = ±6 V, 50% Bias At TA = +25°C, G = +4 V/V, RF = 402 Ω, and RL = 100 Ω, unless otherwise specified. 5 3 0 -5 Normalized Gain (dB) Normalized Gain (dB) 0 -3 -6 -9 -12 -15 -18 10M G = 1 V/V, RF = 511  G = 1 V/V, RF = 475  G = 4 V/V, RF = 402  G = 8 V/V, RF = 250  -10 -15 -20 -25 -30 -35 100M Frequency (Hz) -40 10M 1G VO = 1 VPP VO = 2 VPP VO = 4 VPP VO = 8 VPP 100M Frequency (Hz) . . Figure 7-37. Large-Signal Frequency Response -40 -30 -50 -40 Harmonic Distortion (dBc) Harmonic Distortion (dBc) Figure 7-36. Small-Signal Frequency Response -60 -70 -80 -90 -100 HD2 HD3 -110 1M 10M Frequency (Hz) -50 -60 -70 -80 -90 -100 HD2 HD3 -110 -120 100M 0 1 2 VO = 2 VPP 8 9 10 -60 HD2 HD3 -70 -75 -80 -85 -90 HD2 HD3 -65 Harmonic Distortion (dBc) -65 Harmonic Distortion (dBc) 4 5 6 7 Output Voltage (V PP) Figure 7-39. Harmonic Distortion vs Output Voltage -60 -70 -75 -80 -85 -95 -90 100 1k 1 Resistance () 2 3 4 5 6 Gain (V/V) 7 8 9 10 VO = 2 VPP, f = 20 MHz VO = 2 VPP, f = 20 MHz Figure 7-40. Harmonic Distortion vs Load Resistance 18 3 f = 20 MHz Figure 7-38. Harmonic Distortion vs Frequency -100 50 1G Figure 7-41. Harmonic Distortion vs Noninverting Gain Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: OPA2673 OPA2673 www.ti.com SBOS382G – JUNE 2008 – REVISED DECEMBER 2021 8 Detailed Description 8.1 Overview The OPA2673 is a high-speed, high-current output, current-feedback amplifier (CFA) designed to operate over a wide supply range of ±3.5 V to ±6.5 V for applications requiring large-drive currents along with wide-bandwidth. The OPA2673 features an offline-mode that enables the amplifier to operate in a high-output impedance condition ensuring no loading to the network when connected in a bus-topology. Figure 3-1 shows how the two channels of the OPA2673 can be used as two independent amplifiers or can be connected in a differential-input to differential-output configuration. 8.2 Functional Block Diagram VSIG +IN VREF + (1 + RF/RG)VSIG
(s) OUT VREF OPA2673 ZIN– ZOL(s)×Ierr -IN – Ierr RF AV = VO/VIN+ = 1 + (RF/RG) RG VREF 8.3 Feature Description The OPA2673 gives exceptional ac performance with a highly linear, high-power output stage. Requiring 16mA/ch quiescent current, the OPA2673 swings to within 1.1 V of either supply rail and delivers in excess of 460 mA at room temperature. This low output headroom requirement, along with supply voltage independent biasing, gives remarkable dual (±6 V) supply operation. The OPA2673 delivers greater than 450 MHz bandwidth driving a 2 VPP output into 100 Ω on a single +12 V supply. The primary advantage of a current-feedback op amp over a voltage-feedback op amp is that ac performance (bandwidth and distortion) is relatively independent of signal gain. Figure 8-1 shows the dc-coupled, gain of +4 V/V, dual power-supply circuit configuration used as the test circuit for the ±6 V Electrical Characteristics and Typical Characteristics. Voltage swings reported in the Electrical Characteristics are taken directly at the input and output pins. For measuring the ac performance, the output of the OPA2673 is terminated with a matched 50 Ω loading. Thus, the total effective load seen by the OPA2673 is 100 Ω || 402 Ω = 80 Ω. +6V +VS 0.1mF 6.8mF + 50W Source VI 50W VO 1/2 OPA2673 50W 50W Load RF 402W RG 133W + 6.8mF 0.1mF -VS -6V Figure 8-1. DC-Coupled, G = +4 V/V, Bipolar Supply Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: OPA2673 19 OPA2673 www.ti.com SBOS382G – JUNE 2008 – REVISED DECEMBER 2021 8.3.1 Operating Suggestions 8.3.1.1 Setting Resistor Values to Optimize Bandwidth A current-feedback op amp such as the OPA2673 can hold an almost constant bandwidth over signal gain settings with the proper adjustment of the external resistor values, which are shown in the Typical Characteristics; the small-signal bandwidth decreases only slightly with increasing gain. These characteristic curves also show that the feedback resistor is changed for each gain setting. The absolute values of RF on the inverting side of the circuit for a current-feedback op-amp can be treated as frequency response compensation element, whereas the ratios of RF and RG set the signal gain. Figure 8-2 shows the small-signal frequency response analysis circuit for the OPA2673. 600 Feedback Resistor (W) VI a VO RI Z(S) IERR IERR 500 400 300 RF 200 RG 0 5 10 15 20 Noise Gain Figure 8-2. Current-Feedback Transfer Function Analysis Circuit Figure 8-3. Feedback Resistor Versus Noise Gain The key elements of this current-feedback op amp model are: α = buffer gain from the noninverting input to the inverting input RI = buffer output impedance IERR = feedback error current signal Z(s) = frequency-dependent open-loop transimpedance gain from IERR to VO NG = Noise Gain = 1 + RF RG (1) A current-feedback op amp senses an error current in the inverting node (as opposed to a differential input error voltage for a voltage-feedback op amp) and passes this on to the output through an internal frequencydependent transimpedance gain. The Typical Characteristics show this open-loop transimpedance response, which is analogous to the open-loop voltage gain curve for a voltage-feedback op amp. Refer to the training videos shown in TI Precision Labs for further understanding on the CFA operating theory. The values for RF versus gain shown in Figure 8-3 are approximately equal to the values used to generate the Typical Characteristics and give a good starting point for designs where bandwidth optimization is desired. 8.3.1.2 Output Current and Voltage The OPA2673 provides output voltage and current capabilities that are unsurpassed in a low-cost dual monolithic op amp. Under no-load conditions at +25°C, the output voltage typically swings closer than 1.1 V to either supply rail; the tested (+25°C) swing limit is within 1.2 V of either rail. The OPA2673 is capable of delivering around 700 mA of source and sink current at room temperature. Figure 8-4 and Figure 8-5 shows the relation between current output of the OPA2673 at different temperatures and maximum voltage swing at that current output under loaded conditions. 20 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: OPA2673 OPA2673 www.ti.com SBOS382G – JUNE 2008 – REVISED DECEMBER 2021 6 8 100  Load Line 10  Load Line 6 4 Output Voltage (V) Output Voltage (V) 4 2 +85 C +25 C −40 C 0 -2 2 0 -2 -4 -4 -6 2W Internal Power Dissipation SOA Curve -8 -800 -6 0 0.2 0.4 0.6 0.8 Output Current (A) 1 1.2 Figure 8-4. Output Headroom vs Output Current -600 -400 -200 0 200 Output Current (mA) 400 600 800 Figure 8-5. Output Voltage and Current Limitations For the specifications described previously, consider voltage and current limits separately. In many applications, it is the voltage times the current (or V-I product) that is more relevant to circuit operation. See Figure 8-5. Figure 8-5 shows the zero-voltage output current limit and the zero-current output voltage limit on the X- and Y-axes, respectively. The four quadrants give a more detailed view of the OPA2673 output drive capabilities, noting that the graph is bounded by a safe operating area of 2W maximum internal power dissipation (in this case, for one channel only). Superimposing resistor load lines onto the plot shows that the OPA2673 can drive ±4 V into 10 Ω or ±4.5 V into 25 Ω without exceeding the output capabilities or the 2-W dissipation limit. A 100 Ω load line (the standard test circuit load) shows the full ±4.8 V output swing capability, as stated in the Electrical Characteristics table. 8.3.1.3 Driving Capacitive Loads One of the most demanding and yet very common load conditions for an op amp is capacitive loading. The capacitive load is often the input of an analog-to-digital converter (ADC), including additional external capacitance that may be recommended to improve the ADC linearity. A high-speed, high open-loop gain amplifier such as the OPA2673 can be very susceptible to decreased stability and closed-loop response peaking when a capacitive load is placed directly on the output pin. When the amplifier open-loop output resistance is considered, this capacitive load introduces an additional pole in the signal path that can decrease the phase margin. Several external solutions to this problem have been suggested. 133 402
+VS RISO – VI + OPA2673 49.9  –VS CL RLOAD Figure 8-6. Driving a Large Capacitive Load Using an Output Series Isolation Resistor When the primary considerations are frequency response flatness, pulse response fidelity, and distortion, the simplest and most effective solution is to isolate the capacitive load (CL) from the feedback loop by inserting a series isolation resistor (RISO) between the amplifier output and the capacitive load as shown in Figure 8-6. This approach does not eliminate the pole from the loop response, but rather shifts it and adds a zero at a higher frequency. The additional zero acts to cancel the phase lag from the capacitive load pole, thus increasing the phase margin and improving stability. Figure 8-7 and Figure 8-8 shows the Recommended RISO vs CL and the resulting frequency response with the optimized RISO value. Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: OPA2673 21 OPA2673 www.ti.com SBOS382G – JUNE 2008 – REVISED DECEMBER 2021 20 18 12 10 RISO () Gain (dB) 6 0 -6 -12 -18 10M 1 1 10 100 Capacitance (pF) 1k CL = 10 pF, RISO = 15  CL = 22 pF, RISO = 12.4  CL = 47 pF, RISO = 9.4  CL = 100 pF, RISO = 6.2  100M Frequency (Hz) 1G . . Figure 8-7. Recommended RISO vs Capacitive Load Figure 8-8. Frequency Response vs Capacitive Load 8.3.1.4 Line Driver Headroom Model The first step in a driver design is to compute the peak-to-peak output voltage from the target specifications. This calculation is done using the following equations: PL = 10 ´ log VRMS2 (1mW) ´ RL (2) With PL power and VRMS voltage at the load, and RL load impedance, this calculation gives: VRMS = (1mW) ´ RL ´ 10 P L 10 (3) VP = CrestFactor ´ VRMS = CF ´ VRMS (4) With VP peak voltage at the load and the crest factor, CF: VLPP = 2 ´ CF ´ VRMS (5) with VLPP: peak-to-peak voltage at the load. Consolidating Equation 2 through Equation 5 allows the required peak-to-peak voltage at the load function of the crest factor, the load impedance, and the power in the load to be expressed. Thus: VLPP = 2 ´ CF ´ (1mW) ´ RL ´ 10 P L 10 (6) This VLPP is usually computed for a nominal line impedance and may be taken as a fixed design target. The next step for the driver is to compute the individual amplifier output voltage and currents as a function of VPP on the line and transformer turns ratio. As the turns ratio changes, the minimum allowed supply voltage also changes. The peak current in the amplifier is given by: ±IP = 2 ´ VLPP 1 1 ´ ´ n 2 4RM (7) With VLPP defined in Equation 6 and RM defined in Equation 8. 22 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: OPA2673 OPA2673 www.ti.com RM = SBOS382G – JUNE 2008 – REVISED DECEMBER 2021 ZLINE 2n2 (8) The peak current is computed in Figure 8-9 by noting that the total load is 4RM and that the peak current is half of the peak-to-peak calculated using VLPP. ±IP RM 1:n 2VLPP n VLPP n RL VLPP RM ±IP Figure 8-9. Driver Peak Output Model With the required output voltage and current versus turns ratio set, an output stage headroom model allows the required supply voltage versus turns ratio to be developed. The headroom model (see Figure 8-10) can be described with the following set of equations: First, as available output voltage for each amplifier: VOPP = VCC - (V1 + V2) - IP ´ (R1 + R2) (9) Or, second, as required single-supply voltage: VCC = VOPP + (V1 + V2) + IP ´ (R1 + R2) (10) The minimum supply voltage for a set of power and load requirements is given by Equation 10. Where V1, V2, R1, and R2 are internal to the OPA2673, and values of the same are provided below. Table 8-1 gives V1, V2, R1, and R2 for +12-V operation of the OPA2673. +VCC R1 V1 VO IP V2 R2 Figure 8-10. Line Driver Headroom Model Table 8-1. Line Driver Headroom Model Values V1 R1 V2 R2 0.9 V 2Ω 0.9 V 2Ω Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: OPA2673 23 OPA2673 www.ti.com SBOS382G – JUNE 2008 – REVISED DECEMBER 2021 8.3.1.5 Noise Performance Wideband current-feedback op amps generally have a higher output noise than comparable voltage-feedback op amps. The OPA2673 offers an excellent balance between voltage and current noise terms to achieve low output noise. The low input voltage noise is achieved at the price of higher noninverting input current noise (3 pA/√ Hz). As long as the ac source impedance from the noninverting node is less than 100 Ω, this current noise does not contribute significantly to the total output noise. The op amp input voltage noise and the two input current noise terms combine to give low output noise under a wide variety of operating conditions. Figure 8-11 shows the op amp noise analysis model with all noise terms included. In this model, all noise terms are taken to be noise voltage or current density terms in either nV/√ Hz or pA/√ Hz. The total output spot noise voltage can be computed as the square root of the sum of all squared output noise voltage contributors. Equation 11 shows the general form for the output noise voltage using the terms given in Figure 8-11. EO = 2 2 2 ENI + (IBNRS) + 4kTRS x NG + (IBIRF) + 4kTRFNG (11) ENI 1/2 OPA2673 RS EO IBN ERS RF Ö4kTRS RG 4kT RG IBI Ö4kTRF 4kT = 1.6E -20J at 290°K Figure 8-11. Op Amp Noise Analysis Model Dividing this expression by the noise gain [NG = (1 + RF / RG)] gives the equivalent input-referred spot noise voltage at the noninverting input, as shown in Equation 12. EI = 2 2 2 ENI + (IBN x RS) + 4kTRS + (IBI x RF) + 4kTRF NG2 NG (12) Evaluating these two equations for the OPA2673 circuit and component values of Figure 8-1 gives a total output spot noise voltage of 15.6 nV/√ Hz and a total equivalent input spot noise voltage of 3.9 nV/√ Hz. This total input-referred spot noise voltage is higher than the 2.4 nV/√ Hz specification for the op amp voltage noise alone. This result is due to the noise added to the output by the inverting current noise times the feedback resistor 402 Ω in this case. If the feedback resistor is reduced in high-gain configurations (as suggested previously), the total input-referred voltage noise given by Equation 12 approaches only the 2.4 nV/√ Hz of the op amp. For example, going to a gain of +8 V/V using RF = 250 Ω gives a total input-referred noise of 2.9 nV/√ Hz. 24 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: OPA2673 OPA2673 www.ti.com SBOS382G – JUNE 2008 – REVISED DECEMBER 2021 8.4 Device Functional Modes OPA2673 has four different functional modes set by the A0 and A1 pins. Table 8-2 shows the truth table for the device mode pin configuration and the associated description of each mode. Table 8-2. A0 and A1 Logic Table A0 A1 FUNCTION DESCRIPTION 0 0 Full-bias mode (100%) Both amplifiers are on with the lowest distortion possible 1 0 Mid-bias mode (75%) Both amplifiers are on with power savings and a reduction in distortion performance 0 1 Low-bias mode (50%) Both amplifiers are on with enhanced power savings and a reduction of overall performance 1 1 Offline mode Both amplifiers are off and the output is high impedance OPA2673 can be switched between the full-bias and offline mode using just one control bit by tying the A0 and A1 together. If switching between the mid-bias or low-bias modes and the offline mode is required for the application, then either the A0 or A1 pin can be connected to ground and the control pin can be connected to the non-grounded BIAS pin. The OUT pin of OPA2673 enters high output impedance in offline mode. However, due to the presence of the feedback resistance RF as shown in Figure 8-12, the impedance seen by the load looking into the OPA2673 is (high impedance || RF), making the net impedance as seen from the load equal to RF. The maximum voltage allowed to be incident on the OUT pin and the Inverting Input pin during offline mode is mentioned in the Absolute Maximum Ratings table. The voltage appearing on the Inverting Input pin is a resistor divided value of the voltage on the OUT pin as shown in Figure 8-12. Care should be taken to ensure both the absolute maximum limits mentioned for the OUT and Inverting pins are satisfied. +IN OPA2673 + α(s) OUT Impedance seen into the OPA2673 -IN – RF VOUT * RG RF + RG RG Figure 8-12. OPA2673 Offline Mode Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: OPA2673 25 OPA2673 www.ti.com SBOS382G – JUNE 2008 – REVISED DECEMBER 2021 9 Application and Implementation Note Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes, as well as validating and testing their design implementation to confirm system functionality. 9.1 Application Information 9.1.1 High-Speed Active Filters 9.1.1.1 Design Requirements Wideband current-feedback op amps make ideal elements for implementing high-speed active filters where the amplifier is used as a fixed gain block inside a passive RC circuit network. The relatively constant bandwidth versus gain provides low interaction between the actual filter poles and the required gain for the amplifier. shows an example single-supply buffered filter application. In this case, one of the OPA2673 channels is used to set up the dc operating point and provide impedance isolation from the signal source into the second-stage filter. That stage is set up to implement a 20 MHz, maximally flat Butterworth frequency response and provide an ac gain of +4 V/V. 9.1.1.2 Detailed Design Procedure The 51 Ω input matching resistor is optional in this case. The input signal is ac-coupled to the 5 V dc reference voltage developed through the resistor divider from the +10 V power supply. This first stage acts as a gain of +1 V/V voltage buffer for the signal where the 600-Ω feedback resistor is required for stability. This first stage easily drives the low input resistors required at the input of this high-frequency filter. The second stage is set for a dc gain of +1 V/V, carrying the 5-V operating point through to the output pin, and an ac gain of +4 V/V. The feedback resistor has been adjusted to optimize bandwidth for the amplifier itself. As the single-supply frequency response plots show, the OPA2673 in this configuration gives greater than 400 MHz small-signal bandwidth. The capacitor values were chosen as low as possible but adequate to override the parasitic input capacitance of the amplifier. The resistor values were slightly adjusted to give the desired filter frequency response while accounting for the approximate 1 ns propagation delay through each channel of the OPA2673. 9.1.1.3 Application Curves 12 +VS 100 pF 32.2
+ VI 105  + – 5k 150 pF 600  133  0.1 µF 4 0 4*VI – 50  8 OPA2673 5 k Gain (dB) 0.1 µF -4 402  -8 -12 0.1 1 10 100 Frequency (MHz) Figure 9-1. Buffered Single-Supply Active Filter 26 Figure 9-2. Buffered Single-Supply Active Filter: Gain vs Frequency Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: OPA2673 OPA2673 www.ti.com SBOS382G – JUNE 2008 – REVISED DECEMBER 2021 9.1.2 PLC Line Driver 9.1.2.1 Design Requirements The main design requirements for an ac-coupled wideband current-feedback operation are to choose power supplies that satisfy the output voltage requirement, and also to use a feedback resistor value that allows for the proper bandwidth while maintaining stability. Use the design requirements shown in Table 9-1 to design a broadband PLC application circuit. Table 9-1. Design Requirements DESIGN PARAMETER VALUE Power supply 12 V, single-supply Differential gain GDIFF 8 V/V Output Voltage 18 VPP Large-Signal Bandwidth 220 MHz 9.1.2.2 Detailed Design Procedure The closed-loop gain equation for a differential line driver configuration such as shown below is given as GDIFF = 1 + 2 × (RF / RG), where RF = RF1 = RF2. The OPA2673 is a current-feedback amplifier and thus the bandwidth of the closed-loop configuration is set by the value of the RF resistor. This advantage of the current-feedback architecture allows for flexibility in setting the differential gain by choosing the value of the RG resistor without reducing the bandwidth as is the case with voltage-feedback amplifiers. The OPA2673 is designed to provide optimal bandwidth performance with RF1 = RF2 = 350 Ω. To configure the device in a gain of 8 V/V, the RG resistor is chosen to be 100 Ω. 9.1.2.3 Application Curves 24 +6 V + 5 21 - 18 –6 V 15 2 k 2.25 V RF1 350  +6V 1 μF RG 100 2 k 18 VPP * n 18 VPP RF2 350  1:n 12 9 6 3 0 +6 V – Gain (dB) OPA2673 VO = 18 VPP, G = 8 V/V, RF = 350  -3 5
-6 10M + –6 V Figure 9-3. Typical Schematic for PLC Applications 100M Frequency (Hz) 1G Figure 9-4. Large-Signal Frequency Response Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: OPA2673 27 OPA2673 www.ti.com SBOS382G – JUNE 2008 – REVISED DECEMBER 2021 10 Power Supply Recommendations 10.1 Thermal Analysis As a result of the high output power capability of the OPA2673, heat-sinking or forced airflow may be required under extreme operating conditions. The maximum desired junction temperature sets the maximum allowed internal power dissipation, described below. The maximum junction temperature allowed should not exceed +150°C. Operating junction temperature (TJ) is given by TJ = TA + PD × θJA (13) The total internal power dissipation (PD) is the sum of quiescent power (PDQ) and additional power dissipation in the output stage (PDL) to deliver load power. Quiescent power is the specified no-load supply current times the total supply voltage across the part. PDL depends on the required output signal and load; for a grounded resistive load, however, PDL is at a maximum when the output is fixed at a voltage equal to 1/2 of either supply voltage (for equal bipolar supplies). Under this condition, PDL = VS 2 / (4 × RL), (14) where RL includes feedback network loading. This is the power dissipated at the output stage of OPA2673 that determines the internal power dissipation. As a worst-case example, compute the maximum TJ using an OPA2673 VQFN-16 in the circuit of Figure 8-1 operating at the maximum specified ambient temperature of +85°C with both outputs driving a grounded 20 Ω load to +2.5 V. PD = 12 V × 33 mA + 2 × [52 / (4 × [20 Ω ∥ 535 Ω])] = 1.05 W Maximum TJ = +85°C + (1.05 × 45°C/W) = 132.2°C The output V-I plot in Output Current and Voltage includes a boundary for 2-W maximum internal power dissipation under these conditions. 10.2 Input and ESD Protection The OPA2673 is built using a high-speed complementary bipolar process. The internal junction breakdown voltages are shown in the Absolute Maximum Ratings table. All device pins have limited ESD protection using internal diodes to the power supplies, as shown in Figure 10-1. These diodes provide moderate protection to input overdrive voltages above the supplies as well. The protection diodes can typically support 10 mA continuous current. Where higher currents are possible (for example, in systems with ±15 V supply parts driving into the OPA2673), current-limiting series resistors should be added into the two inputs. +VCC External Pin Internal Circuitry -VCC Figure 10-1. ESD Steering Diodes 28 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: OPA2673 OPA2673 www.ti.com SBOS382G – JUNE 2008 – REVISED DECEMBER 2021 11 Layout 11.1 Layout Guidelines Achieving optimum performance with a high-frequency amplifier such as the OPA2673 requires careful attention to board layout parasitic and external component types. a) Minimize parasitic capacitance to any ac ground for all of the signal I/O pins. Parasitic capacitance on the output and inverting input pins can cause instability; on the noninverting input, it can react with the source impedance to cause unintentional band limiting. To reduce unwanted capacitance, a window around the signal I/O pins should be opened in all of the ground and power planes around those pins. Otherwise, ground and power planes should be unbroken elsewhere on the board. b) Minimize the distance (< 0.25 in, or 6.35 0 mm) from the power-supply pins to high-frequency 0.1 µF decoupling capacitors. The power-supply connections (on pins 7 and 14 for a VQFN package) should always be decoupled with low-ESR capacitors. The ground and power-plane layout should not be in close proximity to the signal I/O pins. Avoid narrow power and ground traces to minimize inductance between the pins and the decoupling capacitors. An optional supply decoupling capacitor connected across the two power supplies (for bipolar operation) improves second-harmonic distortion performance. c) Careful selection and placement of external components preserve the high-frequency performance of the OPA2673. Resistors should be of a very low reactance type. Surface-mount resistors, metal film and carbon composition based axially-leaded resistors can provide good high-frequency performance. Keep the leads and PCB trace length as short as possible. Although the output pin and inverting input pin are the most sensitive to parasitic capacitance, always position the feedback and series output resistor, if any, as close as possible to the output pin. Where double-side component mounting is allowed, place the feedback resistor directly under the package on the other side of the board between the output and inverting input pins. d) The frequency response is primarily determined by the feedback resistor value as described previously. Increasing the value reduces the bandwidth, whereas decreasing it gives a more peaked frequency response. The 402 Ω feedback resistor used in the Typical Characteristics at a gain of +4 V/V on ±6 V supplies is a good starting point for design. Note that a current-feedback op amp requires a feedback resistor even in the unity-gain follower configuration to control stability. A 511 Ω feedback resistor, rather than a direct short, is recommended for the unity-gain follower application. e) Connections to other wideband devices on the board may be made with short direct traces or through onboard transmission lines. For short connections, consider the trace and the input to the next device as a lumped capacitive load. Relatively wide traces (50 mils to 100 mils, or 1.27 mm to 2.54 mm) should be used, preferably with ground and power planes opened up around them. Estimate the total capacitive load and set RISO from the plot of Figure 8-6. Low parasitic capacitive loads (< 5 pF) may not need an RISO because the OPA2673 is nominally compensated to operate with a 2 pF parasitic load. If a long trace is required, and the 6 dB signal loss intrinsic to a doubly-terminated transmission line is acceptable, implement a matched impedance transmission line using microstrip or stripline techniques (consult an ECL design handbook for microstrip and stripline layout techniques). The high output voltage and current capability of the OPA2673 allows multiple destination devices to be handled as separate transmission lines, each with respective series and shunt terminations. If the 6 dB attenuation of a doubly-terminated transmission line is unacceptable, a long trace can be series-terminated at the source end only. Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: OPA2673 29 OPA2673 www.ti.com SBOS382G – JUNE 2008 – REVISED DECEMBER 2021 11.2 Layout Example Place bypass capacitor close to power pins Place the feedback resistors, RF and RG, and the source resistors, RS, as close to the device pins as possible to minimize parasitics 13 14 16 RF 15 CBYP Considering high power capabilities, use wide supply traces to the bypass capacitors to minimize inductance Thermal Pad 1 Ground and power plane exist on inner layers. 12 RG RS 2 11 3 10 4 9 Ground and power plane removed from inner layers. Ground fill on outer layers also removed. - IN A 8 7 6 5 + IN A Place as many vias as possible under the thermal pad and connect them to a heat spreading plane that is at the same potential as VS– Bias Control Connect the thermal pad to a heat spreading plane; the plane must be at the same potential as VS– Layout Recommendations have been shown for Channel A only, follow similar precautions for Channel B. Figure 11-1. Layout Recommendations 30 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: OPA2673 OPA2673 www.ti.com SBOS382G – JUNE 2008 – REVISED DECEMBER 2021 12 Device and Documentation Support 12.1 Receiving Notification of Documentation Updates To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper right corner, click on Alert me to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document. 12.2 Support Resources TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight from the experts. Search existing answers or ask your own question to get the quick design help you need. Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. 12.3 Trademarks TI E2E™ is a trademark of Texas Instruments. All trademarks are the property of their respective owners. 12.4 Electrostatic Discharge Caution This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. 12.5 Glossary TI Glossary This glossary lists and explains terms, acronyms, and definitions. 13 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: OPA2673 31 PACKAGE OPTION ADDENDUM www.ti.com 10-Dec-2020 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) (4/5) (6) OPA2673IRGVR ACTIVE VQFN RGV 16 2500 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 85 OPA 2673 OPA2673IRGVT ACTIVE VQFN RGV 16 250 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 85 OPA 2673 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of