OPA404AG

OPA404 Quad High-Speed Precision Difet ® OPERATIONAL AMPLIFIER FEATURES q WIDE BANDWIDTH: 6.4MHz q HIGH SLEW RATE: 35V/µs q LOW OFFSET: ±750µV max q LOW BIAS CURRENT: ±4pA max q LOW SETTLING: 1.5µs to 0.01% q STANDARD QUAD PINOUT APPLICATIONS q PRECISION INSTRUMENTATION q q q q q OPTOELECTRONICS SONAR, ULTRASOUND PROFESSIONAL AUDIO EQUIPMENT MEDICAL EQUIPMENT DETECTOR ARRAYS DESCRIPTION The OPA404 is a high performance monolithic Difet ®(dielectrically-isolated FET) quad operational amplifier. It offers an unusual combination of verylow bias current together with wide bandwidth and fast slew rate. Noise, bias current, voltage offset, drift, and speed are superior to BIFET® amplifiers. Laser-trimming of thin-film resistors gives very low offset and drift—the best available in a quad FET op amp. The OPA404's input cascode design allows high precision input specifications and uncompromised highspeed performance. Standard quad op amp pin configuration allows upgrading of existing designs to higher performance levels. The OPA404 is unity-gain stable. OPA404 Simplified Circuit (Each Amplifier) +VCC –In +In Cascode Output –VCC Difet ®, Burr-Brown Corp. BIFET®, National Semiconductor Corp. International Airport Industrial Park • Mailing Address: PO Box 11400 Tel: (520) 746-1111 • Twx: 910-952-1111 • Cable: BBRCORP • © 1986 Burr-Brown Corporation • Tucson, AZ 85734 • Street Address: 6730 S. Tucson Blvd. • Tucson, AZ 85706 Telex: 066-6491 • FAX: (520) 889-1510 • Immediate Product Info: (800) 548-6132 PDS-677F Printed in U.S.A. August 1995 SPECIFICATIONS ELECTRICAL At VCC = ±15VDC and TA = +25°C unless otherwise noted. OPA404AG, KP, KU (1) PARAMETER INPUT NOISE Voltage: fO = 10Hz fO = 100Hz fO = 1kHz fO = 10kHz fB = 10Hz to 10kHz fB = 0.1Hz to 10Hz Current: fB = 0.1Hz to 10Hz fO = 0.1Hz thru 20kHz OFFSET VOLTAGE Input Offset Voltage KP, KU Average Drift KP, KU Supply Rejection KP, KU Channel Separation BIAS CURRENT Input Bias Current KP, KU OFFSET CURRENT Input Offset Current KP, KU IMPEDANCE Differential Common-Mode VOTAGE RANGE Common-Mode Input Range Common-Mode Rejection KP, KU OPEN-LOOP GAIN, DC Open-Loop Voltage Gain FREQUENCY RESPONSE Gain Bandwidth Full Power Response Slew Rate Settling Time: 0.1% 0.01% RATED OUTPUT Voltage Output Current Output Output Resistance Load Capacitance Stability Short Circuit Current POWER SUPPLY Rated Voltage Voltage Range, Derated Performance Current, Quiescent TEMPERATURE RANGE Specification KP, KU Operating KP, KU Storage KP, KU θ Junction-Ambient KP, KU ±10.5 88 84 88 4 24 VCM = 0VDC TA = TMIN to TMAX ±VCC = 12V to 18V 100Hz, RL = 2kΩ VCM = 0VDC 80 76 CONDITIONS MIN TYP MAX MIN OPA404BG TYP MAX MIN OPA404SG TYP MAX UNITS 32 19 15 12 1.4 0.95 12 0.6 ±260 ±750 ±3 ±5 100 100 125 ±1 ±1 0.5 0.5 1013 || 1 1014 || 3 +13, –11 100 100 100 6.4 570 35 0.6 1.5 * 92 ±1mV ±2.5mV * * * * * * * * * * 86 * * ±8 ±12 8 12 * ±4 * ±750 * * * * * * * * * * * * * * * nV/√Hz nV/√Hz nV/√Hz nV/√Hz µVrms µVp-p fA, p-p fA/√Hz µV µV µV/°C µV/°C dB dB dB pA pA pA pA Ω || pF Ω || pF V dB dB dB MHz kHz V/µs µs µs V mA Ω pF mA VDC * * +125 * * VDC mA °C °C °C °C °C °C °C/W °C/W VCM = 0VDC * 4 * * * * * * * * * * * * VIN = ±10VDC RL ≥ 2kΩ Gain = 100 20Vp-p, RL = 2kΩ VO = ±10V, RL = 2kΩ Gain = –1, RL = 2kΩ CL = 100 pF, 10V Step RL = 2kΩ VO = ±10VDC 1MHz, Open Loop Gain = +1 92 5 28 * * * * * * * * * * * * * * * * * * * * * * * * * * * ±11.5 +13.2, –13.8 ±5 ±10 80 1000 ±10 ±27 ±15 ±5 * * * * ±40 * * * * IO = 0mADC Ambient Temperature Ambient Temperature Ambient Temperature –25 0 –55 –25 –65 –40 9 ±18 10 +85 +70 +125 +85 +150 +125 * * * * * * * * * * * * * –55 * * * 100 120/100 *Specifications same as OPA404AG. NOTE: (1) OPA404KU may be marked OPA404U. The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes no responsibility for the use of this information, and all use of such information shall be entirely at the user’s own risk. Prices and specifications are subject to change without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant any BURR-BROWN product for use in life support devices and/or systems. ® OPA404 2 ELECTRICAL (FULL TEMPERATURE RANGE SPECIFICATIONS) At VCC = ±15VDC and TA = TMIN to TMAX unless otherwise noted. OPA404AG, KP, KU PARAMETER TEMPERATURE RANGE Specification Range KP, KU INPUT OFFSET VOLTAGE Input Offset Voltage KP KU Average Drift KP, KU Supply Rejection BIAS CURRENT Input Bias Current OFFSET CURRENT Input Offset Current VOLTAGE RANGE Common-Mode Input Range Common-Mode Rejection KP, KU OPEN-LOOP GAIN, DC Open-Loop Voltage Gain RATED OUTPUT Voltage Output Current Output Short Circuit Current POWER SUPPLY Current, Quiescent * Specification same as OPA404AG. CONDITIONS Ambient Temperature MIN –25 0 TYP MAX +85 +70 MIN * OPA404BG TYP MAX * MIN –55 OPA404SG TYP MAX +125 UNITS °C °C VCM = 0VDC 75 VCM = 0VDC VCM = 0VDC ±10 82 80 82 ±450 ±1 ±3 ±5 96 ±32 17 ±12.7, –10.6 99 99 94 2mV ±3.5 * * 80 * * * * 86 * * ±1.5mV ±550 * 70 93 ±500 260 ±10 +12.6, –10.5 80 88 ±2.5mV µV mV µV/°C µV/°C dB pA pA V dB dB dB V mA mA mA ±200 100 ±100 50 ±5nA 2.5nA VIN = ±10VDC RL ≥ 2kΩ RL = 2kΩ VO = ±10VDC VO = 0VDC IO = 0mADC 86 * * * * * * * * 80 88 ±11.5 ±12.9, –13.8 ±5 ±9 ±8 ±20 ±50 9.3 10.5 * * ±11 +12.7, –13.8 * ±8 * * 9.4 * 11 ORDERING INFORMATION MODEL OPA404KP OPA404KU(1) OPA404AG OPA404BG OPA404SG PACKAGE 14-Pin Plastic DIP 16-Pin Plastic SOIC 14-Pin Ceramic DIP 14-Pin Ceramic DIP 14-Pin Ceramic DIP TEMPERATURE RANGE 0°C to +70°C 0°C to +70°C –25°C to +85°C –25°C to +85°C –55°C to +125°C PACKAGE INFORMATION MODEL OPA404KP OPA404KU(2) OPA404AG OPA404BG OPA404SG PACKAGE 14-Pin Plastic DIP 16-Pin Plastic SOIC 14-Pin Ceramic DIP 14-Pin Ceramic DIP 14-Pin Ceramic DIP PACKAGE DRAWING NUMBER(1) 010 211 169 169 169 NOTE: (1) OPA404KU may be marked OPA404U. NOTE: (1) For detailed drawing and dimension table, please see end of data sheet, or Appendix D of Burr-Brown IC Data Book. (2) OPA404KU may be marked OPA404U. Operating Temperature Range .. P, U = –25°C/+85°C, G = –55°C/+125°C Lead Temperature (soldering, 10s) .................................................... 300°C SOIC (soldering, 3s) ..................................................................... +260°C Output Short-Circuit Duration(3) ................................................. Continuous Junction Temperature ....................................................................... +175°C ABSOLUTE MAXIMUM RATINGS Supply ............................................................................................. ±18VDC Internal Power Dissipation(1) ......................................................... 1000mW Differential Input Voltage(2) ............................................................. ±36VDC Input Voltage Range(2) ................................................................... ±18VDC Storage Temperature Range ... P, U = –40°C/+125°C, G = –65°C/+150°C NOTES: (1) Packages must be derated based on θJC = 30°C/W or θJA = 120°C/W. (2) For supply voltages less than ±18VDC the absolute maximum input voltage is equal to: 18V > VIN > –VCC – 8V. See Figure 2. (3) Short circuit may be to power supply common only. Rating applies to +25°C ambient. Observe dissipation limit and TJ. PIN CONFIGURATION Top View Out A –In A + In A + VCC +In B – In B Out B 1 2 A 3 4 5 B 6 7 C 9 –In C 8 Out C D 12 +In D 11 –VCC 10 +In C Top View “G” or “P” (DIP) Package Out A 1 2 A + In A + VCC +In B – In B Out B NC 3 4 5 B 6 7 8 C D “U” (SOIC) Package 16 Out D 15 –In D 14 +In D 13 –VCC 12 +In C 11 –In C 10 Out C 9 NC 14 Out D 13 –In D –In A ® 3 OPA404 DICE INFORMATION 3 4 NC 2 1 NC 14 13 12 NC PAD 1 2 3 4 5 6 7 FUNCTION Output A –Input A +Input A +VCC +Input B –Input B Output B PAD 8 9 10 11 12 13 14 FUNCTION Output C –Input C +Input C –VCC +Input D –Input D Output D Substrate Bias: –VCC NC: No connection MECHANICAL INFORMATION MILS (0.001") NC NC MILLIMETERS 2.74 x 2.74 ±0.13 0.51 ±0.08 0.10 x 0.10 None Die Size Die Thickness Min. Pad Size Backing 108 x 108 ±5 20 ±3 4x4 5 6 7 NC 11 8 9 10 OPA404 DIE TOPOGRAPHY TYPICAL PERFORMANCE CURVES TA = +25°C, VCC = ±15VDC unless otherwise noted. POWER SUPPLY REJECTION AND COMMON-MODE REJECTION vs TEMPERATURE 110 INPUT CURRENT NOISE SPECTRAL DENSITY 100 Current Noise (fA/ Hz) 10 CMR and PSR (dB) 105 PSR 100 CMR 1 95 0.1 1 10 100 1k 10k Frequency (Hz) 100k 1M 90 –75 –50 –25 0 +25 +50 Temperature (°C) +75 +100 +125 TOTAL INPUT VOLTAGE NOISE SPECTRAL DENSITY AT 1kHz vs SOURCE RESISTANCE 1k EO BIAS AND OFFSET CURRENT vs TEMPERATURE 10nA 10nA Voltage Noise, EO (nV/ Hz) 1nA 100 OPA404 + Resistor 1nA 100 Bias Current 10 Offset Current 100 10 10 1 Resistor noise only 1 100 1k 10k 100k 1M Source Resistance (Ω) 10M 100M 1 0.1 0.1 –50 –25 0 +25 +50 +75 +100 Ambient Temperature (°C) +125 ® OPA404 4 Offset Current (pA) Bias Current (pA) RS TYPICAL PERFORMANCE CURVES (CONT) TA = +25°C, VCC = ±15VDC unless otherwise noted. BIAS AND OFFSET CURRENT vs INPUT COMMON-MODE VOLTAGE 10 10 Power Supply Rejection (dB) 140 120 100 80 60 40 20 0 1 10 POWER SUPPLY REJECTION vs FREQUENCY 1 Bias Current Offset Current 1 Offset Current (pA) Bias Current (pA) – + 0.1 0.1 0.01 –15 –10 –5 0 +5 +10 +15 Common-Mode Voltage (V) 0.01 100 1k 10k 100k 1M 10M Frequency (Hz) COMMON-MODE REJECTION vs FREQUENCY 140 Common-Mode Rejection (dB) 120 COMMON-MODE REJECTION vs INPUT COMMON-MODE VOLTAGE Common-Mode Rejection (dB) 120 100 80 60 40 20 0 1 10 100 1k 10k 100k 1M 10M Frequency (Hz) 110 100 90 80 70 –15 –10 0 +5 –5 Common-Mode Voltage (V) +10 +15 OPEN-LOOP FREQUENCY RESPONSE 140 120 Voltage Gain (dB) 10 GAIN BANDWIDTH AND SLEW RATE vs TEMPERATURE 40 RL = 2kΩ CL = 100pF –45 Gain Bandwidth (MHz) Phase Shift (Degrees) GBW 6 Slew Rate 4 34 35 80 60 40 AOL 20 0 1 10 100 1k 10k 100k 1M Frequency (Hz) Ø –90 –135 –180 10M 2 –75 –50 0 +25 +50 –25 +75 Ambient Temperature (°C) +100 33 +125 ® 5 OPA404 Slew Rate (V/µs) 100 8 36 TYPICAL PERFORMANCE CURVES (CONT) TA = +25°C, VCC = ±15VDC unless otherwise noted. GAIN-BANDWIDTH AND SLEW RATE vs SUPPLY VOLTAGE 8 AV = +1 Gain Bandwidth (MHz) OPEN-LOOP GAIN vs TEMPERATURE 38 RL = 10kΩ Slew Rate (V/µs) 120 110 7 GBW 36 Voltage Gain (dB) 100 6 34 90 Slew Rate 5 0 5 10 Supply Voltage (±VCC) 15 20 32 80 –75 –50 –25 +75 0 +25 +50 Ambient Temperature (°C) +100 +125 MAXIMUM OUTPUT VOLTAGE SWING vs FREQUENCY 30 LARGE SIGNAL TRANSIENT RESPONSE Output Voltage (Vp-p) 20 Output Voltage (V) RL = 2kΩ 10k 1M 100k Frequency (Hz) 10M 10 0 10 –10 0 0 1 2 3 4 5 Time(µs) SMALL SIGNAL TRANSIENT RESPONSE SETTLING TIME vs CLOSED-LOOP GAIN 5 150 100 Output Voltage (mV) 50 0 –50 –100 Settling Time (µs) 4 3 2 0.01% RL = 2kΩ CL = 100pF 0.1% –1 –10 –100 –1k 1 –150 0 0 1 Time(µs) 2 Closed-Loop Gain (V/V) ® OPA404 6 TYPICAL PERFORMANCE CURVES (CONT) TA = +25°C, VCC = ±15VDC unless otherwise noted. SUPPLY CURRENT vs TEMPERATURE 11 150 CHANNEL SEPARATION vs FREQUENCY Channel Separation (dB) 140 Supply Current (mA) 10 RL = ∞ 130 9 120 RL = 2kΩ 110 8 7 –75 –50 –25 0 +25 +50 +75 Ambient Temperature (°C) +100 +125 0 10 100 1k Frequency (Hz) 10k 100k TOTAL HARMONIC DISTORTION vs FREQUENCY 1 40.2kΩ 402Ω OPEN-LOOP GAIN vs SUPPLY VOLTAGE 104 AV = +101V/V 6.5Vrms 2kΩ THD + N (% rms) Voltage Gain 100k 0.1 100 AV = +101V/V 0.01 AV = +1V/V Test Limit 0.1 1 10 1k 100 Frequency (Hz) 10k 96 0.001 92 0 5 10 Supply Voltage (±VCC) 15 20 INPUT VOLTAGE NOISE SPECTRAL DENSITY 1k Voltage Noise (nV/ Hz) 100 10 1 1 10 100 1k 10k Frequency (Hz) 100k 1M ® 7 OPA404 APPLICATIONS INFORMATION OFFSET VOLTAGE ADJUSTMENT The OPA404 offset voltage is laser-trimmed and will require no further trim for most applications. If desired, offset voltage can be trimmed by summing (see Figure 1). With this trim method there will be no degradation of input offset drift. GUARDING AND SHIELDING As in any situation where high impedances are involved, careful shielding is required to reduce “hum” pickup in input leads. If large feedback resistors are used, they should also be shielded along with the external input circuitry. Leakage currents across printed circuit boards can easily exceed the bias current of the OPA404. To avoid leakage, utmost care must be used in planning the board layout. A “guard” pattern should completely surround the high impedance input leads and should be connected to a low-impedance point which is at the signal input potential. (See Figure 3). In 1/4 OPA404 Out –15V 100kΩ 20Ω 150kΩ ±2mV Offset Trim +15V Non-Inverting Buffer Out In In Inverting Out FIGURE 1. Offset Voltage Trim. INPUT PROTECTION Conventional monolithic FET operational amplifiers require external current-limiting resistors to protect their inputs against destructive currents that can flow when input FET gate-tosubstrate isolation diodes are forward-biased. Most BIFET amplifiers can be destroyed by the loss of –VCC. Unlike BIFET amplifiers, the Difet OPA404 requires input current limiting resistors only if its input voltage is greater than 8 volts more negative than –VCC. A 10kΩ series resistor will limit the input current to a safe value with up to ±15V input levels even if both supply voltages are lost. (See Figure 2 and Absolute Maximum Ratings). Static damage can cause subtle changes in amplifier input characteristics without necessarily destroying the device. In precision operational amplifiers (both bipolar and FET types), this may cause a noticeable degradation of offset voltage and drift. Static protection is recommended when handling any precision IC operational amplifier. INPUT CURRENT vs INPUT VOLTAGE WITH ±VCC PINS GROUNDED +2 In Out For input guarding, guard top and bottom of board. FIGURE 3. Connection of Input Guard. HANDLING AND TESTING Measuring the unusually low bias current of the OPA404 is difficult without specialized test equipment; most commercial benchtop testers cannot accurately measure the OPA404 bias current. Low-leakage test sockets and special test fixtures are recommended if incoming inspection of bias current is to be performed. To prevent surface leakage between pins, the DIP package should not be handled by bare fingers. Oils and salts from fingerprints or careless handling can create leakage currents that exceed the specified OPA404 bias currents. If necessary, DIP packages and PC board assemblies can be cleaned with Freon TF®, baked for 30 minutes at 85°C, rinsed with de-ionized water, and baked again for 30 minutes at 85°C. Surface contamination can be prevented by the application of a high-quality conformal coating to the cleaned PC board assembly. Input Current (mA) +1 IIN Maximum Safe Current V 0 –1 Maximum Safe Current –2 –15 –10 –5 0 +5 +10 +15 Input Voltage (V) FIGURE 2. Input Current vs Input Voltage with ±VCC Pins Grounded. ® OPA404 8 BIAS CURRENT CHANGE vs COMMON-MODE VOLTAGE The input bias currents of most popular BIFET operational amplifiers are affected by common-mode voltage (Figure 4). Higher input FET gate-to-drain voltage causes leakage and ionization (bias) currents to increase. Due to its cascode input stage, the extremely low bias current of the OPA404 is not compromised by common-mode voltage. 80 70 Input Bias Current (pA) APPLICATIONS CIRCUITS Figures 5 through 11 are circuit diagrams of various applications for the OPA404. 1MΩ Operate In 10kΩ 100Ω 2 3 1/4 OPA404 1 TA = +25°C; curves taken from mfg. published typical data LF156/157 Out Zero 60 50 40 30 20 10 0 –10 –20 –15 –10 –5 0 +5 +10 +15 Common-Mode Voltage (VDC) LF155 AD547 OPA404 OP-15/16/17 LF156/157 AD547 LF155 100kΩ Gain = –100 VOS < 10µV Drift ≈ 0.05µV/°C Zero Droop ≈ 1µV/s Referred to Input 100kΩ Polypropylene 1µF 6 OPA404 7 1/4 OPA404 5 FIGURE 4. Input Bias Current vs Common-Mode Voltage. FIGURE 5. Auto-Zero Amplifier. 10kΩ ≈10pF (1) 1MΩ 6 (1) IN914 2 3 1/4 OPA404 1 IN914 (1) 5 1/4 OPA404 7 Output Input 2N4117 Droop ≈ 0.1mV/s 0.01µF Polstyrene NOTE: (1) Reverse polarity for negative peak detection. FIGURE 6. Low-Droop Positive Peak Detector. ® 9 OPA404 2 1 1 1/4 OPA404 3 Differential Input E1 E1 3 6 2 1MΩ R Load 5 INA105 IO = (E1 – E2) /R Output = 1µA/V IO FIGURE 7. Voltage-Controlled Microamp Current Source.