OPA191, OPA2191, OPA4191
SBOS701D – DECEMBER 2015 – REVISED AUGUST 2021
OPAx191 36-V, Low-Power, Precision, CMOS, Rail-to-Rail Input/Output,
Low Offset Voltage, Low Input Bias Current Op Amp
1 Features
3 Description
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The OPAx191 family (OPA191, OPA2191, and
OPA4191) is a new generation of 36-V, e-trim™
operational amplifiers.
Low offset voltage: ±5 µV
Low offset voltage drift: ±0.1 µV/°C
Low noise: 15 nV/√ Hz at 1 kHz
High common-mode rejection: 140 dB
Low bias current: ±5 pA
Rail-to-rail input and output
Wide bandwidth: 2.5-MHz GBW
High slew rate: 5 V/µs
Low quiescent current: 140 µA per amplifier
Wide supply: ±2.25 V to ±18 V, 4.5 V to 36 V
EMI/RFI filtered inputs
Differential input voltage range to supply rail
High capacitive load drive capability: 1 nF
Industry standard packages:
– Single in SOIC-8, SOT-5, and VSSOP-8
– Dual in SOIC-8 and VSSOP-8
– Quad in SOIC-14, TSSOP-14, and WQFN-16
These devices offer outstanding dc precision and
ac performance, including rail-to-rail input/output, low
offset voltage (±5 µV, typ), low offset drift (±0.2 µV/°C,
typ), and 2-MHz bandwidth.
Unique features, such as differential input-voltage
range to the supply rail, high output current (±65 mA),
high capacitive load drive of up to 1 nF, and high
slew rate (5 V/µs), make the OPAx191 a robust, highperformance operational amplifier for high-voltage
industrial applications.
The OPAx191 family of op amps is available in
standard packages and is specified from –40°C to
+125°C.
2 Applications
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Device Information
Analog input module
Mixed module (AI, AO, DI, DO)
Data acquisition (DAQ)
Source measurement unit (SMU)
Pressure transmitter
Train control and management systems
Lab and field instrumentation
PART NUMBER
OPA191
OPA2191
OPA4191
(1)
PACKAGE(1)
BODY SIZE (NOM)
SOIC (8)
4.90 mm × 3.90 mm
SOT (5)
2.90 mm × 1.60 mm
VSSOP (8)
3.00 mm × 3.00 mm
SOIC (8)
4.90 mm × 3.90 mm
VSSOP (8)
3.00 mm × 3.00 mm
SOIC (14)
8.65 mm x 3.90 mm
TSSOP (14)
5.00 mm x 4.40 mm
WQFN (16)
4.00 mm x 4.00 mm
For all available packages, see the package option
addendum at the end of the data sheet.
Analog Inputs
REF3140
OPA191
Gain
Gain
RC Filter
RC Filter
OPA625
Reference Driver
Bridge Sensor
+
Thermocouple
4:2
HV MUX
+
OPA191
VIN
OPA191
Gain
+
Antialiasing
Filter
ADS8864
VIN
Current Sensing
M
Gain
Optical Sensor
REF
P
High-Voltage Multiplexed Input
High-Voltage Level Translation
VCM
OPA191 in a High-Voltage, Multiplexed, Data-Acquisition System
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
OPA191, OPA2191, OPA4191
www.ti.com
SBOS701D – DECEMBER 2015 – REVISED AUGUST 2021
Table of Contents
1 Features............................................................................1
2 Applications..................................................................... 1
3 Description.......................................................................1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................3
6 Specifications.................................................................. 5
6.1 Absolute Maximum Ratings ....................................... 5
6.2 ESD Ratings .............................................................. 5
6.3 Recommended Operating Conditions ........................5
6.4 Thermal Information: OPA191 ................................... 6
6.5 Thermal Information: OPA2191 ................................. 6
6.6 Thermal Information: OPA4191 ................................. 6
6.7 Electrical Characteristics: VS = ±4 V to ±18 V
(VS = 8 V to 36 V) .........................................................7
6.8 Electrical Characteristics: VS = ±2.25 V to ±4 V
(VS = 4.5 V to 8 V) ........................................................9
6.9 Typical Characteristics.............................................. 11
7 Parameter Measurement Information.......................... 20
7.1 Input Offset Voltage Drift...........................................20
8 Detailed Description......................................................22
8.1 Overview................................................................... 22
8.2 Functional Block Diagram......................................... 22
8.3 Feature Description...................................................23
8.4 Device Functional Modes..........................................30
9 Application and Implementation.................................. 31
9.1 Application Information............................................. 31
9.2 Typical Applications.................................................. 31
10 Power Supply Recommendations..............................35
11 Layout........................................................................... 35
11.1 Layout Guidelines................................................... 35
11.2 Layout Example...................................................... 36
12 Device and Documentation Support..........................37
12.1 Device Support....................................................... 37
12.2 Documentation Support.......................................... 37
12.3 Receiving Notification of Documentation Updates..37
12.4 Support Resources................................................. 37
12.5 Trademarks............................................................. 38
12.6 Electrostatic Discharge Caution..............................38
12.7 Glossary..................................................................38
13 Mechanical, Packaging, and Orderable
Information.................................................................... 38
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision C (October 2019) to Revision D (August 2021)
Page
• Changed OPA4191 PW (TSSOP-14) package from preview to production data (active).................................. 1
Changes from Revision B (July 2019) to Revision C (October 2019)
Page
• Changed OPA4191 RUM package from preview to production data (active).....................................................1
Changes from Revision A (April 2016) to Revision B (July 2019)
Page
• Added advanced information (preview) 16-pin RUM (WQFN) package and associated content to data sheet 1
• Changed Figure 32 condition from G = –1 to G = 1..........................................................................................11
• Changed Figure 33 condition from G = 1 to G = –1 .........................................................................................11
Changes from Revision * (December 2015) to Revision A (April 2016)
Page
• Changed DBV and DGK packages from product preview to production data.................................................... 1
• Changed Figure 23, 0.1-Hz to 10-Hz Noise......................................................................................................11
• Added text regarding capacitive load drive to the Capacitive Load and Stability section................................. 26
• Added Figure 56 .............................................................................................................................................. 26
2
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SBOS701D – DECEMBER 2015 – REVISED AUGUST 2021
5 Pin Configuration and Functions
OUT
1
V±
2
5
±
+
+IN
3
4
NC
1
±IN
2
+IN
3
V±
4
8
NC
±
7
V+
+
6
OUT
5
NC
V+
±IN
Not to scale
Not to scale
Figure 5-1. OPA191 DBV (5-Pin SOT) Package,
Top View
Figure 5-2. OPA191 D (8-Pin SOIC) and
DGK (8-Pin VSSOP) Packages, Top View
Pin Functions: OPA191
PIN
OPA191
NAME
I/O
DESCRIPTION
D (SOIC),
DGK (VSSOP)
DBV (SOT)
+IN
3
3
I
Noninverting input
–IN
2
4
I
Inverting input
NC
1, 5, 8
—
—
No internal connection (can be left floating)
OUT
6
1
O
Output
V+
7
5
—
Positive (highest) power supply
V–
4
2
—
Negative (lowest) power supply
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SBOS701D – DECEMBER 2015 – REVISED AUGUST 2021
OUT A
1
8
V+
±IN A
2
7
OUT B
+IN A
3
6
±IN B
V±
4
5
+IN B
Not to scale
V±
+IN B
5
10
+IN C
±IN B
6
9
±IN C
OUT B
7
8
OUT C
-IN A
1
+IN A
2
NC
11
13
4
12
-IN D
11
+IN D
10
V±
Thermal
V+
3
+IN B
4
Pad
9
8
V+
-IN C
+IN D
OUT D
12
14
3
7
+IN A
OUT C
±IN D
OUT A
13
15
2
6
±IN A
OUT B
OUT D
NC
14
5
1
-IN B
OUT A
16
Figure 5-3. OPA2191 D (8-Pin SOIC) and
DGK (8-Pin VSSOP) Packages, Top View
+IN C
Not to scale
Figure 5-4. OPA4191 D (14-Pin SOIC) and
PW (14-Pin TSSOP) Packages, Top View
Not to scale
Figure 5-5. OPA4191 RUM (16-Pin WQFN With
Exposed Thermal Pad) Package, Top View
Pin Functions: OPA2191 and OPA4191
PIN
OPA2191
4
OPA4191
I/O
DESCRIPTION
NAME
D (SOIC),
DGK (VSSOP)
D (SOIC),
PW (TSSOP)
RUM (QFN)
+IN A
3
3
2
I
Noninverting input, channel A
+IN B
5
5
4
I
Noninverting input, channel B
+IN C
—
10
9
I
Noninverting input, channel C
+IN D
—
12
11
I
Noninverting input, channel D
–IN A
2
2
1
I
Inverting input, channel A
–IN B
6
6
5
I
Inverting input, channel B
–IN C
—
9
8
I
Inverting input,,channel C
–IN D
—
13
12
I
Inverting input, channel D
OUT A
1
1
15
O
Output, channel A
OUT B
7
7
6
O
Output, channel B
OUT C
—
8
7
O
Output, channel C
OUT D
—
14
14
O
Output, channel D
V+
8
4
3
—
Positive (highest) power supply
V–
4
11
10
—
Negative (lowest) power supply
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SBOS701D – DECEMBER 2015 – REVISED AUGUST 2021
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN
±20
(+40, single supply)
Supply voltage, VS = (V+) – (V–)
Signal input pins
MAX
Common-mode
Voltage
(V–) – 0.5
Differential
(V+) + 0.5
(V+) – (V–) + 0.2
Current
±10
Output short circuit(2)
Continuous
Operating
Temperature
(1)
(2)
V
V
mA
Continuous Continuous
–40
150
Junction
150
Storage, Tstg
UNIT
–65
°C
150
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress
ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under
Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability.
Short-circuit to ground, one amplifier per package.
6.2 ESD Ratings
VALUE
Human-body model (HBM), per ANSI/ESDA/JEDEC
V(ESD)
(1)
(2)
Electrostatic discharge
JS-001(1)
UNIT
±3000
Charged-device model (CDM), per JEDEC specification JESD22-C101(2)
±1000
Charged-device model (CDM), per JEDEC specification JESD22-C101(2),
OPA4191IPW package only
±500
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
Supply voltage, VS = (V+) – (V–)
Specified temperature
NOM
MAX
UNIT
4.5 (±2.25)
36 (±18)
V
–40
125
°C
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SBOS701D – DECEMBER 2015 – REVISED AUGUST 2021
6.4 Thermal Information: OPA191
OPA191
THERMAL
METRIC(1)
D (SOIC)
DGK (VSSOP)
8 PINS
DBV (SOT)
UNIT
5 PINS
RθJA
Junction-to-ambient thermal resistance
115.8
180.4
158.8
°C/W
RθJC(top)
Junction-to-case(top) thermal resistance
60.1
67.9
60.7
°C/W
RθJB
Junction-to-board thermal resistance
56.4
102.1
44.8
°C/W
ψJT
Junction-to-top characterization parameter
12.8
10.4
1.6
°C/W
ψJB
Junction-to-board characterization parameter
55.9
100.3
4.2
°C/W
RθJC(bot)
Junction-to-case(bottom) thermal resistance
N/A
N/A
N/A
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
6.5 Thermal Information: OPA2191
OPA2191
THERMAL METRIC(1)
D (SOIC)
DGK (VSSOP)
UNIT
8 PINS
RθJA
Junction-to-ambient thermal resistance
107.9
158
°C/W
RθJC(top)
Junction-to-case(top) thermal resistance
53.9
48.6
°C/W
RθJB
Junction-to-board thermal resistance
48.9
78.7
°C/W
ψJT
Junction-to-top characterization parameter
6.6
3.9
°C/W
ψJB
Junction-to-board characterization parameter
48.3
77.3
°C/W
RθJC(bot)
Junction-to-case(bottom) thermal resistance
N/A
N/A
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
6.6 Thermal Information: OPA4191
OPA4191
THERMAL METRIC(1)
D (SOIC)
PW (TSSOP)
14 PINS
UNIT
16 PINS
RθJA
Junction-to-ambient thermal resistance
86.4
108.1
33.0
°C/W
RθJC(top)
Junction-to-case(top) thermal resistance
46.3
26.3
25.1
°C/W
RθJB
Junction-to-board thermal resistance
41.0
54.4
11.6
°C/W
ψJT
Junction-to-top characterization parameter
11.3
1.4
0.2
°C/W
ψJB
Junction-to-board characterization parameter
40.7
53.3
11.5
°C/W
RθJC(bot)
Junction-to-case(bottom) thermal resistance
N/A
N/A
2.6
°C/W
(1)
6
RUM (QFN)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
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SBOS701D – DECEMBER 2015 – REVISED AUGUST 2021
6.7 Electrical Characteristics: VS = ±4 V to ±18 V (VS = 8 V to 36 V)
at TA = +25°C, VCM = VOUT = VS / 2, and RL = 10 kΩ connected to VS / 2 (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
±5
±25
UNIT
OFFSET VOLTAGE
VS = ±18 V
TA = 0°C to 85°C
TA = –40°C to +125°C
(V+) – 3.0 V < VCM < (V+) – 1.5 V
VOS
Input offset voltage
PSRR
Input offset voltage drift
Power-supply rejection
ratio
±75
±10
±125
See Typical Characteristics
±10
±50
TA = 0°C to 85°C
±25
±150
TA = –40°C to +125°C
±50
±250
±5
±50
TA = 0°C to 85°C
±10
±475
TA = –40°C to +125°C
±20
±740
VS = ±18 V, D and PW packages
only
TA = 0°C to 85°C
±0.1
±0.8
±0.15
±1.2
VS = ±18 V, RUM, DGK and DBV
packages only
TA = 0°C to 85°C
±0.1
±0.9
TA = –40°C to +125°C
±0.15
±1.3
VS = ±18 V, VCM = (V+) – 1.5 V
TA = –40°C to +125°C
±0.5
VS = ±18 V,
VCM = (V+) – 1.5 V
OPA4191 (RUM, PW), VS = ±18 V
VCM = (V+) – 1.5 V
dVOS/dT
±8
TA = –40°C to +125°C
TA = –40°C to +125°C
µV
µV/°C
±0.3
±1.0
µV/V
±5
±20
pA
±9
nA
±20
pA
±2
nA
INPUT BIAS CURRENT
IB
Input bias current
IOS
Input offset current
TA = –40°C to +125°C
±2
TA = –40°C to +125°C
NOISE
En
Input voltage noise
en
Input voltage noise
density
(V–) – 0.1 V < VCM < (V+) – 3 V
f = 0.1 Hz to 10 Hz
1.4
(V+) – 1.5 V < VCM < (V+) + 0.1 V
f = 0.1 Hz to 10 Hz
7
(V–) – 0.1 V < VCM < (V+) – 3 V
(V+) – 1.5 V < VCM < (V+) + 0.1 V
in
Input current noise
density
f = 100 Hz
18
f = 1 kHz
15
f = 100 Hz
53
f = 1 kHz
24
f = 1 kHz
µVPP
nV/√Hz
1.5
fA/√Hz
INPUT VOLTAGE
VCM
Common-mode voltage
range
(V–) – 0.1
VS = ±18 V,
(V–) – 0.1 V < VCM < (V+) – 3 V
CMRR
VS = ±18 V,
Common-mode rejection (V–) < VCM < (V+) – 3 V
ratio
VS = ±18 V,
(V+) – 1.5 V < VCM < (V+)
TA = –40°C to +125°C
TA = –40°C to +125°C
(V+) – 3 V < VCM < (V+) – 1.5 V
(V+) + 0.1
120
140
114
126
96
120
86
100
V
dB
See Typical Characteristics
INPUT IMPEDANCE
ZID
Differential
ZIC
Common-mode
100 || 1.6
MΩ || pF
1 || 6.4
1013Ω ||
pF
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SBOS701D – DECEMBER 2015 – REVISED AUGUST 2021
6.7 Electrical Characteristics: VS = ±4 V to ±18 V (VS = 8 V to 36 V) (continued)
at TA = +25°C, VCM = VOUT = VS / 2, and RL = 10 kΩ connected to VS / 2 (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
VS = ±18 V,
(V–) + 0.6 V < VO < (V+) – 0.6 V,
RL = 2 kΩ
124
134
VS = ±18 V,
(V–) + 0.8 V < VO < (V+) – 0.8 V,
RL = 2 kΩ, RUM package
124
134
MAX
UNIT
OPEN-LOOP GAIN
AOL
Open-loop voltage gain
VS = ±18 V,
(V–) + 0.6 V < VO < (V+) – 0.6 V,
RL = 2 kΩ
TA = –40°C to +125°C
114
126
VS = ±18 V,
(V–) + 0.8 V < VO < (V+) – 0.8 V,
RL = 2 kΩ, RUM package
TA = –40°C to +125°C
114
126
126
140
120
134
dB
VS = ±18 V,
(V–) + 0.3 V < VO < (V+) – 0.3 V,
RL = 10 kΩ
VS = ±18 V,
(V–) + 0.3 V < VO < (V+) – 0.3 V,
RL = 10 kΩ
TA = –40°C to +125°C
FREQUENCY RESPONSE
GBW
Unity gain bandwidth
SR
Slew rate
2.5
VS = ±18 V, G = 1, 10-V step
To 0.01%, CL = 20 pF
ts
Settling time
To 0.001%, CL = 20 pF
tOR
Overload recovery time
THD+N
Total harmonic distortion
G = 1, f = 1 kHz, VO = 3.5 VRMS
+ noise
Crosstalk
VIN × G = VS
Falling
7.5
Rising
5.5
VS = ±18 V, G = 1, 2-V step
0.7
VS = ±18 V, G = 1, 5-V step
1
VS = ±18 V, G = 1, 2-V step
1.8
VS = ±18 V, G = 1, 5-V step
3.7
From overload to negative rail
0.4
From overload to positive rail
MHz
V/µs
µs
µs
1
0.0012%
OPA2191 and OPA4191, at dc
150
dB
OPA2191 and OPA4191, f = 100 kHz
130
dB
OUTPUT
No load
Positive rail
VO
Voltage output swing
from rail
Short-circuit current
CL
Capacitive load drive
ZO
Open-loop output
impedance
15
50
110
RL = 2 kΩ
200
500
5
15
No load
Negative rail
ISC
5
RL = 10 kΩ
RL = 10 kΩ
50
110
RL = 2 kΩ
200
500
VS = ±18 V
±65
mV
mA
See Typical Characteristics
f = 1 MHz, IO = 0 A, See Typical Characteristics
700
Ω
POWER SUPPLY
IQ
Quiescent current per
amplifier
IO = 0 A
140
TA = –40°C to +125°C
200
250
µA
TEMPERATURE
8
Thermal protection
180
°C
Thermal hysteresis
30
°C
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SBOS701D – DECEMBER 2015 – REVISED AUGUST 2021
6.8 Electrical Characteristics: VS = ±2.25 V to ±4 V (VS = 4.5 V to 8 V)
at TA = +25°C, VCM = VOUT = VS / 2, and RL = 10 kΩ connected to VS / 2 (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
±5
±25
UNIT
OFFSET VOLTAGE
VS = ±2.25 V,
VCM = (V+) – 3 V
TA = 0°C to 85°C
TA = –40°C to +125°C
(V+) – 3.0 V < VCM < (V+) – 1.5 V
VOS
Input offset voltage
PSRR
Input offset voltage drift
Power-supply rejection
ratio
±75
±10
±125
See Typical Characteristics
±10
±50
TA = 0°C to 85°C
±25
±150
TA = –40°C to +125°C
±50
±250
±10
±50
TA = –40°C to +85°C
±90
±475
TA = –40°C to +125°C
±150
±740
VS = ±2.25 V, VCM = (V+) – 3 V,
D and PW packages only
TA = 0°C to 85°C
±0.1
±0.8
µV/°C
±0.15
±1.2
µV/°C
VS = ±2.25 V, VCM = (V+) – 3
V, RUM, DGK and DBV packages
only
TA = 0°C to 85°C
±0.1
±0.9
TA = –40°C to +125°C
±0.15
±1.3
VS = ±2.25 V, VCM = (V+) – 1.5 V
TA = –40°C to +125°C
±0.5
VS = ±3 V,
VCM = (V+) – 1.5 V
OPA4191 (RUM, PW), VS = ±3 V,
VCM = (V+) – 1.5 V
dVOS/dT
±8
TA = –40°C to +125°C
TA = –40°C to +125°C, VCM = VS / 2 – 0.75 V
±1
µV
µV/°C
µV/V
INPUT BIAS CURRENT
IB
IOS
Input bias current
Input offset current
±5
±20
pA
±9
nA
±2
±20
pA
±2
nA
TA = –40°C to +125°C
TA = –40°C to +125°C
NOISE
En
Input voltage noise
(V–) – 0.1 V < VCM < (V+) – 3 V
f = 0.1 Hz to 10 Hz
1.4
(V+) – 1.5 V < VCM < (V+) + 0.1 V
f = 0.1 Hz to 10 Hz
7
(V–) – 0.1 V < VCM < (V+) – 3 V
en
Input voltage noise density
(V+) – 1.5 V < VCM < (V+) + 0.1 V
in
Input current noise density
f = 100 Hz
18
f = 1 kHz
15
f = 100 Hz
53
f = 1 kHz
24
f = 1 kHz
1.5
µVPP
nV/√Hz
fA/√Hz
INPUT VOLTAGE
VCM
Common-mode voltage
range
(V–) – 0.1
VS = ±2.25 V,
(V–) – 0.1 V < VCM < (V+) – 3 V
CMRR
Common-mode rejection
ratio
VS = ±2.25 V,
(V–) < VCM < (V+) – 3 V
VS = ±2.25 V,
(V+) – 1.5 V < VCM < (V+)
TA = –40°C to +125°C
TA = –40°C to +125°C
(V+) – 3 V < VCM < (V+) – 1.5 V
(V+) + 0.1
96
110
90
104
96
120
84
100
V
dB
See Typical Characteristics
INPUT IMPEDANCE
ZID
Differential
ZIC
Common-mode
100 || 1.6
MΩ || pF
1 || 6.4
1013Ω ||
pF
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SBOS701D – DECEMBER 2015 – REVISED AUGUST 2021
6.8 Electrical Characteristics: VS = ±2.25 V to ±4 V (VS = 4.5 V to 8 V) (continued)
at TA = +25°C, VCM = VOUT = VS / 2, and RL = 10 kΩ connected to VS / 2 (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
110
120
MAX
UNIT
OPEN-LOOP GAIN
AOL
Open-loop voltage gain
VS = ±2.25 V,
(V–) + 0.6 V < VO < (V+) – 0.6 V,
RL = 2 kΩ
VS = ±2.25 V,
(V–) + 0.3 V < VO < (V+) – 0.3 V,
RL = 10 kΩ
TA = –40°C to +125°C
TA = –40°C to +125°C
100
114
110
126
106
120
dB
FREQUENCY RESPONSE
GBW
Unity gain bandwidth
2.2
SR
Slew rate
VS = ±2.25 V, G = 1, 1-V step
tOR
Overload recovery time
VIN × G = VS
Crosstalk
Falling
6.5
Rising
5.5
From overload to negative rail
0.4
From overload to positive rail
MHz
V/µs
µs
1
OPA2191 and OPA4191, at dc
150
dB
OPA2191 and OPA4191, f = 100 kHz
130
dB
OUTPUT
No load
Positive rail
VO
Voltage output swing from
rail
ISC
Short-circuit current
CL
Capacitive load drive
ZO
Open-loop output
impedance
15
RL = 10 kΩ
15
110
RL = 2 kΩ
60
500
5
15
No load
Negative rail
5
RL = 10 kΩ
15
110
RL = 2 kΩ
60
500
VS = ±2.25 V
±30
mV
mA
See Typical Characteristics
f = 1 MHz, IO = 0 A, see Typical Characteristics
700
Ω
POWER SUPPLY
IQ
Quiescent current per
amplifier
IO = 0 A
140
TA = –40°C to +125°C
200
250
µA
TEMPERATURE
10
Thermal protection
180
°C
Thermal hysteresis
30
°C
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SBOS701D – DECEMBER 2015 – REVISED AUGUST 2021
6.9 Typical Characteristics
at TA = 25°C, VS = ±18 V, VCM = VS / 2, RL = 10 kΩ connected to VS / 2, and CL = 100 pF (unless otherwise noted)
Table 6-1. Table of Graphs
DESCRIPTION
FIGURE
Offset Voltage Production Distribution
Figure 6-1, Figure 6-2, Figure 6-3, Figure 6-4, Figure 6-5, Figure 6-6
Offset Voltage Drift Distribution
Figure 6-7, Figure 6-8,
Offset Voltage vs Temperature
Figure 6-9, Figure 6-10
Offset Voltage vs Common-Mode Voltage
Figure 6-11, Figure 6-12
Offset Voltage vs Power Supply
Figure 6-13
Open-Loop Gain and Phase vs Frequency
Figure 6-14
Closed-Loop Gain and Phase vs Frequency
Figure 6-15
Input Bias Current vs Common-Mode Voltage
Figure 6-16
Input Bias Current vs Temperature
Figure 6-17
Output Voltage Swing vs Output Current (maximum supply)
Figure 6-18, Figure 6-19
CMRR and PSRR vs Frequency
Figure 6-20
CMRR vs Temperature
Figure 6-21
PSRR vs Temperature
Figure 6-22
0.1-Hz to 10-Hz Noise
Figure 6-23
Input Voltage Noise Spectral Density vs Frequency
Figure 6-24
THD+N Ratio vs Frequency
Figure 6-25
THD+N vs Output Amplitude
Figure 6-26
Quiescent Current vs Supply Voltage
Figure 6-27
Quiescent Current vs Temperature
Figure 6-28
Open Loop Gain vs Temperature
Figure 6-29, Figure 6-30
Open Loop Output Impedance vs Frequency
Figure 6-31
Small Signal Overshoot vs Capacitive Load (100-mV output step)
Figure 6-32, Figure 6-33
No Phase Reversal
Figure 6-34
Overload Recovery
Figure 6-35
Small-Signal Step Response (100 mV)
Figure 6-36, Figure 6-37
Large-Signal Step Response
Figure 6-38, Figure 6-39
Settling Time
Figure 6-40, Figure 6-41, Figure 6-42, Figure 6-43
Short-Circuit Current vs Temperature
Figure 6-44
Maximum Output Voltage vs Frequency
Figure 6-45
Propagation Delay Rising Edge
Figure 6-46
Propagation Delay Falling Edge
Figure 6-47
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SBOS701D – DECEMBER 2015 – REVISED AUGUST 2021
6.9 Typical Characteristics (continued)
at TA = 25°C, VS = ±18 V, VCM = VS / 2, RL = 10 kΩ connected to VS / 2, and CL = 100 pF (unless otherwise noted)
35
48
30
42
36
Amplifiers (%)
Amplifiers (%)
25
20
15
10
24
18
12
5
0
-25
30
6
-20
-15
-10
-5
0
5
10
Input Offset Voltage (PV)
15
20
0
-50
25
-40
-30
TA = 25°C
42
42
36
36
Amplifiers (%)
Amplifiers (%)
48
30
24
18
24
18
12
6
6
-20 -10
0
10
20
Input Offset Voltage (PV)
30
40
0
-50
50
-40
-30
TA = 85°C
42
42
36
36
Amplifiers (%)
Amplifiers (%)
48
30
24
18
50
24
18
12
6
6
-30 -15
0
15
30
Input Offset Voltage (PV)
45
60
75
0
-75
-60
-45
TA = –25°C
-30 -15
0
15
30
Input Offset Voltage (PV)
45
60
75
TA = –40°C
Figure 6-5. Offset Voltage Production Distribution
12
40
30
12
-45
30
Figure 6-4. Offset Voltage Production Distribution
48
-60
-20 -10
0
10
20
Input Offset Voltage (PV)
TA = 0°C
Figure 6-3. Offset Voltage Production Distribution
0
-75
50
30
12
-30
40
Figure 6-2. Offset Voltage Production Distribution
48
-40
30
TA = 125°C
Figure 6-1. Offset Voltage Production Distribution
0
-50
-20 -10
0
10
20
Input Offset Voltage (PV)
Figure 6-6. Offset Voltage Production Distribution
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SBOS701D – DECEMBER 2015 – REVISED AUGUST 2021
6.9 Typical Characteristics (continued)
40
30
30
Offset Voltage Drift (µV/ƒC)
Offset Voltage Drift (µV/ƒC)
C013
C013
TA = 0°C to 85°C, SOIC package
TA = –40°C to +125°C, SOIC package
Figure 6-8. Offset Voltage Drift Distribution
Figure 6-7. Offset Voltage Drift Distribution
125
125
Average r 3G
Average r 1G
100
Input Offset Voltage ( V)
75
Input Offset Voltage (PV)
0.8
0.6
0.4
0.2
0
-0.8
1.2
1
0.8
0.6
0.4
0.2
0
-0.2
-0.4
0
-0.6
0
-0.8
10
-1
10
-0.2
20
-0.4
20
-0.6
Amplifiers (%)
40
-1.2
Amplifiers (%)
at TA = 25°C, VS = ±18 V, VCM = VS / 2, RL = 10 kΩ connected to VS / 2, and CL = 100 pF (unless otherwise noted)
50
25
0
-25
-50
-75
75
25
±25
±75
-100
-125
-75
±125
-50
-25
0
25
50
75
Temperature (qC)
100
125
±75
150
±50
±25
0
25
50
75
100
125
Temperature (ƒC)
150
C001
4 typical units
Statistical distribution
Figure 6-10. Offset Voltage vs Temperature
Figure 6-9. Offset Voltage vs Temperature
250
25
Input Offset Voltage (µV)
Input Offset Voltage ( V)
200
15
VCM = ±18.1 V
5
±5
±15
Transition
150
100
P-Channel
VCM = -18.1 V
50
0
±50
N-Channel
VCM = 18 V
±100
±150
±200
±25
±250
±20
±15
±10
±5
0
5
10
Common Mode Voltage (V)
Figure 6-11. Offset Voltage vs Common-Mode Voltage
15
13
14
15
16
17
Common Mode Voltage (V)
C001
18
19
C001
Figure 6-12. Offset Voltage vs Common-Mode Voltage in
Transition Region
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SBOS701D – DECEMBER 2015 – REVISED AUGUST 2021
6.9 Typical Characteristics (continued)
160
20
140
15
120
10
100
5
80
Gain (dB)
25
0
-5
180
Open-loop Gain
135
Phase
90
45
60
0
40
-10
20
-15
0
-20
±20
-45
-90
-135
10M 100M
±40
-25
0
r5
r10
r15
Power Supply Voltage (V)
0.1
r20
Phase (ƒ)
Input Offset Volatge (PV)
at TA = 25°C, VS = ±18 V, VCM = VS / 2, RL = 10 kΩ connected to VS / 2, and CL = 100 pF (unless otherwise noted)
1.0
10.0 100.0
1k
10k
100k
1M
Frequency (Hz)
C001
30 typical units
Figure 6-13. Offset Voltage vs Power Supply
Figure 6-14. Open-Loop Gain and Phase
vs Frequency
1000
60
800
G = +1
600
Input Bias Current (pA)
40
G = -1
G= -10
Gain (dB)
G= -100
20
0
400
200
0
±200
±400
±600
±800
-20
±1000
100
1k
10k
100k
1M
10M
Frequency (Hz)
100M
±20
±10
±5
0
5
10
Common Mode Voltage (V)
Figure 6-15. Closed-Loop Gain vs Frequency
15
20
C001
Figure 6-16. Input Bias Current
vs Common-Mode Voltage
20
10
IB IB+
9
18
8
16
7
14
Output Voltage (V)
Input Bias Current (nA)
±15
C004
6
5
4
3
2
12
10
8
6
40qC
25qC
85qC
125qC
4
1
2
0
±75
±50
±25
0
25
50
75
100
125
Temperature (ƒC)
150
0
0
20
C001
40
60
Output Current (mA)
80
100
Sourcing
Figure 6-17. Input Bias Current vs Temperature
14
Figure 6-18. Output Voltage Swing
vs Output Current
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SBOS701D – DECEMBER 2015 – REVISED AUGUST 2021
6.9 Typical Characteristics (continued)
at TA = 25°C, VS = ±18 V, VCM = VS / 2, RL = 10 kΩ connected to VS / 2, and CL = 100 pF (unless otherwise noted)
0
Common-Mode Rejection Ratio (dB)
-4
Output Voltage (V)
140
40qC
25qC
85qC
125qC
-2
-6
-8
-10
-12
-14
-16
-18
120
100
80
60
40
CMRR
20
+PSRR
±PSRR
0
-20
0
20
40
60
Output Current (mA)
80
0.1
100
1.0
10.0
100.0
1k
10k
100k
1M
Frequency (Hz)
10M
C004
Sinking
Figure 6-20. CMRR and PSRR vs Frequency
10
5
VS = ±2.25 V, (V±) ” 9CM ” 9
8
Power-Supply Rejection Ratio (µV/V)
Common-Mode Rejection Ratio (µV/V)
Figure 6-19. Output Voltage Swing
vs Output Current
±3V
6
4
2
0
-2
VS = ±18 V, (V±) ” 9CM ” 9
±3V
-4
-6
-8
4
3
2
1
0
-1
-2
-3
-4
-5
-10
±75
±50
±25
0
25
50
75
100
Temperature (ƒC)
125
150
±75
±25
0
25
50
100
125
150
C001
Figure 6-22. PSRR vs Temperature
Voltage Noise Spectral Density (nv/¥Hz)
100
10
1
10
100
Time (1 s/div)
1k
10k
Frequency (Hz)
Figure 6-23. 0.1-Hz to 10-Hz Noise
75
Temperature (ƒC)
Figure 6-21. CMRR vs Temperature
400 nV/div
±50
C001
100k
1M
10M
C002
Figure 6-24. Input Voltage Noise Spectral Density vs Frequency
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SBOS701D – DECEMBER 2015 – REVISED AUGUST 2021
6.9 Typical Characteristics (continued)
0.1
0.5
-40
G = -1, 2k- Load
G = -1, 10k- Load
G = +1, 2k- Load
G = +1, 10k- Load
-60
0.01
-80
0.001
-100
0.0001
-120
-140
20k
0.00001
20
200
2k
Frequency (Hz)
C004
Total Harmonic Distortion + Noise (%)
1
Total Harmonic Distortion + Noise (dB)
Total Harmonic Distortion + Noise (%)
at TA = 25°C, VS = ±18 V, VCM = VS / 2, RL = 10 kΩ connected to VS / 2, and CL = 100 pF (unless otherwise noted)
G = 1 V/V, RL = 2 k:
G = 1 V/V, RL = 10 k:
0.1
0.01
0.001
0.0005
0.01
Figure 6-25. THD+N vs Frequency
VS = r2.25 V
20
180
VS = r18 V
160
Quiescent Current (µA)
Quiescent Current (PA)
10
200
180
140
120
100
80
60
40
VS = ±18 V
160
140
VS = ±2.25 V
120
100
80
60
40
20
20
0
0
0
2
4
6
8
10
12
14
Supply Voltage (V)
16
18
±75
20
5.0
4.0
4.0
3.0
3.0
AOL (µV/V)
0.0
±1.0
0
25
50
75
100
125
150
C001
VS = ±2.25 V
2.0
VS = ±2.25 V
1.0
±25
Figure 6-28. Quiescent Current vs Temperature
5.0
2.0
±50
Temperature (ƒC)
Figure 6-27. Quiescent Current vs Supply Voltage
AOL (µV/V)
0.1
1
Output Amplitude (VRMS)
Figure 6-26. THD+N vs Output Amplitude
200
VS = ±18 V
1.0
0.0
±1.0
±2.0
±2.0
±3.0
±3.0
±4.0
±4.0
VS = ±18 V
±5.0
±5.0
±75
±50
±25
0
25
50
75
100
125
Temperature (ƒC)
150
±75
±50
±25
0
25
50
75
100
125
Temperature (ƒC)
C001
RL = 10 kΩ
150
C001
RL = 2 kΩ
Figure 6-29. Open-Loop Gain vs Temperature
16
G = 1 V/V, RL = 2 k:
G = 1 V/V, RL = 10 k:
Figure 6-30. Open-Loop Gain vs Temperature
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SBOS701D – DECEMBER 2015 – REVISED AUGUST 2021
6.9 Typical Characteristics (continued)
at TA = 25°C, VS = ±18 V, VCM = VS / 2, RL = 10 kΩ connected to VS / 2, and CL = 100 pF (unless otherwise noted)
100k
60
RISO = 0
RISO = 25
50
RISO = 50
ZO (:)
Overshoot (%)
10k
1k
40
30
20
10
100
100m
0
1
10
100
1k
10k
Frequency (Hz)
100k
1M
10
10M
100
1000
Capacitive Load (pF)
C004
G = 1, 100-mV output step
Figure 6-32. Small-Signal Overshoot
vs Capacitive Load (100-mV Output Step)
Figure 6-31. Open-Loop Output Impedance
vs Frequency
20
Output
Input
RISO = 0
RISO = 25
Voltage (5 V/div)
Overshoot (%)
RISO = 50
10
0
10
100
1000
Capacitive Load (pF)
Time (50 Ps/div)
C004
G = –1, 100-mV output step
Figure 6-34. No Phase Reversal
20 mV/div
Negative overload
Positive overload
t=0
Output (V)
Figure 6-33. Small-Signal Overshoot
vs Capacitive Load
Time (2.5 µs/div)
Time (Ps)
C017
VS = ±18 V, G = –10 V/V
Figure 6-35. Overload Recovery
G = 1, CL = 10 pF
Figure 6-36. Small-Signal Step Response
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SBOS701D – DECEMBER 2015 – REVISED AUGUST 2021
6.9 Typical Characteristics (continued)
2 V/div
20 mV/div
at TA = 25°C, VS = ±18 V, VCM = VS / 2, RL = 10 kΩ connected to VS / 2, and CL = 100 pF (unless otherwise noted)
Time (2.5 µs/div)
Time (2.5 µs/div)
C017
C017
G = –1, RL = 1 kΩ, CL = 10 pF
G = 1, CL = 10 pF
Figure 6-37. Small-Signal Step Response
Figure 6-38. Large-Signal Step Response
2 V/div
Output Voltage (200 PV/div)
0.01% settling = r200 PV
Time (2.5 µs/div)
Time (500 ns/div)
C017
Gain = 1, 2-V step, rising, step applied at t = 0 µs
G = –1, RL = 1 kΩ, CL = 10 pF
Figure 6-40. 0.01% Settling Time
Figure 6-39. Large-Signal Step Response
Time (500 ns/div)
Time (500 ns/div)
Gain = 1, 2-V step, falling, step applied at t = 0 µs
Gain = 1, 5-V step, rising, step applied at t = 0 µs
Figure 6-41. 0.01% Settling Time
18
0.01% settling = r500 PV
Output Voltage (200 PV/div)
Output Voltage (200 PV/div)
0.01% settling = r200 PV
Figure 6-42. 0.01% Settling Time
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SBOS701D – DECEMBER 2015 – REVISED AUGUST 2021
6.9 Typical Characteristics (continued)
at TA = 25°C, VS = ±18 V, VCM = VS / 2, RL = 10 kΩ connected to VS / 2, and CL = 100 pF (unless otherwise noted)
100
Output Voltage (200 PV/div)
Short Circuit Current (mA)
0.01% settling = r500 PV
ISC, Source
80
60
ISC, Sink
40
20
0
±75
±50
±25
0
Time (500 ns/div)
25
50
75
100
125
Temperature (ƒC)
150
C001
Gain = 1, 5-V step, falling, step applied at t = 0 µs
Figure 6-43. 0.01% Settling Time
Figure 6-44. Short-Circuit Current vs Temperature
35
Maximum output voltage without
slew-rate induced distortion.
VS = ±15 V
25
20
15
10
Overdrive = 100 mV
Output Voltage (10 V/div)
Output Voltage (VPP)
30
VS = ±4 V
tpLH = 26 µs
VOUT Voltage
5
VS = ±2.25 V
0
100
1k
10k
100k
1M
Time (10 µs/div)
10M
Frequency (Hz)
C017
C001
Figure 6-46. Propagation Delay Rising Edge
Output Voltage (10 V/div)
Figure 6-45. Maximum Output Voltage vs Frequency
tpHL = 26 µs
VOUT Voltage
Overdrive = 100 mV
Time (10 µs/div)
C017
Figure 6-47. Propagation Delay Falling Edge
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SBOS701D – DECEMBER 2015 – REVISED AUGUST 2021
7 Parameter Measurement Information
7.1 Input Offset Voltage Drift
The OPAx191 family of operational amplifiers is manufactured using TI’s e-trim operation amplifier technology.
This e-trim operational amplifier technology is a TI proprietary method of trimming internal device parameters
during either wafer probing or final testing. Each amplifier input offset voltage and input offset voltage drift is
trimmed in production, thereby minimizing errors associated with input offset voltage and input offset voltage
drift. When trimming input offset voltage drift, the systematic or linear drift error on each device is trimmed to
zero. Figure 7-1 illustrates this concept.
Input Offset Voltage
VOS before trim
VOS after trim
Linear component of drift
Linear component of drift
Temperature
Figure 7-1. Input Offset Before and After Drift Trim
A common method of specifying input offset voltage drift is the box method. The box method estimates a
maximum input offset drift by bounding an offset voltage versus temperature curve with a box and using the
corners of this bounding box to determine the drift. The slope of the line connecting the diagonal corners of
the box corresponds to the input offset voltage drift. Figure 7-2 illustrates the box method concept. The box
method works particularly well when the input offset drift is dominated by the linear component of drift, but
because the OPA191 family uses TI’s e-trim operational amplifier technology to remove the linear component
input offset voltage drift, the box method is not a particularly useful method of accurately performing an error
analysis. Shown in Figure 7-2 are 30 typical units of OPAx191 with the box method superimposed for illustrative
purposes. The boundaries of the box are determined by the specified temperature range along the x-axis and
the maximum specified input offset voltage across that same temperature range along the y-axis. Using the
box method predicts an input offset voltage drift of 0.9 µV/°C. As shown in Figure 7-2, the slopes of the actual
input offset voltage versus temperature are much less than that predicted by the box method. The box method
predicts a pessimistic value for the maximum input offset voltage drift and is not recommended when performing
an error analysis.
Offset Voltage vs Temperature
100
75
Offset Voltage (PV)
50
25
0
-25
-50
-75
-100
-50
-25
0
25
50
75
Temperature (qC)
100
125
150
Figure 7-2. The Box Method
20
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Instead of the box method, a convenient way to illustrate input offset drift is to compute the slopes of the input
offset voltage versus temperature curve. This is the same as computing the input offset drift at each point along
the input offset voltage versus temperature curve. The results for the OPAx191 family are illustrated in Figure
7-3.
Input Offset Voltage Drift ( V / ºC)
1.2
0.9
0.6
+3 1
0.3
1
0
-1
-0.3
-0.6
-0.9
-3 1
-1.2
±75
±50
±25
0
25
50
75
100
125
Temperature (ƒC)
150
C001
Figure 7-3. Input Offset Voltage Drift vs Temperature (SOIC Package)
As illustrated in Figure 7-3, the input offset drift is typically less than ±0.3 µV/°C over the range from –40°C
to +125°C. When performing an error analysis over the full specified temperature range, use the typical and
maximum values for input offset voltage drift as described in the Electrical Characteristics tables. If a reduced
temperature range is applicable, use the information illustrated in Figure 7-3 when performing an error analysis.
To determine the change in input offset voltage, use Equation 1:
ΔVOS = ΔT × dVOS/dT
(1)
where
•
•
•
ΔVOS = Change in input offset voltage
ΔT = Change in temperature
dVOS/dT = Input offset voltage drift
For example, determine the amount of OPA191ID input offset voltage change over the temperature range of
25°C to 75°C for 1 σ (68%) of the units. As shown in Figure 7-3, the input offset drift is typically 0.25 µV/°C. This
input offset drift results in a typical input offset voltage change of (75°C – 25°C) × 0.25 µV/°C = 12.5 µV.
For 3 σ (99.7%) of the units, Figure 7-3 shows a typical input offset drift of approximately 0.75 µV/°C. This input
offset drift results in a typical input offset voltage change of (75°C – 25°C) × 0.75 µV/°C = 37.5 µV.
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8 Detailed Description
8.1 Overview
The OPAx191 family of e-trim operational amplifiers use a method of package-level trim for offset and offset
temperature drift implemented during the final steps of manufacturing after the plastic molding process. This
method minimizes the influence of inherent input transistor mismatch, as well as errors induced during package
molding. The trim communication occurs on the output pin of the standard pinout, and after the trim points
are set, further communication to the trim structure is permanently disabled. Section 8.2 shows the simplified
diagram of the OPAx191.
Unlike previous e-trim operational amplifiers, the OPAx191 uses a patented two-temperature trim architecture to
achieve a very low offset voltage and low voltage offset drift over the full specified temperature range. This level
of precision performance at wide supply voltages makes these amplifiers useful for high-impedance industrial
sensors, filters, and high-voltage data acquisition.
8.2 Functional Block Diagram
OPAx191
±
NCH Input
Stage
+
IN+
±
36-V
Differential
Front End
Slew
Boost
High
Capacitive Load
Compensation
Output
Stage
VOUT
+
IN±
+
PCH Input
Stage
±
e-WULPŒ
Operational Amplifier
Package Level Trim
22
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8.3 Feature Description
8.3.1 Input Protection Circuitry
The OPAx191 uses a unique input architecture to eliminate the need for input protection diodes but still provides
robust input protection under transient conditions. Conventional input diode protection schemes shown in Figure
8-1 can be activated by fast transient step responses and can introduce signal distortion and settling time
delays because of alternate current paths, as shown in Figure 8-2. For low-gain circuits, these fast-ramping input
signals forward-bias back-to-back diodes that cause an increase in input current, resulting in extended settling
time.
V+
V+
VIN+
VIN+
VOUT
VOUT
OPAx191
36 V
~0.7 V
VIN
VIN
V
OPAx191 Provides Full 36V Differential Input Range
V
Conventional Input Protection
Limits Differential Input Range
Figure 8-1. OPA191 Input Protection Does Not Limit Differential Input Capability
Vn = 10 V
RFILT
10 V
1
Ron_mux
Sn
1
D
10 V
CFILT
2
~±9.3 V
CS
CD
Vn+1 = ±10 V RFILT
±10 V
Ron_mux
Sn+1
VIN±
2
~0.7 V
CFILT
CS
VOUT
Idiode_transient
±10 V
Input Low-Pass Filter
Simplified Mux Model
VIN+
Buffer Amplifier
Figure 8-2. Back-to-Back Diodes Create Settling Issues
The OPAx191 family of operational amplifiers provides a true high-impedance differential input capability
for high-voltage applications. This patented input protection architecture does not introduce additional signal
distortion or delayed settling time, making the device an optimal op amp for multichannel, high-switched, input
applications. The OPAx191 tolerates a maximum differential swing (voltage between inverting and noninverting
pins of the op amp) of up to 36 V, making the device an excellent choice for use as a comparator or in
applications with fast-ramping input signals such as multiplexed data-acquisition systems (see Figure 9-4).
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8.3.2 EMI Rejection
The OPAx191 uses integrated electromagnetic interference (EMI) filtering to reduce the effects of EMI from
sources such as wireless communications and densely-populated boards with a mix of analog signal chain and
digital components. EMI immunity can be improved with circuit design techniques; the OPAx191 benefits from
these design improvements. Texas Instruments has developed the ability to accurately measure and quantify the
immunity of an operational amplifier over a broad frequency spectrum extending from 10 MHz to 6 GHz. Figure
8-3 shows the results of this testing on the OPAx191. Table 8-1 shows the EMIRR IN+ values for the OPAx191 at
particular frequencies commonly encountered in real-world applications. Applications listed in Table 8-1 may be
centered on or operated near the particular frequency shown. Detailed information can also be found in the EMI
Rejection Ratio of Operational Amplifiers application report , available for download from www.ti.com.
120
EMIRR IN+ (dB)
100
80
60
40
20
0
10
100
1k
Frequency (MHz)
10k
PRF = –10 dBm, VS = ±15 V, VCM = 0 V
Figure 8-3. EMIRR Testing
Table 8-1. OPA191 EMIRR IN+ For Frequencies of Interest
FREQUENCY
24
APPLICATION OR ALLOCATION
EMIRR IN+
400 MHz
Mobile radio, mobile satellite, space operation, weather, radar, ultra-high frequency (UHF)
applications
36 dB
900 MHz
Global system for mobile communications (GSM) applications, radio communication, navigation,
GPS (to 1.6 GHz), GSM, aeronautical mobile, UHF applications
45 dB
1.8 GHz
GSM applications, mobile personal communications, broadband, satellite, L-band (1 GHz to 2 GHz)
57 dB
2.4 GHz
802.11b, 802.11g, 802.11n, Bluetooth®, mobile personal communications, industrial, scientific and
medical (ISM) radio band, amateur radio and satellite, S-band (2 GHz to 4 GHz)
62 dB
3.6 GHz
Radiolocation, aero communication and navigation, satellite, mobile, S-band
76 dB
5.0 GHz
802.11a, 802.11n, aero communication and navigation, mobile communication, space and satellite
operation, C-band (4 GHz to 8 GHz)
86 dB
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8.3.3 Phase Reversal Protection
The OPAx191 family has internal phase-reversal protection. Many op amps exhibit phase reversal when the
input is driven beyond the linear common-mode range. This condition is most often encountered in noninverting
circuits when the input is driven beyond the specified common-mode voltage range, causing the output to
reverse into the opposite rail. The OPAx191 is a rail-to-rail input op amp, and therefore the common-mode range
can extend up to the rails. Input signals beyond the rails do not cause phase reversal; instead, the output limits
into the appropriate rail. This performance is shown in Figure 8-4.
5 V/div
VIN
VOUT
Time (35 ms/div)
C017
Figure 8-4. No Phase Reversal
8.3.4 Thermal Protection
The internal power dissipation of any amplifier causes the internal (junction) temperature to rise. This
phenomenon is called self heating. The OPAx191 has a thermal protection feature that prevents damage from
self heating.
This thermal protection works by monitoring the temperature of the output stage and turning off the op
amp output drive for temperatures above approximately 180°C. Thermal protection forces the output to a
high-impedance state. The OPAx191 is also designed with approximately 30°C of thermal hysteresis. Thermal
hysteresis prevents the output stage from cycling in and out of the high-impedance state. The OPAx191 returns
to normal operation when the output stage temperature falls below approximately 150°C.
The absolute maximum junction temperature of the OPAx191 is 150°C. Exceeding the limits shown in Section
6.1 may cause damage to the device. Thermal protection triggers at 180°C because of unit-to-unit variance,
but does not interfere with device operation up to the absolute maximum ratings. This thermal protection is not
designed to prevent this device from exceeding absolute maximum ratings, but rather from excessive thermal
overload.
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8.3.5 Capacitive Load and Stability
The OPAx191 features a patented output stage capable of driving large capacitive loads, and in a unity-gain
configuration, directly drives up to 1 nF of pure capacitive load. Increasing the gain enhances the ability of the
amplifier to drive greater capacitive loads; see Figure 8-5. The particular op amp circuit configuration, layout,
gain, and output loading are some of the factors to consider when establishing whether an amplifier will be stable
in operation.
Output (50 mV/Div)
G = +1 V/V
Time (2 Ps/Div)
Figure 8-5. Transient Response with a Purely Capacitive Load of 1 nF
Like many low-power amplifiers, some ringing can occur even with capacitive loads less than 100 pF. In
unity-gain configurations with no or very light dc loads, place an RC snubber circuit at the OPAx191 output
to reduce any possibility of ringing in lightly-loaded applications. Figure 8-6 illustrates the recommended RC
snubber circuit.
±
Output
Input
+
R 619
C 320 pF
Figure 8-6. RC Snubber Circuit for Lightly-Loaded Applications in Unity Gain
26
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For additional drive capability in unity-gain configurations, improve capacitive load drive by inserting a small,
10-Ω to 20-Ω resistor (RISO) in series with the output, as shown in Figure 8-7. This resistor significantly reduces
ringing while maintaining dc performance for purely capacitive loads. However, if there is a resistive load in
parallel with the capacitive load, a voltage divider is created, introducing a gain error at the output and slightly
reducing the output swing. The error introduced is proportional to the ratio RISO / RL, and is generally negligible
at low output levels. A high capacitive load drive makes the OPA191 a great choice for applications such as
reference buffers, MOSFET gate drives, and cable-shield drives. The circuit shown in Figure 8-7 uses RISO to
stabilize the output of an op amp. RISO modifies the open-loop gain of the system for increased phase margin.
Results using the OPA191 are summarized in Table 8-2. For additional information on techniques to optimize
and design using this circuit, TI Precision Design TIPD128, Capacitive Load Drive Verified Reference Design
Using an Isolation Resistor, details complete design goals, simulation, and test results.
+Vs
Vout
Riso
+
Vin
Cload
+
±
-Vs
Figure 8-7. Extending Capacitive Load Drive With the OPA191
Table 8-2. OPA191 Capacitive Load Drive Solution Using Isolation Resistor Comparison of Calculated
and Measured Results
PARAMETER
VALUE
Capacitive Load
100 pF
Phase Margin
45°
45°
1000 pF
60°
45°
0.01 µF
60°
45°
0.1 µF
60°
45°
1 µF
60°
RISO (Ω)
280
113
432
68
210
17.8
53.6
3.6
10
Measured
Overshoot (%)
23
23
8
23
8
23
8
23
8
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8.3.6 Common-Mode Voltage Range
The OPAx191 is a 36-V, true rail-to-rail input operational amplifier with an input common-mode range that
extends 100 mV beyond either supply rail. This wide range is achieved with paralleled complementary N-channel
and P-channel differential input pairs, as shown in Figure 8-8. The N-channel pair is active for input voltages
close to the positive rail, typically (V+) – 3 V to 100 mV above the positive supply. The P-channel pair is active
for inputs from 100 mV below the negative supply to approximately (V+) – 1.5 V. There is a small transition
region, typically ( V+) –3 V to (V+) – 1.5 V in which both input pairs are active. This transition region varies
modestly with process variation. Within this region PSRR, CMRR, offset voltage, offset drift, noise, and THD
performance are degraded compared to operation outside this region.
+Vsupply
IS1
VIN±
PCH1
NCH4
NCH3
PCH2
VIN+
e-TrimTM Integrated Circuit
FUSE BANK
VOS TRIM
VOS DRIFT TRIM
±Vsupply
Figure 8-8. Rail-to-Rail Input Stage
To achieve the best performance for two-stage rail-to-rail input amplifiers, avoid the transition region when
possible. The OPAx191 uses a precision trim for both the N-channel and P-channel regions. This technique
enables significantly lower levels of offset than previous-generation devices, causing variance in the transition
region of the input stages to appear exaggerated relative to offset over the full common-mode range, as shown
in Figure 8-9.
Transition
Region
N-Channel
Region
P-Channel
Region
200
200
100
100
Input Offset Voltage ( V)
Input Offset Voltage ( V)
P-Channel
Region
0
±100
OPAx191 e-WULPΠ2SHUDWLRQDO $PSOLILHU
Input Offset Voltage vs Vcm
±200
Transition
Region
N-Channel
Region
0
±100
±200
Input Offset Voltage vs Vcm
Without e-WULPΠ,QWHJUDWHG &LUFXLW
±300
±15.0
±14.0
«
11.0
12.0
13.0
Common-Mode Voltage (V)
14.0
15.0
±300
±15.0
±14.0
«
11.0
12.0
13.0
Common-Mode Voltage (V)
14.0
15.0
Figure 8-9. Common-Mode Transition vs Standard Rail-to-Rail Amplifiers
28
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8.3.7 Electrical Overstress
Designers often ask questions about the capability of an operational amplifier to withstand electrical overstress
(EOS). These questions tend to focus on the device inputs, but may involve the supply voltage pins or even
the output pin. Each of these different pin functions have electrical stress limits determined by the voltage
breakdown characteristics of the particular semiconductor fabrication process and specific circuits connected to
the pin. Additionally, internal electrostatic discharge (ESD) protection is built into these circuits to protect them
from accidental ESD events both before and during product assembly.
Having a good understanding of this basic ESD circuitry and its relevance to an electrical overstress event is
helpful. See Figure 8-10 for an illustration of the ESD circuits contained in the OPAx191 (indicated by the dashed
line area). The ESD protection circuitry involves several current-steering diodes connected from the input and
output pins and routed back to the internal power-supply lines, where the diodes meet at an absorption device
or the power-supply ESD cell, internal to the operational amplifier. This protection circuitry is intended to remain
inactive during normal circuit operation.
TVS
±
+
RF
+VS
VDD
R1
RS
IN±
100 Ÿ
IN+
100 Ÿ
OPAx191
±
+
Power-Supply
ESD Cell
ID
VIN
RL
+
±
VSS
±
+
±VS
TVS
Figure 8-10. Equivalent Internal ESD Circuitry Relative to a Typical Circuit Application
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An ESD event is very high voltage for a very short duration (for example, 1 kV for 100 ns); whereas, an EOS
event is lower voltage for a longer duration (for example, 50 V for 100 ms). The ESD diodes are designed for
out-of-circuit ESD protection (that is, during assembly, test, and storage of the device before being soldered to
the PCB). During an ESD event, the ESD signal is passed through the ESD steering diodes to an absorption
circuit labeled ESD power-supply circuit. The ESD absorption circuit clamps the supplies to a safe level.
Although this behavior is necessary for out-of-circuit protection, excessive current and damage is caused if
activated in-circuit. A transient voltage suppressor (TVS) can be used to prevent against damage caused by
turning on the ESD absorption circuit during an in-circuit ESD event. Using the appropriate current limiting
resistors and TVS diodes allows for the use of device ESD diodes to protect against EOS events.
8.3.8 Overload Recovery
Overload recovery is defined as the time required for the op amp output to recover from a saturated state to
a linear state. The output devices of the op amp enter a saturation region when the output voltage exceeds
the rated operating voltage, either due to the high input voltage or the high gain. After the device enters the
saturation region, the charge carriers in the output devices require time to return back to the linear state. After
the charge carriers return back to the linear state, the device begins to slew at the specified slew rate. Thus, the
propagation delay in case of an overload condition is the sum of the overload recovery time and the slew time.
8.4 Device Functional Modes
The OPAx191 has a single functional mode and is operational when the power-supply voltage is greater than
4.5 V (±2.25 V). The maximum power supply voltage for the OPAx191 is 36 V (±18 V).
30
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9 Application and Implementation
Note
Information in the following applications sections is not part of the TI component specification,
and TI does not warrant its accuracy or completeness. TI’s customers are responsible for
determining suitability of components for their purposes, as well as validating and testing their design
implementation to confirm system functionality.
9.1 Application Information
The OPAx191 family offers outstanding dc precision and ac performance. These devices operate up to 36-V
supply rails and offer true rail-to-rail input/output, ultralow offset voltage and offset voltage drift, as well as
2-MHz bandwidth and high capacitive load drive. These features make the OPAx191 a robust, high-performance
operational amplifier for high-voltage industrial applications.
9.2 Typical Applications
9.2.1 Low-side Current Measurement
Figure 9-1 shows the OPA191 configured in a low-side current sensing application. For a full analysis of the
circuit shown in Figure 9-1 including theory, calculations, simulations, and measured data, see TI Precision
Design TIPD129, 0-A to 1-A Single-Supply Low-Side Current-Sensing Solution .
VCC
5V
LOAD
+
OPA191
VOUT
ILOAD
RSHUNT
100 m
±
LM7705
RF
360 k
RG
7.5 k
Figure 9-1. OPA191 in a Low-Side, Current-Sensing Application
9.2.1.1 Design Requirements
The design requirements for this design are:
•
•
•
Load current: 0 A to 1 A
Output voltage: 4.9 V
Maximum shunt voltage: 100 mV
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9.2.1.2 Detailed Design Procedure
The transfer function of the circuit in Figure 9-1 is given in Equation 2
VOUT
ILOAD u RSHUNT u Gain
(2)
The load current (ILOAD) produces a voltage drop across the shunt resistor (RSHUNT). The load current is set
from 0 A to 1 A. To keep the shunt voltage below 100 mV at maximum load current, the largest shunt resistor is
defined using Equation 3.
VSHUNT _ MAX
RSHUNT
100mV
1A
ILOAD _ MAX
100m:
(3)
Using Equation 3, RSHUNT is calculated to be 100 mΩ. The voltage drop produced by ILOAD and RSHUNT is
amplified by the OPA191 to produce an output voltage of 0 V to 4.9 V. The gain needed by the OPA191 to
produce the necessary output voltage is calculated using Equation 4:
VOUT _ MAX
Gain
VIN _ MAX
VOUT _ MIN
VIN _ MIN
(4)
Using Equation 4, the required gain is calculated to be 49 V/V, which is set with resistors RF and RG. Equation 5
is used to size the resistors, RF and RG, to set the gain of the OPA191 to 49 V/V.
Gain 1
RF
RG
(5)
Choosing R F as 360 kΩ, R G is calculated to be 7.5 kΩ. R F and R G were chosen as 360 kΩ and 7.5 kΩ because
they are standard value resistors that create a 49:1 ratio. Other resistors that create a 49:1 ratio can also be
used. Figure 2 shows the measured transfer function of the circuit shown in Figure 9-1.
5
0.1
4
0.08
Error (%FSR)
Output (V)
9.2.1.3 Application Curves
3
2
1
0.04
0.02
0
0
0
0.1
0.2
0.3
0.4
0.5 0.6
ILOAD (A)
0.7
0.8
0.9
1
Figure 9-2. Low-Side, Current-Sense, Transfer
Function
32
0.06
0
0.1
0.2
0.3
0.4
0.5 0.6
ILOAD (A)
0.7
0.8
0.9
1
Figure 9-3. Low-Side, Current-Sense, Full-Scale
Error
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9.2.2 16-Bit Precision Multiplexed Data-Acquisition System
Figure 9-4 shows a 16-bit, differential, 4-channel, multiplexed, data-acquisition system. This example is typical
in industrial applications that require low distortion and a high-voltage differential input. The circuit uses the
ADS8864, a 16-bit, 400-kSPS successive-approximation-resistor (SAR), analog-to-digital converter (ADC), along
with a precision, high-voltage, signal-conditioning front-end, and a 4-channel differential multiplexer (mux). This
application example shows the process for optimizing the precision, high-voltage, front-end drive circuit using the
OPA191 and OPA140 to achieve excellent dynamic performance and linearity with the ADS8864. The full design
can be found in TI Precision Design TIPD151, 16-Bit, 400-kSPS, Four-Channel MUX Data Acquisition System
for High-Voltage Inputs.
1
2
Very Low Output Impedance
Input-Filter Bandwidth
3
High-Impedance Inputs
No Differential Input Clamps
Fast Settling-Time Requirements
Attenuate High-Voltage Input Signal
Fast-Settling Time Requirements
Stability of the Input Driver
Attenuate ADC Kickback Noise
VREF Output: Value and Accuracy
Low Temp and Long-Term Drift
Voltage
Reference
CH0+
±20-V,
10-kHz
Sine Wave
4
+
RC Filter
Buffer
RC Filter
OPA191
Reference Driver
+
Gain
Network
OPA191
CH0-
Gain
Network
+
OPA191
4:2
Mux
REFP
+
CH3+
±20-V,
10-kHz
Sine Wave
OPA140
Gain
Network
OPA191
+
VINP
+
Antialiasing
Filter
OPA191
SAR
ADC
+
VINM
OPA191
n
High-Voltage Multiplexed Input
CONV
Gain
Network
CH3-
16 Bits
400 kSPS
High-Voltage Level Translation
VCM
REF3240
Voltage
Divider
OPA350
VCM Generation Circuit
Counter
n
Shmidtt
Trigger
Delay
Digital Counter For Multiplexer
5
Fast logic transition
Figure 9-4. OPA191 in 16-Bit, 400-kSPS, 4-Channel, Multiplexed Data Acquisition System for High-Voltage
Inputs With Lowest Distortion
9.2.2.1 Design Requirements
The primary objective is to design a ±20-V, differential, 4-channel, multiplexed, data acquisition system with
lowest distortion using the 16-bit ADS8864 at a throughput of 400 kSPS for a 10-kHz, full-scale, pure sine-wave
input. The design requirements for this block design are:
•
•
•
•
•
System supply voltage: ±15 V
ADC supply voltage: 3.3 V
ADC sampling rate: 400 kSPS
ADC reference voltage (REFP): 4.096 V
System input signal: A high-voltage differential input signal with a peak amplitude of 10 V and frequency (fIN)
of 10 kHz are applied to each differential input of the mux.
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9.2.2.2 Detailed Design Procedure
The purpose of this application example is to design an optimal, high-voltage, multiplexed, data-acquisition
system for highest system linearity and fast settling. The overall system block diagram is shown in Figure 9-4.
The circuit is a multichannel, data-acquisition, signal chain consisting of an input low-pass filter, multiplexer
(mux), mux output buffer, attenuating SAR ADC driver, digital counter for the mux, and the reference driver. The
architecture allows fast sampling of multiple channels using a single ADC, providing a low-cost solution. The two
primary design considerations to maximize the performance of a precision, multiplexed, data-acquisition system
are the mux input analog front-end and the high-voltage, level translation, SAR ADC driver design. However,
carefully design each analog circuit block based on the ADC performance specifications in order to achieve
the fastest settling at 16-bit resolution and lowest distortion system. Figure 9-4 includes the most important
specifications for each individual analog block.
This design systematically approaches each analog circuit block to achieve a 16-bit settling for a full-scale input
stage voltage and linearity for a 10-kHz sinusoidal input signal at each input channel. The first step in the
design is to understand the requirement for an extremely-low-impedance input-filter design for the mux. This
understanding helps in the decision of an appropriate input filter and selection of a mux to meet the system
settling requirements. The next important step is the design of the attenuating analog front-end (AFE) used to
level translate the high-voltage input signal to a low-voltage ADC input while maintaining the amplifier stability.
Then, the next step is to design a digital interface to switch the mux input channels with minimum delay. The final
design challenge is to design a high-precision, reference-driver circuit that provides the required REFP reference
voltage with low offset, drift, and noise contributions.
9.2.3 Slew Rate Limit for Input Protection
In control systems for valves or motors, abrupt changes in voltages or currents can cause mechanical damages.
By controlling the slew rate of the command voltages into the drive circuits, the load voltages ramps up and
down at a safe rate. For symmetrical slew-rate applications (positive slew rate equals negative slew rate), one
additional op amp provides slew-rate control for a given analog gain stage. The unique input protection and high
output current and slew rate of the OPAx191 make the device an optimal amplifier to achieve slew rate control
for both dual-supply and single-supply systems. Figure 9-5 shows the OPA191 in a slew-rate limit design. For
step-by-step design procedure, circuit schematics, bill of materials, PCB files, simulation results, and test results,
refer to TI Precision Design TIPD140, Single Op-Amp Slew Rate Limiter..
Op Amp Gain Stage
Slew Rate Limiter
C1
R1
VCC
VCC
+
VIN
R2
OPA191
+
OPA191
+
VOUT
VEE
RL
VEE
Figure 9-5. Slew Rate Limiter Uses One Op Amp
34
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OPA191, OPA2191, OPA4191
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SBOS701D – DECEMBER 2015 – REVISED AUGUST 2021
10 Power Supply Recommendations
The OPAx191 is specified for operation from 4.5 V to 36 V (±2.25 V to ±18 V); many specifications apply from –
40°C to +125°C. Parameters that can exhibit significant variance with regard to operating voltage or temperature
are presented in Section 6.9.
CAUTION
Supply voltages larger than 40 V can permanently damage the device; see Section 6.1.
Place 0.1-μF bypass capacitors close to the power-supply pins to reduce errors coupling in from noisy or
high-impedance power supplies. For more detailed information on bypass capacitor placement, see Section 11.
11 Layout
11.1 Layout Guidelines
For best operational performance of the device, use good PCB layout practices, including:
•
•
•
•
•
•
•
•
Connect low-ESR, 0.1-µF ceramic bypass capacitors between each supply pin and ground, placed as close
to the device as possible. A single bypass capacitor from V+ to ground is applicable for single-supply
applications.
– Noise can propagate into analog circuitry through the power pins of the circuit as a whole and op amp
itself. Bypass capacitors are used to reduce the coupled noise by providing low-impedance power sources
local to the analog circuitry.
Make sure to physically separate digital and analog grounds paying attention to the flow of the ground
current. Separate grounding for analog and digital portions of circuitry is one of the simplest and mosteffective methods of noise suppression. One or more layers on multilayer PCBs are usually devoted to
ground planes. A ground plane helps distribute heat and reduces EMI noise pickup. For more detailed
information, refer to Circuit Board Layout Techniques.
In order to reduce parasitic coupling, run the input traces as far away from the supply or output traces as
possible. If these traces cannot be kept separate, crossing the sensitive trace perpendicular is much better as
opposed to in parallel with the noisy trace.
Place the external components as close to the device as possible. As shown in Figure 11-2, keeping RF and
RG close to the inverting input minimizes parasitic capacitance.
Keep the length of input traces as short as possible. Always remember that the input traces are the most
sensitive part of the circuit.
Consider a driven, low-impedance guard ring around the critical traces. A guard ring can significantly reduce
leakage currents from nearby traces that are at different potentials.
Clean the PCB following board assembly for best performance.
Any precision integrated circuit may experience performance shifts due to moisture ingress into the plastic
package. After any aqueous PCB cleaning process, bake the PCB assembly to remove moisture introduced
into the device packaging during the cleaning process. A low-temperature, post-cleaning bake at 85°C for 30
minutes is sufficient for most circumstances.
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SBOS701D – DECEMBER 2015 – REVISED AUGUST 2021
11.2 Layout Example
+
VIN
VOUT
RG
RF
Figure 11-1. Schematic Representation
Run the input traces
as far away from
the supply lines
as possible
Place components close
to device and to each
other to reduce parasitic
errors
VS+
RF
NC
NC
GND
±IN
V+
VIN
+IN
OUTPUT
V±
NC
Use a low-ESR,
ceramic bypass
capacitor
RG
GND
VS±
GND
VOUT
Ground (GND) plane on another layer
Use low-ESR,
ceramic bypass
capacitor
Figure 11-2. Operational Amplifier Board Layout for Noninverting Configuration
36
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OPA191, OPA2191, OPA4191
www.ti.com
SBOS701D – DECEMBER 2015 – REVISED AUGUST 2021
12 Device and Documentation Support
12.1 Device Support
12.1.1 Development Support
12.1.1.1 TINA-TI™ SImulation Software (Free Download)
TINA™ is a simple, powerful, and easy-to-use circuit simulation program based on a SPICE engine. TINA-TI
simulation software is a free, fully-functional version of the TINA software, preloaded with a library of macro
models in addition to a range of both passive and active models. TINA-TI simulation software provides all the
conventional dc, transient, and frequency domain analysis of SPICE, as well as additional design capabilities.
Available as a free download from the Analog eLab Design Center, TINA-TI simulation software offers extensive
post-processing capability that allows users to format results in a variety of ways. Virtual instruments offer
the ability to select input waveforms and probe circuit nodes, voltages, and waveforms, creating a dynamic
quick-start tool.
Note
These files require that either the TINA software (from DesignSoft™) or TINA-TI software be installed.
Download the free TINA-TI software from the TINA-TI folder at http://www.ti.com/tool/tina-ti.
12.1.1.2 TI Precision Designs
TI Precision Designs, available online at http://www.ti.com/ww/en/analog/precision-designs/, are analog solutions
created by TI’s precision analog applications experts and offer the theory of operation, component selection,
simulation, complete PCB schematic and layout, bill of materials, and measured performance of many useful
circuits.
12.2 Documentation Support
12.2.1 Related Documentation
•
•
Texas Instruments, Circuit Board Layout Techniques
Texas Instruments, Op Amps for Everyone design reference
12.3 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on
Subscribe to updates to register and receive a weekly digest of any product information that has changed. For
change details, review the revision history included in any revised document.
12.4 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
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Product Folder Links: OPA191 OPA2191 OPA4191
37
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SBOS701D – DECEMBER 2015 – REVISED AUGUST 2021
12.5 Trademarks
e-trim™ and TI E2E™ are trademarks of Texas Instruments.
TINA™ and DesignSoft™ are trademarks of DesignSoft, Inc.
Bluetooth® is a registered trademark of Bluetooth SIG, Inc.
All trademarks are the property of their respective owners.
12.6 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
12.7 Glossary
TI Glossary
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
38
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PACKAGE OPTION ADDENDUM
www.ti.com
28-Sep-2021
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
OPA191ID
ACTIVE
SOIC
D
8
75
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
OPA191
OPA191IDBVR
ACTIVE
SOT-23
DBV
5
3000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
ZAMV
OPA191IDBVT
ACTIVE
SOT-23
DBV
5
250
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
ZAMV
OPA191IDGKR
ACTIVE
VSSOP
DGK
8
2500
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
ZANV
OPA191IDGKT
ACTIVE
VSSOP
DGK
8
250
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
ZANV
OPA191IDR
ACTIVE
SOIC
D
8
2500
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
OPA191
OPA2191ID
ACTIVE
SOIC
D
8
75
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
2191
OPA2191IDGKR
ACTIVE
VSSOP
DGK
8
2500
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
2191
OPA2191IDGKT
ACTIVE
VSSOP
DGK
8
250
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
2191
OPA2191IDR
ACTIVE
SOIC
D
8
2500
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
2191
OPA4191ID
ACTIVE
SOIC
D
14
50
RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 125
OPA4191
OPA4191IDR
ACTIVE
SOIC
D
14
2500
RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 125
OPA4191
OPA4191IPWR
ACTIVE
TSSOP
PW
14
2000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
OPA4191
OPA4191IPWT
ACTIVE
TSSOP
PW
14
250
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
OPA4191
OPA4191IRUMR
ACTIVE
WQFN
RUM
16
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
OPA
4191
OPA4191IRUMT
ACTIVE
WQFN
RUM
16
250
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
OPA
4191
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
28-Sep-2021
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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