OPA628

® OPA 628 OPA628 Low Distortion Wideband OPERATIONAL AMPLIFIER FEATURES q EXCELLENT DIFFERENTIAL GAIN: 0.015% q EXCELLENT DIFFERENTIAL PHASE: 0.015° q LOW DISTORTION: 90dB SFDR q TWO-TONE THIRD-ORDER INTERCEPT: 60dBm q LOW NOISE: 2.5nV/√Hz q LOW NOISE FIGURE: 9dB q BANDWIDTH (Gain = +1): 160MHz q 0.1dB GAIN FLATNESS: 30MHz q LOW OFFSET VOLTAGE: 500µV APPLICATIONS q BROADCAST QUALITY VIDEO q MEDICAL IMAGING q LOW NOISE PREAMPLIFIER q PRECISION ADC/DAC BUFFER q TELECOMMUNICATIONS q ANALYTICAL INSTRUMENTS q ACTIVE FILTERS q DC RESTORATION CIRCUITS DESCRIPTION The OPA628 is a low distortion, wideband operational amplifier. It features low differential gain error of 0.015% and low differential phase error of 0.015° at NTSC and PAL frequencies with a 150Ω load (a backterminated 75Ω cable). The 0.1dB gain flatness to 30MHz, and the excellent differential gain and phase make the OPA628 ideal for broadcast quality video applications. In addition, the spurious free dynamic range of 90dB makes the OPA628 an excellent choice to buffer the input of precision Analog-to-Digital converters. It can also be used to provide a buffer for the output of precision high speed Digital-to-Analog converters. The two-tone third-order intercept of the OPA628 is 60dBm. The OPA628 is a unity gain stable, voltage feedback operational amplifier. It has all of the benefits associated with voltage feedback amplifiers including high input impedance, high common mode rejection, and symmetrical differential input flexibility. The unity gain bandwidth of the OPA628 is 160MHz. The low noise of 2.5nV/√Hz and low noise figure of 9dB (RS = 50Ω) make the OPA628 very useful in precision applications requiring wide dynamic range. The superior distortion performance of the OPA628 is achieved by its multistage architecture which provides high open-loop gain. The distortion performance is additionally enhanced by separating the power supplies to the input and output stages requiring four power supply connections as shown in the block diagram below. This separation of supplies eliminates the effects of package and wire bond parasitic capacitance and inductance. The OPA628 is powered with ±5VDC supplies for low power dissipation. The OPA628 is available in 8-pin SOIC package. The temperature range is –40°C to +85°C. +VCC, Input Stage 8 Active Load +VCC, Output Stage 7 Non-Inverting Input 3 +1 6 Output 2 Inverting Input 5 4 –VCC, Input Stage –VCC, Output Stage International Airport Industrial Park • Mailing Address: PO Box 11400, Tucson, AZ 85734 • Street Address: 6730 S. Tucson Blvd., Tucson, AZ 85706 • Tel: (520) 746-1111 • Twx: 910-952-1111 Internet: http://www.burr-brown.com/ • FAXLine: (800) 548-6133 (US/Canada Only) • Cable: BBRCORP • Telex: 066-6491 • FAX: (520) 889-1510 • Immediate Product Info: (800) 548-6132 ® © 1993 Burr-Brown Corporation PDS-1204B 1 Printed in U.S.A. March, 1998 OPA628 SPECIFICATIONS ELECTRICAL At VCC = ±5VDC, RL=100Ω, G = +2, and TA = +25°C, unless otherwise noted. OPA628AU PARAMETER INPUT NOISE Voltage: RS = 0Ω CONDITIONS fO = 100Hz fO = 1kHz fO = 10kHz fO = 100kHz fO = 1MHz to 100MHz fB = 100Hz to 10MHz fO = 100kHz to 100MHz RS = 50Ω, fO = 1MHz to 100MHz VCM = 0VDC TA = T MIN to TMAX ±VCC = ±4.5V to ±5.5V = ±4.5V to ±5.5V, TA = TMIN to TMAX VCM = 0VDC VCM = 0VDC, TA = TMIN to TMAX VCM = 0VDC TA = TMIN to TMAX Open–Loop MIN TYP 8.3 3.5 2.6 2.5 2.5 8.1 2.2 9.3 ±0.5 ±6 105 100 15 22 ±0.3 ±0.8 30 || 2 10 || 6 ±2.5 110 105 100 96 160 77 24 30 0.015 0.015 –91 –98 –90 –97 –83 –87 70 60 60 20 49 310 2 20 64 60 60 3 15 ±3 ±1 MAX UNITS nV/√Hz nv/√Hz nV/√Hz nV/√Hz nV/√Hz µVrms pA/√Hz dB mV µV/°C dB dB µA µA µA µA kΩ || pF MΩ || pF V dB dB dB dB MHz MHz MHz MHz % degrees dBc dBc dBc dBc dBc dBc dBm dBm dBm MHz MHz V/µs % ns ns ns degrees ns ns V V V Ω pF mA mA Current Noise Figure OFFSET VOLTAGE Input Offset Voltage Average Drift Supply Rejection (PSRR) Over Specification Temperature INPUT BIAS CURRENT Input Bias Current Over Specification Temperature Input Offset Current Over Specification Temperature INPUT IMPEDANCE Differential Common-Mode INPUT VOLTAGE RANGE Common-Mode Input Range Common-Mode Rejection (CMRR) Over Specification Temperature OPEN-LOOP GAIN, DC Open-Loop Voltage Gain Over Specification Temperature FREQUENCY RESPONSE Closed-Loop Bandwidth (–3dB) Bandwidth 0.1dB Flat Differential Gain Differential Phase Harmonic Distortion 90 ±VCC 30 ±2 VCM VCM = ±2.5V = ±2.5V, TA = TMIN to TMAX 90 90 TA = TMIN to TMAX 3rd-Order Intercept 3rd-Order Intercept Two-tone 3rd-Order Intercept Full Power Response(1) Slew Rate Overshoot Settling Time: 0.10% 0.01% Overload Recovery Time(2) Phase Margin Rise Time Small Signal Large Signal Gain = +1V/V Gain = +2V/V Gain = +5V/V Gain = +2V/V 3.58MHz, Gain = +2, VO = 1.4V Ramp 3.58MHz, Gain = +2, VO = 1.4V Ramp RL = 100Ω, G = +1V/V, f = 5MHz, VO = 2Vp-p Second Harmonic Third Harmonic RL = 500Ω, G = +2V/V, f = 5MHz, VO = 2Vp-p Second Harmonic Third Harmonic RL = 500Ω, G = +2V/V, f = 10MHz, VO = 2Vp-p Second Harmonic Third Harmonic fC = 5MHz, G = +2 fC = 10MHz, G = +2 fC = 5MHz, G = +2 VO = 5Vp-p, Gain = +1V/V VO = 2Vp-p, Gain = +1V/V 2V Step, Gain = –1V/V 2V Step, Gain = –1V/V 2V Step, Gain = –1V/V Gain = +1V/V Gain = +1V/V, 10% to 90% VO = 100mVp-p VO = 6Vp-p fO = 1MHz, RL = 100Ω fO = 1MHz, RL = 100Ω, TA = TMIN to TMAX fO = 1MHz, RL = 50Ω 1MHz, Gain = +1V/V Gain = +1V/V, VO = 2Vp-p Continuous, Source Continuous, Sink RATED OUTPUT Voltage Output Over Specification Temperature Output Resistance Load Capacitance Stability Short Circuit Current Short Circuit Current ® ±3 ±3 0.0005 20 +180 –130 OPA628 2 SPECIFICATIONS (CONT) ELECTRICAL At VCC = ±5VDC, RL=100Ω, G = +2, and TA = +25°C, unless otherwise noted. OPA628AU PARAMETER POWER SUPPLY Rated Voltage Derated Performance Current, Quiescent Current, Quiescent TEMPERATURE RANGE Specification: AU Storage: AU θ JA AU CONDITIONS ±VCC ±VCC IO = 0mADC IO = 0mADC, TA = TMIN to TMAX TMIN and TMAX Ambient Temperature Junction-to-Ambient MIN TYP ±5 29 31 –40 –55 100 MAX UNITS VDC VDC mA mA °C °C °C/W ±4.5 ±6 32 35 +85 +125 NOTES: (1) Full power response = slew rate/(2πVpeak). (2) Time for output to resume linear operation after saturation. PACKAGE/ORDERING INFORMATION PRODUCT OPA628AU PACKAGE SO-8 Surface Mount PACKAGE DRAWING NUMBER(1) 182 PIN CONFIGURATION Top View 8-Pin Plastic SOIC NOTE: (1) For detailed drawing and dimension table, please see end of data sheet, or Appendix C of Burr-Brown IC Data Book. No Internal Connection 1 2 OPA628 3 4 8 7 6 5 +VCC, Input Stage +VCC, Output Stage Output –VCC, Output Stage ABSOLUTE MAXIMUM RATINGS Supply .............................................................................................. ±7VDC Internal Power Dissipation(1) ........................ See Applications Information Differential Input Voltage ......................................................................... 5V Input Voltage Range ..................................... See Applications Information Storage Temperature Range: AP, AU ............................ –55°C to +125°C Lead Temperature (soldering, SOIC 3s) ........................................ +260°C Output Short Circuit to Ground (+25°C) ................. Continuous to Ground Junction Temperature (TJ ) ............................................................. +175°C NOTE: (1) Packages must be derated based on specified θJA. Maximum TJ must be observed. Inverting Input Non-Inverting Input –VCC, Input Stage ELECTROSTATIC DISCHARGE SENSITIVITY This integrated circuit can be damaged by ESD. Burr-Brown recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes no responsibility for the use of this information, and all use of such information shall be entirely at the user’s own risk. Prices and specifications are subject to change without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant any BURR-BROWN product for use in life support devices and/or systems. ® 3 OPA628 TYPICAL PERFORMANCE CURVES At VCC = ±5VDC, RL=100Ω, G = +2, and TA = +25°C, unless otherwise noted. OPEN-LOOP FREQUENCY RESPONSE 2 A V = +1V/V CLOSED-LOOP SMALL SIGNAL BANDWIDTH Phase Shift (°) AOL 100 80 Gain (dB) Gain Phase 0 Gain (dB) 1 Gain 60 40 20 0 –20 –45 –90 –135 Phase Margin = 60° –180 Phase Shift (°) 0 –1 –2 –3 –4 –5 –6 Phase Margin = 60° 1M 10M 100M 1G Open-Loop Phase Bandwidth = 160MHz –80 –100 –120 –140 –160 –180 100 1k 10k 100k 1M 10M 100M 1G Frequency (Hz) Frequency (Hz) A V = +2V/V CLOSED-LOOP SMALL SIGNAL BANDWIDTH A V = +5V/V CLOSED-LOOP SMALL SIGNAL BANDWIDTH Phase Shift (°) 8 7 6 Gain AOL AOL Gain 14 Gain (dB) Gain (dB) 5 4 3 2 1 0 1M Open-Loop Phase Bandwidth = 77MHz 13 12 11 10 9 8 1M Open-Loop Phase Phase Margin = 84° 10M 100M 1G Bandwidth = 24MHz –80 –100 –80 –100 –120 –140 –160 –180 Phase Margin = 75° 10M 100M 1G –120 –140 –160 –180 Frequency (Hz) Frequency (Hz) HARMONIC DISTORTION vs FREQUENCY –30 –40 Harmonic Distortion (dBc) HARMONIC DISTORTION vs FREQUENCY –30 –40 Harmonic Distortion (dBc) G = +1V/V VO = 2Vp-p RL = 100Ω G = +2V/V VO = 2Vp-p RL = 100Ω 2f –50 –60 –70 3f –80 –90 –100 100k 2f –50 –60 –70 3f –80 –90 –100 100k 1M Frequency (Hz) 10M 100M 1M Frequency (Hz) 10M 100M ® OPA628 4 Phase Shift (°) TYPICAL PERFORMANCE CURVES At VCC = ±5VDC, RL=100Ω, G = +2, and TA = +25°C, unless otherwise noted. (CONT) 5MHz HARMONIC DISTORTION vs OUTPUT SWING –70 G = +2V/V Harmonic Distortion (dBc) –70 –75 –80 –85 –90 –95 –100 5MHz HARMONIC DISTORTION vs LOAD RESISTANCE G = +2V/V VO = 2Vp-p –80 –85 2f –90 –95 3f –100 0 0.5 1.0 1.5 2.0 2.5 3.0 Output Swing (Vp-p) Harmonic Distortion (dBc) –75 2f 3f 0 100 200 300 400 500 600 700 800 900 1000 Load Resistance (Ω) 10MHz HARMONIC DISTORTION vs LOAD RESISTANCE –65 –70 –75 –80 –85 –90 –95 0 100 200 300 400 500 600 700 800 900 1000 Load Resistance (Ω) 2f G = +2V/V VO = 2Vp-p FULL-POWER BANDWIDTH vs OUTPUT SWING 1G Harmonic Distortion (dBc) G = +1V/V Bandwidth (Hz) 100M Slew Rate Limit G = +2V/V 3f G = +5V/V 10M 0 1 Slew Rate Limit for G = +5V/V 2 3 4 5 6 Output Swing (Vp-p) SETTLING TIME vs CLOSED-LOOP GAIN 100 90 80 Settling Time (ns) SETTLING TIME vs OUTPUT VOLTAGE CHANGE 100 90 80 0.01% 0.01% Settling Time (ns) 70 60 50 40 30 20 10 0 –1 –2 –3 Closed-Loop Gain –4 –5 0.1% VO = 2V step 70 60 50 40 30 20 10 0 0 1 2 3 4 5 Output Voltage Change (Vp-p) 0.1% Gain = –1V/V ® 5 OPA628 TYPICAL PERFORMANCE CURVES (CONT) At VCC = ±5VDC, RL=100Ω, G = +2, and TA = +25°C, unless otherwise noted. INPUT VOLTAGE NOISE SPECTRAL DENSITY vs FREQUENCY 100 100 INPUT CURRENT NOISE SPECTRAL DENSITY 10 Input Current Noise (pA/√Hz) 10 100 1k 10k 100k 1M 10M 100M Input Voltage Noise (nV/√Hz 10 1 Frequency (Hz) 1 10 100 1k 10k 100k 1M 10M 100M Frequency (Hz) SMALL SIGNAL TRANSIENT RESPONSE G = +1V/V RL = 100Ω CL = 10pF Output Voltage (V) LARGE SIGNAL TRANSIENT RESPONSE G = +1V/V RL = 100Ω CL = 10pF 60 Output Voltage (mV) 40 20 0 –20 –40 –60 3 2 1 0 –1 –2 –3 Time (ns) Time (ns) COMMON-MODE REJECTION vs FREQUENCY 120 Common-Mode Rejection (dB) POWER SUPPLY REJECTION vs FREQUENCY 120 100 80 60 40 20 0 100 1k 10k 100k 1M 10M 100M 1G Frequency (Hz) Power Supply Rejection (dB) 100 80 60 40 –PSR 20 0 100 1k 10k 100k 1M 10M 100M 1G Frequency (Hz) +PSR ® OPA628 6 TYPICAL PERFORMANCE CURVES (CONT) At VCC = ±5VDC, RL=100Ω, G = +2, and TA = +25°C, unless otherwise noted. BIAS AND OFFSET CURRENT vs INPUT COMMON-MODE VOLTAGE 25 0.9 120 COMMON-MODE REJECTION vs INPUT COMMON-MODE VOLTAGE Magnitude Offset Current (µA) 20 0.7 Bias Current Common-Mode Rejection (dB) Bias Current (µA) 100 15 0.5 80 10 Offset Current 5 –4 –3 –2 –1 0 1 2 3 4 Common-Mode Voltage (V) 0.3 60 0.1 40 –4 –3 –2 –1 0 1 2 3 4 Common-Mode Voltage (V) INPUT OFFSET VOLTAGE WARM-UP DRIFT 125 100 Offset Voltage Change (µV) BIAS AND OFFSET CURRENT vs TEMPERATURE 25 Bias Current 2.5 Bias Current (µA) 50 25 0 –25 –50 –75 –100 –125 0 20 40 60 80 100 120 140 160 180 Time (s) 15 1.5 10 Offset Current 5 1.0 0.5 0 –50 –25 0 25 50 75 100 125 Temperature (°C) 0 SUPPLY CURRENT vs TEMPERATURE 34 32 30 28 26 24 85 CMR, PSR, AOL (dB) Supply Current (mA) CMR, PSR, AND AOL vs TEMPERATURE 120 115 110 105 100 95 90 AOL PSR CMR 22 –50 –25 0 25 50 75 100 125 Temperature (°C) 80 –50 –25 0 25 50 75 100 125 Temperature (°C) Offset Bias Current (µA) ® 75 20 2.0 7 OPA628 TYPICAL PERFORMANCE CURVES At VCC = ±5VDC, RL=100Ω, G = +2, and TA = +25° C, unless otherwise noted. (CONT) RANGE OF CHANGE IN VOS vs TEMPERATURE RELATIVE TO VOS at 25°C 1.0 5MHz HARMONIC DISTORTION vs TEMPERATURE –70 –75 –80 –85 –90 –95 –100 3f 2f G = +2V/V VO = 2Vp-p RL = 100Ω Change In Offset Voltage (mV) 0.5 0 –0.5 –1.0 –50 –25 0 25 50 75 100 125 Temperature (°C) Harmonic Distortion (dBc) –50 –25 0 25 50 75 100 125 Temperature (°C) DISCUSSION OF PERFORMANCE The OPA628’s classical operational amplifier architecture employs true differential and fully symmetrical inputs allowing optimal performance in either inverting or noninverting circuit applications. All traditional circuit configurations and op amp theory apply to the OPA628. The use of low drift thin film resistors allows internal operating currents to be laser trimmed at wafer level to optimize AC performance such as distortion, bandwidth and settling time, as well as DC parameters such as input offset voltage. The result is a wideband, high frequency monolithic operational amplifier with a gain-bandwidth product of 150MHz, a spurious free dynamic range (SFDR) of 90dB, and input offset voltage of 500µV. The layout considerations described in the “Printed Circuit Board Guidelines” section must be followed to achieve the best possible performance of the OPA628. DIFFERENTIAL GAIN AND PHASE Differential Gain (DG) and Differential Phase (DP) are among the more important specifications for video applications. DG is defined as the percent change in closed-loop gain over a specified change in output voltage level. DP is defined as the change in degrees of the closed-loop phase over the same output voltage change. Both DG and DP are specified at the NTSC sub-carrier frequency of 3.58MHz and the PAL subcarrier of 4.43MHz. All NTSC measurements were performed using a Tektronix model VM700A Video Measurement Set. All PAL measurements were performed using a Rohde & Schwarz Video Analyzer UAF. DG and DP of the OPA628 were measured with the amplifier in a gain of +2V/V with 75Ω input impedance and the output back-terminated in 75Ω. The input signal selected from the generator was a 0V to 1.4V modulated ramp with sync pulse. With these conditions the test circuit shown in Figure 1 delivered a 100IRE modulated ramp to the 75Ω input of the video analyzer. The signal averaging feature of the analyzer was used to establish a reference against which the performance of the amplifier was measured. Signal averaging was also used to measure the DG and DP of the test signal in order to eliminate the generator’s contribution to measured amplifier performance. Typical performance of the OPA628 is 0.015% differential gain and 0.015° differential phase to both NTSC and PAL standards. Increasing the closed-loop gain degrades the DP and DG. GAIN FLATNESS Small signal ±0.1dB gain flatness can be achieved up to 30MHz in a non-inverting gain of +2V/V through careful layout of the printed circuit board and frequency shaping of the feedback network. Frequency shaping is achieved empirically by placing a small capacitor in parallel with either the feedback resistor or the input resistor of the OPA628 to compensate for printed circuit parasitic capacitance. A capacitor in the range of approximately 1pF to 20pF is suggested. Printed circuit board layout design will determine if the capacitor should be placed across the feedback resistor or the input resistor. Small signal ±0.1dB gain flatness of greater than 30MHz can be achieved at a gain of +1V/V. To eliminate the effects of package lead inductance, a small value resistor should be included in the feedback path. Maximizing gain flatness for a particular layout requires optimization of the feedback resistor; an approximate value is 50Ω to 75Ω. DISTORTION The OPA628’s Harmonic Distortion characteristics when driving a 100Ω load are shown vs frequency and vs voltage output in the Typical Performance Curves. Distortion can be further optimized by decreasing output loading as also ® OPA628 8 510Ω 510Ω 0.1µF 1 DUT 2 3 OPA628 7 6 VO 4 5 75Ω Tektronix VM700A 75Ω 0.1µF 8 75Ω + Tektronix TSG 130A 75Ω 0.1µF 0.1µF C = 10µF –5V C = 10µF +5V FIGURE 1. Configuration For Testing Differential Gain/Phase. shown in Typical Performance Curves. Include the contribution of the feedback resistance when calculating the effective load resistance at the amplifier output. A high performance spectrum analyzer such as the HP3585B should be used to measure distortion. Two-tone, third-order intermodulation distortion (IM) is an important parameter for many RF amplifier applications. The specification table shows the OPA628’s two-tone, third order IM intercept at 5MHz and 10MHz. For these measurements, tones were spaced 200kHz apart. This data is particularly useful for determining the magnitude of the third-order IM products. The magnitude of the third-order IM products can be easily calculated from the expression: Third IM = 2(OPI3P – PO) where = third-order output intercept, dBm PO = output level/tone, dBm/tone Third IM = third-order intermodulation ratio below each output tone, dB OPI3P As an example, with OPI3P = 60dBm, for PO = 10dBm, the third order IM = 2(60 – 10) = 100dB below either 10dBm tone. The OPA628’s low IM makes the device an excellent choice for a variety of RF signal processing applications. In order to obtain the full low distortion performance of the OPA628, it is imperative to follow the recommendations described in the “Printed Circuit Board Guidelines” section. OUTPUT DRIVE CAPABILITY The OPA628 has been optimized for low distortion performance with back terminated 50Ω and 75Ω loads (RLOAD = 100Ω and 150Ω, respectively). However, it is capable of driving 6Vpp into a 50Ω load with a sacrifice in distortion. This high-output drive capability makes the OPA628 an ideal choice for a wide range of RF, IF, and video applications. All transmission lines should be terminated with the characteristic impedance of the transmission line. Internal current-limiting circuitry limits output current to about 130mA at 25°C. This prevents damage from accidental shorts to common and eliminates the need for external current-limiting circuitry. Although the device can withstand momentary shorts to either power supply, it is not recommended. Many demanding high-speed applications such as ADC/ DAC buffers require op amps with low wideband output impedance. For example, low output impedance is essential when driving the signal-dependent capacitances at the inputs of flash A/D converters. As shown in Figure 2, the OPA628 maintains very low closed-loop output impedance over frequency. Closed-loop output impedance increases with frequency since loop gain is decreasing with frequency. NOISE FIGURE The OPA628’s voltage and current noise spectral densities are specified in the Typical Performance Curves. For RF applications, however, Noise Figure (NF) is often the preferred noise specification since it allows system noise performance to be more easily calculated. The OPA628’s Noise Figure vs Source Resistance is shown in Figure 3 for frequencies above 1MHz. 10 Small Signal Output Impedance (Ω) 1 100m G = +5V/V 10m 1m 100µ 10µ 100 1k 10k 100k Frequency (Hz) 1M 10M 100M G = +1V/V G = +2V/V FIGURE 2. Small Signal Output Impedance vs Frequency. ® 9 OPA628 NOISE FIGURE vs SOURCE RESISTANCE 25 en2 + (inRS)2 4kTRS 20 NFdB = 10log 1 + NF (dB) 15 In general, capacitive loads should be minimized for optimum high frequency performance. Coax lines can be driven if the cable is properly terminated. The capacitance of coax cable (29pF/ft for RG-58) will not load the amplifier when the coaxial cable or transmission line is terminated in its characteristic impedance. COMPENSATION The OPA628 is internally compensated and is stable in unity gain with a phase margin of approximately 60°. However, the unity gain buffer is the most demanding circuit configuration for loop stability and oscillations are most likely to occur in this gain. If possible, use the device in a noise gain of two or greater to improve phase margin and reduce the susceptibility to oscillation. (Note that, from a stability standpoint, an inverting gain of –1V/V is equivalent to a noise gain of 2V/V.) Gain and phase response for other gains are shown in the Typical Performance Curves. The high-frequency response of the OPA628 in a good layout is very flat with frequency. However, some circuit configurations, such as those where large feedback resistances are used, can produce high-frequency gain peaking. This peaking can be minimized by connecting a small capacitor in parallel with the feedback resistor. This capacitor compensates for the closed-loop, high frequency, transfer function zero that results from the time constant formed by the input capacitance of the amplifier (typically 2pF after PC board mounting), and the input and feedback resistors. The selected compensation capacitor may be a trimmer, a fixed capacitor, or a planned PC board capacitance. The capacitance value is strongly dependent on circuit layout and closed-loop gain. Using small resistor values will preserve the phase margin and avoid peaking by keeping the break frequency of this zero sufficiently high. When high closedloop gains are required, a three-resistor attenuator (tee network) is recommended to avoid using large value resistors with large time constants. THERMAL CONSIDERATIONS The OPA628 does not require a heat sink for operation in most environments. The use of a heat sink, however, will reduce the internal thermal rise and will result in cooler, more reliable operation. At extreme temperatures and under full load conditions a heat sink is necessary. See “Maximum Power Dissipation” curve, Figure 6. The internal power dissipation is given by the equation PD = PDQ + PDL, where PDQ is the quiescent power dissipation and PDL is the power dissipation in the output stage due to the load. (For ±VCC = ±5V, PDQ = 10V X 32mA = 320mW, max). For the case where the amplifier is driving a grounded load (RL) with a DC voltage (VOUT) the maximum valueofPDLoccurs at VOUT = VCC/2, and is equal to PDL, max = (VCC)2/4RL. Note that it is the voltage across the output transistor, and not the load, that determines the power dissipated in the output stage. When the output is shorted to common PDL = 5V X 180mA = 900mW. Thus, PD, max = 320mW + 900mW ≈ 1.2W. 10 5 0 10 100 1k Source Resistance (Ω) 10k 100k FIGURE 3. Noise Figure vs Source Resistance. SETTLING TIME Settling time is defined as the total time required, from the input signal step, for the output to settle to within the specified error band around the final value. This error band is expressed as a percentage of the value of the output transition, a 2V step. Thus, settling time to 0.01% requires an error band of ±200µV centered around the final value of 2V. Settling time, specified in an inverting gain of one, is only 64ns to 0.01% for a 2V step. Settling time increases with closed-loop gain and output voltage change as described in the Typical Performance Curves. Preserving settling time requires critical attention to the details as mentioned under “Printed Circuit Board Guidelines.” The amplifier also recovers quickly from input overloads. Overload recovery time to linear operation from a 50% overload is typically only 60ns. Settling time measurements for the OPA628 were performed in the circuit configuration of Figure 5. A sampling oscilloscope was used with signal averaging. CAPACITIVE LOADS Capacitive loads will decrease the OPA628’s phase margin which may cause high frequency peaking or oscillations. Capacitive loads greater than 20pF should be buffered by connecting a small resistance, usually 5Ω to 25Ω, in series with the output as shown in Figure 4. This is particularly important when driving high capacitance loads such as flash A/D converters. (RS typically 5Ω to 25Ω ) RS OPA628 RL CL FIGURE 4. Driving Capacitive Loads. ® OPA628 10 1 of settling response at b n+1 R2 c 50Ω nR2 R3 nR1 G = n+1 nR3 50Ω a R1 R1 50Ω OPA628 OPA620 b Tektronix11402 2V G = –n 1MΩ 15pF FIGURE 5. Settling Time Test Circuit. Note that the short circuit condition represents the maximum amount of internal power dissipation that can be generated. Thus, the “Maximum Power Dissipation” curve starts at 1.2W and is derated based on a 175°C maximum junction temperature and the junction-to-ambient thermal resistance, θJA, of the package. The variation of short circuit current with temperature is shown in Figure 7. INPUT PROTECTION Static damage has been well recognized for MOSFET devices, but any semiconductor device deserves protection from this potentially damaging source. The OPA628 incorporates on-chip ESD protection diodes as shown in Figure 8. This eliminates the need for the user to add external protection diodes, which can add capacitance and degrade AC performance. +VCC Internal Power Dissipation (W) 1.2 1.0 0.8 0.6 0.4 0.2 0 0 +25 +50 +75 +100 +125 +150 Ambient Temperature (°C) –VCC External Pin Internal Circuitry FIGURE 8. Internal ESD Protection. All pins on the OPA628 are internally protected from ESD by means of a pair of back-to-back reverse-biased diodes to either power supply as shown. These diodes will begin to conduct when the input voltage exceeds either power supply by about 0.7V. This situation can occur with loss of the amplifier’s power supplies while a signal source is still present. The diodes can typically withstand a continuous current of 30mA without destruction. To insure long term reliability, however, diode current should be externally limited to approximately 10mA whenever possible. OFFSET VOLTAGE ADJUSTMENT The OPA628’s input offset voltage is laser-trimmed and will require no further adjustment for most applications. However, if additional adjustment is needed, the circuit in Figure 9 can be used without degrading offset drift with temperature. Avoid external adjustment whenever possible since extraneous noise, such as power supply noise, can be inadvertently coupled into the amplifier’s inverting input terminal. Remember that additional offset errors can be created by FIGURE 6. Maximum Power Dissipation. 200 Short Circuit Current (mA) 180 Source 160 140 Sink 120 100 –50 –25 0 25 50 75 100 125 Temperature (°C) FIGURE 7. Short Circuit Current vs Temperature. ® 11 OPA628 the amplifier’s input bias currents. Whenever possible, match the impedance seen by both inputs as is shown with R3. This will reduce error due to the amplifier’s input bias current. of the board. A 2-ounce copper ground plane is recommended. The input signal ground return, the load return, and the power supply common should all be connected to the same physical point to avoid ground loops which can cause unwanted feedback. 2. The entire physical circuit should be as small as practical. All signal and power supply paths should be as short and direct as possible to minimize stray capacitance and inductance which are detrimental to high frequency performance. Minimize signal trace impedance by keeping traces as wide and short as possible. Stray capacitance should be minimized, especially at high impedance nodes such as the amplifier's input terminals. In addition, stray signal coupling from the output of the amplifier back to the input should be minimized. 3. In general, the use of surface mount components improves performance over through-hole components by minimizing parasitics. (However, it should be noted that use of the DIP version of the OPA628 will not compromise amplifier performance.) If circuit elements with leads are used, the leads should be kept as short as possible (6mm) to minimize lead inductance. Resistors used in feedback networks should have values of a few hundred ohms for best performance. Shunt capacitance problems limit the acceptable resistance range to about 1,000Ω on the high end and to a value that is within the amplifier's output drive limits on the low end. Remember that output current must be provided by the amplifier to drive its own feedback network as well as to drive its load. 4. As with any low distortion, wide bandwidth amplifier, power supply bypassing is extremely critical and must always be used. The system power supplies should be well bypassed at the board level with a minimum of 2.2µF tantalum capacitors. In addition, all four power supply leads should be locally bypassed to ground as close as possible to the amplifier pins. Surface mount 0.1µF capacitors will provide the best performance for local bypassing. Johanson 0.1µF capacitors (part number 250R18B104ZP4W) are used on the OPA628 demonstration board. All power supply bypass capacitors should be low impedance designs and should be located on the primary ground plane side of the PC board for the lowest impedance connection to ground. Properly bypassed and modulation free power supply lines allow optimum amplifier performance. 5. The OPA628 should be soldered directly into the PC board for best performance. +VCC RTrim 470kΩ –VCC R1 (1)R R2 20kΩ OPA628 3 = R1 || R 2 VIN or Ground Output Trim Range ≅ +V CC ( R 2 ) to –V CC ( R2 ) RTrim RTrim NOTE: (1) R3 is optional and can be used to reduce error due to input bias currents. FIGURE 9. Offset Voltage Trim. SPICE MODELS Computer simulation using SPICE is often useful when analyzing the performance of analog circuits and systems. This is particularly true for Video and RF amplifier circuits where parasitic capacitance and inductance can have a major effect on circuit performance. SPICE models are available for the OPA628. Contact Burr-Brown Applications Department to receive a SPICE diskette. RELIABILITY DATA Reliability reports are available upon request for each of the package options offered. PRINTED CIRCUIT BOARD GUIDELINES The printed circuit board layout is critical to obtaining the full performance of the OPA628, particularly optimum distortion and gain flatness. The guidelines below should be employed to design the OPA628 printed circuit board. 1. Establish the primary ground plane on the IC side of the PC board. The primary ground plane is the lowest impedance ground plane, it should be as wide as possible with minimal interruptions. Connect all unused space on both sides of the board to the ground plane. The ground plane should extend beneath the body of the IC on both sides ® OPA628 12 APPLICATIONS 390 Ω 390 Ω 75Ω Transmission Line 75Ω OPA628 Video Input 75Ω 75Ω VOUT High output current drive capability (6Vp-p into 75Ω) allows two back-terminated 75Ω transmission lines to be simultaneously driven. VOUT 75Ω 75Ω FIGURE 10. Video Distribution Amplifier. 249 Ω 249 Ω Differential Input SingleEnded Output 150 Ω 75 Ω 5Ω OPA628 RS 10 Ω 46 ADC614 12-Bit, 10MHz A/D Converter Signal Input 75Ω Triax Input 249 Ω OPA628 249 Ω Analog Common FIGURE 12. Low Distortion Unity Gain Difference Amplifier. NOTE: The value of RS varies with the value of the input capacitance of the A/D converter. RS is 0Ω for the ADC614 since the input capacitance in only 5pF. ADC INPUT CAPACITANCE CIN < 20pF CIN > 20pF RS 0Ω 30Ω to 50Ω FIGURE 11. Differential Input Buffer Amplifier (G = 2V/V). ® 13 OPA628