OPA
634
OPA634
OPA635
www.ti.com
Wideband, Single-Supply
OPERATIONAL AMPLIFIERS
TM
FEATURES
DESCRIPTION
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The OPA634 and OPA635 are low-power, voltagefeedback, high-speed amplifiers designed to operate on
+3V or +5V single-supply voltages. Operation on ±5V
or +10V supplies is also supported. The input range
extends below ground and to within 1.2V of the positive
supply. Using complementary common-emitter outputs
provides an output swing to within 30mV of ground and
140mV of positive supply. The high output drive current, low differential gain and phase errors make them
ideal for single-supply composite video line driving.
HIGH BANDWIDTH: 150MHz (G = +2)
+3V TO +10V SUPPLY OPERATION
ZERO POWER DISABLE (OPA635)
INPUT RANGE INCLUDES GROUND
4.8V OUTPUT SWING ON +5V SUPPLY
HIGH OUTPUT CURRENT: 80mA
HIGH SLEW RATE: 250V/µs
LOW INPUT VOLTAGE NOISE: 5.6nV/√HZ
AVAILABLE IN SOT23 PACKAGE
APPLICATIONS
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SINGLE-SUPPLY ADC INPUT BUFFERS
SINGLE SUPPLY VIDEO LINE DRIVERS
WIRELESS LAN IF AMPLIFIERS
CCD IMAGING CHANNELS
LOW-POWER ULTRASOUND
+3V
Disable
2.26kΩ
374Ω
DIS
VIN
100Ω
+3V
Pwrdn
ADS900
10-Bit
20Msps
OPA635
Low-distortion operation is ensured by the high gain
bandwidth product (140MHz) and slew rate (250V/µs).
This makes the OPA634 and OPA635 ideal input buffer
stages to 3V and 5V CMOS converters. Unlike other
low-power, single-supply operational amplifiers, distortion performance improves as the signal swing is decreased.
A low 5.6nV input voltage noise supports wide dynamic
range operation. Multiplexing or system power reduction can be achieved using the high-speed disable line
with the OPA635. Power dissipation can be reduced to
zero by taking the disable line HIGH.
The OPA634 and OPA635 are available in an industry
standard SO-8 package. The OPA634 is also available in
an ultra-small SOT23-5 package, while the OPA635 is
available in the SOT23-6. Where lower supply current
and speed are required, consider the OPA631 and OPA632.
22pF
562Ω
750Ω
RELATED PRODUCTS
DESCRIPTION
Copyright © 1999, Texas Instruments Incorporated
SINGLES
DUALS
Medium Speed, No Disable
With Disable
OPA631
OPA632
OPA2631
—
High Speed, No Disable
With Disable
OPA634
OPA635
OPA2634
—
SBOS097A
Printed in U.S.A. February, 2001
SPECIFICATIONS: VS = +5V
At TA = 25°C, G = +2, RF = 750Ω, and RL = 150Ω to VS/2, unless otherwise noted (see Figure 1).
OPA634U, N
OPA635U, N
TYP
GUARANTEED
CONDITIONS
+25°C
+25°C
0°C to
70°C
–40°C to
+85°C
UNITS
MIN/
MAX
TEST
LEVEL(1)
G = +2, VO ≤ 0.5Vp-p
G = +5, VO ≤ 0.5Vp-p
G = +10, VO ≤ 0.5Vp-p
G ≥ +10
VO ≤ 0.5Vp-p
G = +2, 2V Step
0.5V Step
0.5V Step
G = +2, 1V Step
VO = 2Vp-p, f = 5MHz
f > 1MHz
f > 1MHz
150
36
16
140
5
250
2.4
2.4
15
63
5.6
2.8
0.10
0.16
100
24
11
100
—
170
3.4
3.5
19
56
6.2
3.8
—
—
84
20
10
82
—
125
4.7
4.5
22
51
7.3
4.2
—
—
78
18
8
75
—
115
5.2
4.8
23
50
7.7
5
—
—
MHz
MHz
MHz
MHz
dB
V/µs
ns
ns
ns
dBc
nV/√Hz
pA/√Hz
%
degrees
min
min
min
min
typ
min
max
max
max
min
max
max
typ
typ
B
B
B
B
C
B
B
B
B
B
B
B
C
C
66
3
—
25
0.6
—
63
7
—
47
2.25
—
60
8
—
57
2.6
—
53
10
4.6
84
4.5
15
dB
mV
µV/°C
µA
µA
nA/°C
min
max
max
max
max
max
A
A
B
A
A
B
–0.24
3.8
78
–0.1
3.5
73
–0.05
3.45
71
–0.01
3.4
63
V
V
dB
max
min
min
B
A
A
10 || 2.1
400 || 1.2
—
—
—
—
—
—
kΩ || pF
kΩ || pF
typ
typ
C
C
Current Output, Sourcing
Current Output, Sinking
Short-Circuit Current (output shorted to either supply)
Closed-Loop Output Impedance
G = +2, f ≤ 100kHz
0.03
0.1
4.86
4.65
80
100
100
0.2
0.07
0.14
4.8
4.55
50
73
—
—
0.08
0.15
4.75
4.5
45
59
—
—
0.09
0.22
4.7
4.4
20
18
—
—
V
V
V
V
mA
mA
mA
Ω
max
max
min
min
min
min
typ
typ
A
A
A
A
A
A
C
C
DISABLE (OPA635 only)
On Voltage (device enabled Low)
Off Voltage (device disabled High)
On Disable Current (DIS pin)
Off Disable Current (DIS pin)
Disabled Quiescent Current
Disable Time
Enable Time
Off Isolation
f = 5MHz, Input to Output
1.0
4.0
70
0
0
100
60
70
1.0
4.1
110
—
30
—
—
—
1.0
4.2
120
—
40
—
—
—
1.0
4.3
120
—
50
—
—
—
V
V
µA
µA
µA
ns
ns
dB
max
min
max
typ
max
typ
typ
typ
A
A
A
C
A
C
C
C
Input Referred
—
—
12
12
55
2.7
10.5
12.7
11.3
52
2.7
10.5
13.2
9.75
50
2.7
10.5
13.5
8.5
49
V
V
mA
mA
dB
min
max
max
min
min
B
A
A
A
A
–40 to +85
°C
typ
C
125
150
°C/W
°C/W
typ
typ
C
C
PARAMETER
AC PERFORMANCE (Figure 1)
Small-Signal Bandwidth
Gain Bandwidth Product
Peaking at a Gain of +1
Slew Rate
Rise Time
Fall Time
Settling Time to 0.1%
Spurious Free Dynamic Range
Input Voltage Noise
Input Current Noise
NTSC Differential Gain
NTSC Differential Phase
DC PERFORMANCE
Open-Loop Voltage Gain
Input Offset Voltage
Average Offset Voltage Drift
Input Bias Current
Input Offset Current
Input Offset Current Drift
INPUT
Least Positive Input Voltage
Most Positive Input Voltage
Common-Mode Rejection (CMRR)
Input Impedance
Differential-Mode
Common-Mode
OUTPUT
Least Positive Output Voltage
Most Positive Output Voltage
POWER SUPPLY
Minimum Operating Voltage
Maximum Operating Voltage
Maximum Quiescent Current
Minimum Quiescent Current
Power Supply Rejection Ratio (PSRR)
THERMAL CHARACTERISTICS
Specification: U, N
Thermal Resistance
U
SO-8
N
SOT23-5, SOT23-6
VCM = 2.0V
VCM = 2.0V
Input Referred
RL = 1kΩ to 2.5V
RL = 150Ω to 2.5V
RL = 1kΩ to 2.5V
RL = 150Ω to 2.5V
NOTE: (1) Test Levels: (A) 100% tested at 25°C. Over temperature limits by characterization and simulation. (B) Limits set by characterization and simulation.
(C) Typical value only for information.
2
OPA634, OPA635
SBOS097A
SPECIFICATIONS: VS = +3V
At TA = 25°C, G = +2 and RL = 150Ω to VS/2, unless otherwise noted (see Figure 2).
OPA634U, N
OPA635U, N
TYP
PARAMETER
AC PERFORMANCE (Figure 2)
Small-Signal Bandwidth
Gain Bandwidth Product
Peaking at a Gain of +1
Slew Rate
Rise Time
Fall Time
Settling Time to 0.1%
Spurious Free Dynamic Range
Input Voltage Noise
Input Current Noise
DC PERFORMANCE
Open-Loop Voltage Gain
Input Offset Voltage
Average Offset Voltage Drift
Input Bias Current
Input Offset Current
Input Offset Current Drift
INPUT
Least Positive Input Voltage
Most Positive Input Voltage
Common-Mode Rejection (CMRR)
Input Impedance
Differential-Mode
Common-Mode
OUTPUT
Least Positive Output Voltage
Most Positive Output Voltage
CONDITIONS
+25°C
+25°C
0°C to
70°C
–40°C to
+85°C
UNITS
G = +2, VO ≤ 0.5Vp-p
G = +5, VO ≤ 0.5Vp-p
G = +10, VO ≤ 0.5Vp-p
G ≥ +10
VO ≤ 0.5Vp-p
1V Step
0.5V Step
0.5V Step
1V Step
VO = 1Vp-p, f = 5MHz
f > 1MHz
f > 1MHz
110
39
16
150
5
215
2.8
3.0
14
65
5.6
2.8
77
24
12
100
—
160
4.3
4.4
30
56
6.2
3.7
65
20
10
85
—
123
4.5
4.6
32
52
7.3
4.2
58
19
8
80
—
82
6.3
6.0
38
47
7.7
4.4
MHz
MHz
MHz
MHz
dB
V/µs
ns
ns
ns
dBc
nV/√Hz
pA/√Hz
min
min
min
min
typ
min
max
max
max
min
max
max
B
B
B
B
C
B
B
B
B
B
B
B
67
1.5
—
25
0.6
—
61
4
—
45
2
—
57
5
—
59
2.3
—
53
6
46
64
4
40
dB
mV
µV/°C
µA
µA
nA/°C
min
max
max
max
max
max
A
A
B
A
A
B
–0.25
1.8
75
–0.1
1.6
65
–0.05
1.55
62
–0.01
1.5
59
V
V
dB
max
min
min
B
A
A
10 || 2.1
400 || 1.2
—
—
—
—
—
—
kΩ || p
kΩ || p
typ
typ
C
C
0.035
0.06
2.9
2.8
45
65
100
0.2
0.043
0.16
2.86
2.70
35
30
—
—
0.045
0.19
2.85
2.69
30
27
—
—
0.06
0.43
2.45
2.65
12
10
—
—
V
V
V
V
mA
mA
mA
Ω
max
max
min
min
min
min
typ
typ
A
A
A
A
A
A
C
C
f = 5MHz, Input to Output
1.0
1.8
66
0
0
100
60
70
0.5
1.9
100
—
30
—
—
—
0.5
2.1
110
—
40
—
—
—
0.5
2.2
110
—
50
—
—
—
V
V
µA
µA
µA
ns
ns
dB
max
min
max
typ
max
typ
typ
typ
A
A
A
C
A
C
C
C
Input Referred
—
—
10.8
10.8
50
2.7
10.5
11.5
10.1
49
2.7
10.5
11.8
8.6
45
2.7
10.5
12
8.0
44
V
V
mA
mA
dB
min
max
max
min
min
B
A
A
A
A
–40 to +85
°C
typ
C
125
150
°C/W
°C/W
typ
typ
C
C
VCM = 1.0V
VCM = 1.0V
Input Referred
RL = 1kΩ to 1.5V
RL = 150Ω to 1.5V
RL = 1kΩ to 1.5V
RL = 150Ω to 1.5V
Current Output, Sourcing
Current Output, Sinking
Short Circuit Current (output shorted to either supply)
Closed-Loop Output Impedance
Figure 2, f < 100kHz
DISABLE (OPA635 only)
On Voltage (device enabled Low)
Off Voltage (device disabled High)
On Disable Current (DIS pin)
Off Disable Current (DIS pin)
Disabled Quiescent Current
Disable Time
Enable Time
Off Isolation
POWER SUPPLY
Minimum Operating Voltage
Maximum Operating Voltage
Maximum Quiescent Current
Minimum Quiescent Current
Power Supply Rejection Ratio (PSRR)
THERMAL CHARACTERISTICS
Specification: U, N
Thermal Resistance
U
SO-8
N
SOT23-5, SOT23-6
GUARANTEED
MIN/ TEST
MAX LEVEL(1)
NOTE: (1) Test Levels: (A) 100% tested at 25°C. Over temperature limits by characterization and simulation. (B) Limits set by characterization and simulation.
(C) Typical value only for information.
OPA634, OPA635
SBOS097A
3
PIN CONFIGURATIONS
Top View—OPA634, OPA635
NC
1
8
DIS (OPA635 only)
Inverting Input
2
7
+VS
Non-Inverting Input
3
6
Output
GND
4
5
NC
SO
Top View—OPA635
Top View—OPA634
Non-Inverting Input
3
4
1
6
+VS
GND
2
5
DIS
Inverting Input
Non-Inverting Input
3
4
Inverting Input
6
SOT23-6
4
6
SOT23-5
A35
1
3
2
B34
1
4
2
Output
+VS
3
GND
6
5
1
2
Output
Pin Orientation/Package Marking
Pin Orientation/Package Marking
ELECTROSTATIC
DISCHARGE SENSITIVITY
ABSOLUTE MAXIMUM RATINGS
Power Supply ................................................................................ +11VDC
Internal Power Dissipation .................................... See Thermal Analysis
Differential Input Voltage .................................................................. ±1.2V
Input Voltage Range ............................................................... –0.5 to +VS
Storage Temperature Range: P, U, N ........................... –40°C to +125°C
Lead Temperature (soldering, 10s) .............................................. +300°C
Junction Temperature (TJ ) ........................................................... +175°C
Electrostatic discharge can cause damage ranging from performance degradation to complete device failure. Burr-Brown Corporation recommends that all integrated circuits be handled and stored
using appropriate ESD protection methods.
ESD damage can range from subtle performance degradation to
complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes
could cause the device not to meet published specifications.
PACKAGE/ORDERING INFORMATION
PRODUCT
PACKAGE
PACKAGE
DRAWING
NUMBER
OPA634U
SO-8 Surface-Mount
182
–40°C to +85°C
OPA634U
"
"
"
"
SOT23-5
331
–40°C to +85°C
B34
"
"
"
"
SO-8 Surface-Mount
182
–40°C to +85°C
OPA635U
"
"
"
"
SOT23-6
332
–40°C to +85°C
A35
"
"
"
"
"
OPA634N
"
OPA635U
"
OPA635N
"
SPECIFIED
TEMPERATURE
RANGE
PACKAGE
MARKING
ORDERING
NUMBER(1)
TRANSPORT
MEDIA
OPA634U
OPA634U/2K5
OPA634N/250
OPA634N/3K
Rails
Tape and Reel
Tape and Reel
Tape and Reel
OPA635U
OPA635U/2K5
OPA635N/250
OPA635N/3K
Rails
Tape and Reel
Tape and Reel
Tape and Reel
NOTE: (1) Models with a slash (/) are available only in Tape and Reel in the quantities indicated (e.g., /2K5 indicates 2500 devices per reel). Ordering 3000 pieces
of “OPA635N/3K” will get a single 3000-piece Tape and Reel.
4
OPA634, OPA635
SBOS097A
TYPICAL PERFORMANCE CURVES: VS = +5V
At TA = 25°C, G = +2, RF = 750Ω, and RL = 150Ω to VS/2, unless otherwise noted (see Figure 1).
SMALL-SIGNAL FREQUENCY RESPONSE
LARGE-SIGNAL FREQUENCY RESPONSE
6
12
VO = 0.2Vp-p
9
0
6
G = +5
–3
Gain (dB)
Normalized Gain (dB)
VO = 0.2Vp-p
G = +2
3
–6
–9
G = +10
–12
3
0
VO = 1Vp-p
–3
VO = 2Vp-p
–6
VO = 4Vp-p
–15
–9
–18
–12
1
10
100
300
1
10
Frequency (MHz)
VO = 2Vp-p
Input and Output Voltage (500mV/div)
Input and Output Voltage (50mV/div)
VO = 200mVp-p
VO
VIN
VO
VIN
Time (10ns/div)
Time (10ns/div)
DISABLE FEEDTHROUGH vs FREQUENCY
LARGE-SIGNAL DISABLE/ENABLE RESPONSE
–35
VDIS
–45
Feedthrough (dB)
VO
OPA635 only
VDIS = +5V
–40
Output Voltage (250mV/div)
Disable Voltage (1V/div)
300
LARGE-SIGNAL PULSE RESPONSE
SMALL-SIGNAL PULSE RESPONSE
VIN = 0.5V
OPA635 only
100
Frequency (MHz)
–50
–55
–60
–65
–70
–75
–80
–85
Time (50ns/div)
1
10
100
1000
Frequency (MHz)
OPA634, OPA635
SBOS097A
5
TYPICAL PERFORMANCE CURVES: VS = +5V (Cont.)
At TA = 25°C, G = +2, RF = 750Ω, and RL = 150Ω to VS/2, unless otherwise noted (see Figure 1).
–40
–40
–45
–45
–50
–55
–60
–65
–70
RL = 150Ω
–75
RL = 250Ω
–80
–85
0.1
1
–70
RL = 500Ω
–75
–80
–90
0.1
1
4
Output Voltage (Vp-p)
10MHz 2nd-HARMONIC DISTORTION
vs OUTPUT VOLTAGE
10MHz 3rd-HARMONIC DISTORTION
vs OUTPUT VOLTAGE
–45
3rd-Harmonic Distortion (dBc)
–40
–45
–50
–55
RL = 250Ω
–60
–65
RL = 150Ω
–75
RL = 250Ω
–65
4
–80
RL = 500Ω
RL = 500Ω
–50
–55
RL = 250Ω
–60
–65
RL = 150Ω
–70
–75
–80
–85
–90
–90
0.1
1
0.1
4
1
4
Output Voltage (Vp-p)
Output Voltage (Vp-p)
20MHz 2nd-HARMONIC DISTORTION
vs OUTPUT VOLTAGE
20MHz 3rd-HARMONIC DISTORTION
vs OUTPUT VOLTAGE
–40
–40
RL = 250Ω
–50
–55
–45
RL = 500Ω
3rd-Harmonic Distortion (dBc)
–45
2nd-Harmonic Distortion (dBc)
–60
–40
–70
RL = 150Ω
–55
Output Voltage (Vp-p)
–85
RL = 150Ω
–60
–65
–70
–75
–80
–85
RL = 500Ω
–50
–55
RL = 250Ω
–60
–65
RL = 150Ω
–70
–75
–80
–85
–90
–90
0.1
1
Output Voltage (Vp-p)
6
–50
–85
RL = 500Ω
–90
2nd-Harmonic Distortion (dBc)
5MHz 3rd-HARMONIC DISTORTION
vs OUTPUT VOLTAGE
3rd-Harmonic Distortion (dBc)
2nd-Harmonic Distortion (dBc)
5MHz 2nd-HARMONIC DISTORTION
vs OUTPUT VOLTAGE
4
0.1
1
4
Output Voltage (Vp-p)
OPA634, OPA635
SBOS097A
TYPICAL PERFORMANCE CURVES: VS = +5V (Cont.)
At TA = 25°C, G = +2, RF = 750Ω, and RL = 150Ω to VS/2, unless otherwise noted (see Figure 1).
3rd-HARMONIC DISTORTION vs FREQUENCY
2nd-HARMONIC DISTORTION vs FREQUENCY
–40
VO = 2Vp-p
RL = 100Ω
–45
VO = 2Vp-p
RL = 100Ω
–45
3rd-Harmonic Distortion (dBc)
2nd-Harmonic Distortion (dBc)
–40
–50
–55
–60
–65
–70
G = +2
–75
–80
G = +5
–85
–50
–55
–60
–65
–70
G = +2
–75
G = +5
–80
G = +10
–85
G = +10
–90
–90
1
10
1
20
10
TWO-TONE, 3rd-ORDER
INTERMODULATION SPURIOUS
HARMONIC DISTORTION vs LOAD RESISTANCE
–40
–40
Harmonic Distortion (dBc)
–50
3rd-Order Spurious Level (dBc)
VO = 2Vp-p
fO = 5MHz
–45
3rd-Harmonic
Distortion
–55
–60
–65
–70
–75
–80
2nd-Harmonic
Distortion
–85
–90
fO = 20MHz
–45
–50
fO = 10MHz
–55
–60
–65
–70
–75
fO = 5MHz
–80
Load Power at
Matched 50Ω Load
–85
–90
100
200
300
400
500
–16 –14
–12
RL (Ω)
–10
–8
–6
–4
–2
0
Single-Tone Load Power (dBm)
CMRR AND PSRR vs FREQUENCY
INPUT NOISE DENSITY vs FREQUENCY
80
100
CMRR
75
70
Voltage Noise (nV/√Hz)
Current Noise (pA/√Hz)
Rejection Ratio, Input Referred (dB)
20
Frequency (MHz)
Frequency (MHz)
65
PSRR
60
55
50
45
40
10
Voltage Noise, eni = 5.6nV/√Hz
Current Noise, ini = 2.8pA/√Hz
35
30
1
100
1k
10k
100k
Frequency (Hz)
OPA634, OPA635
SBOS097A
1M
10M
100
1k
10k
100k
1M
10M
Frequency (Hz)
7
TYPICAL PERFORMANCE CURVES: VS = +5V (Cont.)
At TA = 25°C, G = +2, RF = 750Ω, and RL = 150Ω to VS/2, unless otherwise noted (see Figure 1).
RS vs CAPACITIVE LOAD
1000
FREQUENCY RESPONSE vs CAPACITIVE LOAD
2
CL = 1000pF
1
VO = 0.2Vp-p
Normalized Gain (dB)
0
RS (Ω)
100
10
CL = 10pF
–1
CL = 100pF
–2
–3
–4
RS
–5
OPA63x
VO
CL
–6
–7
1
100
1000
CLOSED-LOOP OUTPUT IMPEDANCE
vs FREQUENCY
100k
1M
10M
100M
G = +1
RF = 25Ω
10
1
0.1
1G
1k
10k
100k
Input Offset Voltage
4.0
40
3.5
35
3.0
30
25
Input Bias Current
2.0
20
1.5
15
10X Input Offset Current
10
0.5
5
0.0
0
20
40
Temperature (°C)
8
60
80
100
160
Sinking Output Current
14
Power-Supply Current (mA)
45
Input Bias Current (µA)
4.5
0
100M
16
10X Input Offset Current (µA)
Input Offset Voltage (mV)
50
–20
10M
SUPPLY AND OUTPUT CURRENT vs TEMPERATURE
INPUT DC ERRORS vs TEMPERATURE
–40
1M
Frequency (Hz)
5.0
2.5
300
100
Output Impedance (Ω)
0
–30
–60
–90
–120
–150
–180
–210
–240
–270
–300
–330
–360
Frequency (Hz)
1.0
100
OPEN-LOOP GAIN AND PHASE
Open-Loop Gain
10k
10
Frequency (MHz)
Open-Loop Phase
1k
1
Capacitive Load (pF)
140
Quiescent Supply Current
12
120
10
100
Sourcing Output Current
8
80
6
60
4
40
2
20
0
0
–40
–20
0
20
40
60
80
100
Temperature (°C)
OPA634, OPA635
SBOS097A
Output Current (mA)
10
Open-Loop Phase (°)
Open-Loop Gain (dB)
+VS/2
–8
1
100
90
80
70
60
50
40
30
20
10
0
–10
–20
1kΩ
TYPICAL PERFORMANCE CURVES: VS = +3V
At TA = 25°C, G = +2, RF = 750Ω, and RL = 150Ω to VS/2, unless otherwise noted (see Figure 2).
LARGE-SIGNAL FREQUENCY RESPONSE
SMALL-SIGNAL FREQUENCY RESPONSE
12
6
VO = 0.2Vp-p
VO = 0.2Vp-p
G = +2
9
6
0
G = +5
–3
Gain (dB)
Normalized Gain (dB)
3
–6
–9
G = +10
–12
3
VO = 1Vp-p
0
VO = 2Vp-p
–3
–6
–9
–15
–12
–18
1
10
100
1
300
10
2nd-HARMONIC DISTORTION vs FREQUENCY
–40
VO = 1Vp-p
RL = 100Ω
–50
–55
–60
–65
–70
G = +2
–75
G = +5
–80
–85
VO = 1Vp-p
RL = 100Ω
–45
3rd-Harmonic Distortion (dBc)
–45
2nd-Harmonic Distortion (dBc)
300
3rd-HARMONIC DISTORTION vs FREQUENCY
–40
–50
–55
–60
–65
G = +2
–70
G = +5
–75
G = +10
–80
–85
G = +10
–90
–90
1
10
20
1
Frequency (MHz)
HARMONIC DISTORTION vs LOAD RESISTANCE
TWO-TONE, 3rd-ORDER
INTERMODULATION SPURIOUS
–40
–50
3rd-Order Spurious Level (dBc)
VO = 1Vp-p
fO = 5MHz
–45
10
Frequency (MHz)
–40
Harmonic Distortion (dBc)
100
Frequency (MHz)
Frequency (MHz)
3rd-Harmonic
Distortion
–55
–60
–65
–70
–75
–80
2nd-Harmonic
Distortion
–85
–90
20
fO = 20MHz
–45
–50
–55
–60
fO = 10MHz
–65
–70
–75
–80
fO = 5MHz
–85
Load Power at
Matched 50Ω Load
–90
100
200
300
RL (Ω)
OPA634, OPA635
SBOS097A
400
500
–16
–14
–12
–10
–8
–6
–4
Single-Tone Load Power (dBm)
9
TYPICAL PERFORMANCE CURVES: VS = +3V (Cont.)
At TA = 25°C, G = +2, RF = 750Ω, and RL = 150Ω to VS/2, unless otherwise noted (see Figure 2).
FREQUENCY RESPONSE vs CAPACITIVE LOAD
RS vs CAPACITIVE LOAD
1000
2
CL = 1000pF
1
VO = 0.2Vp-p
Normalized Gain (dB)
0
RS (Ω)
100
10
CL = 10pF
–1
CL = 100pF
–2
–3
–4
RS
–5
OPA63x
VO
CL
–6
–7
1kΩ
+VS/2
–8
1
1
10
100
1
1000
10
100
300
Frequency (MHz)
Capacitive Load (pF)
OUTPUT SWING vs LOAD RESISTANCE
3.0
1.0
0.9
Left Scale
2.8
Maximum VO
2.7
0.8
0.7
2.6
0.6
2.5
0.5
2.4
0.4
2.3
Right Scale
2.2
Minimum VO
2.1
2.0
50
0.3
0.2
Minimum Output Voltage (V)
Maximum Output Voltage (V)
2.9
0.1
0.0
1000
100
RL (Ω)
10
OPA634, OPA635
SBOS097A
APPLICATIONS INFORMATION
WIDEBAND VOLTAGE FEEDBACK OPERATION
The OPA634 and OPA635 are unity-gain stable, very highspeed voltage feedback op amps designed for single supply
operation (+3V to +10V). The input stage supports input
voltages below ground, and to within 1.2V of the positive
supply. The complementary common-emitter output stage
provides an output swing to within 30mV of ground and
140mV of the positive supply. They are compensated to
provide stable operation with a wide range of resistive loads.
The OPA635’s internal disable circuitry is designed to
minimize supply current when disabled.
Figure 1 shows the AC-coupled, gain of +2 configuration
used for the +5V Specifications and Typical Performance
Curves. For test purposes, the input impedance is set to 50Ω
with a resistor to ground. Voltage swings reported in the
Specifications are taken directly at the input and output pins.
For the circuit of Figure 1, the total effective load on the
output at high frequencies is 150Ω || 1500Ω. The disable pin
needs to be driven by a low impedance source, such as a
CMOS inverter. The 1.50kΩ resistors at the non-inverting
input provide the common-mode bias voltage. Their parallel
combination equals the DC resistance at the inverting input,
(RF), minimizing the DC offset.
Figure 2 shows the DC-coupled, gain of +2 configuration
used for the +3V Specifications and Typical Performance
Curves. For test purposes, the input impedance is set to 50Ω
with a resistor to ground. Though not strictly a “rail-to-rail”
design, these parts come very close, while maintaining
excellent performance. They will deliver ≈ 2.8Vp-p on a
single +3V supply with 70MHz bandwidth. The 374Ω and
2.26kΩ resistors at the input level-shift VIN so that VOUT is
within the allowed output voltage range when VIN = 0. See
the typical performance curves for information on driving
capacitive loads.
+VS = 3V
6.8µF
+
2.26kΩ
0.1µF
374Ω
VIN
DIS (OPA635 only)
57.6Ω
VOUT
OPA63x
RL
150Ω
RG
562Ω
RF
750Ω
+VS
2
+VS = 5V
6.8µF
+
FIGURE 2. DC-Coupled Signal—Resistive Load to Supply
Midpoint.
0.1µF
1.50kΩ
0.1µF
VIN
DIS (OPA635 only)
53.6Ω
1.50kΩ
VOUT
OPA63x
RL
150Ω
z
0.1µF
RG
750Ω
RF
750Ω
+VS
2
FIGURE 1. AC-Coupled Signal—Resistive Load to Supply
Midpoint.
OPA634, OPA635
SBOS097A
SINGLE SUPPLY ADC CONVERTER INTERFACE
The front page shows a DC-coupled, single-supply ADC
(Analog-to-Digital Converter) driver circuit. Many systems
are now requiring +3V supply capability of both the ADC
and its driver. The OPA635 provides excellent performance
in this demanding application. Its large input and output
voltage ranges, and low distortion, support converters such
as the ADS900 shown in this figure. The input level-shifting
circuitry was designed so that VIN can be between 0V and
0.5V, while delivering an output voltage of 1V to 2V for the
ADS900. Both the OPA635 and ADS900 have power reduction pins with the same polarity for those systems that need
to conserve power.
11
DC LEVEL SHIFTING
Figure 3 shows a DC-coupled non-inverting amplifier that
level-shifts the input up to accommodate the desired output
voltage range. Given the desired signal gain (G), and the
amount VOUT needs to be shifted up (∆VOUT) when VIN is at
the center of its range, the following equations give the
resistor values that produce the desired performance. Start
by setting R4 between 200Ω and 1.5kΩ.
NG = G + ∆VOUT/VS
R1 = R4/G
NON-INVERTING AMPLIFIER WITH
REDUCED PEAKING
Figure 4 shows a non-inverting amplifier that reduces peaking at low gains. The resistor RC compensates the OPA634
or OPA635 to have higher Noise Gain (NG), which reduces
the AC response peaking (typically 5dB at G = +1 without
RC) without changing the DC gain. VIN needs to be a low
impedance source, such as an op amp. The resistor values
are low to reduce noise. Using both RT and RF helps
minimize the impact of parasitic impedances.
R2 = R4/(NG – G)
R3 = R4/(NG –1)
RT
where:
VIN
NG = 1 + R4/R3
RC
VOUT = (G)VIN + (NG – G)VS
VOUT
OPA63x
Make sure that VIN and VOUT stay within the specified input
and output voltage ranges.
RG
RF
+VS
R2
FIGURE 4. Compensated Non-Inverting Amplifier.
R1
VIN
OPA63x
R3
VOUT
R4
The Noise Gain can be calculated as follows:
G1 = 1 +
RF
RG
G2 = 1 +
R T + R F / G1
RC
NG = G1G 2
FIGURE 3. DC Level-Shifting Circuit.
The front page circuit is a good example of this type
of application. It was designed to take VIN between
0V and 0.5V, and produce VOUT between 1V and 2V,
when using a +3V supply. This means G = 2.00, and
∆VOUT = 1.50V – G • 0.25V = 1.00V. Plugging into the
above equations (with R4 = 750Ω) gives: NG = 2.33,
R1 = 375Ω, R2 = 2.25kΩ, and R3 = 563Ω. The resistors
were changed to the nearest standard values.
12
A unity gain buffer can be designed by selecting RT = RF =
20.0Ω and RC = 40.2Ω (do not use RG ). This gives a Noise
Gain of 2, so its response will be similar to the Characteristics Plots with G = +2. Decreasing RC to 20.0Ω will increase
the Noise Gain to 3, which typically gives a flat frequency
response, but with less bandwidth.
The circuit in Figure 1 can be redesigned to have less
peaking by increasing the noise gain to 3. This is accomplished by adding RC = 2.55kΩ between the op amps inputs.
OPA634, OPA635
SBOS097A
DESIGN-IN TOOLS
DEMONSTRATION BOARDS
Two PC boards are available to assist in the initial evaluation
of circuit performance using the OPA634 and OPA635 in
their three package styles. These are available free as an
unpopulated PC board delivered with descriptive documentation. The summary information for these boards is shown
in Table I.
PRODUCT
PACKAGE
OPA63xU
OPA63xN
SO-8
SOT23-5
SOT23-6
"
BOARD
PART
NUMBER
LITERATURE
REQUEST
NUMBER
DEM-OPA68xU
DEM-OPA6xxN
MKT-351
MKT-348
"
"
TABLE I. Demo Board Summary Information.
Contact the Texas Instruments Technical Applications Support Line at 1-972-644-5580 to request any of these boards.
OPERATING SUGGESTIONS
OPTIMIZING RESISTOR VALUES
Since the OPA634 and OPA635 are voltage feedback op
amps, a wide range of resistor values may be used for the
feedback and gain setting resistors. The primary limits on
these values are set by dynamic range (noise and distortion)
and parasitic capacitance considerations. For a non-inverting
unity gain follower application, the feedback connection
should be made with a 20Ω resistor, not a direct short (see
Figure 4 with RG = ∞). This will isolate the inverting input
capacitance from the output pin and improve the frequency
response flatness. Usually, for G > 1 application, the feedback resistor value should be between 200Ω and 1.5kΩ.
Below 200Ω, the feedback network will present additional
output loading which can degrade the harmonic distortion
performance. Above 1.5kΩ, the typical parasitic capacitance
(approximately 0.2pF) across the feedback resistor may
cause unintentional band-limiting in the amplifier response.
A good rule of thumb is to target the parallel combination of
RF and RG (Figure 1) to be less than approximately 400Ω.
The combined impedance RF || RG interacts with the inverting input capacitance, placing an additional pole in the
feedback network and thus, a zero in the forward response.
Assuming a 3pF total parasitic on the inverting node, holding RF || RG
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