OPA692

OPA692 OPA 692 OPA6 92 SBOS236C – MARCH 2002 – REVISED JANUARY 2003 Wideband, Fixed Gain Video BUFFER AMPLIFIER With Disable FEATURES q FLEXIBLE SUPPLY RANGE: +5V to +12V Single Supply ±2.5V to ±6V Dual Supplies q INTERNALLY FIXED GAIN: +2 or ±1 q HIGH BANDWIDTH (G = +2): 225MHz q LOW SUPPLY CURRENT: 5.1mA q LOW DISABLED CURRENT: 150µA q HIGH OUTPUT CURRENT: 190mA q OUTPUT VOLTAGE SWING: ±4.0V q SOT23-6 AVAILABLE DESCRIPTION The OPA692 provides an easy to use, broadband fixed gain video buffer amplifier. Depending on the external connections, the internal resistor network may be used to provide either a fixed gain of +2 video buffer or a gain of +1 or –1 voltage buffer. Operating on a very low 5.1mA supply current, the OPA692 offers a slew rate and output power normally associated with a much higher supply current. A new output stage architecture delivers high output current with minimal headroom and crossover distortion. This gives exceptional single-supply operation. Using a single +5V supply, the OPA692 can deliver a 1V to 4V output swing with over 120mA drive current and > 200MHz bandwidth. This combination of features makes the OPA692 an ideal RGB line driver or single-supply Analog-to-Digital Converter (ADC) input driver. The low 5.1mA supply current for the OPA692 is precisely trimmed at +25°C. This trim, along with low drift over temperature, ensures a lower maximum supply current than competing products that report only a room temperature nominal supply current. System power may be further reduced by using the optional disable control pin. Leaving this disable pin open, or holding it HIGH, gives normal operation. If pulled LOW, the OPA692 supply current drops to less than 150µA while the I/O pins go into a high-impedance state. APPLICATIONS q q q q q BROADBAND VIDEO LINE DRIVERS MULTIPLE LINE VIDEO DA PORTABLE INSTRUMENTS ADC BUFFERS ACTIVE FILTERS OPA692 RELATED PRODUCTS SINGLES Voltage-Feedback Current-Feedback Fixed Gain OPA690 OPA691 OPA682 DUALS OPA2690 OPA2691 OPA2682 TRIPLES OPA3690 OPA3691 OPA3692 75Ω OPA692 RG-59 1 2 3 8 7 6 75Ω 4 SO-8 G = +2 5 RG-59 75Ω DIS 75Ω +5V RG-59 75Ω 75Ω Video Out Video In 75Ω –5V 75Ω RG-59 75Ω 225MHz, 4-Output Component Video DA Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2002-2003, Texas Instruments Incorporated www.ti.com ABSOLUTE MAXIMUM RATINGS(1) Power Supply ............................................................................... ±6.5VDC Internal Power Dissipation(2) ............................ See Thermal Information Differential Input Voltage(3) ............................................................... ±1.2V Input Voltage Range ............................................................................ ±VS Storage Temperature Range: D, DVB ........................... –40°C to +125°C Lead Temperature (soldering, 10s) .............................................. +300°C Junction Temperature (TJ ) ........................................................... +175°C ESD Resistance: HBM ........................................................................ 2kV MM ........................................................................ 200V NOTES: (1) Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may degrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those specified is not implied. (2) Packages must be derated based on specified θJA. Maximum TJ must be observed. (3) Noninverting input to internal inverting node. ELECTROSTATIC DISCHARGE SENSITIVITY This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. PACKAGE/ORDERING INFORMATION PACKAGE DESIGNATOR(1) D SPECIFIED TEMPERATURE RANGE –40°C to +85°C PACKAGE MARKING OPA692 ORDERING NUMBER OPA692ID OPA692IDR OPA692IDBVT OPA692IDBVR TRANSPORT MEDIA, QUANTITY Rails, 100 Tape and Reel, 2500 Tape and Reel, 250 Tape and Reel, 3000 PRODUCT OPA692ID PACKAGE-LEAD SO-8 Surface-Mount " OPA692IDBV " SOT23-6 " DBV " –40°C to +85°C " OAGI " " " " " NOTES: (1) For the most current specifications and package information, refer to our web site at www.ti.com. PIN CONFIGURATION Top View SO Top View SOT Output 1 RF 402Ω 6 +VS –V S NC –IN +IN –VS 1 2 3 4 NC: No Connection RG 402Ω RF 402Ω 2 RG 402Ω 5 DIS 8 7 6 5 DIS +VS Output +IN 3 4 –IN 6 NC 5 4 OAGI 1 2 3 Pin Orientation/Package Marking 2 OPA692 www.ti.com SBOS236C ELECTRICAL CHARACTERISTICS: VS = ±5V Boldface limits are tested at +25°C. G = +2 (–IN grounded) and RL = 100Ω (see Figure 1 for AC performance only), unless otherwise noted. OPA692ID, IDBV TYP +25°C 280 225 220 120 0.2 220 2000 1.6 1.9 12 8 –69 –79 –76 –94 1.7 12 15 0.07 0.17 0.02 0.07 ±0.2 ±0.3 ±0.2 402 402 VCM = 0V VCM = 0V VCM = 0V VCM = 0V VCM = 0V VCM = 0V ±3.5 100 || 2 ±4.0 ±3.9 +190 –190 VO = 0 G = +2, f = 100kHz ±250 0.12 ±5 +15 +35 ±0.5 –62 –70 –72 –87 2.5 14 17 –59 –67 –70 –82 2.9 15 18 –57 –65 –68 –78 3.1 15 19 1400 1375 1350 40 1 35 1.5 30 2 185 180 170 MIN/MAX OVER TEMPERATURE +25°C(1) 0°C to 70°C –40°C to +85°C MIN/ TEST MAX LEVEL(2 ) PARAMETER AC PERFORMANCE (see Figure 1) Small-Signal Bandwidth (VO < 0.5Vp-p) CONDITIONS UNITS G = +1 G = +2 G = –1 MHz MHz MHz MHz dB MHz V/µs ns ns ns ns dBc dBc dBc dBc nV/√Hz pA/√Hz pA/√Hz % % deg deg typ min typ min max typ min typ typ typ typ max max max max max max max typ typ typ typ C B C B B C B C C C C B B B B B B B C C C C Bandwidth for 0.1dB Gain Flatness Peaking at a Gain of +1 Large-Signal Bandwidth Slew Rate Rise-and-Fall Time Settling Time to 0.02% 0.1% Harmonic Distortion 2nd-Harmonic 3rd-Harmonic Input Voltage Noise Noninverting Input Current Noise Inverting Input Current Noise Differential Gain Differential Phase DC PERFORMANCE(3) Gain Error G = +2, VO < 0.5Vp-p VO < 0.5Vp-p G = +2, VO = 5Vp-p G = +2, 4V Step G = +2, VO = 0.5V Step G = +2, VO = 5V Step G = +2, VO = 2V Step G = +2, VO = 2V Step G = +2, f = 5MHz, VO = 2Vp-p RL = 100Ω RL ≥ 500Ω RL = 100Ω RL ≥ 500Ω f > 1MHz f > 1MHz f > 1MHz NTSC, RL = 150Ω NTSC, RL = 37.5Ω NTSC, RL = 150Ω NTSC, RL = 37.5Ω G = +1 G = +2 G = –1 % typ max max max min max max max max max max max C A B A A B A B A B A B ±1.5 ±1.5 457 347 0.13 ±1.6 ±1.6 462 342 0.13 ±3.2 ±12 +43 –300 ±30 ±90 ±1.7 ±1.7 464 340 0.13 ±3.9 ±20 +45 –300 ±40 ±200 ±3.2 % % Ω Ω %/C° mV µV/°C µA nA/°C µA nA°C V kΩ || pF Internal RF and RG Maximum Minimum Average Drift Input Offset Voltage Average Offset Voltage Drift Noninverting Input Bias Current Average Noninverting Input Bias Current Drift Inverting Input Bias Current Average Inverting Input Bias Current Drift INPUT Common-Mode Input Range Noninverting Input Impedance OUTPUT Voltage Output Swing Current Output, Sourcing Sinking Short-Circuit Current Closed-Loop Output Impedance No Load 100Ω Load ±2.5 ±25 ±3.4 ±3.3 min typ B C ±3.8 ±3.7 +160 –160 ±3.7 ±3.6 +140 –140 ±3.6 ±3.3 +100 –100 V V mA mA mA Ω min min min min typ typ A A A A C C NOTES: (1) Junction temperature = ambient temperature for low temperature limit and +25°C specifications. Junction temperature = ambient temperature +10°C at high temperature limit specifications. (2) Test Levels: (A) 100% tested at +25°C. Over-temperature limits by characterization and simulation. (B) Limits set by characterization and simulation. (C) Typical value only for information. (3) Current is considered positive out-of-node. VCM is the input common-mode voltage. OPA692 SBOS236C www.ti.com 3 ELECTRICAL CHARACTERISTICS: VS = ±5V (Cont.) Boldface limits are tested at +25°C. G = +2 (–IN grounded) and RL = 100Ω (see Figure 1 for AC performance only), unless otherwise noted. OPA692ID, IDBV TYP +25°C MIN/MAX OVER TEMPERATURE +25°C(1) 0°C to 70°C –40°C to +85°C MIN/ TEST MAX LEVEL(2 ) PARAMETER DISABLE/POWER DOWN ( DIS Pin) Power-Down Supply Current (+VS) Disable Time Enable Time Off Isolation Output Capacitance in Disable Turn-On Glitch Turn-Off Glitch Enable Voltage Disable Voltage Control Pin Input Bias Current POWER SUPPLY Specified Operating Voltage Maximum Operating Voltage Range Maximum Quiescent Current Minimum Quiescent Current Power-Supply Rejection Ratio (–PSRR) TEMPERATURE RANGE Specification: D, DBV Thermal Resistance, θJA D DBV SO-8 SOT23-6 CONDITIONS UNITS µA µs ns dB pF mV mV VDIS = 0 VIN = +1VDC VIN = +1VDC G = +2, 5MHz G = +2, RL = 150Ω G = +2, RL= 150Ω –150 1 25 70 4 ±50 ±20 3.3 1.8 –300 –350 –400 max typ typ typ typ typ typ min max max A C C C C C C A A A 3.5 1.7 130 3.6 1.6 150 3.7 1.5 160 V V µA V VDIS = 0 75 ±5 typ max max min min C A A A A ±6 VS = ±5V VS = ±5V Input Referred 5.1 5.1 58 5.3 4.9 52 ±6 5.5 4.5 50 ±6 5.8 4.25 49 V mA mA dB °C °C/W °C/W –40 to +85 125 150 typ typ typ C C C NOTES: (1) Junction temperature = ambient temperature for low temperature limit and +25°C specifications. Junction temperature = ambient temperature +10°C at high temperature limit specifications. (2) Test Levels: (A) 100% tested at +25°C. Over-temperature limits by characterization and simulation. (B) Limits set by characterization and simulation. (C) Typical value only for information. (3) Current is considered positive out-of-node. VCM is the input common-mode voltage. 4 OPA692 www.ti.com SBOS236C ELECTRICAL CHARACTERISTICS: VS = +5V Boldface limits are tested at +25°C. G = +2 (–IN grounded though 0.1µF) and RL = 100Ω to VS/2 (see Figure 2 for AC performance only), unless otherwise noted. OPA692ID, IDBV TYP +25°C 240 190 195 90 0.2 210 830 2.0 2.3 14 10 –66 –73 –72 –77 1.7 12 15 –58 –65 –68 –72 2.5 14 17 –57 –63 –67 –70 2.9 15 18 –56 –62 –65 –69 3.1 15 19 600 575 550 40 1 30 2.5 25 3 168 160 140 MIN/MAX OVER TEMPERATURE +25°C(1) 0°C to 70°C –40°C to +85°C MIN/ TEST MAX LEVEL(2 ) PARAMETER AC PERFORMANCE (see Figure 2) Small-Signal Bandwidth (VO < 0.5Vp-p) CONDITIONS UNITS G = +1 G = +2 G = –1 MHz MHz MHz MHz dB MHz V/µs ns ns ns ns dBc dBc dBc dBc nV/√Hz pA/√Hz pA/√Hz typ min typ min max typ min typ typ typ typ max max max max max max max C B C B B C B C C C C B B B B B B B Bandwidth for 0.1dB Gain Flatness Peaking at a Gain of +1 Large-Signal Bandwidth Slew Rate Rise-and-Fall Time Settling Time to 0.02% 0.1% Harmonic Distortion 2nd-Harmonic 3rd-Harmonic Input Voltage Noise Noninverting Input Current Noise Inverting Input Current Noise DC PERFORMANCE(3) Gain Error G = +2, VO < 0.5Vp-p VO < 0.5Vp-p G = +2, VO = 2Vp-p G = +2, 2V Step G = +2, VO = 0.5V Step G = +2, VO = 2V Step G = +2, VO = 2V Step G = +2, VO = 2V Step G = +2, f = 5MHz, VO = 2Vp-p RL = 100Ω to VS /2 RL ≥ 500Ω to VS /2 RL = 100Ω to VS /2 RL ≥ 500Ω to VS /2 f > 1MHz f > 1MHz f > 1MHz G = +1 G = +2 G = –1 ±0.2 ±0.3 ±0.2 402 402 % typ max max max min max max max max max max max C A B B B B A B A B A B ±1.5 ±1.5 457 347 0.13 ±1.6 ±1.6 462 342 0.13 ±3.6 ±12 +46 –250 ±30 ±112 ±1.7 ±1.7 464 340 0.13 ±4.3 ±20 +56 –250 ±40 ±200 1.8 3.2 % % Ω Ω %/C° mV µV/°C µA nA/°C µA nA°C V V kΩ || pF Internal RF and RG Maximum Minimum Average Drift Input Offset Voltage Average Offset Voltage Drift Noninverting Input Bias Current Average Noninverting Input Bias Current Drift Inverting Input Bias Current Average Inverting Input Bias Current Drift INPUT Least Positive Input Voltage Most Positive Input Voltage Noninverting Input Impedance OUTPUT Most Positive Output Voltage Least Positive Output Voltage Current Output, Sourcing Sinking Short-Circuit Current Output Impedance VO = VS/2 G = +2, f = 100kHz No Load RL = 100Ω No Load RL = 100Ω 4.0 3.9 1.0 1.1 +160 –160 ±250 0.12 3.8 3.7 1.2 1.3 +120 –120 3.7 3.6 1.3 1.4 +100 –100 3.5 3.4 1.5 1.6 +80 –80 V V V V mA mA mA Ω min min max max min min typ typ A A A A A A C C 1.5 3.5 100 || 2 1.6 3.4 1.7 3.3 max min typ B B C VCM = 2.5V VCM = 2.5V VCM = 2.5V VCM = 2.5V VCM = 2.5V VCM = 2.5V ±5 +20 +40 ±0.5 ±3 ±25 NOTES: (1) Junction temperature = ambient temperature for low temperature limit and +25°C specifications. Junction temperature = ambient temperature +10°C at high temperature limit specifications. (2) Test Levels: (A) 100% tested at +25°C. Over-temperature limits by characterization and simulation. (B) Limits set by characterization and simulation. (C) Typical value only for information. (3) Current is considered positive out-of-node. VCM is the input common-mode voltage. OPA692 SBOS236C www.ti.com 5 ELECTRICAL CHARACTERISTICS: VS = +5V (Cont.) Boldface limits are tested at +25°C. G = +2 (–IN grounded though 0.1µF) and RL = 100Ω to VS/2 (see Figure 2 for AC performance only), unless otherwise noted. OPA692ID, IDBV TYP +25°C(1) +25°C MIN/MAX OVER TEMPERATURE 0°C to 70°C –40°C to +85°C MIN/ TEST MAX LEVEL(2 ) PARAMETER DISABLE/POWER DOWN ( DIS Pin) Power-Down Supply Current (+VS) Off Isolation Output Capacitance in Disable Turn-On Glitch Turn-Off Glitch Enable Voltage Disable Voltage Control Pin Input Bias Current ( DIS ) POWER SUPPLY Specified Single-Supply Operating Voltage Maximum Single-Supply Operating Voltage Maximum Quiescent Current Minimum Quiescent Current Power-Supply Rejection Ratio (+PSRR) TEMPERATURE RANGE Specification: D, DBV Thermal Resistance, θJA D SO-8 CONDITIONS UNITS µA dB pF mV mV VDIS = 0 G = +2, 5MHz G = +2, RL = 150Ω, VIN = 2.5V G = +2, RL = 150Ω, VIN = 2.5V –150 65 4 ±50 ±20 3.3 1.8 –300 –350 –400 typ typ typ typ typ min max typ C C C B B B B C 3.5 1.7 130 3.6 1.6 150 3.7 1.5 160 V V µA V VDIS = 0 75 5 12 VS = +5V VS = +5V Input Referred 4.5 4.5 55 4.8 4.1 12 5.0 3.8 12 5.2 3.7 typ max max min typ C A A A C V mA mA dB °C °C/W °C/W –40 to +85 125 150 typ typ typ C C C DBV SOT23-6 NOTES: (1) Junction temperature = ambient temperature for low temperature limit and +25°C specifications. Junction temperature = ambient temperature +10°C at high temperature limit specifications. (2) Test Levels: (A) 100% tested at +25°C. Over-temperature limits by characterization and simulation. (B) Limits set by characterization and simulation. (C) Typical value only for information. (3) Current is considered positive out-of-node. VCM is the input common-mode voltage. 6 OPA692 www.ti.com SBOS236C TYPICAL CHARACTERISTICS: VS = ±5V TA = +25°C, G = +2, and RL = 100Ω (see Figure 1 for DC performance only), unless otherwise noted. SMALL-SIGNAL FREQUENCY RESPONSE 1 0 Normalized Gain (1dB/div) 7 LARGE-SIGNAL FREQUENCY RESPONSE VO = 1Vp-p G = +1 G = –1 Gain (1dB/div) 6 5 4 VO = 4Vp-p 3 2 1 0 –1 –2 –3 –4 –5 –6 –7 –8 0 250MHz Frequency (50MHz/div) 500MHz G = +2 VO = 2Vp-p VO = 7Vp-p 0 125MHz Frequency (25MHz/div) 250MHz SMALL-SIGNAL PULSE RESPONSE 400 Output Voltage (100mV/div) 300 200 100 0 –100 –200 –300 –400 Time (5ns/div) VO = 0.5Vp-p G = +2 Output Voltage (1V/div) 4 3 2 1 0 –1 –2 –3 –4 LARGE-SIGNAL PULSE RESPONSE VO = 5Vp-p G = +2 Time (5ns/div) COMPOSITE VIDEO dG/dP 0.20 0.18 0.16 0.14 dG/dP (%/°) –5V Video In +5V DISABLED FEEDTHROUGH vs FREQUENCY –50 –55 Feedthrough (5dB/div) –60 –65 –70 –75 –80 –85 –90 –95 Forward Reverse VDIS = 0 DIS OPA692 Video Loads No Pull-Down With 1.3kΩ Pull-Down Optional 1.3kΩ Pull-Down dG 0.12 0.10 0.08 0.06 0.04 0.02 0 1 2 3 dG dP dP 4 0.5 1 10 Frequency (MHz) 100 Number of 150Ω Loads OPA692 SBOS236C www.ti.com 7 TYPICAL CHARACTERISTICS: VS = ±5V (Cont.) TA = +25°C, G = +2, and RL = 100Ω (see Figure 1 for DC performance only), unless otherwise noted. HARMONIC DISTORTION vs LOAD RESISTANCE –60 –65 VO = 2Vp-p f = 5MHz 2nd-Harmonic 5MHz HARMONIC DISTORTION vs SUPPLY VOLTAGE –50 –55 Harmonic Distortion (dBc) Harmonic Distortion (dBc) –70 –75 –80 –85 –90 –95 –100 –105 –110 100 Load Resistance (Ω) 1000 3rd-Harmonic VO = 2Vp-p RL = 100Ω f = 5MHz 2nd-Harmonic –60 –65 –70 –75 –80 3rd-Harmonic –85 –90 2 2.5 3 3.5 4 4.5 5 5.5 6 Supply Voltage (±VS) HARMONIC DISTORTION vs FREQUENCY (G = +2) –50 dBc = dB Below Carrier VO = 2Vp-p RL = 100Ω –65 HARMONIC DISTORTION vs OUTPUT VOLTAGE RL = 100Ω f = 5MHz 2nd-Harmonic Harmonic Distortion (dBc) Harmonic Distortion (dBc) –60 2nd-Harmonic –70 –70 –75 3rd-Harmonic –80 –80 3rd-Harmonic –90 –100 0.1 1 Frequency (MHz) 10 20 –85 0.1 1 Output Voltage Swing (Vp-p) 5 HARMONIC DISTORTION vs FREQUENCY (G = –1) –50 dBc = dB Below Carrier VO = 2Vp-p RL = 100Ω Harmonic Distortion (dBc) HARMONIC DISTORTION vs FREQUENCY (G = +1) –50 dBc = dB Below Carrier –60 VO = 2Vp-p RL = 100Ω Harmonic Distortion (dBc) –60 2nd-Harmonic –70 –70 3rd-Harmonic –80 –80 3rd-Harmonic –90 –90 2nd-Harmonic –100 0.1 1 Frequency (MHz) 10 20 –100 0.1 1 Frequency (MHz) 10 20 8 OPA692 www.ti.com SBOS236C TYPICAL CHARACTERISTICS: VS = ±5V (Cont.) TA = +25°C, G = +2, and RL = 100Ω (see Figure 1 for DC performance only), unless otherwise noted. INPUT VOLTAGE AND CURRENT NOISE DENSITY 100 2-TONE, 3RD-ORDER INTERMODULATION SPURIOUS –30 3rd-Order Spurious Level (dBc) dBc = dB below carriers 50MHz –40 –50 –60 20MHz –70 10MHz –80 –90 Load Power at Matched 50Ω Load –8 –6 –4 –2 0 2 4 6 8 10 Current Noise (pA/√Hz) Voltage Noise (nV/√Hz) Inverting Input Current Noise (15pA/√Hz) 10 Noninverting Current Noise (12pA/√Hz) Voltage Noise (1.7nV/√Hz) 1 100 1k 10k 100k 1M 10M Frequency (Hz) Single-Tone Load Power (dBm) RECOMMENDED RS vs CAPACITIVE LOAD FREQUENCY RESPONSE vs CAPACITIVE LOAD Normalized Gain to Capacitive Load (dB) 60 50 40 9 CL = 10pF 6 3 0 CL = 22pF –3 –6 –9 0 125MHz Frequency (25MHz/div) 250MHz VIN RS OPA692 RS (Ω) CL = 47pF 30 20 10 0 1 10 100 1k Capacitive Load (pF) VO CL = 100pF 402Ω 402Ω CL 1kΩ 1kΩ is optional. PSRR vs FREQUENCY 65 Power-Supply Rejection Ratio (dB) 10 SUPPLY AND OUTPUT CURRENT vs TEMPERATURE 250 Sourcing Output Current 60 55 –PSRR 50 45 40 35 30 25 20 1k 10k 100k 1M Supply Current (2mA) 8 Sinking Output Current 6 200 150 4 Quiescent Supply Current 2 100 50 0 0 –50 –25 0 25 50 75 100 125 Ambient Temperature (°C) 10M 100M Frequency (Hz) OPA692 SBOS236C www.ti.com 9 Output Current (50mA/div) +PSRR TYPICAL CHARACTERISTICS: VS = ±5V (Cont.) TA = +25°C, G = +2, and RL = 100Ω (see Figure 1 for DC performance only), unless otherwise noted. OUTPUT VOLTAGE AND CURRENT LIMITATIONS 5 4 3 2 1W Internal Power Limit Output Current Limited 2 1.5 TYPICAL DC DRIFT OVER TEMPERATURE 40 Noninverting Input Bias Current 30 20 10 Inverting Input Bias Current 0 –0.5 Input Offset Voltage –1 –1.5 –2 –20 –30 –40 –50 –25 0 25 50 75 100 125 Ambient Temperature (°C) 0 –10 Input Offset Voltage (mV) 1 0.5 VO (V) 1 0 –1 –2 –3 –4 –5 –300 –250 –200 –150 –100 –50 0 50 Output Current Limit 25Ω Load Line 50Ω Load Line 100Ω Load Line 1W Internal Power Limit 100 150 200 250 300 IO (mA) LARGE-SIGNAL DISABLE/ENABLE RESPONSE 6.0 DISABLE/ENABLE GLITCH 6.0 VDIS (2V/div) Output Voltage (400mV/div) 2.0 0 2.0 1.6 1.2 0.8 0.4 0 VIN = +1V Output Voltage Output Voltage (10mV/div) 2.0 0 30 20 10 0 –10 –20 Output Voltage (0V Input) Time (200ns/div) Time (20ns/div) CLOSED-LOOP OUTPUT IMPEDANCE 10 +5V Output Impedance (Ω) 50Ω OPA692 ZO –5V 402Ω 1 402Ω 0.1 10k 100k 1M Frequency (Hz) 10M 100M 10 OPA692 www.ti.com SBOS236C VDIS (2V/div) VDIS 4.0 VDIS 4.0 Input Bias Currents (µA) TYPICAL CHARACTERISTICS: VS = +5V TA = +25°C, G = +2, and RL = 100Ω (see Figure 2 for AC performance only), unless otherwise noted. SMALL-SIGNAL FREQUENCY RESPONSE 1 0 G = +1 –1 7 LARGE-SIGNAL FREQUENCY RESPONSE VO = 0.5Vp-p 6 5 Normalized Gain (1dB/div) Gain (1dB/div) –2 –3 –4 –5 –6 G = +2 –7 –8 0 G = –1 4 3 2 1 0 VO = 2Vp-p VO = 1Vp-p RL = 100Ω to 2.5V 0 125M Frequency (Hz) 250M 250M Frequency (Hz) 500M SMALL-SIGNAL PULSE RESPONSE 2.9 Output Voltage (100mV/div) Output Voltage (400mV/div) LARGE-SIGNAL PULSE RESPONSE 4.1 G = +2 VO = 2Vp-p 2.8 2.7 2.6 2.5 2.4 2.3 2.2 2.1 Time (5ns/div) G = +2 VO = 0.5Vp-p 3.7 3.3 2.9 2.5 2.1 1.7 1.3 0.9 Time (5ns/div) RECOMMENDED RS vs CAPACITIVE LOAD 70 60 FREQUENCY RESPONSE vs CAPACITIVE LOAD 9 6 Normalized Gain to Capacitive Load (dB) CL = 10pF CL = 22pF 50 3 CL = 47pF 0 +5V RS (Ω) 40 30 20 10 0 1 10 100 1k Capacitive Load (pF) –3 VIN 0.1µF 57.6Ω 806Ω RS 806Ω OPA692 CL 402Ω 402Ω 0.1µF (1kΩ is optional) VO 1kΩ CL = 100pF –6 –9 0 125MHz Frequency (25MHz/div) 250MHz OPA692 SBOS236C www.ti.com 11 TYPICAL CHARACTERISTICS: VS = +5V (Cont.) TA = +25°C, G = +2, and RL = 100Ω (see Figure 2 for AC performance only), unless otherwise noted. HARMONIC DISTORTION vs LOAD RESISTANCE –60 VO = 2Vp-p f = 5MHz HARMONIC DISTORTION vs FREQUENCY –50 VO = 2Vp-p RL = 100Ω to 2.5V –60 2nd-Harmonic –70 Harmonic Distortion (dBc) –65 2nd-Harmonic –70 3rd-Harmonic –75 Harmonic Distortion (dBc) –80 3rd-Harmonic –90 –80 100 Load Resistance (Ω) 1k 0.1 1 Frequency (MHz) 10 20 HARMONIC DISTORTION vs OUTPUT VOLTAGE –60 2-TONE, 3RD-ORDER INTERMODULATION SPURIOUS –30 dBc = dB Below Carriers 50MHz –35 –40 –45 –50 –55 –60 –65 –70 –75 –80 –14 –12 –10 –8 Load Power at Matched 50Ω Load –6 –4 –2 0 2 10MHz 20MHz –65 2nd-Harmonic –70 –75 3rd-Harmonic –80 0.1 1 Output Voltage Swing (Vp-p) 2 3 3rd-Order Spurious Level (dBc) Harmonic Distortion (dBc) RL = 100Ω to 2.5V f = 5MHz Single-Tone Load Power (dBm) 12 OPA692 www.ti.com SBOS236C APPLICATIONS INFORMATION WIDEBAND BUFFER OPERATION The OPA692 gives the exceptional AC performance of a wideband current-feedback op amp with a highly linear, highpower output stage. It features internal RF and RG resistors that make it easy to select a gain of +2, +1, or –1 without any external resistors. Requiring only 5.1mA quiescent current, the OPA692 will swing to within 1V of either supply rail and deliver in excess of 160mA at room temperature. This low output headroom requirement, along with supply voltage independent biasing, gives remarkable single (+5V) supply operation. The OPA692 will deliver greater than 200MHz bandwidth driving a 2Vp-p output into 100Ω on a single +5V supply. Previous boosted output stage amplifiers have typically suffered from very poor crossover distortion as the output current goes through zero. The OPA692 achieves a comparable power gain with much better linearity. The primary advantage of a current-feedback op amp over a voltage-feedback op amp is that AC performance (bandwidth and distortion) is relatively independent of signal gain. Figure 1 shows the DC-coupled, gain of +2, dual power-supply circuit configuration used as the basis of the ±5V Electrical and Typical Characteristics. For test purposes, the input impedance is set to 50Ω with a resistor to ground and the output impedance is set to 50Ω with a series output resistor. Voltage swings reported in the specifications are taken directly at the input and output pins while load powers (dBm) are defined at a matched 50Ω load. For the circuit of Figure 1, the total effective load will be 100Ω || 804Ω = 89Ω. The disable control line (DIS ) is typically left open to ensure normal amplifier operation. In addition to the usual power-supply decoupling capacitors to ground, a 0.1µF capacitor can be included between the two power-supply pins. This optional added capacitor will typically improve the 2nd-harmonic distortion performance by 3dB to 6dB. +5V DIS 0.1µF + 6.8µF Figure 2 shows the AC-coupled, gain of +2, single-supply circuit configuration used as the basis of the +5V Electrical and Typical Characteristics. Though not a rail-to-rail design, the OPA692 requires minimal input and output voltage headroom compared to other very wideband current-feedback op amps. It will deliver a 3Vp-p output swing on a single +5V supply with greater than 150MHz bandwidth. The key requirement of broadband single-supply operation is to maintain input and output signal swings within the usable voltage ranges at both the input and the output. The circuit of Figure 2 establishes an input midpoint bias using a simple resistive divider from the +5V supply (two 806Ω resistors). The input signal is then AC-coupled into this midpoint voltage bias. The input voltage can swing to within 1.5V of either supply pin, giving a 2Vp-p input signal range centered between the supply pins. The input impedance matching resistor (57.6Ω) used for testing is adjusted to give a 50Ω input match when the parallel combination of the biasing divider network is included. The gain resistor (RG) is AC-coupled, giving the circuit a DC gain of +1—which puts the input DC bias voltage (2.5V) on the output as well. Again, on a single +5V supply, the output voltage can swing to within 1V of either supply pin while delivering more than 120mA output current. A demanding 100Ω load to a midpoint bias is used in this characterization circuit. The new output stage used in the OPA692 can deliver large bipolar output currents into this midpoint load with minimal crossover distortion, as shown by the +5V supply, 3rd-harmonic distortion typical characteristics. +VS +5V 0.1µF 50Ω Source 0.1µF VIN 57.6Ω 806Ω VO 806Ω + 6.8µF DIS 100Ω VS/2 OPA692 RF 402Ω RG 402Ω 0.1µF 50Ω Source VIN 50Ω 50Ω 50Ω Load OPA692 RF 402Ω FIGURE 2. AC-Coupled, G = +2, Single-Supply Specification and Test Circuit. RG 402Ω 0.1µF –5V + 6.8µF SINGLE-SUPPLY ADC INTERFACE Most modern, high-performance ADCs (such as the Texas Instruments ADS8xx and ADS9xx series) operate on a single +5V (or lower) power supply. It has been a considerable challenge for single-supply op amps to deliver a low-distortion input signal at the ADC input for signal frequencies FIGURE 1. DC-Coupled, G = +2, Bipolar Supply, Specification and Test Circuit. OPA692 SBOS236C www.ti.com 13 exceeding 5MHz. The high slew rate, exceptional output swing, and high linearity of the OPA692 make it an ideal single-supply ADC driver. Figure 3 shows an example input interface to a very high performance 10-bit, 60MSPS CMOS converter. The OPA692 in the circuit of Figure 3 provides 190MHz bandwidth operating at a signal gain of +2 with a 2Vp-p output swing. The noninverting input bias voltage is referenced to the midpoint of the ADC signal range by dividing off the top and bottom of the internal ADC reference ladder. With the gain resistor (RG) AC-coupled, this bias voltage has a gain of +1 to the output, centering the output voltage swing as well. Tested performance at a 20MHz analog input frequency and a 60MSPS clock rate on the converter gives > 58dBc SFDR. WIDEBAND VIDEO MULTIPLEXING One common application for video speed amplifiers that include a disable pin is to wire multiple amplifier outputs together, then select which one of several possible video inputs to source onto a single line. This simple wired-OR video multiplexer can be easily implemented using the OPA692, as shown in Figure 4. +5V +5V RF 402Ω 0.1µF RG 402Ω 50Ω OPA692 1Vp-p 0.1µF CM DIS +2.5V DC Bias 2kΩ 2kΩ +3.5V REFT 0.1µF +1.5V REFB 0.1µF 2Vp-p 22pF Input Input Clock ADS826 10-Bit 60MSPS FIGURE 3. Wideband, AC-Coupled, Single-Supply ADC Driver. +5V 2kΩ VDIS +5V |VOUT| < 2.6V Video 1 75Ω DIS OPA692 402Ω –5V 402Ω 68.1Ω 75Ω Cable VOUT 402Ω +5V 402Ω 68.1Ω RG-59 Video 2 75Ω 2kΩ OPA692 DIS –5V FIGURE 4. 2-Channel Video Multiplexer. 14 OPA692 www.ti.com SBOS236C Typically, channel switching is performed either on sync or retrace time in the video signal. The two inputs are approximately equal at this time. The make-before-break disable characteristic of the OPA692 ensures that there is always one amplifier controlling the line when using a wired-OR circuit (see Figure 4). Since both inputs may be on for a short period during the transition between channels, the outputs are combined through the output impedance matching resistors (68.1Ω in this case). When one channel is disabled, its feedback network forms part of the output impedance and slightly attenuates the signal in getting out onto the cable. The matching resistors have been set to get a signal gain of +1 at the load while providing > 20dB return loss at the load. The video multiplexer connection (see Figure 4) also insures that the maximum differential voltage across the inputs of the unselected channel do not exceed the rated ±1.2V maximum for standard video signal levels. In any case, VOUT must be < ±2.6Vp-p in order to not exceed the absolute maximum differential input voltage (±1.2V) on the disabled channel. The Disable Operation section shows the turn-on and turn-off switching glitches using a grounded input for a single channel is typically less than ±50mV. Where two outputs are switched (see Figure 4), the output line is always under the control of one amplifier or the other due to the make-beforebreak disable timing. In this case, the switching glitches for two 0V inputs drops to < 20mV. 4-CHANNEL FREQUENCY CHANNELIZER The circuit of Figure 5 is a 4-channel multiplexer. In this circuit the OPA691 provides the drive for all four channels. Each channel includes a bandpass filter and each bandpass filter is set for a different frequency band. This allows the channelizing part of this circuit. The role of the OPA692 is to provide impedance isolation. This is done through the use of four matching resistances (59Ω in this case). These matching resistors ensure that the signals will combine during the transition between channels. They have been used to get a gain of +1 at the load. This circuit may be used with a different number of channels. Its limitation comes from the drive requirement for each channel, as well as the minimum acceptable return loss. The output resistor value (RO) to keep a gain of +1 at the load, depends on the number of channels. For the OPA692, Equation 1 gives: (1) RO = [75Ω • (n – 2) + 804Ω] •   2   1+ [ 241200Ω 75Ω • (n − 2) + 804Ω ] 2  – 1   Where n = number of devices in multiplexer. +5V 75Ω #1 75Ω DIS 1 RO 59Ω OPA692 –5V +5V 75Ω #2 +5V 75Ω DIS 2 RO 59Ω OPA692 75Ω Cable VOUT DIS 3 RO 59Ω RG-59 75Ω Load OPA691 75Ω –5V #3 75Ω –5V +5V OPA692 –5V +5V 75Ω #4 75Ω DIS 4 RO 59Ω OPA692 –5V G = +2 Stages FIGURE 5. 4-Channel Frequency Channelizer. OPA692 SBOS236C www.ti.com 15 DELAY-EQUALIZED LOW-PASS FILTER The circuit in Figure 6 realizes a 5th-order Butterworth lowpass filter with a –3dB bandwidth of 20MHz and group delay equalization. This filter is based on the KRC active filter topology using amplifiers with a fixed positive gain ≥ 1. The OPA692 makes a good amplifier for this type of filter. The first stage is the group delay equalizer, which is based on a gain of –1. The second stage has a high-Q pole, uses a gain of +2 for minimum component sensitivity, and also produces a real pole. The last stage has a low-Q pole, and uses a gain of +1 for minimum component sensitivity. The component values have been predistorted to compensate for the op amps parasitic effects. The low-Q pole section was placed last to minimize noise peaking in the passband, while maintaining good dynamic range performance. VIN 200Ω +5V 80.6kΩ 402Ω OPA692 402Ω VOUT 2.7nF OPA227 –5V 200Ω 2.7nF FIGURE 7. Precision Wideband, Unity-Gain Buffer. PRECISION VOLTAGE BUFFER The precision buffer in Figure 7 combines the DC precision and low 1/f noise of the OPA227 with the high-speed performance of the OPA692. The 80.6kΩ resistor makes the highfrequency and low-frequency nominal gains equal. The OPA692 takes over from the OPA227 at approximately 32kHz. DESIGN-IN TOOLS DEMONSTRATION BOARDS Two PC boards are available to assist in the initial evaluation of circuit performance using the OPA692 in its two package styles. All of these are available free as an unpopulated PC 56pF 402Ω VIN 220pF 115Ω 27pF 402Ω 49.9Ω 105Ω 226Ω OPA692 OPA692 100pF 402Ω 402Ω 68pF 95.3Ω 226Ω VOUT 39pF OPA692 402Ω 402Ω (Open) FIGURE 6. Butterworth LP Filter with Delay Equalization. 16 OPA692 www.ti.com SBOS236C board delivered with descriptive documentation. The summary information for these boards is shown in the table below. BOARD PART NUMBER DEM-OPA68xU DEM-OPA6xxN LITERATURE REQUEST NUMBER SBOU009 SBOU010 over-temperature specifications because the output stage junction temperatures are higher than the minimum specified operating ambient. DRIVING CAPACITIVE LOADS One of the most demanding and yet very common load conditions for an op amp is capacitive loading. Often, the capacitive load is the input of an ADC—including additional external capacitance which may be recommended to improve ADC linearity. A high-speed amplifier like the OPA692 can be very susceptible to decreased stability and frequency response peaking when a capacitive load is placed directly on the output pin. When the amplifier’s open-loop output resistance is considered, this capacitive load introduces an additional pole in the signal path that can decrease the phase margin. Several external solutions to this problem have been suggested. When the primary considerations are frequency response flatness, pulse response fidelity, and/or distortion, the simplest and most effective solution is to isolate the capacitive load from the feedback loop by inserting a series isolation resistor between the amplifier output and the capacitive load. This does not eliminate the pole from the loop response, but rather shifts it and adds a zero at a higher frequency. The additional zero acts to cancel the phase lag from the capacitive load pole, thus increasing the phase margin and improving stability. The Typical Characteristics show the recommended “RS vs Capacitive Load” and the resulting frequency response at the load. Parasitic capacitive loads greater than 2pF can begin to degrade the performance of the OPA692. Long PC board traces, unmatched cables, and connections to multiple devices can easily cause this value to be exceeded. Always consider this effect carefully, and add the recommended series resistor as close as possible to the OPA692 output pin (see the Board Layout Guidelines section). PRODUCT OPA692ID OPA692IDBV PACKAGE SO-8 SOT23-6 To request any of these boards, check the Texas Instruments web site at www.ti.com. OPERATING SUGGESTIONS GAIN SETTING Setting the gain with the OPA692 is very easy. For a gain of +2, ground the –IN pin and drive the +IN pin with the signal. For a gain of +1, leave the –IN pin open and drive the +IN pin with the signal. For a gain of –1, ground the +IN pin and drive the –IN pin with the signal. As the internal resistor values (not their ratio) change over temperature and process, external resistors should not be used to modify the gain. OUTPUT CURRENT AND VOLTAGE The OPA692 provides output voltage and current capabilities that are unsurpassed in a low-cost monolithic op amp. Under no-load conditions at +25°C, the output voltage typically swings closer than 1V to either supply rail; the tested swing limit is within 1.2V of either rail. Into a 15Ω load (the minimum tested load), it is specified to deliver more than ±160mA. The specifications described previously, though familiar in the industry, consider voltage and current limits separately. In many applications, it is the voltage times current, or V-I product, which is more relevant to circuit operation. Refer to the “Output Voltage and Current Limitations” plot in the Typical Characteristics. The X- and Y-axes of this graph show the zero-voltage output current limit and the zero-current output voltage limit, respectively. The four quadrants give a more detailed view of the OPA692 output drive capabilities, noting that the graph is bounded by a safe operating area of 1W maximum internal power dissipation. Superimposing resistor load lines onto the plot shows that the OPA692 can drive ±2.5V into 25Ω, or ±3.5V into 50Ω without exceeding the output capabilities or the 1W dissipation limit. A 100Ω load line (the standard test circuit load) shows the full ±3.9V output swing capability (see the Electrical Characteristics). The minimum specified output voltage and current over temperature are set by worst-case simulations at the cold temperature extreme. Only at cold startup will the output current and voltage decrease to the numbers shown in the Electrical Characteristics. As the output transistors deliver power, their junction temperatures increase, decreasing their VBEs (increasing the available output voltage swing), and increasing their current gains (increasing the available output current). In steady-state operation, the available output voltage and current is always greater than that shown in the DISTORTION PERFORMANCE The OPA692 provides good distortion performance into a 100Ω load on ±5V supplies. Relative to alternative solutions, it provides exceptional performance into lighter loads and/or operating on a single +5V supply. Generally, until the fundamental signal reaches very high-frequency or power levels, the 2nd-harmonic will dominate the distortion with a negligible 3rdharmonic component. Focusing then on the 2nd-harmonic, increasing the load impedance improves distortion directly. Remember that the total load includes the feedback network— in the noninverting configuration (see Figure 1) this is the sum of RF + RG, while in the inverting configuration, it is just RF. Also, providing an additional supply decoupling capacitor (0.1µF) between the supply pins (for bipolar operation) improves the 2nd-order distortion slightly (3dB to 6dB). In most op amps, increasing the output voltage swing increases harmonic distortion directly. The Typical Characteristics show the 2nd-harmonic increasing at a little less than the expected 2x rate while the 3rd-harmonic increases at a much lower rate than the expected 3x. Where the test power doubles, the difference between it and the 2nd-harmonic decreases less than the OPA692 SBOS236C www.ti.com 17 expected 6dB, while the difference between it and the 3rd decreases by less than the expected 12dB. This also shows up in the 2-tone, 3rd-order intermodulation spurious (IM3) response curves. The 3rd-order spurious levels are extremely low at low output power levels. The output stage continues to hold them low even as the fundamental power reaches very high levels. As the Typical Characteristics show, the spurious intermodulation powers do not increase as predicted by a traditional intercept model. As the fundamental power level increases, the dynamic range does not decrease significantly. For two tones centered at 20MHz, with 10dBm/tone into a matched 50Ω load (i.e., 2Vp-p for each tone at the load, which requires 8Vp-p for the overall 2-tone envelope at the output pin), the Typical Characteristics show 58dBc difference between the test-tone power and the 3rdorder intermodulation spurious levels. This exceptional performance improves further when operating at lower frequencies. square root of the sum of all squared output noise voltage contributors. Equation 2 shows the general form for the output noise voltage using the terms shown in Figure 8. (2) 2 2 EO =  ENI2 + (IBNR S ) + 4kTRS  NG2 + (IBIRF ) + 4kTRFNG   Dividing this expression by the noise gain (NG = (1 + RF/RG)) will give the equivalent input-referred spot noise voltage at the noninverting input, as shown in Equation 3. (3) 4kTRF 2 I R  EN = ENI2 + (IBNR S ) + 4kTRS +  BI F  +  NG  NG 2 NOISE PERFORMANCE The OPA692 offers an excellent balance between voltage and current noise terms to achieve low output noise. The inverting current noise (15pA/√Hz ) is significantly lower than earlier solutions while the input voltage noise (1.7nV√Hz ) is lower than most unity-gain stable, wideband, voltage-feedback op amps. This low input voltage noise was achieved at the price of higher noninverting input current noise (12pA/√Hz ). As long as the AC source impedance looking out of the noninverting node is less than 100Ω, this current noise will not contribute significantly to the total output noise. The op amp input voltage noise and the two input current noise terms combine to give low output noise for the gain settings, available using the OPA692. Figure 8 shows the op amp noise analysis model with all the noise terms included. In this model, all noise terms are taken to be noise voltage or current density terms in either nV/√Hz or pA/√Hz . The total output spot noise voltage can be computed as the Evaluating these two equations for the OPA692 circuit and component values (see Figure 1) will give a total output spot noise voltage of 8.2nV/√Hz and a total equivalent input spot noise voltage of 4.1nV/√Hz . This total input-referred spot noise voltage is higher than the 1.7nV/√Hz specification for the op amp voltage noise alone. This reflects the noise added to the output by the inverting current noise times the feedback resistor. DC ACCURACY The OPA692 provides exceptional bandwidth in high gains, giving fast pulse settling but only moderate DC accuracy. The Electrical Characteristics show an input offset voltage comparable to high-speed voltage-feedback amplifiers. However, the two input bias currents are somewhat higher and are unmatched. Bias current cancellation techniques will not reduce the output DC offset for OPA692. As the two input bias currents are unrelated in both magnitude and polarity, matching the source impedance looking out of each input to reduce their error contribution to the output is ineffective. Evaluating the configuration of Figure 1, using worst-case +25°C input offset voltage and the two input bias currents, gives a worst-case output offset range equal to: ±(NG • VOS(max)) + (IBN • RS/2 • NG) ± (IBI • RF) where NG = noninverting signal gain = ±(2 • 2.5mV) + (35µA • 25Ω • 2) ± (402Ω • 25µA) = ±5mV + 1.75mV ± 10.05mV = –13.3mV → +16.80mV Minimizing the resistance seen by the noninverting input will give the best DC offset performance. ENI RS OPA692 IBN EO ERS √4kTRS RF √4kTRF 4kT = 1.6E –20J at 290°K 4kT RG RG IBI For significantly improved DC accuracy, consider the precision buffer circuit (see Figure 7). DISABLE OPERATION The OPA692 provides an optional disable feature that may be used either to reduce system power or to implement a simple channel multiplexing operation. If the DIS control pin is left unconnected, the OPA692 will operate normally. To disable, FIGURE 8. Noise Model. 18 OPA692 www.ti.com SBOS236C the control pin must be asserted LOW. Figure 9 shows a simplified internal circuit for the disable control feature. In normal operation, base current to Q1 is provided through THERMAL ANALYSIS Due to the high output power capability of the OPA692, heatsinking or forced airflow may be required under extreme operating conditions. Maximum desired junction temperature will set the maximum allowed internal power dissipation, as described below. In no case should the maximum junction temperature be allowed to exceed 175°C. Operating junction temperature (TJ) is given by TA + PD • θJA. The total internal power dissipation (PD) is the sum of quiescent power (PDQ) and additional power dissipated in the output stage (PDL) to deliver load power. Quiescent power is simply the specified no-load supply current times the total supply voltage across the part. PDL depends on the required output signal and load but would, for a grounded resistive load, be at a maximum when the output is fixed at a voltage equal to 1/2 either supply voltage (for equal bipolar supplies). Under this condition PDL = VS2/(4 • RL), where RL includes feedback network loading. Note that it is the power in the output stage and not in the load that determines internal power dissipation. As a worst-case example, compute the maximum TJ using an OPA692IDBV (SOT23-6 package) in the circuit of Figure 1 operating at the maximum specified ambient temperature of +85°C and driving a grounded 20Ω load to +2.5VDC: PD = 10V • 5.8mA + 52/(4 • (20Ω || 800Ω)) = 378mW Maximum TJ = +85°C + (0.39W • 150°C/W) = 142°C Although this is still well below the specified maximum junction temperature, system reliability considerations may require lower junction temperatures. Remember, this is a worst-case internal power dissipation—use your actual signal and load to compute PDL. The highest possible internal dissipation occurs if the load requires current to be forced into the output for positive output voltages or sourced from the output for negative output voltages. This puts a high current through a large internal voltage drop in the output transistors. The “Output Voltage and Current Limitations” plot shown in the Typical Characteristics include a boundary for 1W maximum internal power dissipation under these conditions. +VS 15kΩ Q1 110kΩ 25kΩ VDIS IS Control – VS FIGURE 9. Simplified Disable Control Circuit. the 110kΩ resistor while the emitter current through the 15kΩ resistor sets up a voltage drop that is inadequate to turn on the two diodes in Q1’s emitter. As V DIS is pulled LOW, additional current is pulled through the 15kΩ resistor eventually turning on these two diodes (≈ 75µA). At this point, any further current pulled out of V DIS goes through those diodes holding the emitter-base voltage of Q1 at approximately 0V. This shuts off the collector current out of Q1, turning the amplifier off. The supply current in the disable mode is only that required to operate the circuit of Figure 8. Additional circuitry ensures that turn-on time occurs faster than turn-off time (make-before-break). When disabled, the output and input nodes go to a highimpedance state. If the OPA692 is operating in a gain of +1, this will show a very high impedance (4pF || 1MΩ) at the output and exceptional signal isolation. If operating at a gain of +2, the total feedback network resistance (RF + RG) will appear as the impedance looking back into the output, but the circuit will still show very high forward and reverse isolation. If configured at a gain of –1, the input and output will be connected through the feedback network resistance (RF + RG) giving relatively poor input to output isolation. One key parameter in disable operation is the output glitch when switching in and out of the disabled mode. The Typical Characteristics show these glitches for the circuit of Figure 1 with the input signal set to 0V. The glitch waveform at the output pin is plotted along with the DIS pin voltage. The transition edge rate (dV/dt) of the DIS control line will influence this glitch. Slowing this edge can be achieved by adding a simple RC filter into the V DIS pin from a higher speed logic line. If extremely fast transition logic is used, a 2kΩ series resistor between the logic gate and the DIS input pin will provide adequate bandlimiting using just the parasitic input capacitance on the DIS pin while still ensuring an adequate logic level swing. BOARD LAYOUT GUIDELINES Achieving optimum performance with a high-frequency amplifier like the OPA692 requires careful attention to board layout parasitics and external component types. Recommendations that will optimize performance include: a) Minimize parasitic capacitance to any AC ground for all of the signal I/O pins. Parasitic capacitance on the output pin can cause instability: on the noninverting input, it can react with the source impedance to cause unintentional bandlimiting. To reduce unwanted capacitance, a window around the signal I/O pins should be opened in all of the ground and power planes around those pins. Otherwise, ground and power planes should be unbroken elsewhere on the board. OPA692 SBOS236C www.ti.com 19 b) Minimize the distance (< 0.25") from the power-supply pins to high-frequency 0.1µF decoupling capacitors. At the device pins, the ground and power-plane layout should not be in close proximity to the signal I/O pins. Avoid narrow power and ground traces to minimize inductance between the pins and the decoupling capacitors. The power-supply connections (on pins 4 and 7) should always be decoupled with these capacitors. An optional supply decoupling capacitor across the two power supplies (for bipolar operation) will improve 2nd-harmonic distortion performance. Larger (2.2µF to 6.8µF) decoupling capacitors, effective at lower frequencies, should also be used on the main supply pins. These may be placed somewhat further from the device and may be shared among several devices in the same area of the PC board. c) Careful selection and placement of external components will preserve the high-frequency performance of the OPA692. Any external resistors should be a very low reactance type. Surface-mount resistors work best and allow a tighter overall layout. Metal-film and carbon composition, axially-leaded resistors can also provide good high-frequency performance. Again, keep their leads and PC-board trace length as short as possible. Never use wirewound type resistors in a high-frequency application. All external components should also be placed close to the package. d) Connections to other wideband devices on the board may be made with short direct traces or through onboard transmission lines. For short connections, consider the trace and the input to the next device as a lumped capacitive load. Relatively wide traces (50mils to 100mils) should be used, preferably with ground and power planes opened up around them. Estimate the total capacitive load and set RS from the plot of recommended “RS vs Capacitive Load.” Low parasitic capacitive loads (< 5pF) may not need an RS because the OPA692 is nominally compensated to operate with a 2pF parasitic load. If a long trace is required, and the 6dB signal loss intrinsic to a doubly-terminated transmission line is acceptable, implement a matched impedance transmission line using microstrip or stripline techniques (consult an ECL design handbook for microstrip and stripline layout techniques). A 50Ω environment is normally not necessary on board, and in fact, a higher impedance environment will improve distortion as shown in the “Distortion vs Load” plots. With a characteristic board trace impedance defined based on board material and trace dimensions, a matching series resistor into the trace from the output of the OPA692 is used as well as a terminating shunt resistor at the input of the destination device. Remember also that the terminating impedance will be the parallel combination of the shunt resistor and the input impedance of the destination device; this total effective impedance should be set to match the trace impedance. The high output voltage and current capability of the OPA692 allows multiple destination devices to be handled as separate transmission lines, each with their own series and shunt terminations. If the 6dB attenuation of a doubly-terminated transmission line is unacceptable, a long trace can be series-terminated at the source end only. Treat the trace as a capacitive load in this case and set the series resistor value as shown in the plot of “RS vs Capacitive Load.” This will not preserve signal integrity as well as a doubly-terminated line. If the input impedance of the destination device is low, there will be some signal attenuation due to the voltage divider formed by the series output into the terminating impedance. e) Socketing a high-speed part like the OPA692 is not recommended. The additional lead length and pin-to-pin capacitance introduced by the socket can create an extremely troublesome parasitic network which can make it almost impossible to achieve a smooth, stable frequency response. Best results are obtained by soldering the OPA692 onto the board. INPUT AND ESD PROTECTION The OPA692 is built using a very high-speed complementary bipolar process. The internal junction breakdown voltages are relatively low for these very small geometry devices. These breakdowns are reflected in the Absolute Maximum Ratings table. All device pins have limited ESD protection using internal diodes to the power supplies, as shown in Figure 10. +V CC External Pin Internal Circuitry –V CC FIGURE 10. Internal ESD Protection. These diodes provide moderate protection to input overdrive voltages above the supplies as well. The protection diodes can typically support 30mA continuous current. Where higher currents are possible (e.g., in systems with ±15V supply parts driving into the OPA692), current-limiting series resistors should be added into the two inputs. Keep these resistor values as low as possible since high values degrade both noise performance and frequency response. 20 OPA692 www.ti.com SBOS236C PACKAGE DRAWINGS D (R-PDSO-G**) 8 PINS SHOWN 0.050 (1,27) 8 5 0.020 (0,51) 0.014 (0,35) 0.010 (0,25) PLASTIC SMALL-OUTLINE PACKAGE 0.244 (6,20) 0.228 (5,80) 0.157 (4,00) 0.150 (3,81) 0.008 (0,20) NOM Gage Plane 1 A 4 0°– 8° 0.044 (1,12) 0.016 (0,40) 0.010 (0,25) Seating Plane 0.069 (1,75) MAX 0.010 (0,25) 0.004 (0,10) 0.004 (0,10) PINS ** DIM A MAX A MIN 8 0.197 (5,00) 0.189 (4,80) 14 0.344 (8,75) 0.337 (8,55) 16 0.394 (10,00) 0.386 (9,80) 4040047/E 09/01 NOTES: A. B. C. D. All linear dimensions are in inches (millimeters). This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion, not to exceed 0.006 (0,15). Falls within JEDEC MS-012 OPA692 SBOS236C www.ti.com 21 PACKAGE DRAWINGS (Cont.) DBV (R-PDSO-G6) PLASTIC SMALL-OUTLINE 0,95 6 4 6X 0,50 0,25 0,20 M 1,70 1,50 3,00 2,60 0,15 NOM 1 3,00 2,80 3 Gage Plane 0,25 0 –8 0,55 0,35 Seating Plane 1,45 0,95 0,05 MIN 0,10 4073253-5/G 01/02 NOTES: A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion. Leads 1, 2, 3 may be wider than leads 4, 5, 6 for package orientation. 22 OPA692 www.ti.com SBOS236C PACKAGE OPTION ADDENDUM www.ti.com 1-Feb-2005 PACKAGING INFORMATION Orderable Device OPA692ID OPA692IDBVR OPA692IDBVT OPA692IDR (1) Status (1) ACTIVE ACTIVE ACTIVE ACTIVE Package Type SOIC SOT-23 SOT-23 SOIC Package Drawing D DBV DBV D Pins Package Eco Plan (2) Qty 8 6 6 8 100 3000 250 2500 None None None None Lead/Ball Finish CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU MSL Peak Temp (3) Level-3-240C-168 HR Level-3-235C-168 HR Level-3-235C-168 HR Level-3-240C-168 HR The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - May not be currently available - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. None: Not yet available Lead (Pb-Free). Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Green (RoHS & no Sb/Br): TI defines "Green" to mean "Pb-Free" and in addition, uses package materials that do not contain halogens, including bromine (Br) or antimony (Sb) above 0.1% of total product weight. (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDECindustry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 1 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All products are sold subject to TI’s terms and conditions of sale supplied at the time of order acknowledgment. TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI’s standard warranty. Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty. Except where mandated by government requirements, testing of all parameters of each product is not necessarily performed. TI assumes no liability for applications assistance or customer product design. Customers are responsible for their products and applications using TI components. To minimize the risks associated with customer products and applications, customers should provide adequate design and operating safeguards. TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right, copyright, mask work right, or other TI intellectual property right relating to any combination, machine, or process in which TI products or services are used. Information published by TI regarding third-party products or services does not constitute a license from TI to use such products or services or a warranty or endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual property of the third party, or a license from TI under the patents or other intellectual property of TI. Reproduction of information in TI data books or data sheets is permissible only if reproduction is without alteration and is accompanied by all associated warranties, conditions, limitations, and notices. Reproduction of this information with alteration is an unfair and deceptive business practice. TI is not responsible or liable for such altered documentation. Resale of TI products or services with statements different from or beyond the parameters stated by TI for that product or service voids all express and any implied warranties for the associated TI product or service and is an unfair and deceptive business practice. TI is not responsible or liable for any such statements. Following are URLs where you can obtain information on other Texas Instruments products and application solutions: Products Amplifiers Data Converters DSP Interface Logic Power Mgmt Microcontrollers amplifier.ti.com dataconverter.ti.com dsp.ti.com interface.ti.com logic.ti.com power.ti.com microcontroller.ti.com Applications Audio Automotive Broadband Digital Control Military Optical Networking Security Telephony Video & Imaging Wireless Mailing Address: Texas Instruments Post Office Box 655303 Dallas, Texas 75265 Copyright  2005, Texas Instruments Incorporated www.ti.com/audio www.ti.com/automotive www.ti.com/broadband www.ti.com/digitalcontrol www.ti.com/military www.ti.com/opticalnetwork www.ti.com/security www.ti.com/telephony www.ti.com/video www.ti.com/wireless