OPA698
OPA
698
SBOS258D – NOVEMBER 2002 – REVISED DECEMBER 2008
www.ti.com
Unity-Gain Stable, Wideband
Voltage Limiting Amplifier
FEATURES
APPLICATIONS
●
●
●
●
●
●
●
●
● FAST LIMITING ANALOG-TO-DIGITAL
CONVERTER (ADC) INPUT BUFFERS
● CCD PIXEL CLOCK STRIPPING
● VIDEO SYNC STRIPPING
● HF MIXERS
● IF LIMITING AMPLIFIERS
● AM SIGNAL GENERATION
● NONLINEAR ANALOG SIGNAL PROCESSING
● OPA688 UPGRADE
HIGH LINEARITY NEAR LIMITING
FAST RECOVERY FROM OVERDRIVE: 1ns
LIMITING VOLTAGE ACCURACY: ±10mV
–3dB BANDWIDTH (G = +1): 450MHz
GAIN BANDWIDTH PRODUCT: 250MHz
SLEW RATE: 1100V/µs
±5V AND +5V SUPPLY OPERATION
HIGH-GAIN VERSION AVAILABLE: OPA699
DESCRIPTION
The OPA698 is a wideband, unity-gain stable voltagefeedback op amp that offers bipolar output voltage limiting.
Two buffered limiting voltages take control of the output
when it attempts to drive beyond these limits. This new
output limiting architecture holds the limiter offset error to
±10mV. The op amp operates linearly to within 20mV of the
output limit voltages.
function at the output, as opposed to the input, gives the
specified limiting accuracy for any gain, and allows the
OPA698 to be used in all standard op amp applications.
The combination of a narrow nonlinear range and the low
limiting offset allows the limiting voltages to be set within
100mV of the desired linear output range. A fast 1ns
recovery from limiting ensures that overdrive signals will be
transparent to the signal channel. Implementing the limiting
The OPA698 is available in an industry standard pinout SO-8
package. For higher gain, or transimpedance applications
requiring output limiting with fast recovery, consider the
OPA699.
Nonlinear analog signal processing will benefit from the
ability of the OPA698 to sharply transition from linear operation to output limiting. The quick recovery time supports
high-speed applications.
VS = +5V
562Ω
VH = +3.6V
0.1µF
715Ω
VS = +5V
102Ω
+3.5V
VS = +5V
REFT
0.1µF
3
VIN
RSEL
+VS
7
8
OPA698
6
24.9Ω
5
2
ADS822
10-Bit
40MSPS
IN
100pF
10-Bit
Data
4
715Ω
REFB
402Ω
INT/EXT GND
+1.5V
102Ω
402Ω
0.1µF
VL = +1.4V
0.1µF
562Ω
Single-Supply Limiting ADC Input Driver
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
Copyright © 2002-2008, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
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ELECTROSTATIC
DISCHARGE SENSITIVITY
ABSOLUTE MAXIMUM RATINGS(1)
Supply Voltage ............................................................................. ±6.5VDC
Internal Power Dissipation .......................... See Thermal Characteristics
Common-Mode Input Voltage ............................................................. ±VS
Differential Input Voltage ..................................................................... ±VS
Limiter Voltage Range ........................................................... ±(VS – 0.7V)
Storage Temperature Range: ID .................................... –65°C to +125°C
Lead Temperature (SO-8, soldering, 3s) ...................................... +260°C
ESD Resistance: HBM .................................................................... 2000V
MM ........................................................................ 200V
CDM .................................................................... 1000V
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling
and installation procedures can cause damage.
ESD damage can range from subtle performance degradation
to complete device failure. Precision integrated circuits may be
more susceptible to damage because very small parametric
changes could cause the device not to meet its published
specifications.
NOTE: (1) Stresses above these ratings may cause permanent damage.
Exposure to absolute maximum conditions for extended periods may degrade
device reliability.
RELATED PRODUCTS
SINGLES
DUALS
DESCRIPTION
Output Limiting
OPA699
High Gain BW, Non-unity
Gain Stable
Voltage Feedback
OPA690 OPA2690
High Slew, Unity Gain Stable
PACKAGE/ORDERING INFORMATION(1)
PRODUCT
OPA698
"
PACKAGE-LEAD
PACKAGE
DESIGNATOR
SPECIFIED
TEMPERATURE
RANGE
PACKAGE
MARKING
ORDERING
NUMBER
TRANSPORT
MEDIA, QUANTITY
SO-8 Surface Mount
D
–40°C to +85°C
OPA698ID
"
"
"
"
OPA698ID
OPA698IDR
Rails, 100
Tape and Reel, 2500
NOTE: (1) For the most current package and ordering information, see the Package Option Addendum located at the end of this document, or see the TI website
at www.ti.com.
PIN CONFIGURATION
Top View
SO
NC
1
8
VH
Inverting Input
2
7
+VS
Noninverting Input
3
6
Output
–VS
4
5
VL
NC = Not Connected
2
OPA698
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SBOS258D
ELECTRICAL CHARACTERISTICS: VS = ±5V
Boldface limits are tested at +25°C.
G = +2, RF = 402Ω, RL = 500Ω, and VH = –VL = 2V (see Figure 1 for AC performance only), unless otherwise noted.
OPA698ID
TYP
PARAMETER
AC PERFORMANCE (see Figure 1)
Small-Signal Bandwidth
Gain-Bandwidth Product (G ≥ +5)
Gain Peaking
0.1dB Gain Flatness Bandwidth
Large-Signal Bandwidth
Step Response:
Slew Rate
Rise-and-Fall Time
Settling Time: 0.05%
Harmonic Distortion: 2nd
3rd
Differential Gain
Differential Phase
Input Noise:
Voltage Noise Density
Current Noise Density
DC PERFORMANCE (VCM = 0)
Open-Loop Voltage Gain (AOL)
Input Offset Voltage
Average Drift
Input Bias Current(4)
Average Drift
Input Offset Current
Average Drift
INPUT
Common-Mode Rejection
Common-Mode Input Range(5)
Input Impedance
Differential-Mode
Common-Mode
OUTPUT
Output Voltage Range
Current Output, Sourcing
Sinking
Closed-Loop Output Impedance
POWER SUPPLY
Operating Voltage, Specified
Maximum
Quiescent Current, Maximum
Minimum
Power-Supply Rejection Ratio
–PSRR (Input Referred)
OUTPUT VOLTAGE LIMITERS
Output Voltage Limited Range
Default Limit Voltage, Upper
Lower
Minimum Limiter Separation (VH – VL)
Maximum Limit Voltage
Limiter Input Bias Current Magnitude (6)
Maximum
Minimum
Average Drift
Limiter Input Impedance
Limiter Feedthrough(7)
DC Performance in Limit Mode
Limiter Offset
Op Amp Input Bias Current Shift(4)
AC Performance in Limit Mode
Limiter Small-Signal Bandwidth
Limiter Slew Rate(8)
+25°C(1)
0°C to
+70°C(2)
–40°C to
+85°C(2)
150
145
140
180
175
170
110
105
100
1100
1.6
8
–74
–87
0.012
0.008
750
2.3
700
2.4
650
2.5
–65
–83
–64
–83
–63
–82
f ≥ 1MHz
f ≥ 1MHz
5.6
2.2
6.1
2.7
6.7
2.8
VO = ±0.5V
63
±2
—
+3
—
±0.3
—
56
±10
61
±3.3
±3.2
CONDITIONS
+25°C
VO < 0.2VPP
G = +1, RF = 25Ω
G = +2
G = –1
VO < 0.2VPP
G = +1, RF = 25Ω, VO < 0.2VPP
VO < 0.2VPP
VO = 4VPP, VH = –VL = 2.5V
450
215
215
250
5
30
160
4V Step, VH = –VL = 2.5V
0.2V Step
2V Step
f = 5MHz, VO = 2VPP
f = 5MHz, VO = 2VPP
NTSC, PAL, RL = 500Ω
NTSC, PAL, RL = 500Ω
Input Referred, VCM = ±0.5V
±5
±2
55
VH = –VL = 4.3V
RL ≥ 500Ω
VO = 0
VO = 0
G = +1, RF = 25Ω, f < 100kHz
VS = ±5V
VS = ±5V
+VS = 4.5V to 5.5V
Pins 5 and 8
Limiter Pins Open
Limiter Pins Open
±4.0
+120
–120
0.01
±3.9
+90
–90
2VDC + 20mVPP
2x Overdrive, VH or VL
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MIN/ TEST
MAX LEVEL(3)
typ
min
typ
min
typ
typ
min
C
B
C
B
C
C
B
V/µs
ns
ns
dB
dB
%
degrees
min
max
typ
min
min
typ
typ
B
B
C
B
B
C
C
7.2
3
nV/√Hz
pA/√Hz
max
max
B
B
53
±6
±15
±11
±15
±2.5
±10
52
±8
±20
±12
±20
±3
±10
dB
mV
µV/°C
µA
nA/°C
µA
nA/°C
min
max
max
max
max
max
max
A
A
B
A
B
A
B
54
±3.2
52
±3.1
dB
V
min
min
A
A
MΩ || pF
MΩ || pF
typ
typ
C
C
V
mA
mA
Ω
min
min
min
typ
A
A
A
C
±3.9
+85
–85
±3.8
+80
–80
±6
16.6
14.6
V
V
mA
mA
typ
max
max
min
C
A
A
A
±5
—
15.5
15.5
15.9
15.2
±6
16.3
14.9
75
68
67
66
dB
min
A
±3.8
+3.5
–3.5
400
—
+3.3
–3.3
400
±4.3
+3.2
–3.2
400
±4.3
+3.1
–3.1
400
±4.3
V
V
V
mV
V
max
min
max
min
max
C
A
A
B
B
50
50
—
3.4 || 1
–68
60
40
62
38
30
64
36
35
µA
µA
nA/°C
MΩ || pF
dB
max
min
max
typ
typ
A
A
B
C
C
±10
3
±30
±35
±40
mV
µA
max
typ
A
C
MHz
V/µs
typ
typ
C
C
±6
VO = 0
f = 5MHz
VIN = ±2V
(VO – VH) or (VO – VL)
Linear to Limited Output
UNITS
MHz
MHz
MHz
MHz
dB
MHz
MHz
0.32 || 1
3.5 || 1
OPA698
SBOS258D
MIN/MAX OVER TEMPERATURE
600
125
3
ELECTRICAL CHARACTERISTICS: VS = ±5V (Cont.)
Boldface limits are tested at +25°C.
G = +2, RF = 402Ω, RL = 500Ω, and VH = –VL = 2V (see Figure 1 for AC performance only), unless otherwise noted.
OPA698ID
TYP
CONDITIONS
+25°C
+25°C(1)
0°C to
+70°C(2)
–40°C to
+85°C(2)
2x Overdrive
VIN = 0 to ±2V Step
VIN = ±2V to 0V Step
f = 5MHz, VO = 2VPP
250
1
30
1.9
2
2.1
PARAMETER
OUTPUT VOLTAGE LIMITERS (Cont.)
Limited Step Response
Overshoot
Recovery Time
Linearity Guardband(9)
MIN/MAX OVER TEMPERATURE
THERMAL CHARACTERISTICS
Temperature Range
Thermal Resistance
D SO-8
Specification: I
Junction-to-Ambient
–40 to +85
125
—
—
—
UNITS
MIN/ TEST
MAX LEVEL(3)
mV
ns
mV
typ
max
typ
C
B
C
°C
typ
C
°C/W
typ
C
NOTES: (1) Junction temperature = ambient for +25°C specifications.
(2) Junction temperature = ambient at low temperature limit; junction temperature = ambient +23°C at high temperature limit for over temperature
specifications.
(3) Test levels: (A) 100% tested at +25°C. Over temperature limits by characterization and simulation. (B) Limits set by characterization and simulation.
(C) Typical value only for information.
(4) Current is considered positive out of node.
(5) CMIR tested as < 3dB degradation from minimum CMRR at specified limits.
(6) IVH (VH bias current) is positive, and IVL (VL bias current) is negative, under these conditions. See Note 3, Figure 1, and Figure 8.
(7) Limiter feedthrough is the ratio of the output magnitude to the sinewave added to VH (or VL) when VIN = 0.
(8) VH slew rate conditions are: VIN = +2V, G = +2, VL = –2V, VH = step between 2V and 0V. VL slew rate conditions are similar.
(9) Linearity Guardband is defined for an output sinusoid (f = 5MHz, VO = 0VDC ± 1VPP) centered between the limiter levels (VH and VL). It is the difference
between the limiter level and the peak output voltage where SFDR decreases by 3dB (see Figure 9).
4
OPA698
www.ti.com
SBOS258D
ELECTRICAL CHARACTERISTICS: VS = +5V
Boldface limits are tested at +25°C.
G = +2, RL = 500Ω tied to VCM = 2.5V, RF = 402Ω, VL = VCM –1.2V, and VH = VCM +1.2V (see Figure 2 for AC performance only), unless otherwise noted.
OPA698ID
TYP
PARAMETER
AC PERFORMANCE (see Figure 2)
Small-Signal Bandwidth
Gain-Bandwidth Product (G ≥ +5)
Gain Peaking
0.1dB Gain Flatness Bandwidth
Large-Signal Bandwidth
Step Response:
Slew Rate
Rise-and-Fall Time
Settling Time: 0.05%
Harmonic Distortion: 2nd
3rd
Input Noise:
Voltage Noise Density
Current Noise Density
DC PERFORMANCE
Open-Loop Voltage Gain (AOL)
Input Offset Voltage
Average Drift
Input Bias Current(4)
Average Drift
Input Offset Current
Average Drift
INPUT
Common-Mode Rejection
Common-Mode Input Range(5)
Input Impedance
Differential-Mode
Common-Mode
OUTPUT
Output Voltage Range
Current Output, Sourcing
Sinking
Closed-Loop Output Impedance
POWER SUPPLY
Operating Voltage, Specified
Maximum
Quiescent Current, Maximum
Minimum
Power-Supply Rejection Ratio
+PSRR (Input Referred)
OUTPUT VOLTAGE LIMITERS
Maximum Limiter Voltage
Minimum Limiter Voltage
Default Limiter Voltage
Minimum Limiter Separation (VH – VL)
Maximum Limit Voltage
Limiter Input Bias Current Magnitude(6)
Limiter Input Impedance
Limiter Feedthrough(7)
DC Performance in Limit Mode
Limiter Voltage Accuracy
Op Amp Bias Current Shift(4)
AC Performance in Limit Mode
Limiter Small-Signal Bandwidth
Limiter Slew Rate(8)
CONDITIONS
+25°C
VO < 0.2VPP
G = +1, RF = 25Ω
G = +2
G = –1
VO < 0.2VPP
G = +1, RF = 25Ω, VO < 0.2VPP
VO < 0.2VPP
VO = 2VPP
375
200
200
230
7
30
200
2V Step
0.2V Step
1V Step
f = 5MHz, VO = 2VPP
f = 5MHz, VO = 2VPP
820
1.9
12
69
73
f ≥ 1MHz
f ≥ 1MHz
5.7
2.3
VCM = 2.5V
VO = ±0.5V
60
±1
—
+3
—
±0.4
—
Input Referred, VCM = ±0.5V
+25°C(1)
0°C to
+70°C(2)
–40°C to
+85°C(2)
150
145
140
170
165
155
120
110
100
560
2.3
550
2.4
500
2.5
63
69
62
68
61
67
54
±6
±10
±2
52
±7
±15
±11
±25
±2.5
±15
51
±8
±15
±12
±25
±3
±15
58
54
53
52
VCM ± 0.8 VCM ± 0.7 VCM ± 0.7 VCM ± 0.6
0.32 || 1
3.5 || 1
VH = VCM +1.8V, VL = VCM – 1.8V
RL ≥ 500Ω
VO = 2.5V
VO = 2.5V
G = +1, RF = 25Ω, f < 100kHz
VCM ± 1.6 VCM ± 1.4 VCM ± 1.4 VCM ± 1.3
+70
+60
+55
+50
–70
–60
–55
–50
0.2
UNITS
MIN/ TEST
MAX LEVEL(3)
MHz
MHz
MHz
MHz
dB
MHz
MHz
typ
min
typ
min
typ
typ
min
C
B
C
B
C
C
B
V/µs
ns
ns
dB
dB
min
max
typ
min
min
B
B
C
B
B
nV/√Hz
pA/√Hz
typ
typ
C
C
dB
mV
µV/°C
µA
nA/°C
µA
nA/°C
min
max
max
max
max
max
max
A
A
B
A
B
A
B
dB
V
min
min
A
A
MΩ || pF
MΩ || pF
typ
typ
C
C
V
mA
mA
Ω
min
min
min
typ
A
A
A
C
V
V
mA
mA
typ
max
max
min
C
A
A
A
dB
typ
C
typ
typ
min
min
max
typ
typ
typ
C
C
B
B
B
C
C
C
mV
µA
max
typ
A
C
MHz
V/µs
typ
typ
C
C
Single-Supply Operation
VS = +5V
VS = +5V
VS = 4.5V to 5.5V
+5
—
14.3
14.3
+12
14.9
13.6
+12
15.1
13.4
+12
15.3
13.2
70
Pins 5 and 8
Pins 5 and 8
Limiter Pins Open
VO = 2.5V
f = 5MHz
VIN = VCM ± 1.2V
(VO – VH) or (VO – VL)
Linear to Limited Output
VIN = VCM ± 1.2V, VO < 0.02VPP
2x Overdrive, VH or VL
OPA698
SBOS258D
MIN/MAX OVER TEMPERATURE
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+3.9
V
+1.1
V
VCM ± 1.1 VCM ± 0.8 VCM ± 0.7 VCM ± 0.6
V
400
400
400
400
mV
—
VCM ± 1.8 VCM ± 1.8 VCM ± 1.8
V
16
µA
3.4 || 1
MΩ || pF
–60
dB
±15
5
450
100
±30
±35
±40
5
ELECTRICAL CHARACTERISTICS: VS = +5V (Cont.)
Boldface limits are tested at +25°C.
G = +2, RL = 500Ω tied to VCM = 2.5V, RF = 402Ω, VL = VCM –1.2V, and VH = VCM +1.2V (see Figure 2 for AC performance only), unless otherwise noted.
OPA698ID
TYP
THERMAL CHARACTERISTICS
Temperature Range
Thermal Resistance
D SO-8
–40°C to
+85°C(2)
MIN/ TEST
MAX LEVEL(3)
+25°C
2x Overdrive
VIN = VCM to VCM ± 1.2V Step
VIN = VCM ± 1.2V to VCM Step
f = 5MHz, VO = 2VPP
55
3
30
mV
ns
mV
typ
typ
typ
C
C
C
–40 to +85
°C
typ
C
°C/W
typ
C
Specification: I
Junction-to-Ambient
125
+25°C(1)
0°C to
+70°C(2)
CONDITIONS
PARAMETER
OUTPUT VOLTAGE LIMITERS (Cont.)
Limited Step Response
Overshoot
Recovery Time
Linearity Guardband(9)
MIN/MAX OVER TEMPERATURE
—
—
—
UNITS
NOTES: (1) Junction temperature = ambient for +25°C specifications.
(2) Junction temperature = ambient at low temperature limit; junction temperature = ambient +23°C at high temperature limit for over temperature
specifications.
(3) Test levels: (A) 100% tested at +25°C. Over temperature limits by characterization and simulation. (B) Limits set by characterization and simulation.
(C) Typical value only for information.
(4) Current is considered positive out of node.
(5) CMIR tested as < 3dB degradation from minimum CMRR at specified limits.
(6) IVH (VH bias current) is negative, and IVL (VL bias current) is positive, under these conditions. See Note 3, Figures 2, and Figure 8.
(7) Limiter feedthrough is the ratio of the output magnitude to the sinewave added to VH (or VL) when VIN = 0.
(8) VH slew rate conditions are: VIN = VCM + 0.4V, G = +2, VL = VCM – 1.2V, VH = step between VCM + 1.2V and VCM. VL slew rate conditions are similar.
(9) Linearity Guardband is defined for an output sinusoid (f = 5MHz, VO = VCM ± 1VPP) centered between the limiter levels (VH and VL). It is the difference between
the limiter level and the peak output voltage where SFDR decreases by 3dB (see Figure 9).
6
OPA698
www.ti.com
SBOS258D
TYPICAL CHARACTERISTICS: VS = ±5V
TA = +25°C, G = +2, RF = 402Ω, and RL = 500Ω, VH = –VL = 2V, unless otherwise noted.
NONINVERTING SMALL-SIGNAL
FREQUENCY RESPONSE
6
0
–3
VIN
VO
OPA698
RC
–6
RF
–9
VO = 0.2VPP
RF = 402Ω, RG Adjusted
G = +2, RC = ∞
G = –2
–3
G = –5
–6
–9
RG
G = +5, RC = ∞
See Figure 3
–12
–12
1
10
100
Frequency (MHz)
800
1
10
Frequency (MHz)
NONINVERTING LARGE-SIGNAL
FREQUENCY RESPONSE
9
500
9
G = –2V/V, RF = 402Ω
VO =
2VPP
6
Normalized Gain (dB)
Normalized Gain (dB)
100
INVERTING LARGE-SIGNAL
FREQUENCY RESPONSE
VO = 1VPP
6
VO = 4VPP
3
VO = 7VPP
0
–3
VO = 4VPP
3
VO = 7VPP
0
VO = 1VPP
–3
VO = 2VPP
See Figure 1
See Figure 3
–6
–6
1
10
Frequency (MHz)
100
400
1
10
Frequency (MHz)
VH—LIMITER SMALL-SIGNAL
FREQUENCY RESPONSE
100
400
VL—LIMITER SMALL-SIGNAL
FREQUENCY RESPONSE
3
3
G = +2
VO = 0.02VPP
G = +2
VO = 0.02VPP
0
0
Limiter Gain (dB)
Limiter Gain (dB)
G = –1
0
G = +1, RF = 25Ω, RC = 175Ω
Normalized Gain (dB)
Normalized Gain (dB)
3
G = +1, RF = 25Ω, RC = ∞
VO = 0.2VPP
3
INVERTING SMALL-SIGNAL
FREQUENCY RESPONSE
0.02VPP + 2VDC
–3
2VDC
VH
VO
OPA698
402Ω
–6
402Ω
–2VDC
VH Open
VO
OPA698
–3
VL
0.02VPP – 2VDC
402Ω
–6
VL Open
402Ω
–9
–9
1M
10M
100M
1G
1M
Frequency (Hz)
100M
1G
Frequency (Hz)
OPA698
SBOS258D
10M
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7
TYPICAL CHARACTERISTICS: VS = ±5V (Cont.)
TA = +25°C, G = +2, RF = 402Ω, and RL = 500Ω, VH = –VL = 2V, unless otherwise noted.
LARGE-SIGNAL PULSE RESPONSE
SMALL-SIGNAL PULSE RESPONSE
0.25
VO = 0.2VPP
0.15
1.5
0.10
1.0
0.05
0.5
0.00
–0.05
0
–0.5
–0.10
–1.0
–0.15
–1.5
–0.20
VO = 4VPP
VH = –VL = 2.5V
2.0
VOUT (V)
VOUT (V)
0.20
2.5
–2.0
See Figure 1
See Figure 1
–2.5
–0.25
Time (5ns/div)
Time (5ns/div)
VH—LIMITED PULSE RESPONSE
2.5
2.0
2.0
1.5
1.5
VOUT
0.5
VIN
0
–0.5
–1.0
–1.5
–2.0
0.5
–0.5
–2.0
–2.5
Time (5ns/div)
LIMITED OUTPUT RESPONSE
DETAIL OF LIMITED OUTPUT VOLTAGE
2.5
2.10
2.0
1.0
1.95
VIN
–0.5
–1.0
1.90
1.85
1.80
1.75
–1.5
1.70
VH = –VL = 2V
G = +2
1.65
–2.5
1.60
Time (200ns/div)
8
VO
2.00
VOUT (V)
VIN and VOUT (V)
2.05
VOUT
1.5
–2.0
VOUT
–1.5
Time (5ns/div)
0
VIN
0
–1.0
G = +2
VIN = 0 → +2V
VH = +2V
–2.5
0.5
VIN = 0 → –2V
G = +2
VL = –2V
1.0
VOUT (V)
1.0
VOUT (V)
VL—LIMITED PULSE RESPONSE (20MHz)
2.5
Time (50ns/div)
OPA698
www.ti.com
SBOS258D
TYPICAL CHARACTERISTICS: VS = ±5V (Cont.)
TA = +25°C, G = +2, RF = 402Ω, and RL = 500Ω, VH = –VL = 2V, unless otherwise noted.
5MHz HARMONIC DISTORTION
vs LOAD RESISTANCE
5MHz HARMONIC DISTORTION
vs SUPPLY VOLTAGE
–55
–45
VO = 2VPP
f = 5MHz
VO = 2VPP
RL = 500Ω
–50
Harmonic Distortion (dBc)
Harmonic Distortion (dBc)
–60
2nd-Harmonic
–65
–70
–75
3rd-Harmonic
–80
–85
–55
–60
2nd-Harmonic
–65
–70
–75
3rd-Harmonic
–80
–85
See Figure 1
–90
See Figure 1
–90
1k
100
2.5
3.0
3.5
HARMONIC DISTORTION vs FREQUENCY
VO = 2VPP
RL = 500Ω
–55
Harmonic Distortion (dBc)
Harmonic Distortion (dBc)
–50
2nd-Harmonic
–70
–80
–90
–100
See Figure 1
5.0
5.5
6.0
–60
RL = 500Ω
VH = –VL = VOPP /2 + 0.5V
f = 5MHz
–65
–70
2nd-Harmonic
–75
3rd-Harmonic
–80
–85
–90
3rd-Harmonic
–110
See Figure 1
–95
0.5
1
20
10
0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 7.0 7.5 8.0
Frequency (MHz)
Output Voltage (VPP)
HARMONIC DISTORTION vs NONINVERTING GAIN
HARMONIC DISTORTION vs INVERTING GAIN
–60
VO = 2VPP
RL = 500Ω
f = 5MHz
2nd-Harmonic
–70
Harmonic Distortion (dBc)
–60
Harmonic Distortion (dBc)
4.5
5MHz HARMONIC DISTORTION vs OUTPUT VOLTAGE
–50
–60
4.0
± Supply Voltage (V)
Load Resistance (Ω)
–80
3rd-Harmonic
–90
–100
–65
VO = 2VPP
RL = 500Ω
f = 5MHz
2nd-Harmonic
–70
–75
3rd-Harmonic
–80
–85
–90
1
2
3
4
5
6
7
8
9
10
–1
Gain (V/V)
–3
–4
–5
–6
–7
–8
–9
–10
Gain (V/V)
OPA698
SBOS258D
–2
www.ti.com
9
TYPICAL CHARACTERISTICS: VS = ±5V (Cont.)
TA = +25°C, G = +2, RF = 402Ω, and RL = 500Ω, VH = –VL = 2V, unless otherwise noted.
2-TONE, 3RD-ORDER INTERMODULATION
INTERCEPT ±5V 500Ω
HARMONIC DISTORTION NEAR LIMITING VOLTAGES
50
VO = 0VDC ± 1VP
f = 5MHz
RL = 500Ω
–50
G = +2V/V
45
Intercept Point (dBm)
Harmonic Distortion (dBc)
–40
–60
2nd-Harmonic
–70
–80
40
PI
35
PO
50Ω OPA698
30
500Ω
402Ω
25
402Ω
3rd-Harmonic
–90
20
0.9 1.0 1.1
1.2
1.3 1.4
1.5
1.6
1.7 1.8 1.9
2.0
0
10
20
± Limit Voltage (V)
30
50
40
Frequency (MHz)
RECOMMENDED RS vs CAPACITIVE LOAD
FREQUENCY RESPONSE vs CAPACITIVE LOAD
140
9
VO = 0.2VPP
Gain to Capacitive Load (dB)
120
80
60
40
20
6
CL = 100pF
CL = 10pF
3
CL = 22pF
VIN
RS
0
OPA698
1kΩ(1)
402Ω
CL = 47pF
CL
–3
402Ω
NOTE: (1) 1kΩ is optional.
0
–6
1
100
10
1
10
Capacitive Load (pF)
INPUT VOLTAGE AND CURRENT NOISE DENSITY
OPEN-LOOP FREQUENCY RESPONSE
100
70
0
VO = 0.5VPP
Gain
Open-Loop Gain (dB)
Voltage Noise (nV/√Hz)
Current Noise (pA/√Hz)
60
Voltage Noise (5.6nV/√Hz)
10
Current Noise (2.2pA/√Hz)
1
–30
50
–60
40
–90
Phase
30
–120
20
–150
10
–180
0
–210
–10
100
1k
10k
100k
1M
10M
Frequency (Hz)
10
1k
100
Frequency (Hz)
–240
10k
100k
1M
10M
100M
1G
Frequency (Hz)
OPA698
www.ti.com
SBOS258D
Open-Loop Phase (°)
Resistance (Ω)
100
TYPICAL CHARACTERISTICS: VS = ±5V (Cont.)
TA = +25°C, G = +2, RF = 402Ω, and RL = 500Ω, VH = –VL = 2V, unless otherwise noted.
VOLTAGE RANGE vs TEMPERATURE
LIMITED VOLTAGE RANGE vs TEMPERATURE
5.0
3.8
VH = –VL = 4.3V
VH and VL left open
4.5
± Voltage Range (V)
Output Voltage Range
4.0
3.5
3.6
3.5
VH
3.4
3.3
Common-Mode Input Range
VL
3.0
3.2
–50
–25
0
25
50
100
75
–50
–25
0
50
75
Ambient Temperature (°C)
LIMITER INPUT BIAS CURRENT vs BIAS VOLTAGE
SUPPLY AND OUTPUT CURRENTS
vs TEMPERATURE
20
100
100
100
Output Current, Sinking
75
Limiter Input Bias Current (µA)
25
Ambient Temperature (°C)
Maximum Over Temperature
18
Supply Current (mA)
50
Minimum Over Temperature
25
0
Limiter Headroom = +VS – VH
= VL – (–VS)
Current = IVH or –IVL
–25
–50
98
Output Current, Sourcing
16
96
Supply Current
14
94
12
Output Currents (mA)
± Voltage Range (V)
3.7
92
–75
–100
10
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
–50
5.0
–25
25
50
75
COMMON-MODE REJECTION RATIO AND
POWER-SUPPLY REJECTION vs FREQUENCY
TYPICAL DC DRIFT OVER TEMPERATURE
80
4.5
Input Bias and Offset Current (µA)
–PSRR
70
CMRR
60
+PSRR
50
40
30
20
10
0
1.0
Input Bias Current (IB)
4.0
0.9
3.5
0.8
3.0
0.7
2.5
0.6
Input Offset Current (VOS)
2.0
0.5
1.5
0.4
1.0
0.3
0.5
0.2
Input Offset Current (IOS)
0
0.1
–0.5
10k
100k
1M
10M
100M
Frequency (Hz)
–50
–25
0
25
50
75
0
100
Ambient Temperature (°C)
OPA698
SBOS258D
90
100
Ambient Temperature (°C)
Limiter Headroom (V)
CMRR, PSRR (dB)
0
www.ti.com
11
Input Offset Voltage (mV)
0
TYPICAL CHARACTERISTICS: VS = ±5V (Cont.)
TA = +25°C, G = +2, RF = 402Ω, and RL = 500Ω, VH = –VL = 2V, unless otherwise noted.
LIMITER FEEDTHROUGH
CLOSED-LOOP OUTPUT IMPEDANCE
–45
100
–50
10
Output Impedance (Ω)
Feedthrough (dB)
–55
–60
–65
0.02VPP + 2VDC
–70
VH
VO
–75
OPA698
–80
VL 402Ω
–85
G = +1
RF = 25Ω
VO = 0.2VPP
1
0.1
0.01
402Ω
Open
–90
–95
0.001
1
100
10
1M
10M
Frequency (MHz)
OUTPUT VOLTAGE AND CURRENT LIMITATIONS
90
5
85
4
PSRR+
3
PSRR–
2
80
Output Voltage (V)
PSRR and CMRR, Input Referred (dB)
±PSRR AND CMRR vs TEMPERATURE
75
70
65
CMRR
60
VH = –VL = 4.3V
1W Internal
Power Limit
1
0
RL = 25Ω
–1
RL = 50Ω
–2
RL = 100Ω
–3
55
1W Internal
Power Limit
–4
50
–50
–25
0
25
50
75
100
–5
–400
–300
–200
–100
0
100
200
300
400
Output Current (mA)
Ambient Temperature (°C)
12
1G
100M
Frequency (Hz)
OPA698
www.ti.com
SBOS258D
TYPICAL CHARACTERISTICS: VS = +5V
TA = +25°C, G = +2, RF = 402Ω, and RL = 500Ω to VCM = +2.5V, VL = VCM – 1.2V, VH = VCM + 1.2V, unless otherwise noted.
INVERTING SMALL-SIGNAL
FREQUENCY RESPONSE
NONINVERTING SMALL-SIGNAL
FREQUENCY RESPONSE
9
VO = 0.2VPP
6
Normalized Gain (dB)
0
0
–3
G = +2, RC = ∞
–6
G = –1
VO = 0.2VPP
G = ±1, RF = 25Ω,
RC = 175Ω
3
Normalized Gain (dB)
3
G = +1, RF = 25Ω, RC = ∞
G = +5, RC = ∞
–9
G = –2
RF = 402Ω, RG Adjusted
–3
G = –5
–6
–9
–12
–12
See Figure 2
–15
–15
1
10
Frequency (MHz)
100
1
500
10
Frequency (MHz)
2.70
VO = 1VPP, VH = VCM + 1.2V,
VL = VCM – 1.2V
G = +2
2.65
6
2.60
VO = 2VPP, VH = VCM + 1.5V,
VL = VCM – 1.5V
2.55
3
VOUT (V)
Normalized Gain (dB)
400
SMALL-SIGNAL PULSE RESPONSE
LARGE-SIGNAL FREQUENCY RESPONSE
9
0
2.50
2.45
2.40
–3
See Figure 2
VO = 3VPP
VH = VCM + 2V
VL = VCM – 2V
2.35
2.30
–6
1
10
Frequency (MHz)
100
Time (5ns/div)
400
VH and VL—LIMITED PULSE RESPONSE
LARGE-SIGNAL PULSE RESPONSE
4.0
4.0
Input and Output Voltage (V)
VO = 2VPP
VH = VCM + 1.2V
VL = VCM – 1.2V
3.5
3.0
VOUT (V)
100
2.5
2.0
1.5
VIN
3.0
VOUT
2.5
2.0
1.5
1.0
1.0
Time (5ns/div)
Time (5ns/div)
OPA698
SBOS258D
VH = VCM + 1.2V
VL = VCM – 1.2V
3.5
www.ti.com
13
TYPICAL CHARACTERISTICS: VS = +5V
TA = +25°C, G = +2, RF = 402Ω, and RL = 500Ω to VCM = +2.5V, VL = VCM – 1.2V, VH = VCM + 1.2V, unless otherwise noted.
HARMONIC DISTORTION vs FREQUENCY
HARMONIC DISTORTION vs LOAD RESISTANCE
–50
–45
VO = 2VPP
f = 5MHz
–55
VO = 2VPP
RL = 500Ω
–55
Harmonic Distortion (dBc)
Harmonic Distortion (dBc)
–50
2nd-Harmonic
–60
–65
3rd-Harmonic
–70
–60
–65
2nd-Harmonic
–70
–75
–80
3rd-Harmonic
–75
–85
See Figure 2
See Figure 2
–90
–80
1k
100
0.5
1
Frequency (MHz)
2-TONE, 3RD-ORDER
INTERMODULATION INTERCEPT
HARMONIC DISTORTION vs OUTPUT VOLTAGE
–65
45
G = +2V/V
–70
40
Intercept Point (+dBM)
Harmonic Distortion (dBc)
2nd-Harmonic
–75
3rd-Harmonic
–80
RL = 500Ω to VS/2
f = 5MHz
VH = VOPP/2 + VCM + 0.5V
VL = –VOPP/2 + VCM – 0.5V
–85
+2.5V
35
PI
+VS
PO
50Ω
OPA698
30
–VS
25
20
0.5
1.0
1.5
0
2.5
2.0
10
HARMONIC DISTORTION NEAR LIMITING VOLTAGES
–40
–55
–60
–65
2nd-Harmonic
–70
3rd-Harmonic
–75
–80
75
Maximum Over Temperature
50
25
Minimum
Over Temperature
0
–25
–50
Limiter Headroom = +VS – VH
= VL – (–VS)
Current = IVH or –IVL
–75
–100
0.9
1.0
1.1
1.2
1.3
1.4
1.5
50
40
LIMITER INPUT BIAS CURRENT vs BIAS VOLTAGE
Limiter Input Bias Current (µA)
–50
30
100
VO = VCM ±1VP
f = 5MHz
RL = 500Ω
–45
20
Frequency (MHz)
Output Voltage Swing (VPP)
Harmonic Distortion (dBc)
500Ω
–2.5V
402Ω
402Ω
–90
1.6
1.7
1.8
0
Limit Voltages - 2.5V
14
20
10
Load Resistance (Ω)
0.5
1
1.5
2
2.5
Limiter Headroom (V)
OPA698
www.ti.com
SBOS258D
TYPICAL APPLICATIONS
WIDEBAND VOLTAGE LIMITING OPERATION
The OPA698 is a voltage feedback amplifier that combines
features of a wideband, high slew rate amplifier with output
voltage limiters. Its output can swing up to 1V from each rail
and can deliver up to 120mA. These capabilities make it an
ideal interface to drive ADC while adding overdrive protection
for the ADC inputs.
Figure 1 shows the DC-coupled, gain of +2, dual powersupply circuit configuration used as the basis of the ±5V
Electrical Characteristics and Typical Characteristics. For
test purposes, the input impedance is set to 50Ω with a
resistor to ground and the output impedance is set to 500Ω.
Voltage swings reported in the specifications are taken
directly at the input and output pins. For the circuit of Figure
1, the total output load will be 500Ω || 804Ω = 308Ω. The
voltage limiting pins are set to ±2V through a voltage divider
network between the +Vs and ground for VH, and between –
Vs and ground for VL. These limiter voltages are adequately
bypassed with a 0.1µF ceramic capacitor to ground. The
limiter voltages (VH and VL) and the respective bias currents
(IVH and IVL) have the polarities shown. One additional
component is included in Figure 1. An additional resistor
(174Ω) is included in series with the noninverting input.
Combined with the 25Ω DC source resistance looking back
towards the signal generator, this gives an input bias currentcanceling resistance that matches the 200Ω source resistance seen at the inverting input (see the DC accuracy and
offset control section). The power-supply bypass for each
3.01kΩ
supply consists of two capacitors: one electrolytic 2.2µF and
one ceramic 0.1µF. The power-supply bypass capacitors are
shown explicitly in Figures 1 and 2, but will be assumed in the
other figures. An additional 0.01µF power-supply decoupling
capacitor (not shown here) can be included between the
two power-supply pins. In practical PC board layouts, this
optional-added capacitor will typically improve the 2nd
harmonic distortion performance by 3dB to 6dB.
SINGLE-SUPPLY, NONINVERTING AMPLIFIER
Figure 2 shows an AC-coupled, noninverting gain amplifier
for single +5V supply operation. This circuit was used for AC
characterization of the OPA698, with a 50Ω source (which it
matches) and a 500Ω load. The mid-point reference on the
noninverting input is set by two 806Ω resistors. This gives an
input bias current-canceling resistance that matches the
402Ω DC source resistance seen at the inverting input (see
the DC accuracy and offset control section). The powersupply bypass for the supply consists of two capacitors: one
electrolytic 2.2µF and one ceramic 0.1µF. The power-supply
bypass capacitors are shown explicitly in Figures 1 and 2, but
will be assumed in the other figures. The limiter voltages (VH
and VL) and the respective bias currents (IVH and IVL) have
the polarities shown. These limiter voltages are adequately
bypassed with a 0.1µF ceramic capacitor to ground. Notice
that the single-supply circuit can use three resistors to set VH
and VL, where the dual-supply circuit usually uses four to
reference the limit voltages to ground. While this circuit
shows +5V operation, the same circuit may be used for
single supplies up to +12V.
1.91kΩ
+VS = +5V
VS = +5V
+
2.2µF
0.1µF
0.1µF
+
VH = +2V
0.1µF
2.2µF
523Ω
0.1µF
174Ω
VH = 3.7V
7
3
VIN
8
49.9Ω
OPA698
2
RF
402Ω
RG
402Ω
0.1µF
5
806Ω
IVH
0.1µF
6
IVL
VO
3
8
57.6Ω
500Ω
806Ω
4
0.1µF
6
VO
500Ω
IVL
RF
402Ω
0.1µF
3.01kΩ
976Ω
5
4
0.1µF
RG
402Ω
2.2µF
OPA698
2
VL = –2V
+
IVH
7
VIN
0.1µF
1.91kΩ
VL = 1.3V
523Ω
–VS = –5V
FIGURE 1. DC-Coupled, Dual-Supply Amplifier.
FIGURE 2. AC-Coupled, Single-Supply Amplifier.
OPA698
SBOS258D
www.ti.com
15
WIDEBAND INVERTING OPERATION
As the required RG resistor approaches 50Ω at higher gains,
the bandwidth for the circuit in Figure 3 will far exceed the
bandwidth at that same gain magnitude for the noninverting
circuit of Figure 1. This occurs due to the lower noise gain for
the circuit of Figure 3 when the 50Ω source impedance is
included in the analysis. For instance, at a signal gain of –8
(RG = 50Ω, RM = open, RF = 402Ω) the noise gain for the
circuit of Figure 3 will be 1 + 402Ω/(50Ω + 50Ω) = 5 due to
the addition of the 50Ω source in the noise gain equation.
This approach gives considerably higher bandwidth than the
noninverting gain of +8. Using the 250MHz gain bandwidth
product for the OPA698, an inverting gain of –8 from a 50Ω
source to a 50Ω RG will give 52MHz bandwidth, whereas
the noninverting gain of +8 will give 28MHz, as shown in
Figure 4.
Operating the OPA698 as an inverting amplifier has several
benefits and is particularly useful when a matched 50Ω
source and input impedance are required. Figure 3 shows
the inverting gain of –2 circuit used as the basis of the
inverting mode typical characteristics.
+5V
0.1µF
RT
147Ω
+2V
VH
OPA698
VO
VL
500Ω
–5V
50Ω Source
200Ω
–2V
402Ω
VI
21
RM
66.5Ω
G = –8
18
Gain (dB)
FIGURE 3. Inverting G = –2 Specifications and Test Circuit.
In the inverting case, only the feedback resistor appears as
part of the total output load in parallel with the actual load.
For a 500Ω load used in the typical characteristics, this gives
a total load of 222Ω in this inverting configuration. The gain
resistor is set to get the desired gain (in this case, 200Ω for
a gain of –2) while an additional input resistor (RM) can be
used to set the total input impedance equal to the source, if
desired. In this case, RM = 66.5Ω in parallel with the 200Ω
gain setting resistor gives a matched input impedance of
50Ω. This matching is only needed when the input needs to
be matched to a source impedance, as in the characterization testing done using the circuit of Figure 3.
15
12
G = +8
9
6
0
1
10k
Frequency (MHz)
100k
FIGURE 4. G = +8 and –8 Frequency Response.
LIMITED OUTPUT, ADC INPUT DRIVER
Figure 5 shows a simple ADC driver that operates on a single
supply, and gives excellent distortion performance. The limit
voltages track the input range of the converter, completely
protecting against input overdrive. Note that the limiting
voltages have been set 100mV above/below the corresponding reference voltage from the converter.
For bias current-cancellation matching, the noninverting input requires a 147Ω resistor to ground. The calculation for
this resistor includes a DC-coupled 50Ω source impedance
along with RG and RM. Although this resistor will provide
cancellation for the bias current, it must be well-decoupled
(0.1µF in Figure 3) to filter the noise contribution of the
resistor and the input current noise.
VS = +5V
562Ω
VH = +3.6V
0.1µF
715Ω
VS = +5V
102Ω
+3.5V
VS = +5V
REFT
0.1µF
3
VIN
RSEL
+VS
7
8
OPA698
6
24.9Ω
5
2
ADS822
10-Bit
40MSPS
IN
100pF
10-Bit
Data
4
715Ω
REFB
402Ω
INT/EXT GND
+1.5V
102Ω
402Ω
0.1µF
VL = +1.4V
0.1µF
562Ω
FIGURE 5. Single Supply, Limiting ADC Input Driver.
16
OPA698
www.ti.com
SBOS258D
The gain for the circuit in Figure 5 is set at +2. Figure 8 shows
a 100MHz sinewave amplifier, with a gain of +2 and rectified.
LIMITED OUTPUT, DIFFERENTIAL ADC INPUT DRIVER
Figure 6 shows a differential ADC driver that takes advantage of the OPA698 limiters to protect the input of the ADC.
Two OPA698s are used. The first one is an inverting configuration at a gain of –2. The second one is in a noninverting
configuration at a gain of +2. Each amplifier is swinging 2VPP
providing a 4VPP differential signal to drive the input of the
ADC. Limiters have been set 100mV away from the magnitude of each amplifier's maximum signal to provide input
protection for the ADC while maintaining an acceptable
distortion level.
2.0
Output Voltage (V)
PRECISION HALF WAVE RECTIFIER
7
–0.5
–1.5
Time (2ns/div)
NC
8
OPA698
HIGH-SPEED FULL WAVE RECTIFIER
6
There are two methods shown here to build a high-speed full
wave rectifier with a limiting amplifier: use the half-wave
rectifier described previously with another amplifier to obtain
the full wave rectified, or use the input to set the limiting
voltage.
VO
5
4
402Ω
0
FIGURE 8. 100MHz Sinewave Rectified.
VIN
3
0.5
–1.0
+VS = +5V
2
1.0
Input
Figure 7 shows a half wave rectifier with outstanding precision and speed. VH (pin 8) will default to a voltage between
3.1V and 3.8V if left open, while the negative limit is set to
ground.
200Ω
Output
1.5
402Ω
–VS = –5V
FIGURE 7. Precision Half Wave Rectifier.
+5V
+1.1V
OPA698
–1.1V
–5V
100Ω
200Ω
10pF
24.9Ω 0.01µF
IN
1kΩ
+5V
+1.1V
VIN = 1VPP
ADC
VCM
4VPP
24.9Ω 0.01µF
1kΩ
IN
OPA698
100Ω
10pF
–1.1V
–5V
200Ω
200Ω
FIGURE 6. Single to Differential AC-Coupled, Output Limited ADC Driver.
OPA698
SBOS258D
www.ti.com
17
High-Speed Full Wave rectifier #1
The circuit shown in Figure 9 uses only one amplifier, in an
inverting gain of –1 configuration. The upper limiting voltage
is left open, resulting in an upper limiting voltage of +3.5V.
The lower limiting voltage is connected to the input signal,
resulting in the following behavior. When the input voltage is
negative, the amplifier is not limiting, resulting in the inversion
of the input sinewave to the output. During the positive
excursion of the input signal, the output signal is being driven
by the limiting input pin. Since the output is driven from the
limiter input pin from positive inputs, the lower slew rate in the
input path restricts the application of this approach to lower
amplitude and/or frequencies. A 2MHz fully rectified sinewave
is shown in Figure 10.
VH
OPA693
300Ω
OPA698
VL
300Ω
200Ω
200Ω
FIGURE 11. High-Speed Full Wave Rectifier #2.
0.8
OPA698
VL
Input and Output Voltage (V)
VH
402Ω
50Ω 50Ω Load
75Ω
200Ω
50Ω
Source
700MHz
Internal
Gain Set
75Ω
VO
500Ω
402Ω
VOUT
0.6
0.4
0.2
0
–0.2
–0.4
VIN
–0.6
57.2Ω
–0.8
Time (10ns/div)
FIGURE 12. 10MHz Sinewave Rectified.
FIGURE 9. High-Speed Full Wave Rectifier #1.
0.4
If the negative excursion of the rectified signal is not desired,
it can easily be removed by replacing the OPA693 with the
OPA698 configured as a difference amplifier with VL connected to ground and VH left floating.
0.2
SOFT-CLIPPING (Compression) CIRCUIT
Output Voltage (V)
0.6
Figure 13 shows a soft-clipping circuit. As soon as the input
voltage exceeds either VCH or VCL, the limiting voltages are
driven by the following equations:
0
–0.2
–0.4
VH = VH =
–0.6
R 2 × VCH + R1 × VIN
R1 + R 2
(1)
Time (50ns/div)
VL =
FIGURE 10. 2MHz Sinewave Rectified.
In order to reach higher frequencies, a second method is
recommended.
High Speed Full Wave rectifier #2
The circuit shown in Figure 11 combines a half-wave rectifier
driving the OPA693 in an inverting configuration, while the
input signal drives the noninverting input of the fixed gain
amplifier OPA693, resulting in a full wave rectifier function.
Results are shown in Figure 12.
18
R 4 × VCL + R 3 × VIN
R3 + R4
(2)
As the amplifier is operating in the limiting mode, the output
voltage is compressed with a gain of R1+R2/R1 for the
positive excursion above VCH, and by a gain of R3+R4/R3 for
the negative excursion below VCL. Figure 14 shows a 5VPP
on the input being compressed above ±1V with a compression gain of one-third.
OPA698
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SBOS258D
R2
402Ω
R1
1kΩ
VCH
+1V
R1
200Ω
R3
200Ω
VH
OPA698
R3
1kΩ
R4
2kΩ
VOUT
VL
VIN
VIN
VCL
–1V
+2V
VREF
R2
2kΩ
–2V
V
OPA698 VHL
VOUT
FIGURE 15. Very High-Speed Schmitt Trigger.
Figure 16 shows the Schmitt Trigger operating with VREF =
+5V. This gives us VHH = 2.4V and VHL = 1.6V. The propagation delay for the OPA698 in a Schmitt Trigger configuration is 6ns from high-to-low, and 5ns from low-to-high.
24.9Ω
FIGURE 13. Soft-Clipping Circuit.
Input and Output Voltage (V)
4
3
Input and Output Voltage (V)
VIN
2
1
VOUT
0
–1
2
1
0
VOUT
–1
VIN
–2
–3
–4
–2
Time (10ns/div)
–3
FIGURE 16. Schmitt Trigger Time Domain Response for a
10MHz Sinewave.
Time (100ns/div)
FIGURE 14. Soft Clipping with a Gain of 1/3 above the clamp
level (±1V).
VERY HIGH-SPEED SCHMITT TRIGGER
Figure 15 shows a very high-speed Schmitt Trigger. The
output levels are precisely defined, and the switching time is
exceptional. The output voltage swings between VH and VL.
The circuit operates as follow. When the input voltage is less
than VHL then the output is limiting at VH. When the input is
greater than VHH then the output is limiting at VL, with VHL and
VHH defined as the following:
VHL, HH =
3
UNITY-GAIN BUFFER
Figure 17 shows a unity-gain voltage buffer using the OPA698.
The feedback resistor (RF) isolates the output from the input
capacitance at the inverting input. RF = 24.9Ω is recommended for unity-gain buffer applications. RC is an optional
compensation resistor that reduces the peaking typically
seen at G = +1. Choosing RC = RS + RF gives a unity-gain
buffer with approximately the G = +2 frequency response.
The frequency response for this circuit is shown in the
electrical characteristics curves.
R1 || R 2 || R 3
R || R 2 || R 3
× VREF + 1
× VOUT
R1
R2
RS
Due to the inverting function realized by the Schmitt Trigger,
VHL corresponds to VOUT = VH, and VHH corresponds to
VOUT = VL.
OPA688
VS
VO
RC
RF
24.9Ω
FIGURE 17. Unity-Gain Buffer.
OPA698
SBOS258D
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19
DESIGN-IN TOOLS
DC RESTORER
Figure 18 shows a DC restore circuit using the OPA698 and
OPA660. The buffer element of the OPA660 is used to buffer
the input signal while the transconductance element is used
to restore the DC level after the decoupling capacitor C1. The
DC level is set using R1 and R2. The OPA698 is configured
at a gain of 2 to compensate for the 75Ω series into a 75Ω
load. The OPA698 also limits the output to ground.
DEMONSTRATION FIXTURE
A printed circuit board (PCB) is available to assist in the initial
evaluation of circuit performance using the OPA698. The
fixture is offered free of charge as an unpopulated PCB,
delivered with user's guide. The summary information for this
fixture is shown in Table I.
VIDEO SYNC STRIPPER
Figure 19 shows a sync stripper using two OPA698 outputlimiting op amps. One OPA698 is configured as a limiting
inverting comparator. Referred to the input, the negative
excursions lower than –0.2V are clipped to ground, and all
excursions greater than –0.2V generate an output voltage
set by the default limiting value (–3.5V). The second OPA698
is using this waveform to effectively remove the sync pulse
from the video signal.
VIN
VOUT
OPA698
VL
R3
402Ω
OPA698
VH
VL
–0.2V
ORDERING
NUMBER
LITERATURE
NUMBER
OPA698ID
SO-8
DEM-OPA-SO-1A
SBOU009
TABLE I. Demonstration Fixture.
This demonstration fixture can be requested at the Texas
Instruments web site (www.ti.com) through the OPA698
product folder.
THEORY OF OPERATION
R4
75Ω
VH
R2
402Ω
PACKAGE
OPERATING SUGGESTIONS
Open
R1
75Ω
PRODUCT
Open
The OPA698 is a voltage-feedback op amp that is unity-gain
stable. The output voltage is limited to a range set by the
voltage on the limiter pins (5 and 8). When the input tries to
overdrive the output, the limiters take control of the output
buffer. This action from the limiters avoids saturating any part
of the signal path, giving quick overdrive recovery and
excellent limiter accuracy at any signal gain. The limiters
have a very sharp transition from the linear region of operation to output limiting. This transition allows the limiter voltages to be set very near (< 100mV) the desired signal range.
The distortion performance is also very good near the limiter
voltages.
FIGURE 19. Sync Stripper Circuit.
C1
20µF
U1
200Ω
VIN
5
+1
VH = Open
20Ω
6
D1
1
RQ
250Ω
R1
19.6kΩ
75Ω
8
R2
1kΩ
OPA698
VO
5
D2
VL
75Ω
Load
402Ω
U1
C
CCII
402Ω
B
3
E
U1 = OPA660
RQ = 250Ω (sets IQ for U1)
D1, D2 = 1N4148
2
R3
200Ω
FIGURE 18. DC Restore to Ground.
20
OPA698
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SBOS258D
OUTPUT LIMITERS
The output voltage is linearly dependent on the input(s) when
it is between the limiter voltages VH (pin 8) and VL (pin 5).
When the output tries to exceed VH or VL, the corresponding
limiter buffer takes control of the output voltage and holds it
at VH or VL. Because the limiters act on the output, their
accuracy does not change with gain. The transition from the
linear region of operation to output limiting is very sharp—the
desired output signal can safely come to within 30mV of VH
or VL with no onset of non-linearity. The limiter voltages
can be set to within 0.7V of the supplies (VL ≥ –VS + 0.7V,
VH ≤ +VS – 0.7V). They must also be at least 400mV apart
(VH – VL ≥ 0.4V). When pins 5 and 8 are left open, VH and
VL go to the default voltage limit; the minimum values are
given in the electrical specifications. Looking at Figure 20 for
the zero bias current case shows the expected range of
(VS – default limit voltages) = headroom.
• Power supplies, when used to drive resistive dividers that
set VH and VL, can contribute large errors (for example,
±5%). Using a more accurate source, and bypassing pins
5 and 8 with good capacitors, will improve limiter PSRR.
• The resistor tolerances in the resistive divider can also
dominate. Use 1% resistors.
Other error sources also contribute, but should have little
impact on the limiters’ DC accuracy:
• Reduce offsets caused by the Limiter Input Bias Currents.
Select the resistors in the resistive divider(s) as described
above.
• Consider the signal path DC errors as contributing to
uncertainty in the useable output swing.
• The limiter offset voltage only slightly degrades limiter
accuracy. Figure 21 shows how the limiters affect distortion performance. Virtually no degradation in linearity is
observed for output voltage swinging right up to the limiter
voltages.
100
75
Maximum Over Temperature
50
–40
25
Minimum
Over Temperature
0
Harmonic Distortion (dBc)
Limiter Input Bias Current (µA)
voltages. The limiters’ DC accuracy depends on attention to
detail. The two dominant error sources can be improved as
follows:
–25
–50
Limiter Headroom = +VS – VH
= VL – (–VS)
Current = IVH or –IVL
–75
–100
0
0.5
1
1.5
2
2.5
Limiter Headroom (V)
VO = 0VDC ± 1VP
f = 5MHz
RL = 500Ω
–50
–60
2nd-Harmonic
–70
–80
3rd-Harmonic
–90
0.9
1
1.1
When the limiter voltages are more than 2.1V from the
supplies (VL ≥ –VS + 2.1V or VH ≤ +VS – 2.1V), you can use
simple resistor dividers to set VH and VL (see Figure 1). Make
sure to include the limiter input bias currents (Figure 8) in the
calculations (that is, IVL = –50µA out of pin 5, and IVH = +50µA
out of pin 8). For good limiter voltage accuracy, run at least
1mA quiescent bias current through these resistors. When
the limiter voltages need to be within 2.1V of the supplies (VL
≤ –VS + 2.1V or VH ≥ +VS – 2.1V), consider using low
impedance buffers to set VH and VL to minimize errors due
to bias current uncertainty. This condition will typically be the
case for single-supply operation (VS = +5V). Figure 2 runs
2.5mA through the resistive divider that sets VH and VL. This
limits errors due to IVH and IVL < ±1% of the target limit
1.3 1.4
1.5
1.6
1.7 1.8 1.9
2
FIGURE 21. Harmonic Distortion Near Limit Voltages.
OUTPUT DRIVE
The OPA698 has been optimized to drive 500Ω loads, such
as ADCs. It still performs very well driving 100Ω loads; the
specifications are shown for the 500Ω load. This makes the
OPA698 an ideal choice for a wide range of high-frequency
applications.
Many high-speed applications, such as driving ADCs, require
op amps with low output impedance. As shown in the typical
performance curve Output Impedance vs Frequency, the
OPA698 maintains very low closed-loop output impedance
over frequency. Closed-loop output impedance increases
with frequency, since loop gain decreases with frequency.
OPA698
SBOS258D
1.2
± Limit Voltage (V)
FIGURE 20. Limiter Bias Current vs Bias Voltage.
www.ti.com
21
THERMAL CONSIDERATIONS
The OPA698 will not require heat sinking under most operating conditions. Maximum desired junction temperature will
set a maximum allowed internal power dissipation as described below. In no case should the maximum junction
temperature be allowed to exceed 150°C.
The total internal power dissipation (PD) is the sum of
quiescent power (PDQ) and the additional power dissipated in
the output stage (PDL) while delivering load power. PDQ is
simply the specified no-load supply current times the total
supply voltage across the part. PDL depends on the required
output signals and loads. For a grounded resistive load, and
equal bipolar supplies, it is at maximum when the output is
at 1/2 either supply voltage. In this condition, PDL = VS2/(4RL)
where RL includes the feedback network loading. Note that it
is the power in the output stage, and not in the load, that
determines internal power dissipation.
The operating junction temperature is: TJ = TA + PD x θJA,
where TA is the ambient temperature. For example, the
maximum TJ for a OPA698ID with G = +2, RF = 402Ω, RL =
100Ω, and ±VS = ±5V at the maximum TA = +85°C is
calculated as:
PDQ = (10V × 15.5mA ) = 155mW
PDL =
( 5V ) 2
4 × (100Ω || 804Ω)
= 70mW
PD = 155mW + 70mW = 225mW
TJ = 85°C + 225mW × 125°C / W = 113°C
This would be the maximum TJ from VO = ±2.5VDC. Most
applications will be at a lower output stage power and have
a lower TJ.
CAPACITIVE LOADS
Capacitive loads, such as the input to ADCs, will decrease
the amplifier phase margin, which may cause high-frequency
peaking or oscillations. Capacitive loads ≥ 2pF should be
isolated by connecting a small resistor in series with the
output, as shown in Figure 22. Increasing the gain from +2
will improve the capacitive drive capabilities due to increased
phase margin.
RG
In general, capacitive loads should be minimized for optimum
high-frequency performance. The capacitance of coax cable
(29pF/ft for RG-58) will not load the amplifier when the
coaxial cable, or transmission line, is terminated in its characteristic impedance.
FREQUENCY RESPONSE COMPENSATION
The OPA698 is internally compensated to be unity-gain
stable, and has a nominal phase margin of 60° at a gain of
+2. Phase margin and peaking improve at higher gains.
Recall that an inverting gain of –1 is equivalent to a gain of
+2 for bandwidth purposes (that is, noise gain = 2). Standard
external compensation techniques work with this device.
For example, in the inverting configuration, the bandwidth
may be limited without modifying the inverting gain by placing
a series RC network to ground on the inverting node. This
has the effect of increasing the noise gain at high frequencies, which limits the bandwidth.
To maintain a wide bandwidth at high gains, cascade several
op amps, or use the high-gain optimized OPA699.
In applications where a large feedback resistor is required,
such as photodiode transimpedance amplifier, the parasitic
capacitance from the inverting input to ground causes peaking or oscillations. To compensate for this effect, connect a
small capacitor in parallel with the feedback resistor. The
bandwidth will be limited by the pole that the feedback
resistor and this capacitor create. In other high-gain applications, use a three-resistor Tee network to reduce the RC time
constants set by the parasitic capacitances. Be careful not to
increase the noise generated by this feedback network too
much.
PULSE SETTLING TIME
The OPA698 is capable of an extremely fast settling time in
response to a pulse input. Frequency response flatness and
phase linearity are needed to obtain the best settling times.
For capacitive loads, such as an ADC, use the recommended RS in the typical performance curve RS vs Capacitive Load. Extremely fine-scale settling (0.01%) requires
close attention to ground return current in the supply
decoupling capacitors.
The pulse settling characteristics, when recovering from
overdrive, are very good.
DISTORTION
RF
RS
VO
OPA698
RL
RT
The OPA698 distortion performance is specified for a 500Ω
load, such as an ADC. Driving loads with smaller resistance
will increase the distortion, as illustrated in Figure 23. Remember to include the feedback network in the load resistance calculations.
CL
RL is optional
FIGURE 22. Driving Capacitive Loads.
22
OPA698
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SBOS258D
2nd- and 3rd-Harmonic Distortion (dBc)
The total output spot noise voltage can be computed as the
square root of the sum of all squared output noise voltage
contributors. Equation 3 shows the general form for the
output noise voltage using the terms shown in Figure 25.
–40
VO = 2VPP
f1 = 5MHz
–45
–50
(3)
HD2
–55
2
2
EO = ENI2 + (IBNR S ) + 4kTRS NG2 + (IBIRF ) + 4kTRFNG
–60
–65
HD3
–80
Dividing this expression by the noise gain (NG = (1+RF/RG))
will give the equivalent input-referred spot noise voltage at
the noninverting input, as shown in Equation 4.
–85
(4)
–70
–75
–90
50
100
2
4kTRF
2
I R
EN = ENI2 + (IBNR S ) + 4kTRS + BI F +
NG
NG
1000
Load Resistance (Ω)
FIGURE 23. 5MHz Harmonic Distortion vs Load Resistance.
NOISE PERFORMANCE
High slew rate, unity-gain stable, voltage feedback op amps
usually achieve their slew rate at the expense of a higher
input noise voltage. The 5.6nV/√Hz input voltage noise for
the OPA698, however, is much lower than comparable
amplifiers. The input-referred voltage noise, and the two
input-referred current noise terms, combine to give low
output noise under a wide variety of operating conditions.
Figure 24 shows the op amp noise analysis model with all the
noise terms included. In this model, all noise terms are taken
to be noise voltage or current density terms in either nV/√Hz
or pA/√Hz.
Evaluating these two equations for the OPA698 circuit and
component values (see Figure 1) will give a total output spot
noise voltage of 11.9nV/√Hz and a total equivalent input spot
noise voltage of 6nV/√Hz. This total input-referred spot noise
voltage is only slightly higher than the 5.6nV/√Hz specification for the op amp voltage noise alone. This will be the case
as long as the impedances appearing at each op amp input
are limited to a maximum value of 300Ω. Keeping both
(RF || RG) and the noninverting input source impedance less
than 300Ω will satisfy both noise and frequency response
flatness considerations. Since the resistor-induced noise is
relatively negligible, additional capacitive decoupling across
the bias current cancellation resistor (RT) for the inverting op
amp configuration of Figure 3 is not required, but is still
desirable.
DC ACCURACY AND OFFSET CONTROL
ENI
EO
OPA698
RS
IBN
ERS
RF
√ 4kTRS
4kT
RG
RG
IBI
√ 4kTRF
4kT = 1.6E –20J
at 290°K
The balanced input stage of a wideband voltage feedback op
amp allows good output DC accuracy in a large variety of
applications. The power-supply current trim for the OPA698
gives even tighter control than comparable products. Although the high-speed input stage does require relatively
high input bias current (typically ±8µA at each input terminal),
the close matching between them may be used to reduce the
output DC error caused by this current. The total output offset
voltage may be considerably reduced by matching the DC
source resistances appearing at the two inputs. This reduces
the output DC error due to the input bias currents to the offset
current times the feedback resistor. Evaluating the configuration of Figure 1, using worst-case +25°C input offset voltage
and current specifications, gives a worst-case output offset
voltage equal to: –(NG = noninverting signal gain)
±(NG • VOS(MAX)) ± (RF • IOS(MAX))
FIGURE 24. Op Amp Noise Analysis Model.
= ±(2 • 5mV) ± (402Ω • 1.4µA)
= ±10.6mV
OPA698
SBOS258D
www.ti.com
23
A fine-scale output offset null, or DC operating point adjustment, is often required. Numerous techniques are available
for introducing DC offset control into an op amp circuit. Most
of these techniques eventually reduce to adding a DC current
through the feedback resistor. In selecting an offset trim
method, one key consideration is the impact on the desired
signal path frequency response. If the signal path is intended
to be noninverting, the offset control is best applied as an
inverting summing signal to avoid interaction with the signal
source. If the signal path is intended to be inverting, applying
the offset control to the noninverting input may be considered. However, the DC offset voltage on the summing
junction will set up a DC current back into the source which
must be considered. Applying an offset adjustment to the
inverting op amp input can change the noise gain and
frequency response flatness. For a DC-coupled inverting
amplifier, Figure 25 shows one example of an offset adjustment technique that has minimal impact on the signal frequency response. In this case, the DC offsetting current is
brought into the inverting input node through resistor values
that are much larger than the signal path resistors. This will
insure that the adjustment circuit has minimal effect on the
loop gain as well as the frequency response.
+5V
Supply Decoupling
Not Shown
0.1µF
328Ω
OPA698
VO
–5V
RG
500Ω
+5V
5kΩ
RF
1kΩ
±200mV Output Adjustment
10kΩ
0.1µF
5kΩ
VO
VI
=–
RF
RG
= –2
–5V
FIGURE 25. DC-Coupled, Inverting Gain of –2, with Offset
Adjustment.
24
Achieving optimum performance with the high-frequency
OPA698 requires careful attention to layout design and
component selection. Recommended PCB layout techniques
and component selection criteria are:
a) Minimize parasitic capacitance to any AC ground for all
of the signal I/O pins. Open a window in the ground and
power planes around the signal I/O pins, and leave the
ground and power planes unbroken elsewhere.
b) Provide a high quality power supply. Use linear regulators, ground plane and power planes to provide power.
Place high frequency 0.1µF decoupling capacitors < 0.2"
away from each power-supply pin. Use wide, short traces to
connect to these capacitors to the ground and power planes.
Also use larger (2.2µF to 6.8µF) high-frequency decoupling
capacitors to bypass lower frequencies. They may be somewhat further from the device, and be shared among several
adjacent devices.
c) Place external components close to the OPA698. This
minimizes inductance, ground loops, transmission line effects and propagation delay problems. Be extra careful with
the feedback (RF), input and output resistors.
d) Use high-frequency components to minimize parasitic
elements. Resistors should be a very low reactance type.
Surface-mount resistors work best and allow a tighter layout.
Metal film or carbon composition axially-leaded resistors can
also provide good performance when their leads are as short
as possible. Never use wirewound resistors for high-frequency applications. Remember that most potentiometers
have large parasitic capacitances and inductances. Multilayer ceramic chip capacitors work best and take up little
space. Monolithic ceramic capacitors also work very well.
Use RF type capacitors with low ESR and ESL. The large
power pin bypass capacitors (2.2µF to 6.8µF) should be
tantalum for better high frequency and pulse performance.
e) Choose low resistor values to minimize the time constant set by the resistor and its parasitic parallel capacitance.
Good metal film or surface mount resistors have approximately 0.2pF parasitic parallel capacitance. For resistors
> 1.5kΩ, this adds a pole and/or zero below 500MHz. Make
sure that the output loading is not too heavy. The recommended 402Ω feedback resistor is a good starting point in
most designs.
VI
20kΩ
BOARD LAYOUT GUIDELINES
f) Use short direct traces to other wideband devices on
the board. Short traces act as a lumped capacitive load.
Wide traces (50 to 100 mils) should be used. Estimate the
total capacitive load at the output, and use the series isolation resistor recommended in the typical performance curve,
RS vs Capacitive Load. Parasitic loads < 2pF may not need
the isolation resistor.
OPA698
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SBOS258D
g) When long traces are necessary, use transmission line
design techniques (consult an ECL design handbook for
microstrip and stripline layout techniques). A 50Ω transmission line is not required on board—a higher characteristic
impedance will help reduce output loading. Use a matching
series resistor at the output of the op amp to drive a
transmission line, and a matched load resistor at the other
end to make the line appear as a resistor. If the 6dB of
attenuation that the matched load produces is not acceptable, and the line is not too long, use the series resistor at the
source only. This will isolate the source from the reactive load
presented by the line, but the frequency response will be
degraded. Multiple destination devices are best handled as
separate transmission lines, each with its own series source
and shunt load terminations. Any parasitic impedances acting on the terminating resistors will alter the transmission line
match, and can cause unwanted signal reflections and reactive loading.
voltage constraints are observed. The common-mode input
and output voltage specifications can be interpreted as a
required headroom to the supply voltage. Observing this
input and output headroom requirement will allow design of
non-standard or single-supply operation circuits. Figure 2
shows one approach to single-supply operation.
INPUT AND ESD PROTECTION
ESD damage has been known to damage MOSFET devices,
but any semiconductor device is vulnerable to ESD damage.
This is particularly true for very high-speed, fine geometry
processes. ESD damage can cause subtle changes in amplifier input characteristics without necessarily destroying the
device. In precision operational amplifiers, this may cause a
noticeable degradation of offset voltage and drift. Therefore,
ESD handling precautions are required when handling the
OPA698.
h) Do not use sockets for high-speed parts like the OPA698.
The additional lead length and pin-to-pin capacitance introduced by the socket creates an extremely troublesome
parasitic network. Best results are obtained by soldering the
part onto the board.
+V CC
External
Pin
POWER SUPPLIES
The OPA698 is nominally specified for operation using either
±5V supplies or a single +5V supply. The maximum specified
total supply voltage of 12V allows reasonable tolerances on
the supplies. Higher supply voltages can break down internal
junctions, possibly leading to catastrophic failure. Singlesupply operation is possible as long as common mode
–V CC
FIGURE 26. Internal ESD Protection.
OPA698
SBOS258D
Internal
Circuitry
www.ti.com
25
Revision History
DATE
REVISION
PAGE
12/08
D
2
3/06
C
20
SECTION
DESCRIPTION
Absolute Maximum Ratings Changed minimum Storage Temperature Range from −40°C to −65°C.
Design-In Tools
Board part number changed.
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
26
OPA698
www.ti.com
SBOS258D
PACKAGE OPTION ADDENDUM
www.ti.com
13-Aug-2021
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
OPA698ID
ACTIVE
SOIC
D
8
75
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
OPA
698
OPA698IDG4
ACTIVE
SOIC
D
8
75
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
OPA
698
OPA698IDR
ACTIVE
SOIC
D
8
2500
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
OPA
698
OPA698IDRG4
ACTIVE
SOIC
D
8
2500
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
OPA
698
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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