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OPA820
SBOS303D – JUNE 2004 – REVISED DECEMBER 2016
OPA820 Unity-Gain Stable, Low-Noise, Voltage-Feedback Operational Amplifier
1 Features
3 Description
•
•
•
•
•
The OPA820 device provides a wideband, unity-gain
stable, voltage-feedback amplifier with a very-low
input-noise voltage and high-output current using a
low 5.6-mA supply current. At unity-gain, the OPA820
device gives more than 800-MHz bandwidth with less
than 1-dB peaking. The OPA820 device complements
this high-speed operation with excellent DC precision
in a low-power device. A worst-case input-offset
voltage of ±750 µV and an offset current of ±400 nA
provide excellent absolute DC precision for pulse
amplifier applications.
1
•
High Bandwidth (240 MHz, G = 2)
High-Output Current (±110 mA)
Low-Input Noise (2.5 nV/√Hz)
Low-Supply Current (5.6 mA)
Flexible Supply Voltage:
– Dual ±2.5 V to ±6 V
– Single 5 V to 12 V
Excellent DC Accuracy:
– Maximum 25°C Input Offset Voltage = ±750 µV
– Maximum 25°C Input Offset Current = ±400 nA
Minimal input and output voltage-swing headroom
allow the OPA820 device to operate on a single 5-V
supply with more than 2-VPP output swing. While not
a rail-to-rail (RR) output, this swing supports most
emerging analog-to-digital converter (ADC) input
ranges with lower power and noise than typical RR
output op amps.
2 Applications
•
•
•
•
•
•
•
•
•
Low-Cost Video Line Drivers
ADC Preamplifiers
Active Filters
Low-Noise Integrators
Portable Test Equipment
Optical Channel Amplifiers
Low-Power, Baseband Amplifiers
CCD Imaging Channel Amplifiers
OPA650 and OPA620 Upgrade
Exceptionally low dG/dP (0.01% or 0.03°) supports
low-cost composite-video line-driver applications.
Existing designs can use the industry-standard
pinout, 8-pin SOIC package while emerging highdensity portable applications can use the 5-pin SOT23. Offering the lowest thermal impedance of the
industry in a SOT package, along with full
specification over both the commercial and industrial
temperature ranges, provides solid performance over
a wide temperature range.
Device Information(1)
PART NUMBER
OPA820
PACKAGE
BODY SIZE (NOM)
SOIC (8)
4.90 mm × 3.91 mm
SOT-23 (5)
2.90 mm × 1.60 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
AC-Coupled, 14-Bit ADS850 Interface
5V
5V
VIN
0.1 PF
+
RS
24.9
2k
REFT
(3 V)
2k
OPA820
IN
50
100 pF
ADS850
14-Bit
10 MSPS
±5 V
2k
402
IN
402
0.1 µF
2k
(2 V) (1 V)
REFB VREF
SEL
Copyright © 2016, Texas Instruments Incorporated
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
OPA820
SBOS303D – JUNE 2004 – REVISED DECEMBER 2016
www.ti.com
Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Device Comparison Table.....................................
Pin Configuration and Functions .........................
Specifications.........................................................
7.1
7.2
7.3
7.4
7.5
7.6
7.7
8
9
1
1
1
2
3
3
3
Absolute Maximum Ratings ...................................... 3
ESD Ratings.............................................................. 4
Recommended Operating Conditions....................... 4
Thermal Information .................................................. 4
Electrical Characteristics: VS = ±5 V......................... 4
Electrical Characteristics: VS = 5 V........................... 7
Typical Characteristics ............................................ 10
Parameter Measurement Information ................ 18
Detailed Description ............................................ 20
9.1 Overview ................................................................. 20
9.2 Feature Description................................................. 20
9.3 Device Functional Modes........................................ 24
10 Application and Implementation........................ 28
10.1 Application Information.......................................... 28
10.2 Typical Applications .............................................. 28
11 Power Supply Recommendations ..................... 34
12 Layout................................................................... 35
12.1 Layout Guidelines ................................................. 35
12.2 Layout Example .................................................... 36
13 Device and Documentation Support ................. 37
13.1
13.2
13.3
13.4
13.5
13.6
13.7
Device Support......................................................
Documentation Support ........................................
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
37
37
37
38
38
38
38
14 Mechanical, Packaging, and Orderable
Information ........................................................... 38
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision C (August 2008) to Revision D
Page
•
Added Pin Configuration and Functions section, ESD Ratings table, Feature Description section, Device Functional
Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device
and Documentation Support section, and Mechanical, Packaging, and Orderable Information section ............................... 1
•
Deleted Ordering Information table; see Package Option Addendum at the end of the data sheet ...................................... 1
•
Deleted Lead temperature (soldering, 300°C maximum) from Absolute Maximum Ratings table......................................... 3
•
Added Thermal Information table ........................................................................................................................................... 4
•
Changed Open-loop voltage gain test condition in Electrical Characteristics: VS = ±5 V table From: VO To: VCM ................ 5
•
Changed Open-loop voltage gain test condition in Electrical Characteristics: VS = 5 V table From: VO To: VCM .................. 8
•
Changed R2 From: 505 Ω To: 517 Ω, C1 From: 150 pF To: 100 pF, and C2 From: 100 pF To: 160 pF in 5-MHz
Butterworth Low-Pass Active Filter image............................................................................................................................ 28
Changes from Revision B (March 2006) to Revision C
•
Changed Storage Temperature minimum value from –40°C to –65°C .................................................................................. 3
Changes from Revision A (July 2004) to Revision B
•
2
Page
Page
Changed the board part number in the Design-In Tools section.......................................................................................... 37
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OPA820
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SBOS303D – JUNE 2004 – REVISED DECEMBER 2016
5 Device Comparison Table
Table 1. Related Products
SINGLE CHANNEL
DUAL CHANNEL
TRIPLE CHANNEL
QUAD CHANNEL
FEATURES
OPA354
OPA2354
—
OPA4354
CMOS RR output
OPA690
OPA2690
OPA3690
—
High-slew rate
—
OPA2652
—
—
8-Pin SOT23
—
OPA2822
—
—
Low noise
—
—
—
OPA4820
Quad OPA820
6 Pin Configuration and Functions
D Package
8-Pin SOIC
Top View
DBV Package
5-Pin SOT-23
Top View
1
8
NC
Inverting Input
2
7
Noninverting Input
3
6
+VS
Noninverting Input
Output
±VS
4
5
NC
+
Output
1
±VS
2
Noninverting Input
3
5
+VS
Noninverting Input
+
NC
4
Inverting Input
Pin Functions
PIN
I/O
DESCRIPTION
NAME
SOIC
SOT-23
Disable
8
—
I
Disable the op amp (Low = Disable; High = Enable)
Inverting Input
2
4
I
Inverting input
1, 5, 8
—
—
No connection
Noninverting Input
3
3
I
Noninverting input
Output
6
1
O
Output of amplifier
+VS
7
5
—
Positive power supply
–VS
4
2
—
Negative power supply
NC
7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
MIN
Power supply
Internal power dissipation
MAX
UNIT
±6.5
VDC
See Thermal Information
Differential input voltage
±1.2
Input common-mode voltage
±VS
V
Junction temperature, TJ
150
°C
125
°C
Storage temperature, Tstg
(1)
–65
V
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
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OPA820
SBOS303D – JUNE 2004 – REVISED DECEMBER 2016
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7.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1)
±3000
Charged-device model (CDM), per JEDEC specification JESD22-C101 (2)
±1000
Machine model (MM)
±300
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
7.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
VS
Total supply voltage
TA
Operating ambient temperature
MIN
NOM
MAX
5
10
12
UNIT
V
–45
25
85
°C
7.4 Thermal Information
OPA820
THERMAL METRIC (1)
RθJA
Junction-to-ambient thermal resistance
RθJC(top)
DBV (SOT-23)
D (SOIC)
5 PINS
8 PINS
UNIT
150
125
°C/W
Junction-to-case (top) thermal resistance
141.1
72.6
°C/W
RθJB
Junction-to-board thermal resistance
42.9
68.2
°C/W
ψJT
Junction-to-top characterization parameter
23.5
28.1
°C/W
ψJB
Junction-to-board characterization parameter
42
67.8
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
7.5 Electrical Characteristics: VS = ±5 V
RF = 402 Ω, RL = 100 Ω, G = 2, and TA = 25°C (unless otherwise noted) (1) (2) (3)
PARAMETER
TEST CONDITIONS
MIN
TYP MAX
UNIT
AC PERFORMANCE
G = 1, VO = 0.1 VPP, RF = 0 Ω, Test level = C
G = 2, VO = 0.1 VPP,
Test level = B
Small-signal bandwidth
G = 10, VO = 0.1 VPP,
Test level = B
170
TA = 0°C to 70°C
160
TA = –40°C to 85°C
155
TA = 25°C
23
TA = 0°C to 70°C
21
TA = –40°C to 85°C
(2)
(3)
4
240
MHz
30
20
TA = 25°C
220
TA = 0°C to 70°C
204
TA = –40°C to 85°C
200
280
Gain-bandwidth product
G ≥ 20, Test level = B
Bandwidth for 0.1-dB gain flatness
G = 2, VO = 0.1 VPP, Test level = C
38
Peaking at a gain of 1
VO = 0.1 VPP, RF = 0 Ω, Test level = C
0.5
dB
Large-signal bandwidth
G = 2, VO = 2 VPP, Test level = C
85
MHz
Slew rate
G = 2, 2-V step,
Test level = B
Rise time and fall time
(1)
800
TA = 25°C
TA = 25°C
192
TA = 0°C to 70°C
186
TA = –40°C to 85°C
180
G = 2, VO = 0.2-V step, Test level = C
MHz
MHz
240
V/µs
1.5
ns
Test levels: (A) 100% tested at 25°C. Overtemperature limits by characterization and simulation. (B) Limits set by characterization and
simulation. (C) Typical value only for information.
TJ = TA for 25°C specifications.
TJ = TA at low temperature limits; TJ = TA + 9°C at high temperature limit for over temperature.
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SBOS303D – JUNE 2004 – REVISED DECEMBER 2016
Electrical Characteristics: VS = ±5 V (continued)
RF = 402 Ω, RL = 100 Ω, G = 2, and TA = 25°C (unless otherwise noted)(1)(2)(3)
PARAMETER
Settling time
TEST CONDITIONS
G = 2, VO = 2-V step,
Test level = C
G = 2, f = 1 MHz,
VO = 2 VPP, RL = 200 Ω,
Test level = B
Harmonic distortion, 2nd-harmonic
G = 2, f = 1 MHz,
VO = 2 VPP, RL ≥ 500 Ω,
Test level = B
G = 2, f = 1 MHz,
VO = 2 VPP, RL = 200 Ω,
Test level = B
Harmonic distortion, 3rd-harmonic
G = 2, f = 1 MHz,
VO = 2 VPP, RL ≥ 500 Ω,
Test level = B
MIN
To 0.02%
22
To 0.1%
18
TA = 25°C
–85
TA = 0°C to 70°C
f > 100 kHz, Test level = B
f > 100 kHz, Test level = B
ns
–81
–79
TA = 25°C
–90
TA = 0°C to 70°C
dBc
–85
–83
TA = –40°C to 85°C
–81
TA = 25°C
–95
TA = 0°C to 70°C
–90
–89
TA = –40°C to 85°C
–88
TA = 25°C
dBc
–110 –105
TA = 0°C to 70°C
–102
TA = –40°C to 85°C
–100
2.5
2.7
TA = 0°C to 70°C
2.8
TA = –40°C to 85°C
2.9
TA = 25°C
Input current noise
UNIT
–80
TA = –40°C to 85°C
TA = 25°C
Input voltage noise
TYP MAX
1.7
TA = 0°C to 70°C
2.6
2.8
TA = –40°C to 85°C
nV/√Hz
pA/√Hz
3
Differential gain
G = 2, PAL, VO = 1.4 VPP, RL = 150 Ω, Test level = C
0.01%
Differential phase
G = 2, PAL, VO = 1.4 VPP, RL = 150 Ω, Test level = C
0.03
°
DC PERFORMANCE (4)
AOL
Open-loop voltage gain
VCM = 0 V, Test level = A
TA = 25°C
62
TA = 0°C to 70°C
61
TA = –40°C to 85°C
60
TA = 25°C
Input offset voltage
VCM = 0 V, Test level = A
66
dB
±0.2
TA = 0°C to 70°C
VCM = 0 V, Test level = B
Input bias current
VCM = 0 V, Test level = A
Average input bias current drift
VCM = 0 V, Test level = B
Input offset current
VCM = 0 V, Test level = A
4
TA = –40°C to 85°C
4
–9
(4)
VCM = 0 V, Test level = B
µV/°C
–17
TA = 0°C to 70°C
–19
TA = –40°C to 85°C
–23
TA = 0°C to 70°C
30
TA = –40°C to 85°C
50
TA = 25°C
Inverting input bias-current drift
±1.2
TA = 0°C to 70°C
TA = 25°C
mV
±1
TA = –40°C to 85°C
Average input offset voltage drift
±0.7
5
µA
nA/°C
±100 ±400
TA = 0°C to 70°C
±600
TA = –40°C to 85°C
±700
TA = 0°C to 70°C
5
TA = –40°C to 85°C
5
nA
nA/°C
Current is considered positive out-of-node. VCM is the input common-mode voltage.
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Electrical Characteristics: VS = ±5 V (continued)
RF = 402 Ω, RL = 100 Ω, G = 2, and TA = 25°C (unless otherwise noted)(1)(2)(3)
PARAMETER
TEST CONDITIONS
MIN
TYP MAX
UNIT
INPUT
Common-mode input range (5)
CMIR
CMRR
Common-mode rejection ratio
Test level = A
VCM = 0 V, Input-referred,
Test level = A
TA = 25°C
±3.8
TA = 0°C to 70°C
±3.7
TA = –40°C to 85°C
±3.6
TA = 25°C
76
TA = 0°C to 70°C
75
TA = –40°C to 85°C
73
Input impedance, differential mode VCM = 0 V, TA = 25°C, Test level = C
Input impedance, common mode
VCM = 0 V, TA = 25°C, Test level = C
±4
V
85
dB
18 || 0.8
kΩ || pF
6 || 1
MΩ || pF
OUTPUT
No load, Test level = A
Output voltage swing
RL = 100 Ω, Test level = A
TA = 25°C
±3.5
TA = 0°C to 70°C
±3.4
2
TA = –40°C to 85°C
±3.4
TA = 25°C
±3.5
TA = 0°C to 70°C
±3.4
5
TA = –40°C to 85°C
±3.4
TA = 25°C
±90
TA = 0°C to 70°C
±80
TA = –40°C to 85°C
±75
±3.7
V
±3.6
±110
Output current
VO = 0 V, Test level = A
mA
Short-circuit output current
Output shorted to ground, Test level = C
±125
mA
Closed-loop output impedance
G = 2, f ≤ 100 kHz, Test level = C
0.04
Ω
POWER SUPPLY
TA = 25°C
Quiescent current
PSRR
(5)
6
Power-supply rejection ratio
VS = ±5 V, Test level = A
Input referred, Test level = A
TA = 0°C to 70°C
5.45
5.6
5.75
5
6.2
TA = –40°C to 85°C
4.8
6.4
TA = 25°C
64
TA = 0°C to 70°C
63
TA = –40°C to 85°C
62
mA
72
dB
Tested at less than 3 dB below the minimum specified CMRR at ± CMIR limits.
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SBOS303D – JUNE 2004 – REVISED DECEMBER 2016
7.6 Electrical Characteristics: VS = 5 V
RF = 402 Ω, RL = 100 Ω, G = 2, and TA = 25°C (unless otherwise noted) (1) (2) (3)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
AC PERFORMANCE
G = 1, VO = 0.1 VPP, RF = 0 Ω, Test level = C
G = 2, VO = 0.1 VPP,
Test level = B
Small-signal bandwidth
G = 10, VO = 0.1 VPP,
Test level = B
550
TA = 25°C
168
TA = 0°C to 70°C
155
TA = –40°C to 85°C
151
TA = 25°C
21
TA = 0°C to 70°C
20
TA = –40°C to 85°C
230
MHz
28
19
TA = 25°C
200
TA = 0°C to 70°C
190
TA = –40°C to 85°C
185
260
Gain-bandwidth product
G ≥ 20, Test level = B
Peaking at a gain of 1
VO = 0.1 VPP, RF = 0 Ω, Test level = C
0.5
dB
Large-signal bandwidth
G = 2, VO = 2 VPP, Test level = C
70
MHz
Slew rate
G = 2, 2-V step,
Test level = B
TA = 25°C
145
TA = 0°C to 70°C
140
TA = –40°C to 85°C
135
Rise time and fall time
G = 2, VO = 2-V step, Test level = C
Settling time
G = 2, VO = 2-V step,
Test level = C
G = 2, f = 1 MHz,
VO = 2 VPP, RL = 200 Ω,
Test level = B
Harmonic distortion, 2nd-harmonic
G = 2, f = 1 MHz,
VO = 2 VPP, RL ≥ 500 Ω,
Test level = B
G = 2, f = 1 MHz,
VO = 2 VPP, RL = 200 Ω,
Test level = B
Harmonic distortion, 3rd-harmonic
G = 2, f = 1 MHz,
VO = 2 VPP, RL ≥ 500 Ω,
Test level = B
f > 100 kHz, Test level = B
200
V/µs
1.7
To 0.02%
24
To 0.1%
21
TA = 25°C
–80
TA = 0°C to 70°C
TA = 25°C
TA = 0°C to 70°C
(1)
(2)
(3)
–92
–91
TA = –40°C to 85°C
–90
–98
TA = 0°C to 70°C
dBc
–95
–93
TA = –40°C to 85°C
–92
2.5
TA = 0°C to 70°C
TA = 25°C
f > 100 kHz, Test level = B
dBc
–79
–75
–100
2.8
2.9
TA = –40°C to 85°C
Input current noise
–76
–77
TA = –40°C to 85°C
TA = 25°C
ns
–74
–83
TA = 0°C to 70°C
TA = 25°C
ns
–75
TA = –40°C to 85°C
TA = 25°C
Input voltage noise
MHz
nV/√Hz
3
1.6
2.5
TA = 0°C to 70°C
2.7
TA = –40°C to 85°C
2.9
pA/√Hz
Test levels: (A) 100% tested at 25°C. Overtemperature limits by characterization and simulation. (B) Limits set by characterization and
simulation. (C) Typical value only for information.
TJ = TA for 25°C specifications.
TJ = TA at low temperature limits; TJ = TA + 9°C at high temperature limit for over temperature.
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Electrical Characteristics: VS = 5 V (continued)
RF = 402 Ω, RL = 100 Ω, G = 2, and TA = 25°C (unless otherwise noted)(1)(2)(3)
PARAMETER
DC PERFORMANCE
AOL
TEST CONDITIONS
MIN
TYP
TA = 25°C
60
65
TA = 0°C to 70°C
59
TA = –40°C to 85°C
58
MAX
UNIT
(4)
Open-loop voltage gain
VO = 2.5 V, Test level = A
TA = 25°C
Input offset voltage
Average input offset voltage drift
VCM = 2.5 V, Test level = A
VCM = 2.5 V, Test level = B
±0.3
VCM = 2.5 V, Test level = A
Average input bias current drift
VCM = 2.5 V, Test level = B
Input offset current
VCM = 2.5 V, Test level = A
±1.4
TA = –40°C to 85°C
±1.6
TA = 0°C to 70°C
4
TA = –40°C to 85°C
4
–8
–18
TA = –40°C to 85°C
–22
TA = 0°C to 70°C
30
TA = –40°C to 85°C
50
VCM = 2.5 V, Test level = B
Lease positive input voltage
Test level = A
±100
mV
µV/°C
–16
TA = 0°C to 70°C
TA = 25°C
Inverting input bias-current drift
±1.1
TA = 0°C to 70°C
TA = 25°C
Input bias current
dB
µA
nA/°C
±400
TA = 0°C to 70°C
±600
TA = –40°C to 85°C
±700
TA = 0°C to 70°C
5
TA = –40°C to 85°C
5
nA
nA/°C
INPUT
TA = 25°C
Most positive input voltage
CMRR
Common-mode rejection ratio
Test level = A
(4)
8
1.1
1.2
TA = –40°C to 85°C
1.3
TA = 25°C
4.2
TA = 0°C to 70°C
4.1
TA = –40°C to 85°C
4
TA = 25°C
VCM = 2.5 V, Input-referred,
TA = 0°C to 70°C
Test level = A
TA = –40°C to 85°C
74
Input impedance, differential mode VCM = 2.5 V, TA = 25°C, Test level = C
Input impedance, common mode
0.9
TA = 0°C to 70°C
VCM = 2.5 V, TA = 25°C, Test level = C
V
4.5
V
83
73
dB
72
15 || 1
kΩ || pF
5 ||
1.3
MΩ || pF
Current is considered positive out-of-node. VCM is the input common-mode voltage.
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SBOS303D – JUNE 2004 – REVISED DECEMBER 2016
Electrical Characteristics: VS = 5 V (continued)
RF = 402 Ω, RL = 100 Ω, G = 2, and TA = 25°C (unless otherwise noted)(1)(2)(3)
PARAMETER
TEST CONDITIONS
MIN
TYP
3.8
3.9
MAX
UNIT
OUTPUT
TA = 25°C
No load, Test level = A
Most positive output voltage
RL = 100 Ω to 2.5 V,
Test level = A
TA = 0°C to 70°C
3.75
TA = –40°C to 85°C
3.7
TA = 25°C
3.7
TA = 0°C to 70°C
TA = –40°C to 85°C
3.65
3.6
TA = 25°C
No load, Test level = A
1.2
TA = 0°C to 70°C
1.4
TA = 25°C
RL = 100 Ω to 2.5 V,
Test level = A
1.2
TA = 0°C to 70°C
VO = 2.5 V, Test level = A
1.3
V
1.35
TA = –40°C to 85°C
Output current
1.3
1.35
TA = –40°C to 85°C
Least positive output voltage
V
3.8
1.4
TA = 25°C
±80
TA = 0°C to 70°C
±70
TA = –40°C to 85°C
±65
±105
mA
Short-circuit output current
Output shorted to ground, Test level = C
±115
mA
Closed-loop output impedance
G = 2, f ≤ 100 kHz, Test level = C
0.04
Ω
POWER SUPPLY
TA = 25°C
Quiescent current
VS = ±5 V, Test level = A
TA = 0°C to 70°C
TA = –40°C to 85°C
PSRR
Power-supply rejection ratio
Input referred, TA = 25°C, Test level = A
4.4
5
5.4
4.25
5.5
4.1
5.6
68
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7.7 Typical Characteristics
7.7.1 ±5-V Supply Voltage
3
3
0
0
Normalized Gain (dB)
−3
−6
−9
−12
G=1
G=2
G=5
G = 10
−15
−3
−6
−9
−12
G = –1
G = –2
G = –5
G = –10
−15
−18
−18
1M
10M
100M
1G
1
10
Frequency (Hz)
VO = 0.1 VPP
RF = 0 Ω at G = 1
See Figure 55
VO = 0.1 VPP
9
3
6
0
3
−3
0
−3
−9
VO = 0.5 VPP
VO = 1 VPP
VO = 2 VPP
VO = 4 VPP
−15
−12
−18
1
10
100
500
1
10
Frequency (MHz)
G=2
See Figure 55
G = –1
0.3
1.5
0.2
1.0
0.1
0.5
0
0
−0.1
−0.5
−0.2
−1.0
Large Signal ± 1 V
Small Signal ± 100 mV
−1.5
−0.4
−2.0
See Figure 56
0.4
2.0
Large Signal ± 1 V
Small Signal ± 100 mV
0.3
1.5
0.2
1.0
0.1
0.5
0
0
−0.1
−0.5
−0.2
−1.0
−0.3
−1.5
−0.4
−2.0
Time (10 ns/div)
Time (10 ns/div)
See Figure 55
G = –1
Figure 5. Noninverting Pulse Response
10
500
Figure 4. Inverting Large-Signal Frequency Response
Small−Signal Output Voltage (100 mV/div)
2.0
Large−Signal Output Voltage (500 mV/div)
Small−Signal Output Voltage (100 mV/div)
0.4
G=2
100
Frequency (MHz)
Figure 3. Noninverting Large-Signal Frequency Response
−0.3
See Figure 56
−6
−12
VO = 0.5 VPP
VO = 1 VPP
VO = 2 VPP
VO = 4 VPP
−9
500
Figure 2. Inverting Small-Signal Frequency Response
Gain (dB)
Gain (dB)
Figure 1. Noninverting Small-Signal Frequency Response
−6
100
Frequency (MHz)
Large−Signal Output Voltage (500 mV/div)
Normalized Gain (dB)
VS = ±5 V, RF = 402 Ω, RL = 100 Ω, G = 2, and TA = 25°C (unless otherwise noted)
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See Figure 56
Figure 6. Inverting Pulse Response
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±5-V Supply Voltage (continued)
VS = ±5 V, RF = 402 Ω, RL = 100 Ω, G = 2, and TA = 25°C (unless otherwise noted)
−75
2nd−Harmonic
3rd−Harmonic
−75
Harmonic Distortion (dBc)
Harmonic Distortion (dBc)
−70
−80
−85
−90
−95
2nd−Harmonic
3rd−Harmonic
−80
−85
−90
−95
−100
−105
−100
100
2.5
1k
3.0
VO = 2 VPP
See Figure 55
VO = 2 VPP
G = 2 V/V
5.0
5.5
6.0
RL = 200 Ω
See Figure 55
G = 2 V/V
−75
−60
2nd−Harmonic
3rd−Harmonic
2nd−Harmonic
3rd−Harmonic
−80
Harmonic Distortion (dBc)
−65
Harmonic Distortion (dBc)
4.5
Figure 8. 1-MHz Harmonic Distortion vs Supply Voltage
Figure 7. Harmonic Distortion vs Load Resistance
−70
−75
−80
−85
−90
−95
−85
−90
−95
−100
−105
−100
−110
−105
0.1
1
0.1
10
1
VO = 2 VPP
10
Output Voltage (VPP)
Frequency (MHz)
G = 2 V/V
See Figure 55
f = 1 MHz
Figure 9. Harmonic Distortion vs Frequency
RL = 200 Ω
See Figure 55
G = 2 V/V
Figure 10. Harmonic Distortion vs Output Voltage
−70
−70
2nd−Harmonic
3rd−Harmonic
Harmonic Distortion (dBc)
−75
Harmonic Distortion (dBc)
4.0
Supply Voltage (±VS)
Resistance (Ω)
f = 1 MHz
3.5
−80
−85
−90
−95
−100
−105
2nd−Harmonic
3rd−Harmonic
−75
−80
−85
−90
−95
−100
−110
1
10
1
Gain (V/V)
f = 1 MHz
RL = 200 Ω
See Figure 55
10
Gain (|V/V|)
VO = 2 VPP
Figure 11. Harmonic Distortion vs Noninverting Gain
f = 1 MHz
RL = 200 Ω
See Figure 56
VO = 2 VPP
Figure 12. Harmonic Distortion vs Inverting Gain
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±5-V Supply Voltage (continued)
VS = ±5 V, RF = 402 Ω, RL = 100 Ω, G = 2, and TA = 25°C (unless otherwise noted)
50
Voltage Noise (2.5 nV/√HZ)
Current Noise (1.7 pA/√HZ)
45
Intercept Point (+dBm)
Voltage Noise (nV/√Hz)
Current Noise (pA/√Hz)
100
10
40
35
30
25
20
15
1
10
100
1k
10k
100k
1M
0
10M
5
10
15
20
25
30
Frequency (MHz)
Frequency (Hz)
See Figure 48
Figure 14. Two-Tone, 3rd-Order Intermodulation Intercept
Figure 13. Input Voltage and Current Noise
Normalized Gain to Capacitive Load (dB)
10
1
1
10
100
8
7
6
5
4
3
2
1
0
CL = 10 pF
CL = 22 pF
CL = 47 pF
CL = 100 pF
−1
−2
−3
1000
1
10
Capacitive Load (pF)
0-dB peaking targeted
Figure 16. Frequency Response vs Capacitive Load
90
80
80
70
70
60
−40
50
−60
40
−80
30
−100
20
−120
10
−140
0
−160
Open−Loop Gain (dB)
Common−Mode Rejection Ratio (dB)
Power−Supply Rejection Ratio (dB)
400
See Figure 49
Figure 15. Recommended RS vs Capacitive Load
60
50
40
30
20
CMRR
+PSRR
–PSRR
10
0
1k
10k
100k
1M
10M
100M
−10
100
Frequency (Hz)
Figure 17. CMRR and PSRR vs Frequency
12
100
Frequency (MHz)
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0
20 log (AOL)
∠ AOL
−20
Open−Loop Phase (°)
RS (Ω)
100
−180
1k
10k
100k
1M
Frequency (Hz)
10M
100M
1G
Figure 18. Open-Loop Gain and Phase
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±5-V Supply Voltage (continued)
VS = ±5 V, RF = 402 Ω, RL = 100 Ω, G = 2, and TA = 25°C (unless otherwise noted)
5
4
10
1-W Internal
Output Current
Power Limit
Limit
Output Impedance (Ω)
Output Voltage (V)
3
2
1
0
−1
−2
1
0.1
−3
Output Current
Limit
−5
−150
1-W Internal
RL = 25 Ω
−100
RL = 50 Ω
−50
RL = 100 Ω
0
50
Power Limit
100
1k
10k
100k
2
2
1
0
0
−2
−1
−4
−2
−6
−3
−8
−4
Output Voltage (1 V/div)
4
Input Voltage (1 V/div)
3
5
5
4
4
3
3
2
0
0
−1
Output
−2
−3
−4
−4
−5
−5
Time (40 ns/div)
See Figure 55
G = 2 V/V
0.20
1.0
0.40
dG Negative Video
dG Positive Video
dP Negative Video
dP Positive Video
See Figure 56
Figure 22. Inverting Overdrive Recovery
20
10× Input Offset Current (IOS)
Input Offset Voltage (VOS)
Input Bias current (IB)
0.32
0.28
0.12
0.24
0.10
0.20
0.08
0.16
0.06
0.12
0.04
0.08
0.02
0.04
0
0
2
3
4
Input Offset Voltage (mV)
0.36
Differential Phase (°)
Differential Gain (%)
−2
−3
Figure 21. Noninverting Overdrive Recovery
1
1
−1
Time (40 ns/div)
G = 2 V/V
2
Input
1
Input Voltage (1 V/div)
Figure 20. Closed-Loop Output Impedance vs Frequency
6
0.14
100M
Figure 19. Output Voltage and Current Limitations
4
0.16
10M
Frequency (Hz)
Input
Output
0.18
1M
Output Current (mA)
8
Output Voltage (2 V/div)
0.01
150
0.5
10
0
0
−10
−0.5
−1.0
−50
−25
0
25
50
75
100
Input Bias and Offset Current (µV)
−4
−20
125
Ambient Temperature (°C)
Video Loads
G = 2 V/V
Figure 23. Composite Video dG/dP
Figure 24. Typical DC Drift Over Temperature
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±5-V Supply Voltage (continued)
VS = ±5 V, RF = 402 Ω, RL = 100 Ω, G = 2, and TA = 25°C (unless otherwise noted)
125
12
6
–VIN
+VIN
–VOUT
+VOUT
9
100
75
6
50
3
Voltage Range (V)
5
Supply Current (mA)
Output Current (mA)
Supply Current
Source Output Current
Sink Output Current
4
3
2
1
−50
−25
0
25
50
75
0
0
125
25
100
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
Supply Voltage (±VS )
Ambient Temperature (°C)
Figure 26. Common-Mode Input Range and Output Swing
vs Supply Voltage
Figure 25. Supply and Output Current vs Temperature
10M
2500
Count
100k
1500
1000
10k
500
Common-Mode Input Impedance
Differential Input Impedance
0
−730
−660
−580
−510
−440
−370
−290
−220
−150
−70
0
70
150
220
290
370
440
510
580
660
730
Input Impedance (Ω)
2000
1M
1k
100
1k
10k
100k
1M
10M
100M
Frequency (Hz)
Input Offset Voltage (µV)
Mean = –30 µV
Total count = 6115
Standard deviation = 80 µV
Figure 27. Common-Mode and Differential Input
Impedance
Figure 28. Typical Input Offset Voltage Distribution
2000
1800
1600
Count
1400
1200
1000
800
600
400
200
−380
−342
−304
−266
−228
−190
−152
−114
−76
−38
0
38
76
114
152
190
228
266
304
342
380
0
Input Offset Current (nA)
Mean = 26 nA
Standard deviation = 57 nA
Total count = 6115
Figure 29. Typical Input Offset Current Distribution
14
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7.7.2 5-V Supply Voltage
3
3
0
0
Normalized Gain (dB)
−3
−6
−9
−12
G=1
G=2
G=5
G = 10
−15
−3
−6
−9
−12
G = –1
G = –2
G = –5
G = –10
−15
−18
−18
1M
10M
100M
1G
1
10
Frequency (Hz)
VO = 0.1 VPP
See Figure 57
VO = 0.1 VPP
9
3
6
0
3
−3
0
−3
−9
VO = 0.5 VPP
VO = 1 VPP
VO = 2 VPP
VO = 4 VPP
−15
−12
−18
1
10
100
600
1
10
Frequency (MHz)
G = 2 V/V
See Figure 57
G = –1
500
2.8
4.0
2.7
3.5
2.6
3.0
2.5
2.5
2.4
2.0
2.3
1.5
Large Signal ± 1 V
Small Signal ± 100 mV
1.0
2.1
0.5
See Figure 58
Figure 33. Inverting Large-Signal Frequency Response
Small−Signal Output Voltage (100 mV/div)
4.5
Large−Signal Output Voltage (500 mV/div)
Small−Signal Output Voltage (100 mV/div)
2.9
2.9
4.5
Large Signal ± 1 V
Small Signal ± 100 mV
2.8
4.0
2.7
3.5
2.6
3.0
2.5
2.5
2.4
2.0
2.3
1.5
2.2
1.0
2.1
0.5
Time (10 ns/div)
G=2
100
Frequency (MHz)
Figure 32. Noninverting Large-Signal Frequency Response
2.2
See Figure 58
−6
−12
VO = 0.5 VPP
VO = 1 VPP
VO = 2 VPP
VO = 4 VPP
−9
500
Figure 31. Inverting Small-Signal Frequency Response
Gain (dB)
Normalized Gain (dB)
Figure 30. Noninverting Small-Signal Frequency Response
−6
100
Frequency (MHz)
Large−Signal Output Voltage (500 mV/div)
Normalized Gain (dB)
VS = 5 V, RF = 402 Ω, RL = 100 Ω, G = 2, and TA = 25°C (unless otherwise noted)
Time (10 ns/div)
See Figure 57
G = –1
Figure 34. Noninverting Pulse Response
See Figure 58
Figure 35. Inverting Pulse Response
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5-V Supply Voltage (continued)
VS = 5 V, RF = 402 Ω, RL = 100 Ω, G = 2, and TA = 25°C (unless otherwise noted)
−60
2nd−Harmonic
3rd−Harmonic
2nd−Harmonic
3rd−Harmonic
−80
Harmonic Distortion (dBc)
Harmonic Distortion (dBc)
−75
−85
−90
−95
−100
−105
100
−70
−80
−90
−100
−110
0.1
1k
1
G = 2 V/V
f = 1 MHz
See Figure 57
VO = 2 VPP
G = 2 V/V
Figure 36. Harmonic Distortion vs Load Resistance
2nd−Harmonic
3rd−Harmonic
Harmonic Distortion (dBc)
−80
−90
−100
−110
−70
−80
−90
−100
−110
0.1
1
1
10
10
Gain (V/V)
Output Voltage Swing (VPP)
f = 1 MHz
RL = 200 Ω
G = 2 V/V
f = 1 MHz
VO = 2 VPP
RL = 200 Ω
VO = 2 VPP
Figure 39. Harmonic Distortion vs Noninverting Gain
Figure 38. Harmonic Distortion vs Output Voltage
−70
40
2nd−Harmonic
3rd−Harmonic
−75
Intercept Point (+dBm)
Harmonic Distortion (dBc)
VO = 2 VPP
−60
2nd−Harmonic
3rd−Harmonic
Harmonic Distortion (dBc)
RL = 200 Ω
See Figure 57
Figure 37. Harmonic Distortion vs Frequency
−70
−80
−85
−90
35
30
25
20
−95
−100
15
1
10
0
Gain (|V/V|)
f = 1 MHz
RL = 200 Ω
5
10
15
20
25
30
Frequency (MHz)
VO = 2 VPP
Figure 40. Harmonic Distortion vs Inverting Gain
16
10
Frequency (MHz)
Resistance (Ω)
See Figure 50
Figure 41. Two-Tone, 3rd-Order Intermodulation Intercept
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5-V Supply Voltage (continued)
VS = 5 V, RF = 402 Ω, RL = 100 Ω, G = 2, and TA = 25°C (unless otherwise noted)
Normalized Gain to Capacitive Load (dB)
10
1
1
10
100
8
7
6
5
4
3
2
1
0
CL = 10 pF
CL = 22 pF
CL = 47 pF
CL = 100 pF
−1
−2
−3
1000
1
10
Capacitive Load (pF)
0-dB peaking targeted
10
0.5
5
0
0
−0.5
−5
−1.0
−10
−25
0
25
50
75
100
125
12
Supply Current
Source Output Current
Sink Output Current
Output Current (mA)
10× Input Offset Current (IOS)
Input Offset Voltage (VOS)
Input Bias current (IB)
Input Bias and Offset Current (µV)
Input Offset Voltage (mV)
Figure 43. Frequency Response vs Capacitive Load
15
1.5
−1.5
−50
300
See Figure 51
Figure 42. Recommended RS vs Capacitive Load
1.0
100
Frequency (MHz)
100
9
75
6
50
3
25
−15
125
−50
−25
0
25
50
75
100
Supply Current (mA)
RS (Ω)
100
0
125
Ambient Temperature ( C)
Ambient Temperature (°C)
Figure 45. Supply and Output Current vs Temperature
Figure 44. Typical DC Drift Over Temperature
3500
2000
1800
3000
1400
2000
1200
Count
Count
1600
2500
1500
1000
800
600
1000
400
500
200
0
−1.08
−0.97
−0.86
−0.76
−0.65
−0.54
−0.43
−0.32
−0.22
−0.11
0
0.11
0.22
0.32
0.43
0.54
0.65
0.76
0.86
0.97
1.08
−380
−342
−304
−266
−228
−190
−152
−114
−76
−38
0
38
76
114
152
190
228
266
304
342
380
0
Input Offset Voltage (mV)
Input Offset Current (nA)
Mean = 490 µV
Total count = 6115
Standard deviation = 90 µV
Figure 46. Typical Input Offset Voltage Distribution
Mean = 43 nA
Total count = 6115
Standard deviation = 50 nA
Figure 47. Typical Input Offset Current Distribution
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8 Parameter Measurement Information
PI
+
OPA820
PO
50
200
402
402
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Figure 48. Circuit for ±5-V Two-Tone, 3rd-Order Intermodulation Intercept (Figure 14)
VI
+
RS
OPA820
VO
50
CL
1k
(1)
402
402
Copyright © 2016, Texas Instruments Incorporated
(1)
1 kΩ is optional.
Figure 49. Circuit for ±5-V Frequency Response vs Capacitive Load (Figure 55)
5V
806
0.01 µF
PI
+
OPA820
57.6
PO
806
200 k
402
402
0.01 µF
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Figure 50. Circuit for 5-V Two-Tone, 3rd-Order Intermodulation Intercept (Figure 41)
18
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Parameter Measurement Information (continued)
5V
806
0.01 µF
VI
+
RS
OPA820
57.6
806
VO
CL
1k
(1)
402
402
0.01 µF
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(1)
This resistor is optional.
Figure 51. Circuit for 5-V Frequency Response vs Capacitive Load (Figure 43)
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9 Detailed Description
9.1 Overview
The OPA820 provides an exceptional combination of DC precision, wide bandwidth, and low noise while
consuming 5.6 mA of quiescent current. With excellent performance extending from DC to high frequencies, the
OPA820 can be used in a variety of applications ranging from driving the inputs of high-precision SAR ADCs to
video distributions systems.
9.2 Feature Description
9.2.1 Input and ESD Protection
The OPA820 device is built using a very high-speed complementary bipolar process. The internal junction
breakdown voltages are relatively low for these very small geometry devices. These breakdowns are reflected in
Absolute Maximum Ratings. All device pins are protected with internal ESD-protection diodes to the power
supplies, as shown in Figure 52.
VCC
External
Pin
±VCC
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Figure 52. Internal ESD Protection
These diodes provide moderate protection to input overdrive voltages above the supplies as well. The protection
diodes can typically support 30-mA continuous current. Where higher currents are possible (for example, in
systems with ±15-V supply parts driving into the OPA820 device), add current-limiting series resistors into the
two inputs. Keep these resistor values as low as possible because high values degrade both noise performance
and frequency response. Figure 53 shows an example protection circuit for I/O voltages that may exceed the
supplies.
5V
50-
Source
Power-supply
decoupling not shown.
174
V1
50
+
D1
D2
50
OPA820
VO
±
50
RF
301
RG
301
±5 V
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D1 = D2; IN5911 (or equivalent)
Figure 53. Gain of 2 With Input Protection
20
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Feature Description (continued)
9.2.2 Bandwidth versus Gain
Voltage-feedback op amps exhibit decreasing closed-loop bandwidth as the signal gain is increased. In theory,
this relationship is described by the GBP listed in Specifications. Ideally, dividing GBP by the noninverting signal
gain (also called the noise gain, or NG) predicts the closed-loop bandwidth. In practice, this prediction only holds
true when the phase margin approaches 90°, as it does in high-gain configurations. At low signal gains, most
amplifiers exhibit a more complex response with lower phase margin. The OPA820 device is optimized to give a
maximally-flat, 2nd-order Butterworth response in a gain of 2. In this configuration, the OPA820 device has
approximately 64° of phase margin and shows a typical –3-dB bandwidth of 240 MHz. When the phase margin is
64°, the closed-loop bandwidth is approximately √2 greater than the value predicted by dividing GBP by the
noise gain.
Increasing the gain causes the phase margin to approach 90° and the bandwidth to more closely approach the
predicted value of GBP / NG. At a gain of 10, the 30-MHz bandwidth shown in Electrical Characteristics: VS = ±5
V matches the prediction of the simple formula using the typical GBP of 280 MHz.
9.2.3 Output Drive Capability
The OPA820 device has been optimized to drive the demanding load of a doubly-terminated transmission line.
When a 50-Ω line is driven, a series 50-Ω source resistor leading into the cable and a terminating 50-Ω load
resistor at the end of the cable are used. Under these conditions, the cable impedance seems resistive over a
wide frequency range, and the total effective load on the OPA820 device is 100 Ω in parallel with the resistance
of the feedback network. Specifications lists a ±3.6-V swing into this load—which is then reduced to a ±1.8-V
swing at the termination resistor. The ±75-mA output drive over temperature provides adequate current-drive
margin for this load. Higher voltage swings (and lower distortion) are achievable when driving higher impedance
loads.
A single video load typically appears as a 150-Ω load (using standard 75-Ω cables) to the driving amplifier. The
OPA820 device provides adequate voltage and current drive to support up to three parallel video loads (50-Ω
total load) for an NTSC signal. With only one load, the OPA820 device achieves an exceptionally low 0.01% or
0.03° dG/dP error.
9.2.4 Driving Capacitive Loads
One of the most demanding, and yet very common, load conditions for an op amp is capacitive loading. A highspeed, high open-loop gain amplifier like the OPA820 device can be very susceptible to decreased stability and
closed-loop response peaking when a capacitive load is placed directly on the output pin. In simple terms, the
capacitive load reacts with the open-loop output resistance of the amplifier to introduce an additional pole into the
loop and thereby decrease the phase margin. This issue has become a popular topic of application notes and
articles, and several external solutions to this problem have been suggested. When the primary considerations
are frequency response flatness, pulse response fidelity, distortion, or a combination, the simplest and most
effective solution is to isolate the capacitive load from the feedback loop by inserting a series isolation resistor
between the amplifier output and the capacitive load. This solution does not eliminate the pole from the loop
response, but rather shifts it and adds a zero at a higher frequency. The additional zero acts to cancel the phase
lag from the capacitive load pole, thus increasing the phase margin and improving stability.
Figure 15 (±5 V) and Figure 42 (5 V) show the recommended RS versus capacitive load and the resulting
frequency response at the load. The criterion for setting the recommended resistor is the maximum-bandwidth,
flat-frequency response at the load. Because a passive low-pass filter is now between the output pin and the
load capacitance, the response at the output pin is typically somewhat peaked, and becomes flat after the roll-off
action of the RC network. This response is not a concern in most applications, but can cause clipping if the
desired signal swing at the load is very close to the swing limit of the amplifier. Such clipping most likely to
occurs in pulse response applications where the frequency peaking is manifested as an overshoot in the step
response.
Parasitic capacitive loads greater than 2 pF can begin to degrade the performance of the OPA820 device. Long
printed-circuit board traces, unmatched cables, and connections to multiple devices can easily cause this value
to be exceeded. Always consider this effect carefully, and add the recommended series resistor as close as
possible to the OPA820 output pin (see Layout Guidelines).
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Feature Description (continued)
9.2.5 Distortion Performance
The OPA820 device is capable of delivering an exceptionally-low distortion signal at high frequencies and low
gains. The distortion plots in Typical Characteristics show the typical distortion under a wide variety of conditions.
Most of these plots are limited to 100-dB dynamic range. The OPA820 distortion does not rise above –90 dBc
until either the signal level exceeds 0.9 V, the fundamental frequency exceeds 500 kHz, or both occur. Distortion
in the audio band is less than or equal to –100 dBc.
Generally, until the fundamental signal reaches very high frequencies or powers, the 2nd-harmonic dominates
the distortion with a negligible 3rd-harmonic component. Focusing then on the 2nd-harmonic, increasing the load
impedance improves distortion directly. Remember that the total load includes the feedback network—in the
noninverting configuration this is the sum of RF + RG, whereas in the inverting configuration this is just RF (see
Figure 55). Increasing the output voltage swing directly increases harmonic distortion. Increasing the signal gain
also increases the 2nd-harmonic distortion. Again, a 6-dB increase in gain increases the 2nd and 3rd-harmonic
by 6 dB even with a constant output power and frequency. Finally, the distortion increases as the fundamental
frequency increases because of the roll-off in the loop gain with frequency. Conversely, the distortion improves
going to lower frequencies down to the dominant open-loop pole at approximately 100 kHz. Starting from the
–85-dBc 2nd-harmonic for 2 VPP into 200 Ω, G = 2 distortion at 1 MHz (from Typical Characteristics), the 2ndharmonic distortion does not show any improvement below 100 kHz and then becomes Equation 1.
–100 dB – 20log (1 MHz / 100 kHz) = –105 dBc
(1)
9.2.6 Noise Performance
The OPA820 device complements low harmonic distortion with low input-noise terms. Both the input-referred
voltage noise and the two input-referred current noise terms combine to give a low output noise under a wide
variety of operating conditions. Figure 54 shows the op amp noise analysis model with all the noise terms
included. In this model, all the noise terms are taken to be noise voltage or current density terms in either nV/√Hz
or pA/√Hz.
ENI
OPA820
RS
EO
+
IBN
ERS
RF
4kTRS
RG
4kTRF
IBI
4kT
RG
4kT = 1.6E ± 20J
at 290° K
Copyright © 2016, Texas Instruments Incorporated
Figure 54. Op Amp Noise Analysis Model
The total output spot noise voltage is computed as the square root of the squared contributing terms to the
output noise voltage. This computation is adding all the contributing noise powers at the output by superposition,
then taking the square root to get back to a spot noise voltage. Equation 2 shows the general form for this output
noise voltage using the terms presented in Figure 54.
EO
22
2
ªENI
¬
IBNRS
4kTRS º NG2
¼
IBIRF
2
4kTRFNG
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(2)
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Feature Description (continued)
Dividing this expression by the noise gain (NG = 1 + RF / RG) gives the equivalent input referred spot noise
voltage at the noninverting input, as shown in Equation 3.
2
ENI
EN
IBNRS
2
4kTRS
§ IBIRF ·
¨ NG ¸
©
¹
2
4kTRF
NG
(3)
Evaluating these two equations for the OPA820 circuit shown in Figure 55 gives a total output spot noise voltage
of 6.44 nV/√Hz and an equivalent input spot noise voltage of 3.22 nV/√Hz.
9.2.7 DC Offset Control
The OPA820 device can provide excellent DC-signal accuracy because of high open-loop gain, high commonmode rejection, high power-supply rejection, low input-offset voltage, and low bias-current offset errors. To take
full advantage of this low input-offset voltage, careful attention to input bias-current cancellation is also required.
The high-speed input stage for the OPA820 device has a moderately high input bias current (9 µA typical into the
pins) but with a very close match between the two input currents—typically 100-nA input offset current. The total
output-offset voltage can be considerably reduced by matching the source impedances looking out of the two
inputs. For example, one way to add bias current cancellation to the circuit of Figure 55 is to insert a 175-Ω
series resistor into the noninverting input from the 50-Ω terminating resistor. When the 50-Ω source resistor is
DC-coupled, the source impedance for the noninverting input bias current increases to 200 Ω. Because this value
is now equal to the impedance looking out of the inverting input (RF || RG), the circuit cancels the gains for the
bias currents to the output leaving only the offset current times the feedback resistor as a residual DC error term
at the output. Using a 402-Ω feedback resistor, this output error is now less than ±0.4 µA × 402 Ω = ±160 µV at
25°C.
9.2.8 Thermal Analysis
The OPA820 device does not require heat sinking or airflow in most applications. The maximum desired junction
temperature sets the maximum allowed internal power dissipation as described in this section. Make sure that
the maximum junction temperature does not exceed 150°C.
Use Equation 4 to calculate the operating junction temperature (TJ).
TA + PD × RθJA
(4)
The total internal power dissipation (PD) is the sum of quiescent power (PDQ) and additional power dissipated in
the output stage (PDL) to deliver load power. Quiescent power is the specified no-load supply current times the
total supply voltage across the part. PDL depends on the required output signal and load but, for a grounded
resistive load, is at a maximum when the output is fixed at a voltage equal to ½ of either supply voltage (for equal
bipolar supplies). Under this worst-case condition, use Equation 5 to calculate PDL.
PDL = VS2 / (4 × RL)
where
•
RL includes feedback network loading.
(5)
NOTE
The power in the output stage and not in the load that determines internal power
dissipation.
As a worst-case example, compute the maximum TJ using an OPA820IDBV (SOT23-5 package) in the circuit of
Figure 55 operating at the maximum specified ambient temperature of 85°C.
PD = 10 V (6.4 mA) + 52 / (4 × (100 Ω || 800 Ω)) = 134 mW
Maximum TJ = 85°C + (134 mW × 150°C/W) = 105°C
(6)
(7)
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9.3 Device Functional Modes
9.3.1 Wideband Noninverting Operation
The combination of speed and dynamic range offered by the OPA820 device is easily achieved in a wide variety
of application circuits, providing that simple principles of good design practice are observed. For example, good
power-supply decoupling, as shown in Figure 55, is essential to achieve the lowest-possible harmonic distortion
and smooth frequency response.
Proper PCB layout and careful component selection maximize the performance of the OPA820 device in all
applications, as discussed in the following sections of this data sheet.
Figure 55 shows the gain of 2 configuration used as the basis for most of the typical characteristics. Most of the
curves in Typical Characteristics were characterized using signal sources with a 50-Ω driving impedance and
with measurement equipment presenting 50-Ω load impedance. In Figure 55, the 50-Ω shunt resistor at the VI
terminal matches the source impedance of the test generator while, the 50-Ω series resistor at the VO terminal
provides a matching resistor for the measurement equipment load. Generally, data sheet specifications refer to
the voltage swings at the output pin (VO in Figure 55). The 100-Ω load, combined with the 804-Ω total feedback
network load, presents the OPA820 device with an effective load of approximately 90 Ω in Figure 55.
5V
+VS
+
0.1 µF
50-
2.2 µF
Source
+
VIN
VO
50-
50
Load
OPA820
50
RF
402
RG
402
0.1 µF
+
2.2 µF
±VS
±5 V
Copyright © 2016, Texas Instruments Incorporated
Figure 55. Gain of 2, High-Frequency Application and Characterization Circuit
9.3.2 Wideband Inverting Operation
Operating the OPA820 device as an inverting amplifier has several benefits and is particularly useful when a
matched 50-Ω source and input impedance is required. Figure 56 shows the inverting gain of –1 circuit used as
the basis of the inverting mode curves in Typical Characteristics.
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Device Functional Modes (continued)
5V
+
0.1 µF
+
RT
205
0.01 µF
50-
50
50-
Load
OPA820
RG
402
Source
VO
2.2 µF
RF
402
VI
RM
57.6
0.1 µF
+
2.2 µF
±5 V
Copyright © 2016, Texas Instruments Incorporated
Figure 56. Inverting G = –1 Specifications and Test Circuit
In the inverting case, only the feedback resistor appears as part of the total output load in parallel with the actual
load. For the 100-Ω load used in the curves in Typical Characteristics, this results in a total load of 80 Ω in this
inverting configuration. The gain resistor is set to get the desired gain (in this case 402 Ω for a gain of –1) while
an additional input-matching resistor (RM) can be used to set the total input impedance equal to the source if
desired. In this case, RM is 57.6 Ω in parallel with the 402-Ω gain setting resistor results in a matched input
impedance of 50 Ω. This matching is only required when the input must be matched to a source impedance, as
in the characterization testing done using the circuit of Figure 56.
The OPA820 device offers extremely good DC accuracy as well as low noise and distortion. To take full
advantage of that DC precision, the total DC impedance at each of the input nodes must be matched to get bias
current cancellation. For the circuit of Figure 56, this matching requires the 205-Ω resistor to ground on the
noninverting input. The calculation for this resistor includes a DC-coupled 50-Ω source impedance along with RG
and RM. Although this resistor provides cancellation for the bias current, it must be well decoupled (0.01 µF in
Figure 56) to filter the noise contribution of the resistor and the input current noise.
As the required RG resistor approaches 50 Ω at higher gains, the bandwidth for the circuit in Figure 56 exceeds
the bandwidth at that same gain magnitude for the noninverting circuit of Figure 55 which occurs because of the
lower noise gain for the circuit of Figure 56 when the 50-Ω source impedance is included in the analysis. For
instance, at a signal gain of –10 (RG = 50 Ω, RM = open, RF = 499 Ω) the noise gain for the circuit of Figure 56 is
shown in Equation 8.
1 + 499 Ω / (50 Ω + 50 Ω) = 6
(8)
Equation 8 is a result of adding the 50-Ω source in the noise gain equation which results in a considerably higher
bandwidth than the noninverting gain of 10. Using the 240-MHz gain bandwidth product for the OPA820 device,
an inverting gain of –10 from a 50-Ω source to a 50-Ω RG gives 55-MHz bandwidth, whereas the noninverting
gain of 10 gives 30 MHz.
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Device Functional Modes (continued)
9.3.3 Wideband Single-Supply Operation
Figure 57 shows the AC-coupled, single 5-V supply, gain of 2-V/V circuit configuration used as a basis only for
the 5-V specifications in Specifications. The most important requirement for single-supply operation is to maintain
input and output-signal swings within the useable voltage ranges at both the input and the output. The circuit of
Figure 57 establishes an input midpoint bias using a simple resistive divider from the 5-V supply (two 806-Ω
resistors) to the noninverting input. The input signal is then AC-coupled into this midpoint voltage bias. The input
voltage can swing to within 0.9 V of the negative supply and 0.5 V of the positive supply, giving a 3.6-VPP inputsignal range. The input impedance-matching resistor (57.6 Ω) used in Figure 57 is adjusted to give a 50-Ω input
match when the parallel combination of the biasing divider network is included. The gain resistor (RG) is ACcoupled, giving the circuit a DC gain of 1 which puts the input DC bias voltage (2.5 V) on the output as well. On a
single 5-V supply, the output voltage can swing to within 1.3 V of either supply pin while delivering more than 80mA output current giving 2.4-V output swing into 100 Ω (5.6 dBm maximum at the matched load).
Figure 58 shows the AC-coupled, single 5-V supply, gain of –1-V/V circuit configuration used as a basis only for
the 5-V specifications in Specifications. In this case, the midpoint DC bias on the noninverting input is also
decoupled with an additional 0.01-µF decoupling capacitor which reduces the source impedance at higher
frequencies for the noninverting-input bias-current noise. This 2.5-V bias on the noninverting input pin appears
on the inverting input pin and, because RG is DC blocked by the input capacitor, also appears at the output pin.
The single-supply test circuits of Figure 57 and Figure 58 show 5-V operation. These same circuits can be used
with a single-supply of 5 V to 12 V. Operating on a single 12-V supply, with the absolute-maximum supplyvoltage specification of 13 V, gives adequate design margin for the typical ±5% supply tolerance.
5V
+VS
+
0.1 µF
50-
Source
806
0.01 µF
DIS
VI
+
VO
OPA820
57.6
6.8 µF
100
VS/2
806
RF
402
RG
402
0.01 µF
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Figure 57. AC-Coupled, G = 2 V/V, Single-Supply Specifications and Test Circuit
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Device Functional Modes (continued)
5V
+VS
+
0.1 µF
806
6.8 µF
DIS
+
VO
OPA820
100
VS/2
806
0.01 µF
0.01 µF
RG
402
RF
402
VI
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Figure 58. AC-Coupled, G = –1 V/V, Single-Supply Specifications and Test Circuit
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10 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
10.1 Application Information
10.1.1 Optimizing Resistor Values
Because the OPA820 device is a unity-gain stable, voltage-feedback op amp, a wide range of resistor values can
be used for the feedback and gain-setting resistors. The primary limits on these values are set by dynamic range
(noise and distortion) and parasitic capacitance considerations. Usually, the feedback resistor value is from
200 Ω to 1 kΩ. At less than 200 Ω, the feedback network presents additional output loading which can degrade
the harmonic distortion performance of the OPA820 device. At greater than 1 kΩ, the typical parasitic
capacitance (approximately 0.2 pF) across the feedback resistor can cause unintentional band limiting in the
amplifier response. A direct short is suggested as a feedback for AV = 1 V/V.
A good design practice is to target the parallel combination of RF and RG (see Figure 55) to be less than
approximately 200 Ω. The combined impedance RF || RG interacts with the inverting input capacitance, placing an
additional pole in the feedback network, and thus a zero in the forward response. Assuming a total parasitic of
2 pF on the inverting node, holding RF || RG < 200 Ω keeps this pole above 400 MHz. This constraint implies that
the feedback resistor RF can increase to several kΩ at high gains which is acceptable as long as the pole formed
by RF and any parasitic capacitance appearing in parallel is kept out of the frequency range of interest.
In the inverting configuration, an additional design consideration must be considered. RG becomes the input
resistor and therefore the load impedance to the driving source. If impedance matching is desired, RG can be set
equal to the required termination value. However, at low inverting gains, the resulting feedback resistor value can
present a significant load to the amplifier output. For example, an inverting gain of 2 with a 50-Ω input matching
resistor (RG) requires a 100-Ω feedback resistor, which contributes to output loading in parallel with the external
load. In such a case, increasing both the RF and RG values is preferable, and then achieve the input matching
impedance with a third resistor to ground (see Figure 56). The total input impedance becomes the parallel
combination of RG and the additional shunt resistor.
10.2 Typical Applications
10.2.1 Active Filter Design
Most active filter topologies have exceptional performance using the broad bandwidth and unity-gain stability of
the OPA820 device. Topologies employing capacitive feedback require a unity-gain stable, voltage-feedback op
amp. Sallen-Key filters simply use the op amp as a noninverting gain stage inside an RC network. Either current
feedback or voltage-feedback op amps can be used in Sallen-Key implementations.
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Typical Applications (continued)
C2
160 pF
R3
500
+
OPA820
R4
500
5V
R1
124
R2
517
+
V1
C2
1000 pF
VO
OPA820
C1
100 pF
R1
1.58 k
RF
402
RG
402
R5
158
R2
158
VOUT
OPA820
+
VIN
C1
1000 pF
±5 V
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Figure 59. 5-MHz Butterworth Low-Pass Active
Filter
Figure 60. High-Q 1-MHz Bandpass Filter
10.2.1.1 Design Requirements
The design requirements for the active filters are given in Table 2:
Table 2. Design Requirements
FILTER TYPE
Second order Butterworth, low-pass filter
High-Q, bandpass filter
Q
FILTER CUTOFF FREQUENCY
f-3dB (MHz)
0.707
5
6
10
1
—
DC GAIN (dB)
10.2.1.2 Detailed Design Procedure
10.2.1.2.1 High-Q Bandpass Filter Design Procedure
The transfer function of a high-Q bandpass filter shown in Figure 64 is given by Equation 9.
R R4
S 3
VOUT
R1R4C1
R3
1
VIN
S2 S
R1C1 R2R4R5C1C2
ZO2
R3
R2R4R5C1C2
(9)
(10)
1
R1C1
wO
; 1MHz
fO =
2p
ZO
Q
(11)
(12)
Use Equation 11 and Equation 12, along with the filter specifications in table to find the relationship between ω0,
Q, R1, and C1. Set C1 = 1000 pF, which results in R1= 1.5915 kΩ. The closest E96 standard value resistor value
is 1.58 kΩ.
Notice that the DC load driven by the OPA820 driving the output VOUT = R3 + R4. Select the total load to be 1 kΩ
and R3 = R4, which results in a value of 500 Ω.
To simplify the filter design, set C1 = C2 = 1000 pF.
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Plugging the values of R3, R4, C1, and C2 into Equation 10 and assuming R2 = R5 results in a value of 159.15 Ω.
The closest standard E96 value is 158 Ω.
See Figure 61 for the frequency response of the filter shown in Figure 60.
10.2.1.2.2 Low-Pass Butterworth Filter Design Procedure
The transfer function of a low-pass Butterworth filter shown in Figure 59 is given by Equation 13.
VOUT
K
= 2
VIN
s (R1R2C1C2 ) + s R1C1 + R2C1 + R1C2 (1 - K ) + 1
(
)
where
•
æ
R ö
K = ç1 + F ÷
è RG ø is the low-frequency DC gain
(13)
The values for RF and RG are the standard recommended values in the data sheet.
The cutoff frequency is in Equation 14.
1
w0 =
R
C
( 1 1R2C2 )
(14)
The Q of the filter is given by Equation 15.
Q =
R1R2C1C2
R1C1 + R2C1 + R1C2 (1 - K )
(15)
From Table 1, Q = 0.707 and ω0 = 2π × 5 MHz. To aid in solving this circuit, assume C1 = 100 pF and
R1 = 124 Ω. Plugging these values into Equation 14 and Equation 15 and finding the closest standard value
components results in R2 = 517 Ω and C2 = 160 pF. See Figure 62 for the frequency response of the filter shown
in Figure 59.
9
6
0
−6
−12
−18
−24
−30
−36
−42
−48
−54
−60
−66
−72
6
3
Gain (dB)
Gain (dB)
10.2.1.3 Application Curves
0
-3
-6
100k
1M
10M
100M
-9
10k
100k
1M
Frequency (Hz)
Frequency (Hz)
Figure 61. High-Q 1-MHz Bandpass Filter Frequency
Response
10M
D001
Figure 62. Frequency Response
10.2.2 Buffering High-Performance ADCs
To achieve full performance from a high-dynamic range ADC, take considerable care in the design of the inputamplifier interface circuit. The example circuit in Figure 63 shows a typical AC-coupled interface to a very-high
dynamic-range converter. This AC-coupled example allows the OPA820 device to operate using a signal range
that swings symmetrically around ground (0 V). The 2-VPP swing is then level-shifted through the blocking
capacitor to a midscale reference level, which is created by a well-decoupled resistive divider off the internal
reference voltages of the converter. To have a negligible effect (1 dB) on the rated spurious-free dynamic range
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(SFDR) of the converter, the SFDR of the amplifier must be at least 18 dB greater than the converter. The
OPA820 device has a minimal effect on the rated distortion of the ADS850 device, given the 79-dB SFDR at 2
VPP, 1 MHz of the ADS850 device. The greater than 90-dB (
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