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OPA857
SBOS630D – DECEMBER 2013 – REVISED AUGUST 2016
OPA857 Ultralow-Noise, Wideband, Selectable-Feedback Resistance
Transimpedance Amplifier
1 Features
3 Description
•
•
•
•
The OPA857 is a wideband, fast overdrive recovery,
fast-settling, ultralow-noise transimpedance amplifier
targeted at photodiode monitoring applications. With
selectable feedback resistance, the OPA857
simplifies the design of high-performance optical
systems. Very fast overload recovery time and
internal input protection provide the best combination
to protect the remainder of the signal chain from
overdrive while minimizing recovery time. The two
selectable transimpedance gain configurations allow
high dynamic range and flexibility required in modern
transimpedance amplifier applications. The OPA857
is available in a 3-mm × 3-mm VQFN package.
1
•
•
•
•
•
Internal Midscale Reference Voltage
Pseudo-Differential Output Voltage
Wide Dynamic Range
Closed-Loop Transimpedance Bandwidth:
– 125 MHz (5-kΩ Transimpedance Gain,
1.5-pF External Parasitic Capacitance)
– 105 MHz (20-kΩ Transimpedance Gain,
1.5-pF External Parasitic Capacitance)
Ultralow Input-Referred Current Noise
(Brickwall Filter BW = 135 MHz):
15 nARMS (20-kΩ Transimpedance)
Very Fast Overload Recovery Time: < 25 ns
Internal Input Protection Diode
Power Supply:
– Voltage: 2.7 V to 3.6 V
– Current: 23.4 mA
Extended Temperature Range: –40°C to +85°C
The device is characterized for operation over the full
industrial temperature range from –40°C to +85°C.
Device Information(1)
DEVICE NAME
OPA857
PACKAGE
VQFN (16)
BODY SIZE
3 mm × 3 mm
(1) For all available packages, see the package option addendum
at the end of the datasheet.
2 Applications
•
•
•
•
Photodiode Monitoring
High-Speed I/V Conversion
Optical Amplifiers
CAT-Scanner Front-Ends
Functional Block Diagram
+VS
CTRL
GND
TIA
RF2
RF1
25 W
OUT
25 W
OUTN
IN
Test_SD
TEST
CLAMP
1:1
2 kW
Clamping
Circuit
REF
Test_IN
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
OPA857
SBOS630D – DECEMBER 2013 – REVISED AUGUST 2016
www.ti.com
Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
4
5
6.1
6.2
6.3
6.4
6.5
6.6
5
5
5
5
6
8
Absolute Maximum Ratings .....................................
ESD Ratings..............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics...........................................
Typical Characteristics ..............................................
Detailed Description ............................................ 14
7.1
7.2
7.3
7.4
Overview .................................................................
Functional Block Diagram .......................................
Feature Description.................................................
Device Functional Modes........................................
14
14
15
17
8
Application and Implementation ........................ 18
8.1 Application Information............................................ 18
8.2 Typical Application ................................................. 18
9 Power-Supply Recommendations...................... 23
10 Layout................................................................... 23
10.1 Layout Guidelines ................................................. 23
10.2 Layout Example .................................................... 24
11 Device and Documentation Support ................. 25
11.1
11.2
11.3
11.4
11.5
11.6
11.7
Device Support......................................................
Documentation Support ........................................
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
25
25
25
25
25
26
26
12 Mechanical, Packaging, and Orderable
Information ........................................................... 26
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision C (April 2014) to Revision D
Page
•
Changed Features bullets ...................................................................................................................................................... 1
•
Changed "Precision" to "High-Speed" in 2nd Applications bullet ........................................................................................... 1
•
Changed pin configuration drawing and pin functions table................................................................................................... 4
•
Changed Handling Ratings table to ESD Ratings and moved storage temperature to Absolute Maximum Ratings ............ 5
•
Changed Supply Input Voltage min value from 3.0 to 2.7 in Recommended Operating Conditions ..................................... 5
•
Changed VOUT unit from VP to VPP in Electrical Charateristics condition line ...................................................................... 6
•
Changed all AC Performance values except Closed-Loop Output Impedance ..................................................................... 6
•
Changed test conditions for Equivalent Input-Referred Current Noise parameter in Electrical Characteristics .................... 6
•
Deleted Operating Voltage from Electrical Characteristics; already in Recommended Operating Conditions ...................... 7
•
Deleted Temperature Range from Electrical Characteristics; already in Recommended Operating Conditions ................... 7
•
Changed all plots in Typical Characteristics section except figures 17, 35, and 36 ............................................................. 8
•
Changed 4.5 kΩ and 18.2 kΩ to 5 kΩ and 20 kΩ, respectively, in first paragrpah of Overview section.............................. 14
•
Changed text in Transimpedance Amplifier (TIA) Block section .......................................................................................... 15
•
Changed text in Reference Voltage (REF) Block section..................................................................................................... 15
•
Changed text in Integrated Test Structure (TEST) Block section ........................................................................................ 15
•
Changed Table 2 values....................................................................................................................................................... 17
•
Added Test Mode section..................................................................................................................................................... 17
•
Changed Application Information section ............................................................................................................................. 18
•
Changed Figure 50; updated pin names .............................................................................................................................. 24
Changes from Revision B (January 2014) to Revision C
Page
•
Changed document format to meet new data sheet standards; added Handling Ratings and Device and
Documentation Support sections, and moved existing sections ............................................................................................ 1
•
Changed OUTN to OUT in Output Voltage Swing parameter test conditions ....................................................................... 6
•
Changed Functional Block Diagram .................................................................................................................................... 14
2
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SBOS630D – DECEMBER 2013 – REVISED AUGUST 2016
Changes from Revision A (December 2013) to Revision B
Page
•
Changed document status to Production Data....................................................................................................................... 1
•
Changed transimpedance value in both sub-bullets of Bandwidth Features bullet................................................................ 1
•
Changed Extended Temperature Range Features bullet to a range of –40°C to +85°C....................................................... 1
•
Changed first sentence of Description section: added "targeted at photodiode monitoring applications" ............................. 1
•
Changed temperature range to –40°C to +85°C in last sentence of Description section ...................................................... 1
•
Changed front-page graphic................................................................................................................................................... 1
•
Added pages 2 through end of document .............................................................................................................................. 4
Changes from Original (December 2013) to Revision A
Page
•
Changed document status to Product Preview ...................................................................................................................... 1
•
Deleted all pages past page 1................................................................................................................................................ 1
•
Deleted fourth Applications bullet ........................................................................................................................................... 1
•
Changed first sentence of Description section ....................................................................................................................... 1
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OPA857
SBOS630D – DECEMBER 2013 – REVISED AUGUST 2016
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5 Pin Configuration and Functions
NC
IN
Test_IN
Test_SD
15
14
13
8
4
OUT
GND
Pad
7
3
GND
GND
Thermal
6
2
GND
CTRL
5
1
OUTN
GND
16
RGT Package
16-Pin VQFN
Top View
12
GND
11
+VS
10
+VS
9
+VS
Not to scale
Pin Functions
PIN
NAME
NO.
I/O
DESCRIPTION
CTRL
2
I
Control pin for transimpedance gain.
GND, logic 0 = 5-kΩ internal resistance; +VS, logic 1 = 20-kΩ internal resistance.
GND
1, 3, 4, 6, 7, 12
I
Ground
Input
IN
15
I
NC
16
—
Not connected
OUT
8
O
Signal output
OUTN
5
O
Common-mode voltage output reference
Test_IN
14
I
Test mode input. Connect to +VS during normal operation.
Test_SD
13
I
Test mode enable. Connect to GND for normal operation, and connect to +VS to enable test mode.
9, 10, 11
I
Supply voltage
+VS
4
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SBOS630D – DECEMBER 2013 – REVISED AUGUST 2016
6 Specifications
6.1 Absolute Maximum Ratings (1)
over operating free-air temperature range (unless otherwise noted)
MIN
MAX
Supply voltage, VS– to VS+
Voltage
Input and output voltage, VIN, VOUT pins
Current
(VS–) – 0.7
(VS+) + 0.7
Differential input voltage
1
Output current
50
Input current, VIN pin
10
Continuous power dissipation
(1)
V
mA
See Thermal Information table
Maximum junction, TJ
150
Maximum junction, TJ (continuous operation, long-term reliability)
Temperature
UNIT
3.8
140
Operating free-air, TA
–40
85
Storage, Tstg
–65
150
°C
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
6.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1)
±2000
Charged-device model (CDM), per JEDEC specification JESD22-C101 (2)
±500
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
NOM
MAX
VSS Supply input voltage
2.7
3.3
3.6
V
TJ
–40
85
°C
Operating junction temperature
UNIT
6.4 Thermal Information
OPA857
THERMAL METRIC
(1)
RGT (VQFN)
UNIT
16 PINS
RθJA
Junction-to-ambient thermal resistance
67.1
°C/W
RθJC(top)
Junction-to-case(top) thermal resistance
91.6
°C/W
RθJB
Junction-to-board thermal resistance
41.6
°C/W
ψJT
Junction-to-top characterization parameter
7.1
°C/W
ψJB
Junction-to-board characterization parameter
41.7
°C/W
RθJC(bot)
Junction-to-case(bottom) thermal resistance
23.1
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report (SPRA953).
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OPA857
SBOS630D – DECEMBER 2013 – REVISED AUGUST 2016
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6.5 Electrical Characteristics
at TA = 25°C (1), VS = 3.3 V, VS+ – VS– = 3.3 V, CSource = 1.5 pF, VOUT = 0.5 VPP (differential), RL = 500-Ω differential, singleended input, pseudo-differential output, and input and output referenced to midsupply (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
TEST
LEVEL (2)
AC PERFORMANCE
Small-signal bandwidth
SR
Slew rate (differential)
MHz
C
125
MHz
C
VOUT = 1-V step
215
V/μs
C
B
8
ns
VOUT = 0.5-V step, CTRL = 1, TA = 25°C
8
ns
B
VOUT = 0.5-V step, CTRL = 0
600
ns
C
VOUT = 0.5-V step, CTRL = 1
700
ns
C
VOUT = 0.5 VPP, f = 10 MHz, RF = 5 kΩ, TA = 25°C
–80
dBc
C
VOUT = 0.5 VPP, f = 10 MHz, RF = 20 kΩ, TA = 25°C
–83
dBc
C
VOUT = 0.5 VPP, f = 10 MHz, RF = 5 kΩ, TA = 25°C
–88
dBc
C
VOUT = 0.5 VPP, f = 10 MHz, RF = 20 kΩ, TA = 25°C
–83
dBc
C
CTRL = 0, using 135-MHz brickwall filter
25
nARMS
C
CTRL = 1, using 135-MHz brickwall filter
15
nARMS
C
Overdrive recovery time
IIN = 2x overload, CTRL = 1, settling to 1% of final
value
25
ns
B
Closed-loop output
impedance
f = 1 MHz (differential)
50
Ω
C
CTRL = 1 into 500 Ω (3) (4)
18.2
kΩ
C
CTRL = 0 into 500 Ω (3) (4)
4.5
kΩ
C
tS
Settling time to 0.001%
Second-harmonic distortion
HD3
105
CTRL = 0, TA = –40°C to +85°C
VOUT = 0.5-V step, CTRL = 0, TA = 25°C
Settling time to 1%
HD2
CTRL = 1, TA = –40°C to +85°C
Third-harmonic distortion
Equivalent input-referred
current noise
DC PERFORMANCE
Transimpedance gain
Transimpedance gain error
VOO
±1%
±15%
±1
±5
mV
TA = –40°C to +85°C (5)
±6
mV
B
Output offset voltage drift
TA = –40°C to +85°C (5)
±15
μV/°C
C
Common-mode voltage
range
TA = 25°C, OUTN
1.88
V
A
pF
C
1.9
V
A
1.9
V
B
+5
mA
C
–20
mA
C
Output offset voltage
VICR
TA = 25°C, RF = 20 kΩ and RF = 5 kΩ
TA = +25°C
1.78
1.83
A
A
INPUT
Input pin capacitance
2
OUTPUT
Output voltage swing
Output current drive
(for linear operation)
(1)
(2)
(3)
(4)
(5)
6
OUT, TA = 25°C
0.6
TA = –40°C to +85°C (5)
OUT, differential 50-Ω between OUT and OUTN
Junction temperature = ambient for 70°C specifications.
Test levels: (A) 100% tested at 25°C. Overtemperature limits set by characterization and simulation. (B) Limits set by characterization
and simulation. (C) Typical value only for information.
See the Application and Implementation section for details on loading and effective transimpedance gain.
Note that the effective transimpedance gain is reduced to 18.2 kΩ and 4.5 kΩ, respectively, with a 500-Ω load resulting from the internal
series resistance on OUT and OUTN.
Junction temperature = ambient at low temperature; junction temperature = ambient + 3.5°C for overtemperature specifications.
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Electrical Characteristics (continued)
at TA = 25°C(1), VS = 3.3 V, VS+ – VS– = 3.3 V, CSource = 1.5 pF, VOUT = 0.5 VPP (differential), RL = 500-Ω differential, singleended input, pseudo-differential output, and input and output referenced to midsupply (unless otherwise noted)
MIN
TYP
MAX
UNIT
TEST
LEVEL (2)
CTRL = 0, TA = 25°C
20.5
23.4
26.3
mA
A
CTRL = 0, TA = –40°C to +85°C (5)
20.0
26.8
mA
B
CTRL = 1, TA = 25°C
20.5
26.3
mA
A
CTRL = 1, TA = –40°C to +85°C (5)
20.0
26.8
mA
B
PARAMETER
TEST CONDITIONS
POWER SUPPLY
Quiescent operating current
PSRR
Power-supply rejection ratio
23.4
At dc, TA = 25°C
70
80
dB
A
f = 10 MHz, TA = –40°C to +85°C (5)
15
18
dB
B
LOGIC LEVEL (CTRL)
VIH
High-level input voltage
VIL
Low-level input voltage
2
V
A
0.8
V
A
High-level control pin input
bias current
1
µA
A
Low-level control pin input
bias current
1
µA
A
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6.6 Typical Characteristics
3
3
2
0
Normalized Gain (dB:)
Normalized Gain (dB:)
At TA = 25°C, CS = 1.5 pF, and RL = 500-Ω differential between OUT and OUTN (unless otherwise noted).
1
0
-1
-2
100 :
500 :
1 k:
5 k:
-3
-3
-6
-9
-12
-40qC
25qC
85qC
-15
-4
-18
1M
10M
Frequency (Hz)
100M
1M
10M
Frequency (Hz)
D001
TZ Gain = 20 kΩ
3
2
0
Normalized Gain (dB:)
Normalized Gain (dB:)
3
1
0
-1
-2
100 :
500 :
1 k:
5 k:
-3
-6
-9
-12
-40qC
25qC
85qC
-15
-18
1M
10M
Frequency (Hz)
1M
100M
D003
TZ Gain = 5 kΩ
10M
Frequency (Hz)
100M
500M
D004
TZ Gain = 5 kΩ
Figure 3. Frequency Response vs Load Resistance
Figure 4. Frequency Response vs Temperature
0.25
0.25
0
0
Output Voltage (V)
Output Voltage (V)
D002
Figure 2. Frequency Response vs Temperature
-4
-0.25
-0.5
-0.75
-1
-0.25
-0.5
-0.75
-1
-1.25
-1.25
Time (50 ns/div)
Time (50 ns/div)
D005
TZ Gain = 20 kΩ
D006
TZ Gain = 5 kΩ
Figure 5. 1-VPP Pulse Response
8
500M
TZ Gain = 20 kΩ
Figure 1. Frequency Response vs Load Resistance
-3
100M
Figure 6. 1-VPP Pulse Response
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Typical Characteristics (continued)
At TA = 25°C, CS = 1.5 pF, and RL = 500-Ω differential between OUT and OUTN (unless otherwise noted).
30
Input-Referred Current Noise (nARMS)
Input-Referred Current Noise (nARMS)
30
25
20
15
5-k: Gain
20-k: Gain
10
-50
-25
0
25
50
Temperature (qC)
75
25
20
15
5-k: Gain
20-k: Gain
10
2.5
100
Figure 7. RMS Input-Referred Current Noise
vs Temperature
Input-Referred Current Noise (nARMS)
60
40
20
20-k: Gain
D008
60
40
20
5-k: Gain
0
0
5
10
15
Source Capacitance (pF)
20
25
0
5
D009
Figure 9. RMS Input-Referred
Current Noise vs Capacitance
10
15
Source Capacitance (pF)
20
25
D010
Figure 10. Gain RMS Input-Referred
Current Noise vs Input Capacitance
3
3
2
2
Normalized Gain (dB:)
Normalized Gain (dB:)
3.75
80
0
1
0
-1
-3
3.5
100
80
-2
3
3.25
Supply Voltage (V)
Figure 8. RMS Input-Referred Current Noise
vs Supply Voltage
100
Input-Referred Current Noise (nARMS)
2.75
D007
Parasitic
1.5 pF
4.7 pF
10 pF
22 pF
1
0
-1
-2
-3
-4
Parasitic
1.5 pF
4.7 pF
10 pF
22 pF
-4
1M
10M
Frequency (Hz)
100M
1M
D011
TZ Gain = 20 kΩ
10M
Frequency (Hz)
100M
D012
TZ Gain = 5 kΩ
Figure 11. Gain Frequency Response vs
Input Capacitance
Figure 12. Gain Frequency Response vs
Input Capacitance
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Typical Characteristics (continued)
2
2
1.6
1.6
1.2
1.2
Output Voltage (V)
Output Voltage (V)
At TA = 25°C, CS = 1.5 pF, and RL = 500-Ω differential between OUT and OUTN (unless otherwise noted).
0.8
0.4
0
-0.4
0.8
0.4
0
-0.4
Measured Output
Ideal Output
-0.8
Measured Output
Ideal Output
-0.8
Time (100 ns/div)
Time (100 ns/div)
D013
D014
TZ Gain = 20 kΩ
TZ Gain = 5 kΩ
Figure 14. 2x Overdrive Recovery
0
±10
±10
±20
±20
±30
±30
PSRR (dB)
PSRR (dB)
Figure 13. 2x Overdrive Recovery
0
±40
±50
±60
-40ƒC
+0ƒC
+25ƒC
+70ƒC
+105ƒC
±70
±80
±90
±100
0.001
0.01
0.1
1
10
100
±50
±60
-40ƒC
+0ƒC
+25ƒC
+70ƒC
+105ƒC
±70
±80
±90
±100
0.001
1000
Frequency (MHz)
±40
0.01
TZ Gain = 20-kΩ
10
100
1000
C015
Figure 16. Power-Supply Rejection Ratio
vs Frequency
-50
Source
Sink
HD2
HD3
-55
Harmonic Distortion (dBc)
20
Output Current (mA)
1
TZ Gain = 5 kΩ
Figure 15. Power-Supply Rejection Ratio
vs Frequency
25
0.1
Frequency (MHz)
C014
15
10
5
-60
-65
-70
-75
-80
-85
0
-50
-25
0
25
50
75
100
125
Temperature (ƒC)
C016
-90
1M
10M
Frequency (Hz)
100M
D018
TZ Gain = 5 kΩ, RLOAD = 500 Ω
Figure 17. Output Current vs Temperature
10
Figure 18. Harmonic Distortion vs Frequency
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Typical Characteristics (continued)
At TA = 25°C, CS = 1.5 pF, and RL = 500-Ω differential between OUT and OUTN (unless otherwise noted).
-50
-50
HD2
HD3
HD2
HD3
-55
Harmonic Distortion (dBc)
Harmonic Distortion (dBc)
-55
-60
-65
-70
-75
-80
-85
-60
-65
-70
-75
-80
-85
-90
1M
-90
10M
Frequency (Hz)
100M
0
TZ Gain = 20 kΩ, RLOAD = 500 Ω
Figure 19. Harmonic Distortion vs Frequency
1
1.25
D020
Figure 20. Harmonic Distortion vs Output Voltage
-50
HD2
HD3
HD2
HD3
-55
Harmonic Distortion (dBc)
-55
-60
-65
-70
-75
-80
-85
-60
-65
-70
-75
-80
-85
-90
-90
0
0.25
0.5
0.75
Output Voltage (V)
1
1.25
0
1000
D021
TZ Gain = 20 kΩ, RLOAD = 500 Ω, f = 50 MHz
2000
3000
4000
Output Load (:)
5000
6000
D022
TZ Gain = 5 kΩ, f = 50 MHz
Figure 21. Harmonic Distortion vs Output Voltage
Figure 22. Harmonic Distortion vs RLOAD
-50
-50
HD2
HD3
HD2
HD3
-55
Harmonic Distortion (dBc)
-55
Harmonic Distortion (dBc)
0.5
0.75
Output Voltage (V)
TZ Gain = 5 kΩ, RLOAD = 500 Ω, f = 50 MHz
-50
Harmonic Distortion (dBc)
0.25
D019
-60
-65
-70
-75
-80
-85
-60
-65
-70
-75
-80
-85
-90
0
1000
2000
3000
4000
Output Load (:)
5000
6000
-90
2.5
D023
TZ Gain = 20 kΩ, f = 50 MHz
2.7
2.9
3.1
3.3
Supply Voltage (V)
3.5
3.7
D024
TZ Gain = 5 kΩ, TA = 25°C, RLOAD = 500 Ω, f = 50 MHz
Figure 23. Harmonic Distortion vs RLOAD
Figure 24. Harmonic Distortion vs Supply Voltage
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Typical Characteristics (continued)
At TA = 25°C, CS = 1.5 pF, and RL = 500-Ω differential between OUT and OUTN (unless otherwise noted).
100
-50
Harmonic Distortion (dBc)
-55
Input Referred Current Noise (pA/—Hz)
HD2
HD3
-60
-65
-70
-75
-80
-85
-90
2.5
2.7
2.9
3.1
3.3
Supply Voltage (V)
3.5
No Cap
1.5 pF
4.7 pF
10 pF
22 pF
10
1
0.1
1M
3.7
10M
D025
TZ Gain = 20 kΩ, TA = 25°C, RLOAD = 500 Ω, f = 50 MHz
1G
D026
TZ Gain = 5 kΩ
Figure 25. Harmonic Distortion vs Supply Voltage
Figure 26. Input-Referred Current Noise Density vs
Frequency
100
2500
No Cap
1.5 pF
4.7 pF
10 pF
22 pF
10
2000
Count
1500
1000
1
500
0.1
1M
0
10M
100M
Frequency (Hz)
27.2
Input Referred Current Noise (pA/—Hz)
100M
Frequency (Hz)
1G
D027
Quiescent Current (mA)
C027
TZ Gain = 20 kΩ
TZ Gain = 20 kΩ
Figure 28. IQ Histogram
Figure 27. Input-Referred Current Noise Density vs
Frequency
2500
23.6
23.5
Quiescent Current (mA)
Count
2000
1500
1000
500
23.4
23.3
23.2
23.1
0
27.4
23
Quiescent Current (mA)
5 kΩ
20 kΩ
22.9
–50
–25
0
25
50
75
100
Temperature (°C)
125
C029
C028
TZ Gain = 5 kΩ
Figure 29. IQ Histogram
12
Figure 30. Quiescent Current vs Temperature
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Typical Characteristics (continued)
At TA = 25°C, CS = 1.5 pF, and RL = 500-Ω differential between OUT and OUTN (unless otherwise noted).
26
3000
2500
22
2000
20
Count
18
16
1500
1000
14
500
12
5 kΩ
20 kΩ
10
2
2.2
2.4
2.6
2.8
3
3.2
3.4
Supply Voltage (V)
0
5
Quiescent Current (mA)
24
3.6
Output Offset Voltage (mV)
C030
C031
TZ Gain = 5 kΩ
Figure 32. Differential VOSO Histogram
Figure 31. Quiescent Current vs Supply Voltage
3500
0.6
Output Offset Voltage (mV)
3000
Count
2500
2000
1500
1000
500
0.4
Same Characteristic Unit
0.2
0
–0.2
–0.4
–0.6
–50
6
0
5 kΩ
20 kΩ
–25
0
25
50
75
100
Temperature (°C)
Output Offset Voltage (mV)
125
C033
C032
TZ Gain = 20 kΩ
Figure 33. Differential VOSO Histogram
Figure 34. Output Offset Voltage vs Temperature
4500
1.89
Reference Voltage (mV)
4000
3500
Count
3000
2500
2000
1500
1000
1.87
1.85
1.83
1.81
1.79
1.77
0
1.75
1.9
500
Reference Voltage (mV)
Characteristic unit
±50
±25
0
25
50
75
100
Temperature (ƒC)
125
C035
C034
Figure 35. Reference Voltage (VOUTN) Distribution Histogram
Figure 36. Reference Voltage (VOUTN) vs Temperature
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7 Detailed Description
7.1 Overview
The OPA857 provides a unique combination of low-noise, high-bandwidth, and high-transimpedance gain. The
amplifier is optimized to achieve greater than 100-MHz bandwidth on either the 5-kΩ or 20-kΩ transimpedance
gain for the lowest possible RMS noise on the output for a targeted low input capacitance of
1.5 pF. Note that this 1.5-pF capacitance includes the board parasitic; thus, great attention must be placed on
minimizing stray capacitance in the layout. This value is selected because the device is expected to be driven by
a photodiode with biasing high enough to include the photodiode capacitance contribution between
approximately 0.5 pF and 0.7 pF, leaving between 0.8 pF to 1 pF for the external parasitic.
The OPA857 is a dedicated transimpedance amplifier with a pseudo-differential output. A block diagram is
provided in the Functional Block Diagram section.
There are four distinct blocks in this diagram: a transimpedance amplifier (TIA), a reference voltage (REF), a test
structure (TEST), and an internal clamping circuit (CLAMP).
The TIA block of the Functional Block Diagram includes two selectable gain configurations: RF1 and RF2. For a
500-Ω load, including the GND alternatives resulting from the internal 25-Ω series resistor on each output, the
resulting gain is 4.5 kΩ or 18.2 kΩ. The TIA block is designed to provide excellent bandwidth (> 100 MHz) in both
gain configurations with the lowest possible RMS noise over the entire bandwidth. This level of performance is
achieved by minimizing the noise gain peaking at higher frequencies. The noise gain peaking resulting from
feedback and source capacitance is the main noise contributor in high-speed transimpedance amplifiers.
The reference voltage block of the Functional Block Diagram has several purposes: this block provides an
adequate dc reference voltage to the input, and provides a dc reference at the output (thus allowing the dccoupled solution to interface to a fully-differential signal chain). The CMRR provided by the fully-differential signal
chain reduces any feedthrough from the OPA857 power supply, thereby increasing the PSRR of the amplifier.
The test structure block is available on the pinout, but the main purpose of this structure is to allow the device
characterization to proceed as smoothly as possible.
The internal clamping circuit block and ESD diodes on the IN pin are used for internal protection and to make
sure that the amplifier can recover quickly after saturation.
These blocks are each described in further detail in the Feature Description section.
7.2 Functional Block Diagram
+VS
CTRL
GND
TIA
RF2
RF1
25 W
OUT
25 W
OUTN
IN
Test_SD
TEST
CLAMP
1:1
2 kW
Clamping
Circuit
REF
Test_IN
14
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7.3 Feature Description
7.3.1 Transimpedance Amplifier (TIA) Block
The amplifier of the TIA block has a class-A output stage, which limits its usable swing from the common-mode
voltage of 1.83 V to the negative rail. Because the internal protection allows excellent overdrive recovery, the
negative swing cannot go closer than 0.6 V to the rail. The resulting output dynamic range of the OPA857 on a
3.3-V supply is 1.2 V. This 1.2-V swing corresponds to a maximum input current of 60 µA in the high-gain
configuration, and 240 µA in the low-gain configuration. A 25-Ω series resistor between the internal output of the
TIA block and OUT (pin 8) limits the amplifier load during short-circuit conditions. A similar 25-Ω series resistor
also exists between the output of the reference voltage amplifier and OUTN (pin 5). The internal resistors on
OUT and OUTN reduce the overall gain of the OPA857. With a 500-Ω differential load, the attenuation resulting
from the load is 0.83 dB, which affects the overall transimpedance gain. Because of the load attenuation, the 20kΩ transimpedance gain is reduced to an effective 18.2 kΩ, while the 5-kΩ internal resistor gain is reduced to an
effective 4.5-kΩ internal resistor.
7.3.2 Reference Voltage (REF) Block
The reference output voltage is set to be 5/9th of the power supply. Thus, for a single 3.3-V supply, the reference
voltage is 1.83 V. A wideband amplifier with low output impedance to high frequencies is used in the reference
voltage block. The amplifier output drives two paths: the first path drives the output (OUTN) through a 25-Ω
series resistor, while the second path drives the noninverting input of the TIA block. The output from the second
path is filtered through an RC filter in order to reduce the noise contribution from the reference block.
7.3.3 Integrated Test Structure (TEST) Block
In order to evaluate the low input capacitance condition on the input of the OPA857, simply evaluate the OPA857
performance without the photodiode. An integrated voltage-to-current conversion is implemented and can be
accessed with the use of Test_SD (pin 13) and Test_IN (pin 14). This V-to-I converter structure is represented in
Figure 37. If required, a capacitor can be added to IN (pin 15) to match the target input capacitance during
normal operation with an external photodiode. The test structure in Figure 37 allows for the evaluation of the
OPA857 as a TIA using standard lab equipment, such as function generators and network analyzers.
+VS
Test_SD
IN
+VS
Test_IN
2 kW
Figure 37. Internal V-to-I Converter
When using a photodiode, make sure that this source is turned off completely. This test structure is not intended
to be used as a output dc-control voltage.
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Feature Description (continued)
7.3.4 Internal Clamping Circuit (CLAMP) Block
The OPA857 is built using a very high-speed, complementary, BICMOS process. The internal junction
breakdown voltages are relatively low for these very small geometry devices. These breakdowns are reflected in
the Absolute Maximum Ratings (1) table. All device pins are protected with internal ESD protection diodes to the
power supplies, as shown in Figure 38.
+VCC
External
Pin
Internal
Circuitry
−VCC
Figure 38. Internal ESD Protection
These diodes provide moderate protection to input overdrive voltages above the supplies as well. The protection
diodes can typically support 30-mA continuous current. Use additional external low-capacitance protection where
higher currents are possible.
(1)
16
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
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7.4 Device Functional Modes
7.4.1 Gain Control
The device transimpedance gain is controlled with the CTRL pin. Setting the CTRL pin high results in selecting
the high-gain configuration. Setting the CTRL pin low results in selecting the low-gain configuration, as described
in Table 1.
Table 1. Gain Control Logic Table
GAIN
CTRL (Pin 2)
5 kΩ
Logic 0 (GND)
20 kΩ
Logic 1 (+VS)
7.4.2 Test Mode
The OPA857 operates in normal mode when the input is driven by a photodiode. In test mode, the test structure
described in the Integrated Test Structure (TEST) Block section is used to emulate a photodiode using a voltage
input. Table 2 describes how to configure the OPA857 in each mode.
Table 2. Mode Configuration
MODE
Test_IN PIN CONNECTED TO
Test_SD PIN CONNECTED TO
Normal mode
+VS
GND
Test mode
AC-coupled input using a series cap or
dc-coupled signal on a 2.1-V (approx) offset voltage
+VS
Set an adequate dc voltage at the input to make sure that the output is operating within normal operation. At
minimum, the output of the TIA block must be set to 5/9th of the supply voltage in preparation for a pulse
configuration. For sine-wave operation, as required when measuring a frequency response, set the dc voltage on
the OUT pin to allow the full sine-wave amplitude and avoid clipping. In such a case, the OUT pin voltage is set
lower than 5/9th of the supply voltage.
Note that the 2-kΩ internal resistance used for the V-to-I conversion is not trimmed and can vary ±15% with
process. Therefore, the source must be capable of sourcing both dc and ac voltages to make sure that the output
voltage swing is compliant with the class-A output stage of the TIA block. Any change in the test circuit
configuration (such as gain change) requires a new calibration of the internal V-to-I converter.
Again if a photodiode is used, the internal V-to-I converter must be shut off completely. Failure to do so results in
degraded performance and higher than normal quiescent current.
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8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The OPA857 is a transimpedance amplifier offering two selectable gains. This device is used in conjunction with
a photodiode at its input. The output is pseudo differential and may or may not require the use of a fully
differential amplifier, depending on the analog-to-digital converter (ADC) used for implementation.
The OPA857 requires a photodiode to be connected to the positive bias voltage because the output voltage can
only swing down from the reference voltage (1.85 V for a 3.3-V supply) to ground.
8.2 Typical Application
8.2.1 TIA With Associated Signal Chain
Figure 39 presents a complete end-to-end receive signal chain for an optical input. It includes a high-speed
photodiode, the OPA857, a THS4541 fully-differential amplifier, and a 16-bit, 160-MSPS, high-speed ADC. For
the complete wide-bandwidth, optical front-end reference design, go to http://www.ti.com/tool/TIDA-00725.
VBIAS
Clocking + FPGA+ Memory
THS4541
2k
OPA857
50
1k
VREF
+
±
+
Bias
Reference
±
374
374
50
ADC34J45
1k
2k
Figure 39. TIA With Associated Signal Chain
18
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Typical Application (continued)
8.2.1.1 Design Requirements
For this example, use the values listed in Table 3 for the input parameters.
Table 3. Design Parameters
DESIGN PARAMETER
EXAMPLE VALUE
Supply voltage
5-V external supply
Analog bandwidth
120 MHz
ADC sampling rate
160 MSPS
Maximum system gain
100 kΩ
Programmable transimpedance gain
5 kΩ / 20 kΩ
Maximum signal swing
1 VPP
Noise performance
≥ 60-dB SNR
Averaged noise performance
< 10-µVRMS
8.2.1.2 Detailed Design Procedure
1. Use a high-speed, low input capacitance photodiode, such as the NR7500 or NR8300, as the front-end
optical sensor. Take care during layout to minimize parasitic capacitance added because of the PCB.
2. Bias the photodiode with the cathode connected to a positive supply, and the anode connected to IN pin of
the OPA857. These connections make sure that the photodiode sources an output current that results in the
OPA857 output swinging down below the reference voltage = (5 / 9) × 3.3 V = 1.83 V.
3. Disable the OPA857 test mode by setting Test_IN = +VS and Test_SD = GND. The transimpedance gain is
selected by setting CTRL = +VS (gain = 20 kΩ) or CTRL = GND (gain = 5 kΩ).
4. The THS4541 is configured in a gain of 5 V/V in order to achieve a maximum signal transimpedance gain of
100 kΩ. It is important to carefully select the value of the RG gain resistors for the THS4541.
5. Setting RG very low increases the resistive loading on the previous OPA857 output stage, and reduces the
bandwidth of the OPA857.
6. Setting RG very high results in a large value of feedback resistance, RF, on the THS4541 in order to achieve
the desired 5V/V gain. RF interacts with the input capacitance of the THS4541 to create a zero in the noisegain response of the amplifier, and if not properly compensated, results in reduced phase-margin and
potential instability.
7. A value of RG = 374 Ω was selected that results in a total differential load of 798 Ω on the OPA857. The
resultant RF = 2 kΩ.
8. The response to an optical pulsed input is shown in Figure 40 to Figure 43. To prevent signal reflections
between the THS4541 output and the ADC34J45 input, the signal is doubly terminated through 50-Ω
resistors. If the THS4541 and ADC34J45 are physically close together on the PCB, then the doubletermination is eliminated, which increases the overall gain of the signal chain without affecting the transient
response of the system. These results were verified, and the complete data is available in reference design
TIDA-00725.
9. An optional antialiasing filter can be added between the THS4541 and the ADC34J45 to reduce system
noise caused by aliasing.
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8.2.1.3 Application Curves
400P
1
125 mV
250 mV
500 mV
950 mV
300P
Output Voltage (V)
Output Voltage (V)
100m
125 mV
250 mV
500 mV
1V
350P
10m
1m
250P
200P
150P
100P
50P
100P
0
-50P
10P
0
0.25
0.5
0.75
1
1.25
1.5
1.75
2
2.25
Time (Ps)
2.5
2.75
3
3.25
3.5
3.75
0
4
1
2
3
5
Time (Ps)
6
7
8
9
10
D005
TZ Gain = 20 kΩ
TZ Gain = 20 kΩ
Figure 41. Long-Term Settling Response vs Output
Voltage
Figure 40. Pulse Response vs Output Voltage
400P
1
125 mV
250 mV
500 mV
950 mV
100m
125 mV
250 mV
500 mV
1V
350P
300P
Output Voltage (V)
Output Voltage (V)
4
D004
10m
1m
250P
200P
150P
100P
50P
100P
0P
-50P
10P
0
0.25
0.5
0.75
1
1.25
1.5
1.75
2
2.25
Time (Ps)
2.5
2.75
3
3.25
3.5
3.75
4
0
1
D006
3
4
5
Time (Ps)
6
7
8
9
10
D007
TZ Gain = 5 kΩ
TZ Gain = 5 kΩ
Figure 42. Pulse Response vs Output Voltage
20
2
Figure 43. Long-Term Settling Response vs Output
Voltage
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8.2.2 Extending Transimpedance Bandwidth
At the core of the OPA857 is an ultrawide bandwidth op amp. One of the highlights of the OPA857 is the
relatively small change in the transimpedance bandwidth as a function of the internal gain selected; 130 MHz
(gain = 5 kΩ) and 105 MHz (gain = 20 kΩ). Theoretically, for a four times increase in gain, the bandwidth should
reduce by two times; however, as observed in the case of the OPA857, the results do not follow theory. For more
information on the various factors that contribute to an amplifier frequency-response performance when
configured as a TIA, see What You Need To Know About Transimpedance Amplifiers – Part 1 on the TI E2E
Community website at e2e.ti.com. This blog also contains a reference to an excel calculator to simplify TIA
designs when using discrete opamps. The OPA857 is unique in displaying this type of behavior because the
CTRL logic controls an internal switch in the amplifier core that recompensates the amplifier open-loop gain
characteristic depending upon the logic level. In this application, it it shown how the closed-loop transimpedance
bandwidth can be increased to greater than 250 MHz. The circuit used for this test is shown in Figure 44. An
external feedback resistor, RF, is added in parallel to the internal transimpedance gain resistors of the OPA857.
This resistor has the effect of reducing the overall transimpedance gain, but with increased bandwidth.
External CF
External RF
CTRL
+VS
GND
TIA
RF2
VBIAS
RF1
25
±
OUT
IN
+
25
OUTN
CLAMP
Test_SD
TEST
Clamping
Cicuit
REF
1:1
2k
Test_In
Figure 44. Extending Transimpedance Bandwidth
8.2.2.1 Design Requirements
For this example, use the values listed in Table 4 for the input parameters.
Table 4. Design Parameters
DESIGN PARAMETER
EXAMPLE VALUE
Supply voltage
3.3 V
Output swing
500 mVPP
Differential output load
500 kΩ and 1 kΩ
Target bandwidth
250 MHz
Effective transimpedance gain
5 kΩ
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8.2.2.2 Application Curves
4
2
3
1.5
2
1
1
0.5
Output (dB)
Output (dB)
Figure 45 shows the frequency response with a feedback resistance of 6.8 kΩ and an output load of 500 Ω. The
large amount of peaking indicates a low phase-margin and potential instability. Next, a 0.1-pF feedback
capacitor, CF, is added in parallel to the 6.8-kΩ RF. Both RF and CF interact to create pole in the noise gain curve
that counteracts the effect of the zero caused by RF, and the total input capacitance at pin IN of the OPA857.
The input capacitance is caused by the opamps inherent input capacitance, the photodiode capacitance, and the
parasitic input capacitance from the PCB. The pole zero cancellation increases the phase margin, as is evident in
the reduced peaking shown in Figure 46. In Figure 47, an output load of 1 kΩ was used, along with an RF = 6.8
kΩ and CF = 0.1 pF. The reduced load helps to increase the op amp open-loop gain, which in turn increases the
closed-loop bandwidth of the OPA857 circuit.
0
-1
-2
-3
RF(Internal) = 20 k:, RF || CF(External) = 6.8 k: || 0.1 pF
RF(Internal) = 5 k:, RF || CF(External) = 6.8 k: || 0.1 pF
0
-0.5
-1
-1.5
RF = 20 k: (Internal) || 6.8 k: (External)
RF = 5 k: (Internal) || 6.8 k: (External)
-4
1M
10M
Frequency (Hz)
100M
-2
1M
1G
10M
Frequency (Hz)
D003
RF = 6.8 kΩ
100M
D004
RF = 6.8 kΩ, CF = 0.1 pF
Figure 45. Frequency Response With External Feedback
Figure 46. Frequency Response With External Feedback
4
3
RF(Internal) = 20 k:, RF || CF(External) = 6.8 k: || 0.1 pF
RF(Internal) = 5 k:, RF || CF(External) = 6.8 k: || 0.1 pF
Output (dB)
2
1
0
-1
-2
-3
-4
1M
10M
Frequency (Hz)
100M
1G
D007
RF = 6.8 kΩ, CF = 0.1 pF
Figure 47. Frequency Response With External Feedback
22
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9 Power-Supply Recommendations
Use a linear power supply with good PSRR. For a good, high-frequency, power-supply bypass, use a ceramic
capacitor connected as close as possible to the +VS pin.
10 Layout
10.1 Layout Guidelines
Achieving optimum performance with a high-frequency amplifier such as the OPA857 requires careful attention to
board layout parasitics and external component types. Recommendations that optimize performance include:
a. Minimize parasitic capacitance to any ac ground for all signal I/O pins. Parasitic capacitance on the
inverting input pin can cause instability. To reduce unwanted capacitance, open a window around the signal
I/O pins in all ground and power planes around those pins. Otherwise, make sure that ground and power
planes are unbroken elsewhere on the board.
b. Minimize the distance (< 0.25") from the power-supply pins to high-frequency 0.1-µF decoupling capacitors,
as shown in Figure 48. At the device pins, make sure that the ground and power-plane layout are not in
close proximity to the signal I/O pins. Avoid narrow power and ground traces to minimize inductance between
the pins and decoupling capacitors. Always decouple the power-supply connections with these capacitors.
An optional supply decoupling capacitor (0.1 µF) across the two power supplies (for bipolar operation)
improves second-harmonic distortion performance. Use larger (2.2 µF to 6.8 µF) decoupling capacitors,
effective at lower frequencies, on the main supply pins. These capacitors can be placed somewhat farther
from the device and can be shared among several devices in the same area of the PC board.
c. Careful selection and placement of external components preserves the high-frequency performance
of the OPA857. Use very low reactance type resistors. Surface-mount resistors function best and allow a
tighter overall layout. Metal-film or carbon composition, axially-leaded resistors also provide good highfrequency performance. Again, keep the leads and PC board traces as short as possible. Never use
wirewound type resistors in a high-frequency application.
d. Connections to other wideband devices on the board can be made with short, direct traces or through
onboard transmission lines. For short connections, consider the trace and the input to the next device as a
lumped capacitive load. Use relatively wide traces (50 mils to 100 mils), preferably with ground and power
planes opened up around them.
e. Do not socket a high-speed part such as the OPA857. The additional lead length and pin-to-pin
capacitance introduced by the socket can create an extremely troublesome parasitic network that makes
achieving a smooth, stable frequency response almost impossible. Best results are obtained by soldering the
OPA857 onto the board.
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10.2 Layout Example
10-nF
Bypass Capacitor
100-nF
Bypass Capacitor
C2 and C3
as Close as Possible
to +Vs and GND Pins
< 0.25"
OUT
Test_IN
GND
IN
GND
NC
OUTN
CTRL
Open Planes to
Minimize Parasitic
Input Capacitance
Test_SD
Figure 48. Layout Example
24
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Product Folder Links: OPA857
OPA857
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SBOS630D – DECEMBER 2013 – REVISED AUGUST 2016
11 Device and Documentation Support
11.1 Device Support
11.1.1 Development Support
11.1.1.1 Evaluation Module
An evaluation module (EVM) is available to assist in the initial circuit performance evaluation using the OPA857.
The summary information for this fixture is shown in Table 5.
Table 5. EVM Ordering Information
PRODUCT
PACKAGE
ORDERING NUMBER
LITERATURE NUMBER
OPA857IRGT
RGT
OPA857EVM
SBOU138
The EVM can be requested at the Texas Instruments web site (www.ti.com) through the OPA857 product folder.
11.1.1.2 Spice Model
Computer simulation of circuit performance using spice is often useful when analyzing the performance of analog
circuits and systems. The previous statement is particularly true for transimpedance applications where parasitic
capacitance and inductance can have a major effect on circuit performance. A spice model for the OPA857 is
available through the OPA857 product folder under simulation models. These models do a good job of predicting
small-signal ac and transient performance under a wide variety of operating conditions. These models, however,
do not do as well in predicting harmonic distortion.
11.2 Documentation Support
11.2.1 Related Documentation
For related documentation, see the following:
• OPA857EVM Evaluation Module (SBOU138)
• Transimpedance Considerations for High-speed Amplifiers (SBOA122)
• Wide Bandwidth Optical Front-end Reference Design (TIDUAZ1)
• Reference Design for Extending the OPA857 Transimpedance Bandwidth (TIDUBX7)
• Learn how to compensate transimpedance amplifiers intuitively in:
What You Need To Know About Transimpedance Amplifiers – Part 1 (Cherian 2016)
11.3 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
11.4 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
11.5 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
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Product Folder Links: OPA857
25
OPA857
SBOS630D – DECEMBER 2013 – REVISED AUGUST 2016
www.ti.com
11.6 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
11.7 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical packaging and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
26
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Product Folder Links: OPA857
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
OPA857IRGTR
ACTIVE
VQFN
RGT
16
3000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
OPA857
OPA857IRGTT
ACTIVE
VQFN
RGT
16
250
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
OPA857
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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