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OPT8320
SBAS748 – DECEMBER 2015
OPT8320 3D Time-of-Flight Sensor
1 Features
2 Applications
•
•
1
•
•
•
•
•
•
•
•
Imaging Array:
– 80 × 60 Array
– 1/6” Sensor Format
– Pixel Pitch: 30 µm
– Frame Rate: Scalable Up to 1000-FPS Depth
Output Rate with an Internal Raw Rate of
4000 FPS
Optical Properties:
– Responsivity: 0.35 A/W at 850 nm
– Demodulation Contrast: 70% at 50 MHz
– Demodulation Frequency: 10 MHz to 100 MHz
Output Interface:
– Digital Video Port (DVP): 8 Data Lanes,
HD and VD Pins, and Clock
– Synchronous Serial Interface (SSI):
1 Data Lane, Clock, and Chip Select
Timing Generator:
– Sensor Addressing Engine
– Modulation Control
– De-Aliasing
– Master, Slave Sync Operation
– High Dynamic Range Operation
Depth Engine:
– Pixel Binning
– De-Aliasing
– Histogram
– Calibration
Power Supply:
– 3.3-V I/O, Analog
– 1.8-V Analog, Digital, I/O
– 1.8-V Demodulation (Typical)
Optimized Optical Package (COG-56):
– 8.03 mm × 5.32 mm × 0.745 mm
– Integrated Optical Band-Pass Filter
(830 nm to 867 nm)
– Optical Fiducials for Easy Alignment
Built-In Illumination Driver for Low-Power
Applications
Operating Temperature: 0°C to 70°C
Depth Sensing:
– Location and Proximity Sensing
– 3D Scanning
– 3D Machine Vision
– Security and Surveillance
– Gesture Controls
– Augmented and Virtual Reality
3 Description
The OPT8320 time-of-flight (ToF) sensor is part of
the TI 3D ToF image sensor family. The device is a
high-performance,
highly-integrated,
complete
system-on-chip (SoC) for array depth sensing,
consisting of a versatile timing generator (TG), an
optimally designed analog-to-digital converter (ADC),
a depth engine, and an illumination driver.
The programmability of the built-in TG offers the
flexibility to optimize for various depth-sensing
performance metrics [such as power, motion
robustness, signal-to-noise ratio (SNR), and ambient
cancellation]. The built-in depth engine computes the
depth data from the digitized sensor data. In addition
to the phase data, the depth engine provides auxiliary
information consisting of amplitude, ambient, and
flags for each pixel and the full-array statistical
information in the form of a histogram.
Device Information(1)
PART NUMBER
OPT8320
PACKAGE
COG (56)
BODY SIZE (NOM)
8.03 mm x 5.32 mm x
0.745 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Application Block Diagram
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
OPT8320
SBAS748 – DECEMBER 2015
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Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
5
6.1
6.2
6.3
6.4
6.5
6.6
6.7
6.8
6.9
5
5
5
6
6
7
7
8
9
Absolute Maximum Ratings ......................................
ESD Ratings..............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics...........................................
Timing Requirements ................................................
Switching Characteristics ..........................................
Optical Characteristics ..............................................
Typical Characteristics ..............................................
7.5 Register Maps ......................................................... 29
8
8.1 Application Information............................................ 65
8.2 Typical Applications ............................................... 66
8.3 Initialization Set Up ................................................ 77
9
Overview .................................................................
Functional Block Diagram .......................................
Feature Description.................................................
Device Functional Modes........................................
Power Supply Recommendations...................... 78
9.1 Example Power Consumption Numbers ................. 78
9.2 Power Trade-Off...................................................... 78
10 Layout................................................................... 79
10.1 Layout Guidelines ................................................. 79
10.2 Layout Example .................................................... 81
10.3 Mechanical Assembly Guidelines ......................... 81
11 Device and Documentation Support ................. 82
11.1
11.2
11.3
11.4
11.5
Detailed Description ............................................ 10
7.1
7.2
7.3
7.4
Application and Implementation ........................ 65
10
10
11
28
Documentation Support .......................................
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
82
82
82
82
82
12 Mechanical, Packaging, and Orderable
Information ........................................................... 82
4 Revision History
2
DATE
REVISION
NOTES
December 2015
*
Initial release.
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5 Pin Configuration and Functions
MIXH
MIXH
GND
GND
ILLUM_P
ILLUM_N
DVDDH
AVDD_PLL
AVSS_PLL
MOD_CDRIV
VSS_CDRIV
ILLUM_EN
ILLUM_FB
ILLUM_PWM_CTRL
ILLUM_PWM_SYNC
I2C_MAS_SDA
I2C_MAS_SCL
NBP Package
56-Pin COG
Top View, Not to Scale
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
DVDD
GND
1
38
DVSS
SUB_BIAS
2
37
OP_DATA[7]
PVDD
3
36
OP_DATA[6]
AVDDH
4
35
OP_DATA[5]
AVDD
5
34
OP_DATA[4]
Thermal Pad
29
OP_CLK
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
HD
10
VD
MCLK
IOVDD
OP_DATA[0]
IOVSS
30
IOVDD
9
I2C_SLV_ADDR[0]
AVSS
SLEEP
OP_DATA[1]
DEBUG
31
VD_IN
8
DVDD
REFP
DVSS
OP_DATA[2]
I2C_SLV_SDA
32
I2C_SLV_SCL
7
RESET
REFM
GPO[1]
OP_DATA[3]
GPO[0]
33
TP1
6
TP2
AVSS
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Pin Functions
PIN
NAME
NO.
I/O
I/O
VOLTAGE
DOMAIN
DESCRIPTION
AVDD
5
Power
—
Analog 1.8-V supply
AVDD_PLL
49
Power
—
Analog 1.8-V PLL supply
AVSS_PLL
48
Power
—
Analog PLL ground
AVDDH
4
Power
—
Analog 3.3-V supply
6, 9
Power
—
Analog ground
AVSS
DEBUG
21
Bidirectional
IOVDD
19, 39
Power
—
Digital 1.8-V supply
50
Power
—
Digital 3.3-V supply
DVSS
18, 38
Power
—
Digital ground
GND
1, 53, 54
Power
—
Connect to ground
GPO[0]
13
Output
IOVDD
General-purpose output 0
GPO[1]
14
Output
IOVDD
General-purpose output 1
HD
28
Output
IOVDD
Indicates the row boundary
I2C_MAS_SCL
40
Output
IOVDD
Host I2C clock output
I2C_MAS_SDA
41
Bidirectional
IOVDD
Host I2C data
I2C_SLV_ADDR[0]
23
Input
IOVDD
I2C address bit 0
I2C_SLV_SCL
16
Input
IOVDD
Slave I2C interface clock input
I2C_SLV_SDA
17
Bidirectional
IOVDD
Slave I2C Interface data
ILLUM_EN
45
Output
DVDDH
Illumination enable
ILLUM_FB
44
Input
DVDDH
Feedback signal for illumination power control
ILLUM_N
51
Bidirectional
DVDDH
Illumination modulation signal
ILLUM_P
52
Bidirectional
DVDDH
Illumination modulation signal
ILLUM_PWM_CTRL
43
Output
DVDDH
PWM signal for illumination power control
ILLUM_PWM_SYNC
42
Output
DVDDH
PWM signal for illumination power control
IOVDD
24, 26
Power
—
IO voltage 1.8 V, 3.3 V
IOVSS
25
Power
—
IO ground
MCLK
10
Input
IOVDD
Main clock input for the device
MIXH
55, 56
Power
—
Modulation voltage power pin
MOD_CDRIV
47
Output
—
Illumination current driver
OP_CLK
29
Output
IOVDD
CMOS data bus clock output
OP_DATA[0]
30
Output
IOVDD
CMOS data out bit 0
OP_DATA[1]
31
Output
IOVDD
CMOS data out bit 1
OP_DATA[2]
32
Output
IOVDD
CMOS data out bit 2
OP_DATA[3]
33
Output
IOVDD
CMOS data out bit 3
OP_DATA[4]
34
Output
IOVDD
CMOS data out bit 4
OP_DATA[5]
35
Output
IOVDD
CMOS data out bit 5
OP_DATA[6]
36
Output
IOVDD
CMOS data out bit 6
OP_DATA[7]
37
Output
IOVDD
CMOS data out bit 7
PVDD
3
Power
—
Pixel 3.3-V supply
REFM
7
Analog input
—
Connect REFM to GND
REFP
8
Analog output
—
ADC reference.
Connect a 10-nF capacitor between REFP and REFM.
RESET
15
Input
IOVDD
Reset; active low
SLEEP
22
Input
IOVDD
Power-down pin
SUB_BIAS
2
Power
—
Negative bias voltage
Power
—
Exposed thermal pad. Do not solder.
DVDD
DVDDH
Thermal pad
4
Debug port. Pullup to IOVDD with a 10-kΩ resistor.
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Pin Functions (continued)
PIN
NAME
NO.
I/O
I/O
VOLTAGE
DOMAIN
DESCRIPTION
TP1
12
Passive
IOVDD
Test point 1
TP2
11
Passive
IOVDD
Test point 2
VD
27
Output
IOVDD
Indicates the frame boundary
VD_IN
20
Input
IOVDD
External sync input
VSS_CDRIV
46
Power
—
Illumination current driver ground
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
MIN
MAX
UNIT
IOVDD
Digital I/O supply
–0.3
4.0
V
AVDDH
Analog supply
–0.3
4.0
V
DVDDH
Digital I/O supply
–0.3
4.0
V
PVDD
Pixel supply
–0.3
4.0
V
AVDD
Analog supply
–0.3
2.2
V
VMIXH
Mix supply
–0.3
2.5
V
DVDD
Digital supply
–0.3
2.2
V
AVDD_PLL
PLL supply
–0.3
2.2
V
VI
Input voltage at input pins
–0.3
VCC + 0.3 (2)
V
TJ
Operating junction temperature
0
125
°C
Tstg
Storage temperature
–40
125
°C
(1)
(2)
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
VCC refers to the I/O bank voltage.
6.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1)
±1000
Charged-device model (CDM), per JEDEC specification JESD22-C101 (2)
±250
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
NOM
MAX
IOVDD
Digital I/O supply
1.7
1.8 to 3.3
3.6
UNIT
V
AVDDH
Analog supply
3.0
3.3
3.6
V
DVDDH
Digital I/O supply
3.0
3.3
3.6
V
PVDD
Pixel supply
2.4
3.3
3.6
V
AVDD
Analog supply
1.7
1.8
1.9
V
VMIXH
Mix supply
0.8
1.5
2.0
V
DVDD
Digital supply
1.7
1.8
1.9
V
AVDD_PLL
PLL supply
1.7
1.8
1.9
V
VDRV
MOD_CDRIV pin voltage
0.7
3.3
V
TA
Operating ambient temperature
0
70
°C
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6.4 Thermal Information
OPT8320
THERMAL METRIC (1)
NBP (COG)
UNIT
56 PINS
Without underfill
93.4
With underfill
44.0
RθJA
Junction-to-ambient thermal resistance
RθJC(top)
Junction-to-case (top) thermal resistance
22.7
°C/W
RθJB
Junction-to-board thermal resistance
61.6
°C/W
ψJT
Junction-to-top characterization parameter
7.2
°C/W
ψJB
(1)
Junction-to-board characterization parameter
Without underfill
61.4
With underfill
11.9
°C/W
°C/W
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
6.5 Electrical Characteristics
all specifications at TA = 25°C, VAVDDH = 3.3 V, VAVDD = 1.8 V, VVMIXH = 1.8 V, VDVDD = 1.8 V, VDVDDH = 3.3 V, VPVDD = 3.3 V,
VSUB_BIAS = 0 V, integration duty cycle = 20%, system clock frequency = 24 MHz, VIOVDD = 1.8 V, modulation frequency =
48 MHz, quads = 4, sub-frames = 4, frame-rate = 30 FPS, and 850-nm illumination (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
SENSOR
V
Rows
60
Rows
H
Columns
80
Columns
PP
Pixel pitch
30
μm
ILLUMINATION DRIVER
IDRV
Max built-in illumination driver current
150
mA
fDRV
Max Built-in illumination driver
frequency
100
MHz
Minimum pulse duration
10.4
ns
Starting duty cycle
50%
ILLUMINATION POWER CONTROL
POWER (Normal Operation)
IAVDD_PLL PLL supply current
IAVDD
Analog supply current
IDVDDH
3.3-V digital supply current
IAVDDH
3.3-V analog supply current
IPVDD
Pixel VDD current
IVMIXH
Demodulation current
IIOVDD
I/O supply current (CMOS mode)
IDVDD
Digital supply current
4
Without dynamic power-down
With dynamic power-down
20.7
6.7
0.3
Without dynamic power-down
5.5
With dynamic power-down
1.5
0.5
10% integration duty cycle
56
100% integration duty cycle
560
mA
mA
mA
mA
mA
mA
4.2
mA
19.7
mA
POWER (Standby)
IIOVDD
I/O supply current
IAVDD_PLL PLL supply current
1
mA
100
μA
IAVDD
Analog supply current
1
mA
IDVDD
Digital supply current
4
mA
IDVDDH
3.3-V digital supply current
50
μA
IAVDDH
3.3-V analog supply current
200
μA
IVMIXH
Demodulation current
0
mA
IPVDD
Pixel VDD current
100
μA
6
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Electrical Characteristics (continued)
all specifications at TA = 25°C, VAVDDH = 3.3 V, VAVDD = 1.8 V, VVMIXH = 1.8 V, VDVDD = 1.8 V, VDVDDH = 3.3 V, VPVDD = 3.3 V,
VSUB_BIAS = 0 V, integration duty cycle = 20%, system clock frequency = 24 MHz, VIOVDD = 1.8 V, modulation frequency =
48 MHz, quads = 4, sub-frames = 4, frame-rate = 30 FPS, and 850-nm illumination (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
CMOS INPUTS/OUTPUTS
VIH
0.7 × VCC (1)
Input high-level threshold
VIL
V
Input low-level threshold
VOH
0.3 × VCC
IOH = –2 mA
VCC (1) –
0.45
IOH = –8 mA
VCC (1) –
0.5
Min Output high level
IOL = 2 mA
0.35
IOL = 8 mA
0.65
(1)
V
V
VOL
Max Output low level
II
Input pin leakage current
CI
Input capacitance
5
pF
IOH
Max output current high level
10
mA
IOL
Max output current low level
10
mA
(1)
V
Pins with pullup, pulldown resistor
±50
Pins without pullup, pulldown
resistor
±10
µA
VCC is equal to IOVDD or DVDDH, based on the I/O bank listed in the table.
6.6 Timing Requirements
MIN
MCLK duty cycle
NOM
MAX
48%
MCLK frequency
52%
24
VD_IN pulse duration
UNIT
MHz
2 × MCLK period
RESET low pulse duration (reset)
100
ns
6.7 Switching Characteristics
over operating free-air temperature range (unless otherwise noted); VDVDD = 1.8 V, VDVDDH = 3.3 V, and VIOVDD = 1.8 V
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
PARALLEL CMOS MODE (VIOVDD = 1.8 V)
tSU
Data setup time
Data valid to zero crossing of CLKOUT
18.4
ns
tH
Data hold time
Zero crossing of CLKOUT to data becoming invalid
21.1
ns
tFALL, tRISE
Data fall time, data rise time
Rise time measured from 30% to 70% of IOVDD
1.75
ns
tCLKRISE,
tCLKFALL
Output clock rise time,
output clock fall time
Rise time measured from 30% to 70% of IOVDD
1.72
ns
PARALLEL CMOS MODE (VIOVDD = 3.3 V)
tSU
Data setup time
Data valid to zero crossing of CLKOUT
18.3
ns
tH
Data hold time
Zero crossing of CLKOUT to data becoming invalid
21.4
ns
tFALL, tRISE
Data fall time, data rise time
Rise time measured from 30% to 70% of IOVDD
1.32
ns
tCLKRISE,
tCLKFALL
Output clock rise time,
output clock fall time
Rise time measured from 30% to 70% of IOVDD
1.39
ns
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6.8 Optical Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
Glass side
AOI
Top
UNIT
Side
Passband
(50% relative transmittance (1))
0° incident angle
813 to 893
nm
30° incident angle
798 to 877
nm
Passband
(90% relative transmittance (1))
0° incident angle
830 to 881
nm
30° incident angle
838 to 867
Recommended angle of incidence
Maximum absolute transmittance
(1)
MAX
0
nm
35
Degrees
0° incident angle
87.34% at 863
nm
30° incident angle
81.89% at 855
nm
Relative transmittance is a ratio of transmittance to maximum absolute transmittance at the same angle of incidence.
Output Clock
(OP_CLK)
tSU
Output Data
(OP_DATAn)
tH
Dn
NOTE: In SSI output mode, clock polarity is inverted when compared to DVP mode.
Figure 1. Output Block Timing Diagram
8
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6.9 Typical Characteristics
all specifications at TA = 25°C, VAVDDH = 3.3 V, VAVDD = 1.8 V, VVMIXH = 1.8 V, VDVDD = 1.8 V, VDVDDH = 3.3 V, VPVDD = 3.3 V,
VSUB_BIAS = 0 V, integration duty cycle = 20%, system clock frequency = 24 MHz, modulation frequency = 48 MHz, quads = 4,
sub-frames = 4, frame-rate = 30 FPS, and 850-nm illumination (unless otherwise noted)
25
1.2
1
ISUB_BIAS (mA)
Normalized IVMIXH
20
0.8
0.6
0.4
15
10
0.2
5
0
-0.2
0
0.2
0.4
0.6
0.8
1
1.2
VVMIXH (V)
1.4
1.6
1.8
2
0
-8
-7
-6
-5
-4
-3
VSUB_BIAS (V)
-2
-1
0
Normalized to VMIXH = 1.50 V
Figure 2. Normalized VMIXH Supply Current vs
VMIXH Supply Voltage
Figure 3. VSUB_BIAS Supply Current vs
VSUB_BIAS Supply Voltage
90
80
Incident Angle = 0q
Incident Angle = 30q
Transmitivity (%)
70
60
50
40
30
20
10
0
350
450
550
650
750
850
Light Wavelength (nm)
950
1050
Figure 4. Optical Transitivity vs Wavelength
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7 Detailed Description
7.1 Overview
The OPT8320 system-on-chip (SoC) has the following blocks:
• Timing generator: generates the sequencing signals for the sensor, illumination, and depth processor
• Sensor: the pixel array
• Addressing engine
• Analog-to-digital converter (ADC)
• Modulation block
• Illumination driver
• Depth engine: calculates phase and amplitude
• Internal memory for depth computation
• Illumination power control
• Output data interface module
• I2C slave for configuring the device registers via the host processor
• I2C master for temperature sensing
Reset
Power
Control
External
Illumination
Driver
LED, Laser
1.8 V
3.3 V
7.2 Functional Block Diagram
Illumination Driver
PLL
CLK
VD_IN
Timing Generator
CMOS Parallel
Interface, DVP, SSI
Output Interface
Phase
Amplitude
Ambient
Depth Engine
Illumination
Power Control
Modulation Block
Phase
Correlation
Data
Address
Engine
ADC
Readout
Sensor Array
(80 x 60)
Calibration
Memory
Registers
I2C Master, Slave
Controller
I2C Control
External
Temperature
Sensor
Temperature Sensor
10
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7.3 Feature Description
7.3.1 Timing Generator
The timing generator (TG) generates the timing sequence for each frame. The TG includes frame rate control,
quad sequencing, and integration time control.
7.3.1.1 Basic Frame Structure
Each frame is divided into sub-frames used for internal averaging, as shown in Table 1.
Table 1. Frame Structure
FRAME
Sub-frame 1
Sub-frame 2
…
Sub-frame n
Frame dead time
Each sub-frame is divided into quads, as shown in Table 2. Each quad can have a different phase between the
illumination and sensor modulation signals.
Table 2. Sub-Frame Division
SUB-FRAME
Quad 1
Quad 2
Quad 3
…
Quad n
Each quad is further split into four stages, as shown in Table 3. These stages are described in Table 3.
Table 3. Quad Stages
QUAD
Reset
Integration
Readout
Quad dead time
The description of the quad stages is given in Table 4.
Table 4. Quad Stage Descriptions
QUAD STAGE
DESCRIPTION
Reset
The sensor is reset to clear the accumulated signal
Integration
The pixel array and illumination are modulated by the modulation block. The sensor captures the raw time-offlight (ToF) signal.
Readout
The raw pixel data in the selected region of interest is readout from the sensor on to the ADC and then by the
depth engine.
Dead
The sensor is inactive. The ADC enters a low-power mode.
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7.3.1.2 System Clock
The input clock to the system must be 24 MHz. By default, the TG functions at the same frequency as the input
frequency. Therefore, the system clock frequency (SYS_CLK_FREQ) is equal to the input frequency at the
MCLK pin.
7.3.1.3 Frame Rate Control and Sub-Frames
The OPT8320 supports master and slave modes of operation for the start of frame timing. The parameters
shown in Table 5 control the master and slave behavior.
Table 5. Master and Slave Parameters
PARAMETER
DEFAULT
DESCRIPTION
TG_EN
0
Start the timing generator and, thus, the full chipset operation.
0 = Disable the timing generator
1 = Enable the timing generator
SLAVE_MODE
0
Puts the timing controller in slave mode. The timing controller waits for an external
sync through the VD_IN pin for the start of frames. By default, the timing controller
is in master mode.
SYNC_MODE
0
Puts the timing controller in SYNC_MODE. The timing controller synchronizes with
an external input through the VD_IN pin for the start of frames, but does not
depend on the input. If both SLAVE_MODE and SYNC_MODE are enabled,
SYNC_MODE takes higher priority. By default, this mode is disabled.
FRAME_SYNC_DELAY
1
The programmable delay between the external VD_IN pulse and the internal start
of frame. The delay must be at least one cycle.
In slave mode or sync mode, a positive pulse on the VD_IN pin can be used for synchronization. The pulse must
be a minimum of two system clocks cycles wide in order to be recognized correctly, as shown in Figure 5. In
slave mode, if another pulse is received before the end of the previous frame, the pulse is ignored. In sync
mode, because a pulse can be received by the OPT8320 anytime within a frame, the frame during which the
pulse is received is aborted and therefore disruption of output data is possible, resulting in a loss of information.
Min 2 Cycles
VD_IN
System Clock
FRAME_SYNC_DELAY
Frame Number
X
X+1
Figure 5. VD_IN Timing Diagram
12
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When the OPT8320 is operated in master mode or sync mode, the frame rate is controlled using the parameters
shown in Table 6. In the OPT8320, the number of quads (QUAD_CNT_MAX) are fixed to four. Using the
functionality of alternate frames, two kinds of frames are possible with a different set of sub-frames, integration
duty cycle, and modulation frequency. The resulting information can be also combined to give out a single dealiased frame. When alternate frames are enabled, every alternate frame with the different set of timing
parameters is called the supplementary frame.
Table 6. Frame Rate Parameters
PARAMETER
DEFAULT
DESCRIPTION
ALT_FRM_EN
0
When set to 1, enables alternate frames with a different set of sub-frames,
integration duty cycle, and frequency.
SUB_FRAME_CNT_MAX1
16
Total number of sub-frames in each frame for the base frame. Only values that are
powers of 2 are valid. Behavior is unpredictable when set to other values.
SUB_FRAME_CNT_MAX2
4
Total number of sub-frames in each frame for the supplementary frame. Only
values that are powers of 2 are valid. Behavior is unpredictable when set to other
values.
PIX_CNT_MAX
12500
The number of system clock cycles in one frame divided by the product of
QUAD_CNT_MAX and SUB_FRAME_CNT_MAX.
PIX_CNT_MAX_SET_FAILED
0
Read-only flag that indicates if the last setting of the PIX_CNT_MAX value is
successful. If the PIX_CNT_MAX is smaller than the minimum size required to
accommodate the reset and readout time, PIX_CNT_MAX_SET_FAILED is set.
LUMPED_DEAD_TIME
0
Dead time can be either distributed equally among all quads or can be lumped at
the end of each frame. Distributed quad dead time is typically better for phase
offset cancellation. Lumped frame dead time is typically better for reducing motion
artefacts and power consumption. By default, distributed dead time is used.
Dead time is automatically calculated by the device based on the values of the integration duty cycle and readout
time. If LUMPED_DEAD_TIME is set to 0, the dead time for each quad in relation to the number of system
clocks is given by Equation 1:
Quad Dead Time
PIX_CNT_MAX u 1 Integration Duty Cycle
Sensor Reset Time Readout Time
(1)
If LUMPED_DEAD_TIME is set to 1, then the dead time for each frame in relation to the number of system
clocks is given by Equation 2:
Frame Dead Time SUB_FRAME_CNT_MAX uQUAD_CNT_MAX u
ª¬PIX_CNT_MAX u 1 Integration Duty Cycle
Sensor Reset Time Readout Time º¼
(2)
Sensor reset time is equal to 720 system clock cycles. The readout time is given by Equation 9.
The calculation of PIX_CNT_MAX for when ALT_FRM_EN is 0 is given by Equation 3:
PIX_CNT_MAX
SYS_CLK_FREQ
FRAME_RATE uQUAD_CNT_MAX u SUB_FRAME_CNT_MAX
(3)
When ALT_FRM_EN is set to 1, alternate frames can have different frame times depending on the number of
sub-frames (parameters are described in Table 6). Also, in most cases alternate frames are combined to form a
single frame either internally or externally. In such cases, the frame rate is given by Equation 4:
SUB_FRM_CNT_MAX1
§
·
De-Aliasing Frame Rate = SET_FRAME_RATE u ¨
¸
SUB_FRM_CNT_MAX1
+
SUB_FRM_CNT_MAX2
©
¹
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7.3.1.4 Integration Time
Integration time is the time that the sensor demodulation and the illumination modulation are active. The
configurable parameters are listed in Table 7.
Table 7. Integration Time Parameters
PARAMETER
INTG_DUTY_CYCLE
DEFAULT
DESCRIPTION
13
This parameter controls the ratio of integration time to total frame time.
0
This flag indicates if the INTG_DUTY_CYCLE setting has taken effect. If the
INTG_DUTY_CYCLE is not feasible for a given set of conditions, this flag is set.
This flag is cleared when a feasible value of INTG_DUTY_CYCLE is programmed.
If this flag is set, a lower value of INTG_DUTY_CYCLE must be programmed and
the value of the flag checked again. This process must be repeated until the flag
clears.
INTG_DUTY_CYCLE_
SET_FAILED
The INTG_DUTY_CYCLE registers allows 64 settings from 0 to 63. The relationship between effective
integration duty cycle of the base frame and the register value is given by Equation 5:
INTG_DUTY_CYCLE =
Integration Duty Cycle u64
100
(5)
Internally, the INTG_DUTY_CYCLE value is clamped to a minimum of 1. Maximum integration duty cycle is given
by Equation 6:
Maximum Integration Duty Cycle =
PIX_CNT_MAX
Reset Time + Readout Time
PIX_CNT_MAX
(6)
The INTG_DUTY_CYCLE parameter must be reprogrammed whenever any of the registers related to frame rate
control or region of interest are programmed. The related registers are:
• SUB_FRAME_CNT_MAX1
• SUB_FRAME_CNT_MAX2
• PIX_CNT_MAX
• LUMPED_DEAD_TIME
• ROW_START
• COL_START
• ROW_END
• COL_END
When the OPT8320 is in slave mode, the duty cycle still corresponds to the frame length calculated as per the
internal registers and not as per the period of the external sync signal. The sync signal period must be large
enough to make sure that the frame data are streamed successfully. When the sync signal period is larger than
the internal frame period, the actual integration duty cycle is less than the programmed value.
7.3.1.4.1 High Dynamic Range Functionality
When frame alternation is enabled, alternate frames can use different integration times. The supplementary
frame integration time is scaled down as compared to the base frame by a factor. The relevant parameters are
listed in Table 8.
Table 8. High Dynamic Range Functionality Parameter
PARAMETER NAME
DEFAULT
SUP_FRM_INTG_SCALE
63
DESCRIPTION
Denotes the percentage of INTG_PHASE in the supplementary frame in terms
of the base frame. INTG_DUTY_CYCLE2 = INTG_DUTY_CYCLE1 ×
(SUP_FRM_INTG_SCALE + 1) / 64.
The supplementary frame integration time is given in Equation 7:
Supplementary Frame Integration Time =
SUP_FRM_INTG_SCALE + 1
Base Frame Integration Time u
64
14
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7.3.2 Pixel Array
The pixel array consists of 80 × 60 demodulating pixels. With a 30-μm × 30-μm pixel size, the pixels exhibit
excellent dynamic range. The pixels also have a built-in shutter feature that helps in achieving higher ambient
robustness. For convenience, either the entire or part of the pixel array can be readout through register
configurations.
7.3.2.1 Region of Interest (ROI)
A subset of the sensor array can be readout to enhance frame rate or to reduce the power consumption of the
ToF system. An ROI is comprised of a set of row and column limits. The row and column counts start from zero.
Both row and column limits can be any of the valid row numbers for the given sensor size. The relevant
parameters are listed in Table 9.
Table 9. ROI Parameters
PARAMETER
DEFAULT
DESCRIPTION
ROW_START
0
Start address for the row address bus
COL_START
0
Start address for the column address bus
ROW_END
59
End address for the row address bus
COL_END
79
End address for the column address bus
Sensor readout time is affected by ROI. A minimum row-to-row switching time of half the row readout time is
enforced internally. Thus, reducing the column count to less than half of the total number of columns for a given
sensor does not lead to a reduction in sensor readout time. For a number of columns greater than the total
number of columns divided by 2, use Equation 8:
Readout Time = Preparation Time + ª¬ Rows + 1 u Cols + 1 º¼
Measured in System Clock Cycles
(8)
For a number of columns less than half of the total number of columns, use Equation 9:
Readout Time = Preparation Time + ª¬ Rows + 1 u Total Cols/2 + 1 º¼
Measured in System Clock Cycles
where:
•
Preparation time = 100 clock cycles
(9)
7.3.2.2 Readout Sequence
The readout sequence can be controlled to achieve mirroring along horizontal or vertical axis. The programmable
parameters are listed in Table 10.
Table 10. Readout Sequence Parameters
PARAMETER
DEFAULT
ROW_RDOUT_DIR
0
COL_RDOUT_DIR
0
DESCRIPTION
0 = Vertical inversion disabled
1 = Vertical inversion enabled
0 = Horizontal inversion disabled
1 = Horizontal inversion enabled
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7.3.2.3 Shutter Operation
Shutter operation can be used to control the exposure to ambient light. The shutter switch separates the charge
storage node from the pixel charge collection node. The shutter can be programmed to become inactive (switch
is on) at the start of integration and become active (switch is off) at the end of integration time to avoid collection
of unwanted ambient light during the sensor readout. The behavior of the shutter switch is shown in Table 11.
Table 11. Shutter Operation
QUAD STATE
OPERATION
RESET
INTEGRATION
READOUT
QUAD DEAD
TIME
State of the shutter software with the shutter operation
enabled (default)
On
On
Off
Off
State of the shutter software with the shutter operation
disabled
On
On
On
On
The SHUTTER_EN parameter enables or disables the shutter operation. The SHUTTER_EN description is given
in Table 12.
Table 12. Shutter Operation Registers
PARAMETER
DEFAULT
SHUTTER_EN
0
DESCRIPTION
Set to 1 to enable shutter operation.
7.3.3 Modulation Block
The OPT8320 modulation block provides the high-frequency demodulation to the pixels as well as the
illumination module. The modulation block controls the phase between the modulation signals connected to the
pixels and the illumination module from quad to quad.
7.3.3.1 Sensor Output Signals
The phase between illumination modulation and the sensor demodulation signals is stepped automatically as per
the quad number illustrated in Figure 6. Because the OPT8320 uses four quads per modulation frequency, the
phase is typically stepped between 0º, 90º, 180º, and 270º. The phase stepping sequence of the sensor is
programmable through the OPT8320 registers. A different sequence can be enabled for odd and even subframes. Also, the phase registers for the base frequency and de-aliasing frequency are separately
programmable. The OPT8320 output signals are listed in Table 13.
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Quad
Integration
ILLUM_EN
ILLUM_P
ILLUM_N
DMIX0
DMIX1
phq
ILLUM_P
ILLUM_N
DMIX0
DMIX1
Figure 6. Integration Timing Diagram
Table 13. Sensor Output Signals
PIN NAME
DESCRIPTION
ILLUM_P
High-frequency input to the illumination driver, noninverting. Modulates during integration time. Held low by default
during rest of the time.
ILLUM_N
High-frequency input to the illumination driver, inverting. Modulates during integration time. Held high by default during
rest of the time.
ILLUM_EN
If an external driver is used for driving the illumination current, this signal can be used to switch the driver between
active and standby mode. Normally, this signal is active high just before the integration time and goes low just after the
integration time.
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The programmable parameters are listed in Table 14 and Table 15.
Table 14. Pin Programmability
PARAMETER
DEFAULT
DESCRIPTION
MODULATION_HOLD
0
Disable modulation during the integration period. Set to 0 for normal operation.
DEMOD_STATIC_POL
0
DC state of illumination pins during the integration period if MODULATION_HOLD
= 1.
ILLUM_STATIC_POL
0
DC state of illumination pins during the integration period if MODULATION_HOLD
= 1. ILLUM_P = ILLUM_STATIC_POL, ILLUM_N = not (ILLUM_STATIC_POL).
ILLUM_EN_EARLY
0
Activates the illumination enable signal 15 µs before the integration period starts
when set to 1.
ILLUM_DC_CORR_DIR
0
Sets the direction of the duty cycle correction for illumination output waveforms.
Note that when duty cycle is increased, the ILLUM_P duty cycle increases and the
ILLUM_N duty cycle decreases.
0 = Increases duty cycle
1 = Reduces duty cycle
ILLUM_DC_CORR
0
The illumination duty cycle can be corrected in steps of approximately 450 ps. The
maximum value of this register is 11 (0Bh), resulting in a total correction of
approximately ±5 ns.
Table 15. Phase Sequence Programmability
PARAMETER
DEFAULT
DESCRIPTION
QUAD_HOP_EN
0
Enables a different sequence of quads for odd and even sub-frames
QUAD_HOP_OFFSET
0
The offset of the quad sequence for alternate sub-frames
The relative phase of the illumination modulation with respect to sensor modulation (Phq for any quad) can be
calculated as shown in Equation 10:
Phq = 360 u
Quad Number
QUAD_CNT_MAX
(10)
Note that the quad number is offset by the quad hop offset for that sub-frame.
The effective quad number = quad number + quad hop offset.
7.3.3.2 Modulation Frequency
The OPT8320 sensor has an internal PLL for generating the base modulation frequency (MOD_F) and the
supplementary frame frequency. The formula for calculating the modulation frequency is given in Equation 11:
MOD_M u 24 MHz
MOD_F
2
MOD_N-1
u QUAD_CNT_MAX u 1 + MOD_PS
(11)
The internal VCO frequency is given by Equation 12:
VCO_FREQ
MOD_M u 24 MHz
2
18
MOD_N-1
(12)
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MOD_M and MOD_N must be chosen to meet the internal VCO frequency range limitation. The internal VCO
can operate between 300 MHz and 600 MHz. The PLL block diagram is shown in Figure 7.
SYS_CLK
(24 MHz)
Divide by 2(MOD_N-1)
PFD
VCO
Divide by
[QUAD_CNT_MAX x
(MOD PS + 1)]
MOD_F
Divide by MOD_M
Figure 7. Modulation PLL Block Diagram
To enable accurate setting of the desired modulation frequency, MOD_M is split into an integer and a fractional
part. The effective MOD_M is given by Equation 13:
Effective MOD_M = MOD_M +
MOD_M_FRAC
2 16
(13)
The programmable parameters are listed in Table 16. The default base modulation frequency on start-up is
48 MHz.
Table 16. Programmable Parameters
PARAMETER
DEFAULT
DESCRIPTION
MOD_M
16
VCO multiplier
MOD_M_FRAC
0
VCO multiplier
MOD_N
1
VCO divider
MOD_PS
1
Divider for generation of the base modulation frequency
MOD_PLL_UPDATE
0
Set this bit to 1 and back to 0 for updating any modulation frequency
setting.
7.3.4 Depth Engine
The depth engine calculates the phase and amplitude information using the digitized data obtained from the
sensor block. The depth engine uses an internal RAM to temporarily store the data obtained and to process data.
The data engine has the following features:
• Phase, amplitude calculation
• Binning
• De-aliasing
• Histogram computation
• Phase offset correction
• Temperature correction
• Nonlinearity correction
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7.3.4.1 Phase Data
The computed phase for each pixel is proportional to the distance of the corresponding object in the scene. For a
phase varying from 0 π to 2 π, the distance varies from 0 to R, where R is the unambiguous range. The
equations describing the relationship between phase and distance are given in Equation 14 and Equation 15.
Phase × R
2N
C
R=
2F
d=
(14)
where
•
•
C is the speed of light
F is the modulation frequency
(15)
At the output of the depth processor block, the phase of 2 π is typically represented by a full 12-bit code (that is,
212). If the application requires the distance (in meters) of the points in the scene, this value must be calculated
from the OPT8320 output using Equation 16:
d=
Phase u R
2 12
(16)
Equation 16 assumes that the phase has no offset. If offset correction is not done within the OPT8320, the
formula is as shown in Equation 17:
d=
Phase Offset × R
2 12
(17)
7.3.4.2 De-Aliasing
The unambiguous range of a ToF system is defined by the modulation frequency (F). The unambiguous range is
given by Equation 18:
R=
C
2F
where
•
C is the speed of light in the medium
(18)
For example, for a modulation frequency of 50 MHz, R = 3m in open air. If the total range of the application is
beyond the unambiguous range for a given modulation frequency, de-aliasing can be enabled to extend the
unambiguous range. The OPT8320 employs a dual modulation frequency technique to extend the unambiguous
range. Two different frames are used to phase data corresponding to base frequency and supplementary
frequency. The supplementary frequency is chosen to be lower than the base frequency and sets the
unambiguous range. For example, if the base frequency is F, the supplementary frequency is chosen to be F / 4
to increase the unambiguous range by four times. The data from the two frames can then be combined to obtain
the unambiguous phase. To provide a full 16-bit phase after range extension, the flag bits in the data stream are
replaced by the MSBs of the de-aliased phase automatically when de-aliasing is enabled.
7.3.4.2.1 Procedure for Enabling De-Aliasing Mode
1.
2.
3.
4.
5.
6.
7.
20
Disable the timing generator by setting the TG_EN parameter to 0.
Set the ALT_FRM_EN parameter to enable alternate frames.
Set the ALT_FREQ_SEL parameter to select the range extension ratio.
Set the phase calibration parameters for each frequency as described in the Phase Offset Correction section.
Set SUB_FRAME_CNT_MAX1 and SUB_FRAME_CNT_MAX2 for the base and supplementary frames.
Set the PIX_CNT_MAX parameter to meet the frame rate requirements.
Set INTG_DUTY_CYCLE and SUP_FRM_INTG_SCALE to set the integration time for the base and
supplementary frames.
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8. Set the DEALIAS_EN parameter to 1 to combine the frames. Note that if the DEALIAS_EN parameter is not
set, the base and supplementary frame data are given out as is. If the DEALIAS_EN parameter is set, the
base and supplementary frame data are combined to give out de-aliased data and the effective frame rate
must be recalculated as per Equation 4.
9. Enable the timing generator using the TG_ENABLE parameter.
7.3.4.3 Binning
Multiple pixel data can be averaged to form a single large pixel data. This feature is useful in cases where the
application requires less pixel resolution but needs better phase noise performance. Rows and columns can be
binned in powers of 2. The programmable parameters are listed in Table 17.
Table 17. Binning Parameters
PARAMETER
DEFAULT
DESCRIPTION
ROWS_TO_MERGE
0
number of rows to merge for binning = 2ROWS_TO_MERGE
COLS_TO_MERGE
0
Number of columns to merge for binning = 2COLS_TO_MERGE
7.3.4.4 Auxiliary Depth Data
Amplitude data represents the amplitude of the received signal at each pixel. If the amplitude is higher, signal
amplitude is higher and thus the phase SNR is higher. The amplitude output value is given by Equation 19:
Amplitude 4 2 u 2 12 u Signal Amplitude u0.825
where
•
the signal amplitude is the amplitude of the single-ended modulating signal (A or B) generated on the pixel in
each quad
(19)
When binning is enabled, the signal amplitude is the vector sum of the signals of all the binned pixels divided by
the nearest power of 2 that is greater than the number of pixels binned together.
Ambient data are an indicator of the non-modulating component of voltage on the pixels. Ambient data are the
sum of the ambient light, pixel offsets, and the non-demodulated component of the ToF illumination. The output
ambient data values decrease with increase in voltage. Therefore, near-zero values indicate pixel saturation.
The OPT8320 provides masking of data based on the amplitude and single-ended voltage values in a pixel for
the purpose of basic filtering. The related parameters are listed in Table 18.
Table 18. Auxiliary Depth Data Parameters
PARAMETER
DEFAULT
DESCRIPTION
AMPLITUDE_THRESHOLD
0
If the amplitude of the pixel is lower than this number, the pixel
phase data are set to 000h
IQ_SCALE
0
Left shifts the acquired sensor data by the configured value. The
scaling results in an equivalent scaling in amplitude. Care must be
taken to avoid bit overflow in the depth engine because this scaling
is done before the computation of phase and amplitude.
IQ_SCALE_EN
0
When set to '1', enable scaling of I and Q according to the iq_scale
register
SATURATION_THRESHOLD
0
The saturation flag is set if the ambient value of the pixel is less than
or equal to this value. Also, pixel phase data are set to 000h.
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Flags[3:0] indicate important pixel data reliability parameters. The flags are described in Table 19.
Table 19. Flag Data
FLAG BIT
DEFAULT
DEALIAS_EN = 1
Flag[3]
0 = No pixel saturation
1 = Pixel is saturated
Phase[15]
Flag[2]
Reserved. Set to 0.
Phase[14]
Flag[1]
Frame counter[1]
Phase[13]
Flag[0]
Frame counter[0]
Phase[12]
When de-aliasing is enabled, an additional option to provide flags instead of ambient data is provided using the
MV_FLAGS_TO_AMBIENT parameter.
7.3.4.5 Phase Offset Correction
Time delay between sensor modulation and the illumination modulation manifests as phase offset. The offset
must be calibrated individually for each system because this delay can vary from one system to another. The
measured offset can be programmed into a PHASE_CORR parameter in the OPT8320 registers. The device
adds the PHASE_CORR parameter to the computed phase. The programmable parameters are listed in
Table 20.
Table 20. Phase Offset Correction Parameters
PARAMETER
DESCRIPTION
PHASE_CORR_1
Phase offset correction for the base frame
PHASE_CORR_2
Phase offset correction for the supplementary frame
DISABLE_OFFSET_CORR
Disables phase offset correction in the device. Phase offset correction is enabled by default.
System delays in the illumination and sensor modulation path can vary differently as a result of temperature
variations. This variation leads to a change in the measured phase. To compensate for phase change versus
temperature, the OPT8320 uses two programmable temperature coefficients. The built-in temperature sensor in
the OPT8320 is used for measuring the ToF sensor temperature, and an external I2C interface-based
temperature sensor is used for measuring the illumination driver temperature. The programmable parameters are
listed in Table 21.
Table 21. Temperature Coefficient Parameters
PARAMETER
DESCRIPTION
TILLUM_CALIB
Illumination driver temperature when PHASE_CORR is measured.
TSENSOR_CALIB
Sensor temperature when PHASE_CORR is measured.
COEFF_ILLUM
Phase versus temperature coefficients for the illumination driver for the base frame.
COEFF_SENSOR
Phase versus temperature coefficients for the sensor for the base frame.
DISABLE_TEMP_CORR
Disables phase offset correction resulting from temperature.
(Temperature correction is enabled by default.)
CALIB_PREC
Adjusts the precision of temperature correction. Coefficients are scaled by CALIB_PREC. Internal
COEFF = [programmed COEFF
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