PCA8550DBR

PCA8550 NONVOLATILE 5-BIT REGISTER WITH I2C INTERFACE SCPS050A – MARCH 1999 – REVISED APRIL 1999 D D D D D D D D EPIC  (Enhanced-Performance Implanted CMOS) Submicron Process Useful for Jumperless Configuration of PC Motherboard Inputs Accept Voltages to 5.5 V MUX OUT Signals are 2.5-V Outputs NON-MUXED OUT Signal is a 3.3-V Output Minimum of 1000 Write Cycles Minimum of 10 Years Data Retention Package Options Include Plastic Small-Outline (D), Shrink Small-Outline (DB), and Thin Shrink Small-Outline (PW) Packages D, DB, OR PW PACKAGE (TOP VIEW) I2C SCL I2C SDA OVERRIDE MUX IN A MUX IN B MUX IN C MUX IN D GND 1 16 2 15 3 14 4 13 5 12 6 11 7 10 8 9 VCC WP NON-MUXED OUT MUX SELECT MUX OUT A MUX OUT B MUX OUT C MUX OUT D description This 4-bit 1-of-2 multiplexer with I2C input interface is designed for 3-V to 3.6-V VCC operation. The PCA8550 is designed to multiplex four bits of data from parallel inputs or from I2C input data stored in a nonvolatile register. An additional bit of register output also is provided, which is latched to prevent changes in the output value during the write cycle. The factory default for the contents of the register is all low. These stored values can be read from, or written to, using the I2C bus. The ability to control writing to the register is provided by the write protect (WP) input. The override (OVERRIDE) input forces all the register outputs to a low. This device provides a fast-mode (400 kbit/s) or standard-mode (100 kbit/s) I2C serial interface for data input and output. The implementation is as a slave. The device address is specified in the I2C interface definition table. Both of the I2C Schmitt-trigger inputs (SCL and SDA) provide integrated pullup resistors and are 5-V tolerant. The PCA8550 is characterized for operation from 0°C to 70°C. FUNCTION TABLE INPUTS OUTPUTS MUX OUT NON-MUXED OUT MUX SELECT OVERRIDE L L L L L H Nonvolatile register Nonvolatile register H X MUX IN Latched NON-MUXED OUT† † The latched NON-MUXED OUT state is the value present on the NON-MUXED OUT output at the time the MUX SELECT input transitions from the low to the high state. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. EPIC is a trademark of Texas Instruments Incorporated. Copyright  1999, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 PCA8550 NONVOLATILE 5-BIT REGISTER WITH I2C INTERFACE SCPS050A – MARCH 1999 – REVISED APRIL 1999 logic diagram (positive logic) VCC SCL I2C Interface Logic 1 2 5-Bit Nonvolatile Register Address: 1001110 SDA VCC VCC 15 WP OVERRIDE 3 1-Bit Transparent Latch VCC 14 MUX IN A MUX IN B MUX IN C MUX IN D 4 12 5 11 MUX OUT A 4-Bit 1-of-2 Multiplexer 6 2 10 9 7 VCC MUX SELECT NON-MUXED OUT 13 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 MUX OUT B MUX OUT C MUX OUT D PCA8550 NONVOLATILE 5-BIT REGISTER WITH I2C INTERFACE SCPS050A – MARCH 1999 – REVISED APRIL 1999 I2C interface I2C communication with this device is initiated by a master sending a start condition, a high-to-low transition on the serial data (SDA) input/output while the serial clock (SCL) input is high. After the start condition, the device address byte is sent, MSB first, including the data-direction bit (R/W). This device does not respond to the general call address. After receiving the valid address byte, this device responds with an acknowledge, a low on the SDA input/output during the high of the acknowledge-related clock pulse. The data byte follows the address acknowledge. If the R/W bit is high, the data from this device are the values read from the nonvolatile register. If the R/W bit is low, the data are from the master, to be written into the register. A valid data byte is one in which the three high-order bits are low. The first valid data byte that is received is written into the register, following the stop condition. If an invalid data byte is received, it is acknowledged, but is not written into the register. The data byte is followed by an acknowledge sent from this device. If other data bytes are sent from the master following the acknowledge, they are ignored by this device. A stop condition, a low-to-high transition on the SDA input/output while the SCL input is high, is sent by the master. If the WP input is low during the falling edge of the first valid data byte acknowledge on the SCL input and the R/W bit is low, the stop condition causes the I2C interface logic to write the data byte value into the nonvolatile register. Data are written only if complete bytes are received and acknowledged. Writing to the register takes time (twr), during which the device does not respond to its slave address. If the WP input is high, the I2C interface logic does not write to the register. I2C INTERFACE DEFINITION TABLE BIT BYTE Address Data 4 3 2 1 0 (LSB) L H H H L R/W L NONMUXED OUT MUX OUT D MUX OUT C MUX OUT B MUX OUT A 7 (MSB) 6 5 H L L L absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 6.5 V Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 6.5 V Output voltage range, VO (SDA) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 6.5 V Output voltage range, VO (MUX OUT outputs) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 2.9 V Output voltage range, VO (NON-MUXED OUT output) (see Notes 1 and 2) . . . . . . . . . –0.5 V to VCC + 0.5 V Input clamp current, IIK (VI < 0 ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA Output clamp current, IOK (VO < 0 or VO > VCC) (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . –50 mA, +10 mA Input/output clamp current, IOK (VO < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA Continuous output current, IO (VO = 0 to VCC) (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±15 mA Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±30 mA Package thermal impedance, θJA (see Note 3): D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113°C/W DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131°C/W PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149°C/W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 85°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed. 2. The value of VCC is provided in the recommended operating conditions table. 3. The package thermal impedance is calculated in accordance with JESD 51. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3 PCA8550 NONVOLATILE 5-BIT REGISTER WITH I2C INTERFACE SCPS050A – MARCH 1999 – REVISED APRIL 1999 recommended operating conditions VCC Supply voltage VIH High-level input voltage VIL Low-level input voltage IOH High-level output current IOL Low-level output current ∆t/∆v Input transition rise or fall rate TA Operating free-air temperature MIN MAX 3 3.6 2.7 4 2 4 SCL, SDA –0.5 0.9 OVERRIDE, MUX IN, MUX SELECT, WP –0.5 0.8 SCL, SDA OVERRIDE, MUX IN, MUX SELECT, WP MUX OUT, NON-MUXED OUT –2 SDA 6 MUX OUT, NON-MUXED OUT 2 OVERRIDE, MUX IN, MUX SELECT, WP 0 UNIT V V V mA mA 10 ns/V 70 °C electrical characteristics over recommended operating free-air temperature range, VCC = 3.3 V ± 0.3 V (unless otherwise noted) PARAMETER VIK Vhys† Input diode clamp voltage MIN 0.19 NON MUXED OUT NON-MUXED IOH = –100 µA IOH = –2 mA MUX OUT IOL = 100 µA IOL = 2 mA –0.3 0.4 –0.3 0.7 NON MUXED OUT NON-MUXED IOL = 100 µA IOL = 2 mA –0.5 0.4 –0.5 0.7 SDA IOL = 3 mA IOL = 6 mA VIH = 2.4 V VIL = 0.4 V MUX IN ICC During read or write cycle Not during read or write cycle VI = 0 to VCC, VI = VCC, IO = 0, IO = 0 Ci VI = VCC or GND † Vhys is the hysteresis of Schmitt-trigger inputs. 4 POST OFFICE BOX 655303 2.625 1.7 2.625 2.4 3.6 2 3.6 V V 0.6 SCL, SDA OVERRIDE, MUX SELECT, WP 2 0.4 MUX IN IIL V MUX OUT OVERRIDE, MUX SELECT, WP UNIT V IOH = –100 µA IOH = –1 mA SCL, SDA IIH MAX –1.5 SCL, SDA VOH VOL TEST CONDITIONS II = –18 mA • DALLAS, TEXAS 75265 VCC = 3.3 V –1.5 –12 –20 –100 –0.166 –0.75 –7 –32 –86 –267 –0.72 –2 mA 10 mA 500 µA 10 pF µA mA µA PCA8550 NONVOLATILE 5-BIT REGISTER WITH I2C INTERFACE SCPS050A – MARCH 1999 – REVISED APRIL 1999 nonvolatile storage specifications PARAMETER SPECIFICATIONS Write time (twr) 10 ms, typical Memory-cell data retention 10 years, minimum Maximum number of memory-cell write cycles 1000 cycles, minimum I2C interface timing requirements over recommended operating free-air temperature range (unless otherwise noted) (see Figure 1) VCC = 3.3 V ± 0.3 V MIN MAX fscl Tsch I2C clock frequency I2C clock high time Tscl Tsp I2C clock low time I2C spike time 1.3 Tsds Tsdh I2C serial data setup time I2C serial data hold time 100 Ticr Ticf I2C input rise time I2C input fall time Tocf Tbuf I2C output fall time (10-pF to 400-pF bus) I2C bus free time between stop and start Tsts Tsth Tsps Cb† 10 UNIT 400 kHz 600 ns µs 0 50 ns ns 0 900 ns 20 300 ns 300 ns 20 20 + 0.1 Cb† 250 ns 1.3 µs I2C start or repeated start condition setup I2C start or repeated start condition hold 600 ns 600 ns I2C stop condition setup I2C bus capacitive load 600 ns 400 pF † Cb = capacitance of one bus line in pF. switching characteristics over recommended operating free-air temperature range (unless otherwise noted) (see Figure 2) PARAMETER VCC = 3.3 V ± 0.3 V FROM (INPUT) TO (OUTPUT) MUX IN MUX OUT 20 ns MIN UNIT MAX tmpd Mux input to output propagation delay tsov MUX SELECT to output valid MUX SELECT Output valid 22 ns tovn OVERRIDE to NON-MUXED OUT output delay OVERRIDE NON-MUXED OUT 15 ns tovm OVERRIDE to MUX OUT output delay OVERRIDE MUX OUT 25 ns tsu Setup time WP Falling edge of first valid data byte acknowledge on the SCL input 30 ns th Hold time WP Falling edge of first valid data byte acknowledge on the SCL input 120 ns tr Output rise time 1 3 ns/V tf Output fall time 1 3 ns/V POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5 PCA8550 NONVOLATILE 5-BIT REGISTER WITH I2C INTERFACE SCPS050A – MARCH 1999 – REVISED APRIL 1999 PARAMETER MEASUREMENT INFORMATION VO = 3.3 V RL = 1 kΩ DUT CL = 10 pF or CL = 400 pF GND LOAD CIRCUIT 2 Bytes for Complete Device Programming Stop Condition (P) Start Condition (S) Bit 7 MSB Bit 0 LSB (R/W) Bit 6 Stop Condition (P) Acknowledge (A) 2.7 V 1.5 V WP 1.5 V 0V th tsu Tscl Tsts Tsch 0.7 × VCC SCL 0.3 × VCC ticr tPHL ticf Tbuf tPLH Tsp 0.7 × VCC SDA 0.3 × VCC Ticf Ticr Tsth Tsdh Tsds Tsps Repeat Start Condition Start or Repeat Start Condition VOLTAGE WAVEFORMS BYTE DESCRIPTION 1 I2C address 2 Nonvolatile register data Figure 1. I2C Interface Load Circuit and Voltage Waveforms 6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 Stop Condition PCA8550 NONVOLATILE 5-BIT REGISTER WITH I2C INTERFACE SCPS050A – MARCH 1999 – REVISED APRIL 1999 PARAMETER MEASUREMENT INFORMATION From Output Under Test CL = 15 pF (see Note A) LOAD CIRCUIT 2.7 V Input 1.5 V 1.5 V 2.7 V Input 1.5 V 1.5 V 0V 0V tPHL tPLH Output (see Note D) 1.5 V 1.5 V VOH VOL Output (see Note E) 1.25 V 1.25 V VOH VOL VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES FOR MUXED OUT OUTPUTS VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES FOR NON-MUXED OUT OUTPUT NOTES: A. B. C. D. E. tPHL tPLH CL includes probe and jig capacitance. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf ≤ 2.5 ns. The outputs are measured one at a time with one transition per measurement. tPLH and tPHL are the same as tsov and tovn. tPLH and tPHL are the same as tmpd, tsov, and tovm. Figure 2. Load Circuit and Voltage Waveforms POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 7 IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those pertaining to warranty, patent infringement, and limitation of liability. TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent TI deems necessary to support this warranty. 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