PCA9548A
SCPS143G – JUNE 2009 – REVISEDPCA9548A
MARCH 2021
SCPS143G – JUNE 2009 – REVISED MARCH 2021
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PCA9548A Low Voltage 8-Channel I2C Switch with Reset
eight downstream pairs, or channels. Any individual
SCx/SDx channel or combination of channels can
be selected, determined by the contents of the
programmable control register. These downstream
channels can be used to resolve I2C slave address
conflicts. For example, if eight identical digital
temperature sensors are needed in the application,
one sensor can be connected at each channel: 0-7.
1 Features
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
1-of-8 Bidirectional Translating Switches
I2C Bus and SMBus Compatible
Active-Low Reset Input
Three Hardware Address Pins for Use of up to
Eight PCA9548A Devices on the I2C Bus
Channel Selection Via I2C Bus
Power-Up with All Switch Channels Deselected
Low RON Switches
Allows Voltage-Level Translation Between
1.8-V, 2.5-V, 3.3-V, and 5-V Buses
No Glitch on Power Up
Supports Hot Insertion
Low Standby Current
Operating Power-Supply Voltage Range of
2.3 V to 5.5 V
5-V Tolerant Inputs
0-kHz to 400-kHz Clock Frequency
Latch-Up Performance Exceeds 100 mA Per JESD
78, Class II
ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
– 1000-V Charged-Device Model (C101)
The system master can reset the PCA9548A in the
event of a time-out or other improper operation by
asserting a low in the RESET input. Similarly, the
power-on reset deselects all channels and initializes
the I2C/SMBus state machine. Asserting RESET
causes the same reset and initialization to occur
without powering down the part. This allows recovery
should once of the downstream I2C buses get stuck in
a low state.
The pass gates of the switches are constructed so
that the VCC pin can be used to limit the maximum
high voltage, which is passed by the PCA9548A.
This allows the use of different bus voltages on
each pair, so that 1.8-V, 2.5-V or 3.3-V parts can
communicate with 5-V parts, without any additional
protection. External pull-up resistors pull the bus up to
the desired voltage level for each channel. All I/O pins
are 5-V tolerant.
Device Information
2 Applications
•
•
•
•
DEVICE NAME
Servers
Routers (Telecom Switching Equipment)
Factory Automation
Products With I2C Slave Address Conflicts (For
Example, Multiple, Identical Temp Sensors)
PCA9548A
3 Description
(1)
The PCA9548A device has eight bidirectional
translating switches that can be controlled through
the I2C bus. The SCL/SDA upstream pair fans out to
VCC
I2C or SMBus
Master
BODY SIZE (NOM)
SSOP (24)
8.20 mm × 5.30 mm
TVSOP (24)
5.00 mm × 4.40 mm
SOIC (24)
15.40 mm × 7.50 mm
TSSOP (24)
7.80 mm × 4.40 mm
VQFN (24)
4.00 mm × 4.00 mm
For all available packages, see the orderable addendum at
the end of the datasheet.
Channel 0
SDA
SCL
SD0
SC0
RESET
SD1
SC1
(processor)
PACKAGE(1)
Slaves A0, A1...AN
Channel 1
Slaves B0, B1...BN
PCA9548A
A0
A1
A2
GND
SD2
SC2
Channel 2
Slaves C0, C1...CN
Channel 7
SD7
SC7
Slaves H0, H1...HN
Simplified Schematic
An©IMPORTANT
NOTICEIncorporated
at the end of this data sheet addresses availability, warranty, changes, use in
safety-critical
applications,
Copyright
2021 Texas Instruments
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SCPS143G – JUNE 2009 – REVISED MARCH 2021
Table of Contents
1 Features............................................................................1
2 Applications..................................................................... 1
3 Description.......................................................................1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................3
6 Specifications.................................................................. 5
6.1 Absolute Maximum Ratings........................................ 5
6.2 ESD Ratings............................................................... 5
6.3 Recommended Operating Conditions.........................5
6.4 Thermal Information....................................................5
6.5 Electrical Characteristics.............................................6
6.6 I2C Interface Timing Requirements.............................7
6.7 Reset Timing Requirements........................................8
6.8 Switching Characteristics............................................8
6.9 Typical Characteristics................................................ 9
7 Parameter Measurement Information.......................... 10
8 Detailed Description......................................................12
8.1 Overview................................................................... 12
8.2 Functional Block Diagram......................................... 13
8.3 Feature Description...................................................13
8.4 Device Functional Modes..........................................14
8.5 Programming............................................................ 14
8.6 Register Maps...........................................................15
9 Application Information Disclaimer............................. 19
9.1 Application Information............................................. 19
9.2 Typical Application.................................................... 19
10 Power Supply Recommendations..............................23
10.1 Power-On Reset Requirements.............................. 23
11 Layout........................................................................... 25
11.1 Layout Guidelines................................................... 25
11.2 Layout Example...................................................... 26
12 Device and Documentation Support..........................27
12.1 Related Documentation.......................................... 27
12.2 Receiving Notification of Documentation Updates..27
12.3 Support Resources................................................. 27
12.4 Trademarks............................................................. 27
12.5 Electrostatic Discharge Caution..............................27
12.6 Glossary..................................................................27
13 Mechanical, Packaging, and Orderable
Information.................................................................... 27
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision F (April 2019) to Revision G (March 2021)
Page
• Changed the PW and RGE package values in the Thermal Information. ..........................................................5
• Changed the VPORR row in the Electrical Characteristics .................................................................................. 6
• Added VPORF row to the Electrical Characteristics ............................................................................................ 6
• Changed the ICC Low inputs and High inputs values in the Electrical Characteristics .......................................6
• Changed the Power Supply Recommendations .............................................................................................. 23
Changes from Revision E (February 2015) to Revision F (April 2019)
Page
• Updated the Section 3 section ...........................................................................................................................1
• Changed the Pin Configuration images.............................................................................................................. 3
• Updated Pin Name for Pin 8 From: SC2 To: SD2 in the Pin Functions table..................................................... 3
• Added the Typical Characteristics section.......................................................................................................... 9
Changes from Revision D (June 2014) to Revision E (February 2015)
Page
• Changed front page image................................................................................................................................. 1
• Added Thermal Information. .............................................................................................................................. 5
• Changed Note (2) in the Electrical Characteristics ............................................................................................. 6
• Added Layout Example.....................................................................................................................................26
Changes from Revision C (June 2007) to Revision D (June 2014)
Page
• Added RESET Errata section........................................................................................................................... 14
• Updated Typical Application schematic. .......................................................................................................... 19
2
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SCPS143G – JUNE 2009 – REVISED MARCH 2021
5 Pin Configuration and Functions
A0
1
24
VCC
A1
2
23
SDA
RE SET
3
22
SCL
SD0
4
21
A2
SC0
5
20
SC7
SD1
6
19
SD7
SC1
7
18
SC6
SD2
8
17
SD6
SC2
9
16
SC5
SD3
10
15
SD5
SC3
11
14
SC4
GND
12
13
SD4
No t to scale
Figure 5-1. DB, DGV, DW or PW Package, 24-Pin SSOP, TVSOP, SOIC or TSSOP , Top View
Table 5-1. Pin Functions
PIN
NO.
NAME
A0
I/O
DESCRIPTION
DB, DW, DGV ,
PW
1
I
Address input 0. Connect directly to VCC or ground
A1
2
I
Address input 1. Connect directly to VCC or ground
RESET
3
I
SD0
4
I/O
Active-low reset input. Connect to VCC through a pull-up resistor, if not used
Serial data 0. Connect to VCC through a pull-up resistor
SC0
5
I/O
Serial clock 0. Connect to VCC through a pull-up resistor
SD1
6
I/O
Serial data 1. Connect to VCC through a pull-up resistor
SC1
7
I/O
Serial clock 1. Connect to VCC through a pull-up resistor
SD2
8
I/O
Serial data 2. Connect to VCC through a pull-up resistor
SC2
9
I/O
Serial clock 2. Connect to VCC through a pull-up resistor
SD3
10
I/O
Serial data 3. Connect to VCC through a pull-up resistor
SC3
11
I/O
Serial clock 3. Connect to VCC through a pull-up resistor
GND
12
—
Ground
SD4
13
I/O
Serial data 4. Connect to VCC through a pull-up resistor
SC4
14
I/O
Serial clock 4. Connect to VCC through a pull-up resistor
Serial data 5. Connect to VCC through a pull-up resistor
SD5
15
I/O
SC5
16
I/O
Serial clock 5. Connect to VCC through a pull-up resistor
SD6
17
I/O
Serial data 6. Connect to VCC through a pull-up resistor
SC6
18
I/O
Serial clock 6. Connect to VCC through a pull-up resistor
SD7
19
I/O
Serial data 7. Connect to VCC through a pull-up resistor
SC7
20
I/O
A2
21
I
Serial clock 7. Connect to VCC through a pull-up resistor
SCL
22
I/O
Serial clock bus. Connect to VCC through a pull-up resistor
SDA
23
I/O
Serial data bus. Connect to VCC through a pull-up resistor
VCC
24
—
Supply voltage
Address input 2. Connect directly to VCC or ground
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RE SET
A1
A0
VCC
SDA
SCL
24
23
22
21
20
19
SCPS143G – JUNE 2009 – REVISED MARCH 2021
SD0
1
18
A2
SC0
2
17
SC7
SD1
3
16
SD7
15
SC6
Th ermal
Pad
11
12
SD5
SC5
SC4
13
10
6
SD4
SC2
9
SD6
GND
14
8
5
SC3
SD2
7
4
SD3
SC1
No t to scale
Figure 5-2. RGE Package, 24-Pin VQFN , Top View
Table 5-2. Pin Functions, RGE
PIN
NAME
4
NO.
I/O
DESCRIPTION
SD0
1
I/O
Serial data 0. Connect to VCC through a pull-up resistor
SC0
2
I/O
Serial clock 0. Connect to VCC through a pull-up resistor
SD1
3
I/O
Serial data 1. Connect to VCC through a pull-up resistor
SC1
4
I/O
Serial clock 1. Connect to VCC through a pull-up resistor
SD2
5
I/O
Serial data 2. Connect to VCC through a pull-up resistor
Serial clock 2. Connect to VCC through a pull-up resistor
SC2
6
I/O
SD3
7
I/O
Serial data 3. Connect to VCC through a pull-up resistor
SC3
8
I/O
Serial clock 3. Connect to VCC through a pull-up resistor
GND
9
—
Ground
SD4
10
I/O
Serial data 4. Connect to VCC through a pull-up resistor
SC4
11
I/O
Serial clock 4. Connect to VCC through a pull-up resistor
SD5
12
I/O
Serial data 5. Connect to VCC through a pull-up resistor
SC5
13
I/O
Serial clock 5. Connect to VCC through a pull-up resistor
SD6
14
I/O
Serial data 6. Connect to VCC through a pull-up resistor
SC6
15
I/O
Serial clock 6. Connect to VCC through a pull-up resistor
SD7
16
I/O
Serial data 7. Connect to VCC through a pull-up resistor
SC7
17
I/O
A2
18
I
SCL
19
I/O
Serial clock 7. Connect to VCC through a pull-up resistor
Address input 2. Connect directly to VCC or ground
Serial clock bus. Connect to VCC through a pull-up resistor
SDA
20
I/O
Serial data bus. Connect to VCC through a pull-up resistor
VCC
21
—
Supply voltage
A0
22
I
Address input 0. Connect directly to VCC or ground
A1
23
I
Address input 1. Connect directly to VCC or ground
RESET
24
I
Active-low reset input. Connect to VCC through a pull-up resistor, if not used
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
VCC
MIN
MAX
UNIT
Supply voltage
–0.5
7
V
voltage(2)
–0.5
7
V
–20
20
mA
VI
Input
II
Input current
IO
Output current
–25
25
mA
ICC
Supply current
–100
100
mA
Tstg
Storage temperature
–65
150
°C
(1)
(2)
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress
ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under
Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability.
The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.
6.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic
discharge
Human body model (HBM), per ANSI/ESDA/JEDEC
JS-001(1)
UNIT
±2000
Charged-device model (CDM), per JEDEC specification JESD22-C101 or
ANSI/ESDA/JEDEC JS-002(2)
V
±1000
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
See (1)
VCC
MAX
Supply voltage
VIH
High-level input voltage
VIL
Low-level input voltage
TA
Operating free-air temperature
(1)
MIN
2.3
5.5
SCL, SDA
0.7 × VCC
6
A2–A0, RESET
0.7 × VCC
VCC + 0.5
SCL, SDA
–0.5
0.3 × VCC
A2–A0, RESET
–0.5
0.3 × VCC
–40
85
UNIT
V
V
V
°C
All unused control inputs of the device must be held at VCC or GND to ensure proper device operation. See the Implications of Slow or
Floating CMOS Inputs application report.
6.4 Thermal Information
PCA9548A
THERMAL METRIC(1)
DB (SSOP)
DGV (TVSOP)
DW (SOIC)
PW (TSSOP)
RGE (VQFN)
UNIT
24 PINS
RθJA
Junction-to-ambient thermal resistance
89.1
99.6
73.2
108.8
57.2
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
51.1
31.1
41.3
54.1
62.5
°C/W
RθJB
Junction-to-board thermal resistance
46.6
53.1
42.9
62.7
34.4
°C/W
ψJT
Junction-to-top characterization parameter
18.5
0.9
15.3
10.9
3.8
°C/W
ψJB
Junction-to-board characterization parameter
46.3
52.6
42.6
62.3
34.4
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
N/A
N/A
N/A
N/A
15.5
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
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6.5 Electrical Characteristics
VCC = 2.3 V to 3.6 V, over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VPORR
Power-on reset voltage, VCC rising
VPORF
Power-on reset voltage, VCC falling(2) No load, VI = VCC or GND
MIN TYP(1)
VCC
No load, VI = VCC or GND
1.2
0.8
5V
Switch output voltage
Vi(sw) = VCC, ISWout = –100 μA
2.6
3.3 V
3 V to 3.6 V
VOL = 0.4 V
SDA
VOL = 0.6 V
2.3 V to 5.5 V
SCL, SDA
SC7–SC0, SD7–SD0
II
A2–A0
VI = VCC or GND
2.3 V to 5.5 V
RESET
1.9
VI = VCC or GND, IO = 0
Operating mode
fSCL = 100 kHz
VI = VCC or GND, IO = 0
ICC
Low inputs
VI = GND, IO = 0
Standby mode
High inputs
Supply-current
change
ΔICC
SCL, SDA
A2–A0
Ci
RESET
SCL
Cio(off) (3)
RON
SDA
SC7–SC0, SD7–SD0
Switch-on resistance
VI = VCC, IO = 0
SCL or SDA input at 0.6 V,
Other inputs at VCC or GND
SCL or SDA input at VCC – 0.6 V,
Other inputs at VCC or GND
VI = VCC or GND
VI = VCC or GND, Switch OFF
VO = 0.4 V, IO = 15 mA
6
2
3
6
6
9
mA
–1
1
–1
1
–1
1
μA
1
5.5 V
50
80
3.6 V
20
35
2.7 V
11
20
5.5 V
9
30
3.6 V
6
15
2.7 V
4
8
5.5 V
0.2
2
3.6 V
0.1
2
2.7 V
0.1
1
5.5 V
0.2
2
3.6 V
0.1
2
2.7 V
0.1
1
3
20
3
20
4
5
2.3 V to 5.5 V
μA
μA
2.3 V to 5.5 V
4
5
20
28
20
28
5.5
7.5
4
10
20
3 V to 3.6 V
5
12
30
2.3 V to 2.7 V
7
15
45
2.3 V to 5.5 V
4.5 V to 5.5 V
V
1.5
1.1
VI = VCC or GND, Switch OFF
VO = 0.4 V, IO = 10 mA
(1)
(2)
(3)
2.8
–1
fSCL = 400 kHz
V
V
4.5
1.6
2.5 V
2.3 V to 2.7 V
IOL
1.5
1
3.6
4.5 V to 5.5 V
Vo(sw)
MAX UNIT
pF
pF
Ω
All typical values are at nominal supply voltage (2.5-, 3.3-, or 5-V VCC), TA = 25°C.
The power-on reset circuit resets the I2C bus logic with VCC < VPORF.
Cio(ON) depends on internal capacitance and external capacitance added to the SCn lines when channels(s) are ON.
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6.6 I2C Interface Timing Requirements
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 7-1)
MIN
MAX
UNIT
STANDARD MODE
fscl
I2C clock frequency
tsch
I2C
tscl
I2C clock low time
tsp
I2C
tsds
I2C serial-data setup time
250
tsdh
I2C serial-data hold time
0(1)
ticr
I2C
input rise time
input fall time
0
clock high time
100
kHz
4
μs
4.7
μs
spike time
50
ns
ns
μs
1000
ns
300
ns
ticf
I2C
tocf
I2C output (SDn) fall time (10-pF to 400-pF bus)
tbuf
I2C bus free time between stop and start
4.7
tsts
I2C start or repeated start condition setup
4.7
μs
tsth
I2C start or repeated start condition hold
4
μs
tsps
I2C stop condition setup
tvdL(Data)
Valid-data time (high to low)(3)
tvdH(Data)
high)(3)
Valid-data time (low to
tvd(ack)
Valid-data time of ACK condition
Cb
I2C bus capacitive load
300
4
SCL low to SDA output low valid
SCL low to SDA output high valid
ACK signal from SCL low
to SDA output low
ns
μs
μs
1
μs
0.6
μs
1
μs
400
pF
400
kHz
FAST MODE
fscl
I2C clock frequency
tsch
I2C
tscl
I2C clock low time
0
clock high time
0.6
μs
1.3
μs
tsp
I2C
tsds
I2C serial-data setup time
100
ns
tsdh
I2C
0(1)
μs
spike time
50
serial-data hold time
ns
ticr
I2C input rise time
20 + 0.1Cb
ticf
I2C input fall time
20 + 0.1Cb
300
ns
tocf
I2C output (SDn) fall time (10-pF to 400-pF bus)
20 + 0.1Cb
300
ns
tbuf
I2C bus free time between stop and start
1.3
μs
tsts
I2C start or repeated start condition setup
0.6
μs
tsth
I2C start or repeated start condition hold
0.6
μs
tsps
I2C stop condition setup
0.6
μs
tvdL(Data)
Valid-data time (high to low)(3)
SCL low to SDA output low valid
tvdH(Data)
Valid-data time (low to high)(3)
SCL low to SDA output high valid
tvd(ack)
Valid-data time of ACK condition
ACK signal from SCL low
to SDA output low
Cb
I2C bus capacitive load
(1)
(2)
(3)
(2)
(2)
(2)
300
ns
1
μs
0.6
μs
1
μs
400
pF
A device internally must provide a hold time of at least 300 ns for the SDA signal (referred to the VIH min of the SCL signal), to bridge
the undefined region of the falling edge of SCL.
Cb = total bus capacitance of one bus line in pF.
Data taken using a 1-kΩ pull-up resistor and 50-pF load (see Figure 7-2).
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6.7 Reset Timing Requirements
over recommended operating free-air temperature range (unless otherwise noted)
MIN
MAX
UNIT
tW(L)
Pulse duration, RESET low
6
ns
tREC(STA)
Recovery time from RESET to start
0
ns
6.8 Switching Characteristics
over recommended operating free-air temperature range, CL ≤ 100 pF (unless otherwise noted) (see Figure 7-1)
FROM
(INPUT)
PARAMETER
tpd (1)
Propagation delay time
trst (2)
RESET time (SDA clear)
(1)
(2)
8
TO
(OUTPUT)
MIN
MAX
RON = 20 Ω, CL = 15 pF
SDA or SCL
SDn or SCn
0.3
RON = 20 Ω, CL = 50 pF
SDA or SCL
SDn or SCn
1
RESET
SDA
UNIT
500
ns
ns
The propagation delay is the calculated RC time constant of the typical ON-state resistance of the switch and the specified load
capacitance, when driven by an ideal voltage source (zero output impedance).
trst is the propagation delay measured from the time the RESET pin is first asserted low to the time the SDA pin is asserted high,
signaling a stop condition. It must be a minimum of tWL.
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6.9 Typical Characteristics
25
1.8
Standard-mode
Fast-mode
1.6
1.4
Rp(min) (kOhm)
Rp(max) (kOhm)
20
15
10
1.2
1
0.8
0.6
0.4
5
VDPUX > 2V
VDPUX 2 V
Figure 6-2. Minimum Pull-Up Resistance (Rp(min)) vs Pull-Up
Reference Voltage (VDPUX)
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7 Parameter Measurement Information
VCC
R L = 1 kW
SDA
DUT
CL = 50 pF
(see Note A)
SDA LOAD CONFIGURATION
Three Bytes for Complete
Device Programming
Address
Stop
Start
Bit 7 Address
Condition Condition
Bit 6
(MSB)
(P)
(S)
R/W
Bit 0
(LSB)
Address
Bit 1
tscl
ACK
(A)
Data
Bit 7
(MSB)
Data
Bit 0
(LSB)
Stop
Condition
(P)
tsch
0.7 ´ VCC
SCL
0.3 ´ VCC
ticr
tvd(ack)
ticf
tbuf
tsp
tsts
tvdH(Data)
0.7 ´ VCC
SDA
0.3 ´ VCC
ticr
ticf
tsth
tvdL(Data)
tsdh
tsds
tsps
Repeat Start
Condition
Start or
Repeat Start
Condition
Stop
Condition
VOLTAGE WAVEFORMS
BYTE
DESCRIPTION
1
I C address
2, 3
P-port data
2
A. CL includes probe and jig capacitance.
B. All inputs are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr/tf ≤ 30 ns.
C. Not all parameters and waveforms are applicable to all devices.
Figure 7-1. I2C Load Circuit and Voltage Waveforms
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VCC
RL = 1 kW
DUT
SDA
CL = 50 pF
(see Note A)
SDA LOAD CONFIGURATION
Start
SCL
ACK or Read Cycle
SDA
0.3
VCC
tRESET
RESET
VCC/2
tREC
tw
SDn, SCn
0.3
VCC
tRESET
A.
B.
C.
D.
CL includes probe and jig capacitance.
All inputs are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr/tf ≤ 30 ns.
I/Os are configured as inputs.
Not all parameters and waveforms are applicable to all devices.
Figure 7-2. Reset Load Circuit and Voltage Waveforms
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8 Detailed Description
8.1 Overview
The PCA9548A is a 8-channel, bidirectional translating I2C switch. The master SCL/SDA signal pair is directed
to eight channels of slave devices, SC0/SD0-SC3/SD3. Any individual downstream channel can be selected as
well as any combination of the eight channels.
The device offers an active-low RESET input which resets the state machine and allows the PCA9548A to
recover if one of the downstream I2C buses get stuck in a low state. The state machine of the device can also be
reset by cycling the power supply, VCC, also known as a power-on reset (POR). Both the RESET function and a
POR cause all channels to be deselected.
The connections of the I2C data path are controlled by the same I2C master device that is switched to
communicate with multiple I2C slaves. After the successful acknowledgment of the slave address (hardware
selectable by A0 and A1 pins), a single 8-bit control register is written to or read from to determine the selected
channels.
The PCA9548A may also be used for voltage translation, allowing the use of different bus voltages on each
SCn/SDn pair such that 1.8-V, 2.5-V, or 3.3-V parts can communicate with 5-V parts. This is achieved by using
external pull-up resistors to pull the bus up to the desired voltage for the master and each slave channel.
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8.2 Functional Block Diagram
PCA9548A
SC0
SC1
SC2
SC3
SC4
SC5
SC6
SC7
SD0
SD1
SD2
SD3
SD4
SD5
SD6
SD7
Switch Control Logic
GND
VCC
RESET
SCL
Reset Circuit
A0
Input Filter
SDA
2
I C Bus Control
A1
A2
8.3 Feature Description
The PCA9548A is an 8-channel, bidirectional translating switch for I2C buses that supports Standard-Mode
(100 kHz) and Fast-Mode (400 kHz) operation. The PCA9548A features I2C control using a single 8-bit control
register in which each bit controls the enabling and disabling for one of the 8 switch channels of I2C data flow.
Depending on the application, voltage translation of the I2C bus can also be achieved using the PCA9548A to
allow 1.8-V, 2.5-V, or 3.3-V parts to communicate with 5-V parts. Additionally, in the event that communication on
the I2C bus enters a fault state, the PCA9548A can be reset to resume normal operation using the RESET pin
feature or by a power-on reset which results from cycling power to the device.
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8.4 Device Functional Modes
8.4.1 RESET Input
The RESET input is an active-low signal that may be used to recover from a bus-fault condition. When this signal
is asserted low for a minimum of tWL, the PCA9548A resets its registers and I2C state machine and deselects all
channels. The RESET input must be connected to VCC through a pull-up resistor.
8.4.1.1 RESET Errata
If RESET voltage set higher than VCC, current flows from RESET pin to VCC pin.
8.4.1.1.1 System Impact
VCC is pulled above its regular voltage level.
8.4.1.1.2 System Workaround
Design such that RESET voltage is same or lower than VCC.
8.4.2 Power-On Reset
When power (from 0 V) is applied to VCC, an internal power-on reset holds the PCA9548A in a reset condition
until VCC has reached VPOR. At that point, the reset condition is released and the PCA9548A registers and I2C
state machine initialize to their default states. After that, V CC must be lowered to below VPOR and then back up to
the operating voltage for a power-reset cycle.
8.5 Programming
8.5.1 I2C Interface
The bidirectional I2C bus consists of the serial clock (SCL) and serial data (SDA) lines. Both lines must be
connected to a positive supply through a pull-up resistor when connected to the output stages of a device. Data
transfer may be initiated only when the bus is not busy.
I2C communication with this device is initiated by a master sending a start condition, a high-to-low transition on
the SDA input/output while the SCL input is high (see Figure 8-1). After the start condition, the device address
byte is sent, most significant bit (MSB) first, including the data direction bit (R/ W).
After receiving the valid address byte, this device responds with an acknowledge (ACK), a low on the SDA
input/output during the high of the ACK-related clock pulse. The address inputs (A0–A2) of the slave device must
not be changed between the start and the stop conditions.
On the I2C bus, only one data bit is transferred during each clock pulse. The data on the SDA line must remain
stable during the high pulse of the clock period, as changes in the data line at this time are interpreted as control
commands (start or stop) (see Figure 8-2).
A stop condition, a low-to-high transition on the SDA input/output while the SCL input is high, is sent by the
master (see Figure 8-1).
Any number of data bytes can be transferred from the transmitter to receiver between the start and the stop
conditions. Each byte of eight bits is followed by one ACK bit. The transmitter must release the SDA line before
the receiver can send an ACK bit. The device that acknowledges must pull down the SDA line during the ACK
clock pulse so that the SDA line is stable low during the high pulse of the ACK-related clock period (see Figure
8-3). When a slave receiver is addressed, it must generate an ACK after each byte is received. Similarly, the
master must generate an ACK after each byte that it receives from the slave transmitter. Setup and hold times
must be met to ensure proper operation.
A master receiver signals an end of data to the slave transmitter by not generating an acknowledge (NACK) after
the last byte has been clocked out of the slave. This is done by the master receiver by holding the SDA line high.
In this event, the transmitter must release the data line to enable the master to generate a stop condition.
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SDA
SCL
S
P
Start Condition
Stop Condition
Figure 8-1. Definition of Start and Stop Conditions
SDA
SCL
Data Line
Stable;
Data Valid
Change
of Data
Allowed
Figure 8-2. Bit Transfer
Data Output
by Transmitter
NACK
Data Output
by Receiver
ACK
SCL From
Master
1
2
8
9
S
Clock Pulse for
Acknowledgment
Start
Condition
Figure 8-3. Acknowledgment on I2C Bus
8.6 Register Maps
8.6.1 Device Address
Figure 8-4 shows the address byte of the PCA9548A.
Slave Address
1
1
1
Fixed
0
A2
A1
A0 R/W
Hardware
Selectable
Figure 8-4. PCA9548A Address
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The last bit of the slave address defines the operation (read or write) to be performed. When it is high (1), a read
is selected, while a low (0) selects a write operation.
Table 8-1 shows the PCA9548A address reference.
Table 8-1. Address Reference
INPUTS
A2
A1
I2C BUS SLAVE ADDRESS
A0
L
L
L
112 (decimal), 70 (hexadecimal)
L
L
H
113 (decimal), 71 (hexadecimal)
L
H
L
114 (decimal), 72 (hexadecimal)
L
H
H
115 (decimal), 73 (hexadecimal)
H
L
L
116 (decimal), 74 (hexadecimal)
H
L
H
117 (decimal), 75 (hexadecimal)
H
H
L
118 (decimal), 76 (hexadecimal)
H
H
H
119 (decimal), 77 (hexadecimal)
8.6.2 Control Register
Following the successful acknowledgment of the address byte, the bus master sends a command byte that
is stored in the control register in the PCA9548A (see Figure 8-5). This register can be written and read via
the I2C bus. Each bit in the command byte corresponds to a SCn/SDn channel and a high (or 1) selects
this channel. Multiple SCn/SDn channels may be selected at the same time. When a channel is selected, the
channel becomes active after a stop condition has been placed on the I2C bus. This ensures that all SCn/SDn
lines are in a high state when the channel is made active, so that no false conditions are generated at the time
of connection. A stop condition always must occur immediately after the acknowledge cycle. If multiple bytes are
received by the PCA9548A, it saves the last byte received.
Channel Selection Bits (Read/Write)
B7
B6
B5
B4
B3
B2
B1
B0
Channel 0
Channel 1
Channel 2
Channel 3
Channel 4
Channel 5
Channel 6
Channel 7
Figure 8-5. Control Register
Table 8-2 shows the PCA9548A Command byte definition.
Table 8-2. Command Byte Definition
CONTROL REGISTER BITS
16
B7
B6
B5
B4
B3
B2
B1
X
X
X
X
X
X
X
X
X
X
X
X
X
0
1
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B0
COMMAND
0
Channel 0 disabled
1
Channel 0 enabled
X
Channel 1 disabled
Channel 1 enabled
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Table 8-2. Command Byte Definition (continued)
CONTROL REGISTER BITS
B7
B6
B5
B4
B3
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
0
1
0
B1
B0
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
0
0
0
0
0
0
0
0
1
0
1
0
1
0
1
B2
0
1
COMMAND
Channel 2 disabled
Channel 2 enabled
Channel 3 disabled
Channel 3 enabled
Channel 4 disabled
Channel 4 enabled
Channel 5 disabled
Channel 5 enabled
Channel 6 disabled
Channel 6 enabled
Channel 7 disabled
Channel 7 enabled
No channel selected, power-up/reset
default state
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8.6.3 Bus Transactions
Data is exchanged between the master and PCA9548A through write and read commands.
8.6.3.1 Writes
Data is transmitted to the PCA9548A by sending the device address and setting the least-significant bit (LSB) to
a logic 0 (see Figure 8-4 for device address). The command byte is sent after the address and determines which
SCn/SDn channel receives the data that follows the command byte (see Figure 8-6). There is no limitation on the
number of data bytes sent in one write transmission.
Slave Address
SDA
S
1
1
1
0
Control Register
A2 A1 A0
Start Condition
0
A
B7
B6 B5
B4 B3 B2 B1 B0
R/W ACK From Slave
A
ACK From Slave
P
Stop Condition
Figure 8-6. Write to Control Register
8.6.3.2 Reads
The bus master first must send the PCA9548A address with the LSB set to a logic 1 (see Figure 8-4 for device
address). The command byte is sent after the address and determines which SCn/SDn channel is accessed.
After a restart, the device address is sent again, but this time, the LSB is set to a logic 1. Data from the SCn/SDn
channel defined by the command byte then is sent by the PCA9548A (see Figure 8-7). After a restart, the value
of the SCn/SDn channel defined by the command byte matches the SCn/SDn channel being accessed when the
restart occurred. Data is clocked into the SCn/SDn channel on the rising edge of the ACK clock pulse. There is
no limitation on the number of data bytes received in one read transmission, but when the final byte is received,
the bus master must not acknowledge the data.
Slave Address
SDA
S
1
1
1
Start Condition
0
Control Register
A2 A1 A0
1
R/W
A
B7
B6 B5
B4 B3
ACK From Slave
B2 B1 B0 NA
NACK From Master
P
Stop Condition
Figure 8-7. Read From Control Register
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9 Application Information Disclaimer
Note
Information in the following applications sections is not part of the TI component specification,
and TI does not warrant its accuracy or completeness. TI’s customers are responsible for
determining suitability of components for their purposes, as well as validating and testing their design
implementation to confirm system functionality.
9.1 Application Information
Applications of the PCA9548A contain an I2C (or SMBus) master device and up to eight I2C slave devices.
The downstream channels are ideally used to resolve I2C slave address conflicts. For example, if eight identical
digital temperature sensors are needed in the application, one sensor can be connected at each channel: 0, 1,
2, and 3. When the temperature at a specific location needs to be read, the appropriate channel can be enabled
and all other channels switched off, the data can be retrieved, and the I2C master can move on and read the
next channel.
In an application where the I2C bus contains many additional slave devices that do not result in I2C slave
address conflicts, these slave devices can be connected to any desired channel to distribute the total bus
capacitance across multiple channels. If multiple switches are enabled simultaneously, additional design
requirements must be considered (See the Design Requirements and Detailed Design Procedure sections).
9.2 Typical Application
A typical application of the PCA9548A contains 1 or many separate data pull-up voltages, VCC , one for
the master device and one for each of the selectable slave channels, 0 through 7. In the event where the
master device and all slave devices operate at the same voltage, then the VCC pin can be connected to this
supply voltage. In an application where voltage translation is necessary, additional design requirements must be
considered (See the Design Requirements section).
Figure 9-1 shows an application in which the PCA9548A can be used.
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VCC = 2.7 V to 5.5 V
VCC = 3.3 V
VCC = 2.7 V to 5.5 V
24
See Note A
SDA
I2C/SMBus
Master
SCL
23
22
3
RESET
4
SDA
SD0
SCL
SC0
Channel 0
5
VCC = 2.7 V to 5.5 V
RESET
See Note A
SD1
6
SC1
7
Channel 1
VCC = 2.7 V to 5.5 V
See Note A
SD2
SC2
8
Channel 2
9
VCC = 2.7 V to 5.5 V
See Note A
10
SD3
SC3
Channel 3
11
VCC = 2.7 V to 5.5 V
PCA9548A
See Note A
13
SD4
SC4
Channel 4
14
VCC = 2.7 V to 5.5 V
See Note A
SD5
15
SC5
16
Channel 5
VCC = 2.7 V to 5.5 V
See Note A
SD6
SC6
21
2
1
12
17
Channel 6
18
VCC = 2.7 V to 5.5 V
A2
See Note A
A1
A0
SD7
GND
SC7
19
Channel 7
20
A. Pin numbers shown are for the PW and RTW packages.
Figure 9-1. PCA9548A Typical Application Schematic
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9.2.1 Design Requirements
The A0, A1, and A2 pins are hardware selectable to control the slave address of the PCA9548A. These pins
may be tied directly to GND or VCC in the application.
If multiple slave channels are activated simultaneously in the application, then the total IOL from SCL/SDA to
GND on the master side is the sum of the currents through all pull-up resistors, Rp.
The pass-gate transistors of the PCA9548A are constructed such that the VCC voltage can be used to limit the
maximum voltage that is passed from one I2C bus to another.
Figure 9-2 shows the voltage characteristics of the pass-gate transistors (note that the graph was generated
using data specified in the Electrical Characteristics section of this data sheet). In order for the PCA9548A to act
as a voltage translator, the Vpass voltage must be equal to or lower than the lowest bus voltage. For example,
if the main bus is running at 5 V and the downstream buses are 3.3 V and 2.7 V, Vpass must be equal to or
below 2.7 V to effectively clamp the downstream bus voltages. As shown in Figure 9-2, Vpass(max) is 2.7 V when
the PCA9548A supply voltage is 4 V or lower, so the PCA9548A supply voltage could be set to 3.3 V. Pull-up
resistors then can be used to bring the bus voltages to their appropriate levels (see Figure 9-1).
9.2.2 Detailed Design Procedure
Once all the slaves are assigned to the appropriate slave channels and bus voltages are identified, the pull-up
resistors, Rp, for each of the buses need to be selected appropriately. The minimum pull-up resistance is a
function of the reference voltage of the specific I2C channel (VDPUX), VOL,(max), and IOL as shown in Equation 1.
Rp(min)
VDPUX
VOL(max)
IOL
(1)
The maximum pull-up resistance is a function of the maximum rise time, tr (300 ns for fast-mode operation, fSCL
= 400 kHz) and bus capacitance, Cbis given by Equation 2.
Rp(max)
tr
0.8473 u Cb
(2)
The maximum bus capacitance for an I2C bus must not exceed 400 pF for fast-mode operation. The bus
capacitance can be approximated by adding the capacitance of the PCA9548A, Cio(OFF), the capacitance of
wires, connections, traces, and the capacitance of each individual slave on a given channel. If multiple channels
are activated simultaneously, each of the slaves on all channels contribute to total bus capacitance.
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9.2.3 Application Curves
5
25
20
Rp(max) (kOhm)
4
Vpass (V)
Standard-mode
Fast-mode
25ºC (Room Temperature)
85ºC
-40ºC
3
2
15
10
5
1
0
0
0
0.5
1
1.5
2
Standard-mode (fSCL kHz, tr
2.5
3
VCC (V)
3.5
4
4.5
5
5.5
0
50
100
150
D007
200
250
Cb (pF)
Standard-mode (fSCL = 100
kHz, tr = 1 µs)
SPACE (fSCL kHz, tr)
Figure 9-2. Pass-Gate Voltage (Vpass) vs Supply
Voltage (VCC) at Three Temperature Points
300
350
400
450
D008
Fast-mode (fSCL = 400 kHz, tr
= 300 ns)
Figure 9-3. Maximum Pull-Up Resistance (Rp(max))
vs Bus Capacitance (Cb)
1.8
1.6
Rp(min) (kOhm)
1.4
1.2
1
0.8
0.6
0.4
VDPUX > 2V
VDPUX 2 V
Figure 9-4. Minimum Pullup Resistance (Rp(min)) vs Pullup Reference Voltage (VDPUX)
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10 Power Supply Recommendations
10.1 Power-On Reset Requirements
In the event of a glitch or data corruption, PCA9548A can be reset to its default conditions by using the power-on
reset feature. Power-on reset requires that the device go through a power cycle to be completely reset. This
reset also happens when the device is powered on for the first time in an application.
The two types of power-on reset are shown in Figure 10-1 and Figure 10-2.
VCC
Ramp-Up
Re-Ramp-Up
Ramp-Down
VCC_TRR_GND
Time
VCC_RT
VCC_FT
Time to Re-Ramp
VCC_RT
Figure 10-1. VCC Is Lowered Below 0.2 V Or 0 V And Then Ramped Up To VCC
VCC
Ramp-Down
Ramp-Up
VCC_TRR_VPOR50
VIN drops below POR levels
Time
Time to Re-Ramp
VCC_FT
VCC_RT
Figure 10-2. VCC Is Lowered Below The Por Threshold, Then Ramped Back Up To VCC
Table 10-1 specifies the performance of the power-on reset feature for PCA9548A for both types of power-on
reset.
Table 10-1. Recommended Supply Sequencing And Ramp Rates (1)
PARAMETER
MAX
UNIT
1
100
ms
See Figure 10-1
0.01
100
ms
See Figure 10-1
0.001
ms
Time to re-ramp (when VCC drops to VPOR_MIN – 50 mV)
See Figure 10-2
0.001
ms
VCC_GH
Level that VCCP can glitch down to, but not cause a functional
disruption when VCCX_GW = 1 μs
See Figure 10-3
VCC_GW
Glitch width that will not cause a functional disruption when
VCCX_GH = 0.5 × VCCx
See Figure 10-3
VPORF
Voltage trip point of POR on falling VCC
0.767
1.144
V
VPORR
Voltage trip point of POR on rising VCC
1.033
1.428
V
VCC_FT
MIN
Fall rate
See Figure 10-1
VCC_RT
Rise rate
VCC_TRR_GND
Time to re-ramp (when VCC drops to GND)
VCC_TRR_POR50
(1)
TYP
1.2
V
μs
TA = –40°C to 85°C (unless otherwise noted)
Glitches in the power supply can also affect the power-on reset performance of this device. The glitch width
(VCC_GW) and height (VCC_GH) are dependent on each other. The bypass capacitance, source impedance, and
the device impedance are factors that affect power-on reset performance. Figure 10-3 and Table 10-1 provide
more information on how to measure these specifications.
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VCC
VCC_GH
Time
VCC_GW
Figure 10-3. Glitch Width And Glitch Height
VPOR is critical to the power-on reset. VPOR is the voltage level at which the reset condition is released and
all the registers and the I2C/SMBus state machine are initialized to their default states. The value of VPOR
differs based on the VCC being lowered to or from 0. Figure 10-4 and Table 10-1 provide more details on this
specification.
VCC
VPOR
VPORF
Time
POR
Time
Figure 10-4. VPOR
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11 Layout
11.1 Layout Guidelines
For PCB layout of the PCA9548A, common PCB layout practices must be followed but additional concerns
related to high-speed data transfer such as matched impedances and differential pairs are not a concern for I2C
signal speeds. It is common to have a dedicated ground plane on an inner layer of the board and pins that are
connected to ground must have a low-impedance path to the ground plane in the form of wide polygon pours
and multiple vias. By-pass and de-coupling capacitors are commonly used to control the voltage on the VCC pin,
using a larger capacitor to provide additional power in the event of a short power supply glitch and a smaller
capacitor to filter out high-frequency ripple.
In an application where voltage translation is not required, all VDPUX voltages and VCC could be at the same
potential and a single copper plane could connect all of pull-up resistors to the appropriate reference voltage. In
an application where voltage translation is required, VDPUM and VDPU0 – VDPU7 may all be on the same layer of
the board with split planes to isolate different voltage potentials.
To reduce the total I2C bus capacitance added by PCB parasitics, data lines (SCn and SDn) must be a short
as possible and the widths of the traces must also be minimized (For example, 5-10 mils depending on copper
weight).
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11.2 Layout Example
LEGEND
Partial Power Plane
(inner layer)
To I2C Master
Copper Pour
(outer layer)
Via to Power Plane
Via to GND Plane
By-pass/de-coupling
capacitors
VDPU2
2
23
SDA
RESET
3
22
SCL
SD0
4
21
A2
SC0
5
20
SC7
SD1
6
19
SD7
SC1
7
18
SC6
SD2
8
17
SD6
SC2
9
16
SC5
SD3
10
15
SD5
SC3
11
14
SC4
GND
12
13
SD4
A1
PW package
PCA9548A
To Slave Channel 1
VDPU1
VCC
1
VDPU7
VDPU6
VDPU5
To Slave Channel 5
To Slave Channel 2
VDPU0
24
A0
To Slave Channel 6
VDPU3
GND
VDPU4
To Slave Channel 4
To Slave Channel 3
VCC
GND
To Slave Channel 7
To Slave Channel 0
VDPUM
Figure 11-1. Layout Example
26
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Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: PCA9548A
PCA9548A
www.ti.com
SCPS143G – JUNE 2009 – REVISED MARCH 2021
12 Device and Documentation Support
12.1 Related Documentation
For related documentation see the following:
• I2C Bus Pull-Up Resistor Calculation
• Maximum Clock Frequency of I2C Bus Using Repeaters
• Introduction to Logic
• Understanding the I2C Bus
• Choosing the Correct I2C Device for New Designs
12.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates—including silicon errata—go to the product folder for your
device on ti.com. In the upper right-hand corner, click the Alert me button. This registers you to receive a weekly
digest of product information that has changed (if any). For change details, check the revision history of any
revised document.
12.3 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
12.4 Trademarks
TI E2E™ is a trademark of Texas Instruments.
All trademarks are the property of their respective owners.
12.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
12.6 Glossary
TI Glossary
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
Submit Document Feedback
Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: PCA9548A
27
PACKAGE OPTION ADDENDUM
www.ti.com
13-Aug-2021
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
PCA9548ADB
ACTIVE
SSOP
DB
24
60
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
PD548A
PCA9548ADBG4
ACTIVE
SSOP
DB
24
60
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
PD548A
PCA9548ADBR
ACTIVE
SSOP
DB
24
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
PD548A
PCA9548ADGV
NRND
TVSOP
DGV
24
TBD
Call TI
Call TI
-40 to 85
PCA9548ADGVR
ACTIVE
TVSOP
DGV
24
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
PD548A
PCA9548ADW
ACTIVE
SOIC
DW
24
25
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
PCA9548A
PCA9548ADWG4
ACTIVE
SOIC
DW
24
25
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
PCA9548A
PCA9548ADWR
ACTIVE
SOIC
DW
24
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
PCA9548A
PCA9548APW
LIFEBUY
TSSOP
PW
24
60
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
PD548A
PCA9548APWR
ACTIVE
TSSOP
PW
24
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
PD548A
PCA9548APWRG4
ACTIVE
TSSOP
PW
24
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
PD548A
PCA9548ARGER
NRND
VQFN
RGE
24
3000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
PD548A
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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