PCM1681PWPG4

Product Folder Sample & Buy Support & Community Tools & Software Technical Documents PCM1681, PCM1681-Q1 Burr-Brown Audio SLES211C – FEBRUARY 2008 – REVISED JULY 2015 PCM1681 24-Bit, 192-kHz Sampling, Enhanced Multilevel Delta-Sigma, Eight-Channel Audio Digital-to-Analog Converter 1 Features 2 Applications • • • • • • • • • BODY SIZE (NOM) HTSSOP (28) 9.70 mm × 4.40 mm (1) For all available packages, see the orderable addendum at the end of the datasheet. Functional Block Diagram DAC BCK LRCK DATA1 (1, 2) DATA2 (3, 4) DAC Serial Input I/F 8 Oversampling Digital Filter With Function Controller Enhanced Multilevel Delta-Sigma Modulator MD/SDA/MUTE Function Control I/F Output Amp and VOUT2 DAC Output Amp and Low-Pass Filter VOUT3 DAC Output Amp and Low-Pass Filter VCOM DAC Output Amp and Low-Pass Filter DAC Output Amp and Low-Pass Filter DAC Output Amp and Low-Pass Filter DAC Output Amp and Low-Pass Filter MS/ADR/FMT1 MC/SCL/DEMP VOUT1 Low-Pass Filter DATA3 (5, 6) DATA4 (7, 8) Output Amp and Low-Pass Filter MSEL VOUT4 VOUT5 VOUT6 VOUT7 VOUT8 System Clock SCK System Clock Manager Zero Detect Power Supply VCC2 • • • PCM1681-Q1 PACKAGE AGND2 • PART NUMBER PCM1681 VCC1 • Device Information(1) AGND1 • • The PCM1681 and PCM1681-Q1 are CMOS monolithic integrated circuits which feature an eightchannel 24-bit audio digital-to-analog converter (DAC) and support circuitry in small 28-lead TSSOP PowerPAD packages. The DACs utilize Burr-Brown's enhanced multilevel delta-sigma (ΔΣ) architecture to achieve excellent signal-to-noise performance and a high tolerance to clock jitter. VDD • • 3 Description DGND • Car Audio External Amplifiers Car Audio AVN Applications Integrated A/V Receivers DVD Movie and Audio Players HDTV Receivers DVD Add-On Cards for High-End PCs Digital Audio Workstations Other Multichannel Audio Systems ZR2 • • Qualified for Automotive Applications: PCM1681Q1 24-Bit Resolution Analog Performance: – Dynamic Range: 105 dB Typical – SNR: 105 dB Typical – THD+N: 0.002% Typical – Full-Scale Output: 3.75 VPP Typical 4×/8× Oversampling Interpolation Filter: – Stop-Band Attenuation: –57 dB – Pass-Band Ripple: ±0.015 dB Sampling Frequency: 5 kHz to 200 kHz System Clock: 128 fS, 192 fS, 256 fS, 384 fS, 512 fS, 768 fS, or 1152 fS with Autodetect Zero Flags for Selectable Channel Combinations Flexible Mode Control: – SPI™/I2C™ Dual Mode for Serial Port – Parallel Hardware Control with 4 Functions User-Programmable Functions (in SPI/I2C): – Flexible Audio Data Formats: – Right-Justified, I2S™, Left-Justified, TDM, DSP – 16- and 24-Bit Audio Data – Digital Attenuation: Mode Selectable – 0 dB to –63 dB, 0.5 dB/step – 0 dB to –100 dB, 1 dB/step – Soft Mute – Digital De-Emphasis – Digital Filter Roll-Off: Sharp or Slow – Oversampling Mode User-Programmable Functions (in H/W): – Flexible Audio Data Formats: – Right-Justified, I2S, Left-Justified, TDM – Soft Mute – Digital De-Emphasis – Oversampling Mode Power Supply Voltage: 5-V Analog, 3.3-V Digital Package: 28-Lead HTSSOP PowerPAD™ Operation Temperature Range: – –40°C to 85°C for Consumer Grade – –40°C to 105°C for Automotive Audio Grade ZR1/ZR1/FMT0 1 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. PCM1681, PCM1681-Q1 SLES211C – FEBRUARY 2008 – REVISED JULY 2015 www.ti.com Table of Contents 1 2 3 4 5 6 7 Features .................................................................. Applications ........................................................... Description ............................................................. Revision History..................................................... Description (continued)......................................... Pin Configuration and Functions ......................... Specifications......................................................... 7.1 7.2 7.3 7.4 7.5 7.6 7.7 7.8 8 1 1 1 2 3 4 5 Absolute Maximum Ratings ..................................... 5 ESD Ratings: PCM1681 ........................................... 5 ESD Ratings: PCM1681-Q1 ..................................... 5 Recommended Operating Conditions....................... 6 Thermal Information .................................................. 6 Electrical Characteristics........................................... 7 Interface Timing Requirements................................. 9 Typical Characteristics ............................................ 10 Detailed Description ............................................ 14 8.1 Overview ................................................................. 14 8.2 Functional Block Diagram ....................................... 14 8.3 Feature Description................................................. 15 8.4 Device Functional Modes........................................ 24 8.5 Programming........................................................... 24 8.6 Register Maps ......................................................... 26 9 Application and Implementation ........................ 32 9.1 Application Information............................................ 32 9.2 Typical Application ................................................. 32 10 Power Supply Recommendations ..................... 34 11 Layout................................................................... 35 11.1 Layout Guidelines ................................................. 35 11.2 Layout Example .................................................... 35 12 Device and Documentation Support ................. 36 12.1 12.2 12.3 12.4 12.5 12.6 Device Support .................................................... Documentation Support ........................................ Related Links ........................................................ Trademarks ........................................................... Electrostatic Discharge Caution ............................ Glossary ................................................................ 36 36 36 36 36 36 13 Mechanical, Packaging, and Orderable Information ........................................................... 36 4 Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision B (June 2008) to Revision C • Page Added Pin Configuration and Functions section, ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information section .............................. 1 Changes from Revision A (June 2008) to Revision B Page • Added new device grade PCM1681-Q1 ................................................................................................................................. 1 • Changed device names in Operating Free-Air Temperature row of the Recommended Operating Conditions table ........... 6 • Changed device names in Operating Temperature row of Temperature Range section in the Electrical Characteristics table ............................................................................................................................................................... 8 • Added third paragraph to PCB Layout Guidelines section................................................................................................... 35 Changes from Original (February 2008) to Revision A Page • Added last sub-level bullet to Features ................................................................................................................................. 1 • Added first two bullets to Applications ................................................................................................................................... 1 • Changed last sentence in Description ................................................................................................................................... 1 • Added last row to Recommended Operating Conditions table............................................................................................... 6 • Added second row to Temperature Range section of the Electrical Characteristics table .................................................... 8 2 Submit Documentation Feedback Copyright © 2008–2015, Texas Instruments Incorporated Product Folder Links: PCM1681 PCM1681-Q1 PCM1681, PCM1681-Q1 www.ti.com SLES211C – FEBRUARY 2008 – REVISED JULY 2015 5 Description (continued) The PCM1681 and PCM1681-Q1 accept TDM (time-division multiplexed) format in addition to industry-standard audio data formats with 16- to 24-bit audio data width. Sampling rates up to 200 kHz are supported. The PCM1681 and PCM1681-Q1 provide a sub-set of user-programmable functions through a parallel control port, in addition to a full set of user-programmable functions through a serial control port, SPI, or I2C. The PCM1681 supports –40°C to +85°C for consumer grade applications and the PCM1681-Q1 supports –40°C to +105°C for automotive audio grade systems. Copyright © 2008–2015, Texas Instruments Incorporated Product Folder Links: PCM1681 PCM1681-Q1 Submit Documentation Feedback 3 PCM1681, PCM1681-Q1 SLES211C – FEBRUARY 2008 – REVISED JULY 2015 www.ti.com 6 Pin Configuration and Functions PWP Package 28-Pin HTSSOP PowerPAD Top View ZR1/ZR1/FMT0 MS/ADR/FMT1 MC/SCL/DEMP MD/SDA/MUTE SCK DATA1 BCK LRCK VDD DGND DATA2 DATA3 DATA4 MSEL 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 ZR2 VOUT1 VOUT2 VCOM AGND2 VCC2 VOUT3 VOUT4 VOUT5 VOUT6 AGND1 VCC1 VOUT7 VOUT8 Pin Functions PIN NAME NO. I/O DESCRIPTION AGND1 18 – Analog ground AGND2 24 – Analog ground BCK 7 I Shift clock input for serial audio data DATA1 6 I Serial audio data input for VOUT1 and VOUT2 (1) (2) DATA2 11 I Serial audio data input for VOUT3 and VOUT4 (1) (2) DATA3 12 I Serial audio data input for VOUT5 and VOUT6 (1) (2) DATA4 13 I Serial audio data input for VOUT7 and VOUT8 (1) (2) DGND 10 – Digital ground LRCK 8 I Left and right clock input. The frequency of this clock is equal to the sampling rate, fS. MC/SCL/ DEMP 3 I Shift clock input for SPI, serial clock input for I2C, de-emphasis control for H/W MD/SDA/ MUTE 4 I/O Serial data input for SPI, serial data input/output for I2C, mute control for H/W MS/ADR/ FMT1 2 I Select input for SPI, address input for I2C, format control input 1 for H/W MSEL 14 I Mode control select, I2C, H/W with narrow mode O/S, H/W with wide mode O/S, SPI select (1) SCK 5 I System clock input. Input frequency is 128, 192, 256, 384, 512, 768, or 1152 fS. VCC1 17 – Analog power supply, 5-V VCC2 23 – Analog power supply, 5-V VCOM 25 – Common voltage output. This pin should be bypassed with a 10-μF capacitor to AGND. (1) (2) VDD 9 – Digital power supply, 3.3-V VOUT1 27 O Voltage output for audio signal corresponding to L-ch on DATA1 VOUT2 26 O Voltage output for audio signal corresponding to R-ch on DATA1 VOUT3 22 O Voltage output for audio signal corresponding to L-ch on DATA2 VOUT4 21 O Voltage output for audio signal corresponding to R-ch on DATA2 VOUT5 20 O Voltage output for audio signal corresponding to L-ch on DATA3 (1) (2) (3) (4) 4 (1) (2) (1) (2) (1) (2) (3) (1) (2) (4) (1) (2) Schmitt-trigger input. 5-V tolerant. Open-drain output in I2C mode. VDD/2 biased, quad state input. Submit Documentation Feedback Copyright © 2008–2015, Texas Instruments Incorporated Product Folder Links: PCM1681 PCM1681-Q1 PCM1681, PCM1681-Q1 www.ti.com SLES211C – FEBRUARY 2008 – REVISED JULY 2015 Pin Functions (continued) PIN NAME NO. I/O DESCRIPTION VOUT6 19 O Voltage output for audio signal corresponding to R-ch on DATA3 VOUT7 16 O Voltage output for audio signal corresponding to L-ch on DATA4 VOUT8 15 O Voltage output for audio signal corresponding to R-ch on DATA4 ZR1/ZR1 /FMT0 1 I/O Zero-flag output 1 for SPI, zero-flag output 1 for I2C, format control input 0 for H/W (1) ZR2 28 O Zero-flag output 2 7 Specifications 7.1 Absolute Maximum Ratings (1) Over operating free-air temperature range (unless otherwise noted). MIN MAX UNIT VCC1, VCC2 –0.3 6.5 V VDD –0.3 4 V Supply voltage differences VCC1, VCC2 –0.1 0.1 V Ground voltage differences AGND1, AGND2, DGND –0.1 ZR1/ZR1/FMT0, ZR2, MSEL –0.3 VDD + 0.3, < 4 V MS/ADR/FMT1, MC/SCL/DEMP, MD/SDA/MUTE, SCK, BCK, LRCK, DATA1, 2, 3, 4 –0.3 6.5 V Input voltage to analog pins –0.3 VCC + 0.3, < 6.5 V Input current any pins except supplies –10 10 mA Ambient temperature under bias –40 125 °C 150 °C 260 °C 150 °C Supply voltage Input voltage to digital pins Junction temperature , TJ Package temperature (IR reflow, peak) Storage temperature, Tstg (1) –55 V Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 7.2 ESD Ratings: PCM1681 VALUE V(ESD) (1) (2) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1) ±4000 Charged-device model (CDM), per JEDEC specification JESD22C101 (2) ±1000 UNIT V JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. 7.3 ESD Ratings: PCM1681-Q1 VALUE V(ESD) (1) Electrostatic discharge Human-body model (HBM), per AEC Q100-002 (1) ±2000 Charged-device model (CDM), per AEC Q100-011 ±1000 UNIT V AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification. Copyright © 2008–2015, Texas Instruments Incorporated Product Folder Links: PCM1681 PCM1681-Q1 Submit Documentation Feedback 5 PCM1681, PCM1681-Q1 SLES211C – FEBRUARY 2008 – REVISED JULY 2015 www.ti.com 7.4 Recommended Operating Conditions Over operating free-air temperature range. MIN Analog supply voltage, VCC1, VCC2 Digital supply voltage, VDD NOM MAX 4.5 5 5.5 V 3 3.3 3.6 V Digital input logic family Digital input clock frequency TTL System clock Sampling clock Analog output load resistance 1.024 36.864 MHz 8 192 kHz 5 kΩ Analog output load capacitance Digital output load capacitance Operating free-air temperature, TA UNIT 50 pF 20 pF PCM1681 –40 85 °C PCM1681-Q1 –40 105 °C 7.5 Thermal Information PCM1681, PCM1681-Q1 THERMAL METRIC (1) PWP (HTSSOP) UNIT 28 PINS RθJA Junction-to-ambient thermal resistance 31 °C/W RθJC(top) RθJB Junction-to-case (top) thermal resistance 14.9 °C/W Junction-to-board thermal resistance 12.6 °C/W ψJT Junction-to-top characterization parameter 0.4 °C/W ψJB Junction-to-board characterization parameter 12.4 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance 1.1 °C/W (1) 6 For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953. Submit Documentation Feedback Copyright © 2008–2015, Texas Instruments Incorporated Product Folder Links: PCM1681 PCM1681-Q1 PCM1681, PCM1681-Q1 www.ti.com SLES211C – FEBRUARY 2008 – REVISED JULY 2015 7.6 Electrical Characteristics All specifications at VCC = 5.0 V, VDD = 3.3 V, fS = 48 kHz, system clock = 512 fS, and 24-bit data, narrow o/s mode, unless otherwise noted. PARAMETER TEST CONDITIONS MIN RESOLUTION TYP MAX UNIT 24 bits DATA FORMAT Audio data interface format Right-justified, I2S, leftjustified, TDM Audio data bit length 16-, 18-, 20-, or 24-bits, selectable Audio data format fS MSB-first, 2s complement Sampling frequency 5 200 kHz 128, 192, 256, 384, 512, 768, 1152 fS System clock frequency DIGITAL INPUT/OUTPUT Logic family VIH (1) VIL (1) VIH (2) TTL compatible 2.0 VDD 0.8 Input logic level 2.0 (2) VIL IIH (1) (2) IIL (1) (2) VOH (3) VOL (3) (4) VDC 5.5 0.8 Input logic current Output logic level VIN = VDD 10 VIN = 0 V –10 IOH = –1 mA μA 2.4 IOL = 1 mA VDC 0.4 DYNAMIC PERFORMANCE (5) THD+N Total harmonic distortion + noise VOUT = 0 dB, fS = 48 kHz 0.002% VOUT = 0 dB, fS = 96 kHz, system clock = 256 fS 0.002% VOUT = 0 dB, fS = 192 kHz, system clock = 128 fS 0.002% EIAJ, A-weighted, fS = 48 kHz Dynamic range Signal-to-noise ratio 105 A-weighted, fS = 192 kHz, system clock = 128 fS 105 100 105 A-weighted, fS = 192 kHz, system clock = 128 fS 105 94 dB 105 A-weighted, fS = 96 kHz, system clock = 256 fS fS = 48 kHz Channel separation 105 A-weighted, fS = 96 kHz, system clock = 256 fS EIAJ, A-weighted, fS = 48 kHz SNR 100 0.008% dB 102 fS = 96 kHz, system clock = 256 fS 102 fS = 192 kHz, system clock = 128 fS 102 dB DC ACCURACY Gain error ±2.0 ±6 % of FSR Gain mismatch, channel-tochannel ±2.0 ±6 % of FSR ±30 ±80 mV Bipolar zero error (1) (2) (3) (4) (5) VOUT = 0.486 VCC at BPZ input Pins 1, 14: ZR1/ZR1/FMT0 (input mode), MSEL Pins 2, 3, 4, 5, 6, 7, 8, 11, 12, 13: MS/ADR/FMT1, MC/SCL/DEMP, MD/SDA/MUTE (input mode), SCK, DATA1, BCK, LRCK, DATA2, DATA3, DATA4 Pins 1, 28: ZR1/ZR1/FMT0 (output mode), ZR2 Pin 4: MD/SDA/MUTE (output mode) Analog performance characteristics are measured using the System Two™ Cascade audio measurement system by Audio Precision™, fIN = 1 kHz, average mode, with 20-kHz LPF and 400-Hz HPF. Copyright © 2008–2015, Texas Instruments Incorporated Product Folder Links: PCM1681 PCM1681-Q1 Submit Documentation Feedback 7 PCM1681, PCM1681-Q1 SLES211C – FEBRUARY 2008 – REVISED JULY 2015 www.ti.com Electrical Characteristics (continued) All specifications at VCC = 5.0 V, VDD = 3.3 V, fS = 48 kHz, system clock = 512 fS, and 24-bit data, narrow o/s mode, unless otherwise noted. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT ANALOG OUTPUT Output voltage Full-scale (–0 dB) Bipolar zero voltage Load impedance AC-coupled load 0.75 VCC VPP 0.486 VCC VDC 5 kΩ DIGITAL FILTER PERFORMANCE Filter Characteristics (Sharp Roll-Off) Passband ±0.015 dB 0.454 fS Stop band 0.546 fS Passband ripple Stop band attenuation ±0.015 Stop band = 0.546 fS –57 dB dB Filter Characteristics (Slow Roll-Off) Passband ±0.004 dB 0.261 fS Stop band 0.727 fS Passband ripple Stop band attenuation ±0.004 Stop band = 0.727 fS –56 dB dB Filter Characteristics Delay time 24/fS De-emphasis error ±0.1 dB ANALOG FILTER PERFORMANCE Frequency response at 20 kHz –0.02 at 44 kHz –0.07 dB POWER-SUPPLY REQUIREMENTS VDD VCC IDD ICC 3 3.3 3.6 4.5 5.0 5.5 fS = 48 kHz 13 20 fS = 96 kHz, system clock = 256 fS 18 fS = 192 kHz, system clock = 128 fS 23 fS = 48 kHz 62 fS = 96 kHz, system clock = 256 fS 62 Voltage range Supply current Supply current fS = 192 kHz, system clock = 128 fS Power dissipation VDC mA 80 mA 62 fS = 48 kHz 353 fS = 96 kHz, system clock = 256 fS 369 fS = 192 kHz, system clock = 128 fS 386 466 mW TEMPERATURE RANGE Operating temperature θJA 8 Thermal resistance Submit Documentation Feedback PCM1681 –40 85 °C PCM1681-Q1 –40 105 °C 28-pin TSSOP PowerPAD™ 28 °C/W Copyright © 2008–2015, Texas Instruments Incorporated Product Folder Links: PCM1681 PCM1681-Q1 PCM1681, PCM1681-Q1 www.ti.com SLES211C – FEBRUARY 2008 – REVISED JULY 2015 7.7 Interface Timing Requirements PARAMETER MIN MAX UNIT 100 kHz f(SCL) SCL clock frequency t(BUF) Bus free time between a STOP and START condition 4.7 μs t(LOW) Low period of the SCL clock 4.7 μs t(HI) High period of the SCL clock t(RS-SU) Setup time for (repeated) START condition t(S-HD) t(RS-HD) Hold time for (repeated) START condition t(D-SU) Data setup time t(D-HD) Data hold time t(SCL-R) t(SCL-R1) 4 μs 4.7 μs 4 μs 250 ns 0 900 ns Rise time of SCL signal 20 + 0.1 CB 1000 ns Rise time of SCL signal after a repeated START condition and after an acknowledge bit 20 + 0.1 CB 1000 ns t(SCL-F) Fall time of SCL signal 20 + 0.1 CB 1000 ns t(SDA-R) Rise time of SDA signal 20 + 0.1 CB 1000 ns t(SDA-F) Fall time of SDA signal 20 + 0.1 CB 1000 t(P-SU) Setup time for STOP condition CB Capacitive load for SDA and SCL lines VNH Noise margin at high level for each connected device (including hysteresis) 400 0.2 VDD Stop t(D-HD) t(BUF) pF V Repeated Start Start ns μs 4 t(SDA-F) t(D-SU) t(SDA-R) t(P-SU) SDA t(SCL-R) t(RS-HD) t(SP) t(LOW) SCL t(S-HD) t(HI) t(RS-SU) t(SCL-F) T0050-01 Figure 1. Interface Timing Copyright © 2008–2015, Texas Instruments Incorporated Product Folder Links: PCM1681 PCM1681-Q1 Submit Documentation Feedback 9 PCM1681, PCM1681-Q1 SLES211C – FEBRUARY 2008 – REVISED JULY 2015 www.ti.com 7.8 Typical Characteristics All specifications at TA = +25°C, VCC = 5 V, VDD = 3.3 V, fS = 48 kHz, system clock = 512 fS, and 24-bit data, unless otherwise noted. 7.8.1 Digital Filter (De-Emphasis Off) 0.05 0 0.04 0.03 0.02 −40 Amplitude – dB Amplitude – dB −20 −60 −80 0.01 0.00 −0.01 −0.02 −0.03 −100 −0.04 −0.05 0.0 −120 0 1 2 3 4 Frequency [× fS] 0.1 G001 Figure 2. Frequency Response (Sharp Roll-off) 0.2 0.3 0.4 Frequency [× fS] 0.5 G002 Figure 3. Passband Frequency Response (Sharp Roll-off) 0.0 0 −0.5 −1.0 −1.5 −40 Amplitude – dB Amplitude – dB −20 −60 −80 −2.0 −2.5 −3.0 −3.5 −4.0 −100 −4.5 −120 0 1 2 Frequency [× fS] 3 −5.0 0.0 4 Figure 4. Frequency Response (Slow Roll-off) 10 Submit Documentation Feedback 0.1 0.2 0.3 Frequency [× fS] G003 0.4 0.5 G004 Figure 5. Transition Characteristics (Slow Roll-off) Copyright © 2008–2015, Texas Instruments Incorporated Product Folder Links: PCM1681 PCM1681-Q1 PCM1681, PCM1681-Q1 www.ti.com SLES211C – FEBRUARY 2008 – REVISED JULY 2015 7.8.2 De-Emphasis Filter 0.5 0 fS = 32 kHz −1 0.3 De-Emphasis Error – dB −2 De-Emphasis Level – dB fS = 32 kHz 0.4 −3 −4 −5 −6 −7 0.2 0.1 0.0 −0.1 −0.2 −8 −0.3 −9 −0.4 −0.5 −10 0 2 4 6 8 10 12 0 14 2 4 6 8 10 12 14 f – Frequency – kHz f – Frequency – kHz G006 G005 Figure 7. De-Emphasis Error Figure 6. De-Emphasis 0.5 0 fS = 44.1 kHz −1 0.3 De-Emphasis Error – dB −2 De-Emphasis Level – dB fS = 44.1 kHz 0.4 −3 −4 −5 −6 −7 0.2 0.1 0.0 −0.1 −0.2 −8 −0.3 −9 −0.4 −0.5 −10 0 2 4 6 8 10 12 14 16 18 0 20 2 4 6 8 10 12 14 16 18 G008 G007 Figure 9. De-Emphasis Error Figure 8. De-Emphasis 0.5 0 fS = 48 kHz −1 fS = 48 kHz 0.4 0.3 De-Emphasis Error – dB −2 De-Emphasis Level – dB 20 f – Frequency – kHz f – Frequency – kHz −3 −4 −5 −6 −7 0.2 0.1 0.0 −0.1 −0.2 −8 −0.3 −9 −0.4 −0.5 −10 0 2 4 6 8 10 12 14 16 18 20 22 0 2 4 6 8 10 12 14 16 18 20 22 f – Frequency – kHz f – Frequency – kHz G010 G009 Figure 10. De-Emphasis Figure 11. De-Emphasis Error Copyright © 2008–2015, Texas Instruments Incorporated Product Folder Links: PCM1681 PCM1681-Q1 Submit Documentation Feedback 11 PCM1681, PCM1681-Q1 SLES211C – FEBRUARY 2008 – REVISED JULY 2015 www.ti.com 7.8.3 Analog Filter 10 0 Amplitude − dB −10 −20 −30 −40 −50 −60 −70 1 10 100 1,000 10,000 f − Frequency − kHz G011 Figure 12. Analog Filter Performance 7.8.4 Analog Dynamic Performance 7.8.4.1 Supply Voltage Characteristics 0.01 THD+N − Total Harmonic Distortion + Noise − % 108 Dynamic Range – dB 106 5.00 98 4.50 5.25 VCC − Supply Voltage − V 106 Channel Separation – dB 106 102 100 5.25 5.50 G013 Figure 14. Dynamic Range vs Supply Voltage 108 104 5.00 VCC – Supply Voltage – V 108 98 4.50 4.75 G012 Figure 13. Total Harmonic Distortion + Noise vs Supply Voltage SNR – Signal-to-Noise Ratio − dB 102 100 0.001 4.75 104 102 100 4.75 5.00 5.25 VCC – Supply Voltage – V 5.50 Submit Documentation Feedback 98 4.50 4.75 5.00 5.25 VCC – Supply Voltage – V G014 Figure 15. Signal-to-Noise Ratio vs Supply Voltage 12 104 5.50 G015 Figure 16. Channel Separation vs Supply Voltage Copyright © 2008–2015, Texas Instruments Incorporated Product Folder Links: PCM1681 PCM1681-Q1 PCM1681, PCM1681-Q1 www.ti.com SLES211C – FEBRUARY 2008 – REVISED JULY 2015 Analog Dynamic Performance (continued) 7.8.4.2 Temperature Characteristics 0.01 THD+N − Total Harmonic Distortion + Noise − % 108 Dynamic Range – dB 106 102 100 0.001 −40 −15 10 35 60 85 TA − Free-Air Temperature − °C 98 −40 110 G016 106 106 Channel Separation – dB 108 102 100 98 −40 10 35 60 85 110 G017 Figure 18. Dynamic Range vs Temperature 108 104 −15 TA − Free-Air Temperature − °C Figure 17. Total Harmonic Distortion + Noise vs Temperature SNR – Signal-to-Noise Ratio − dB 104 104 102 100 −15 10 35 60 85 TA − Free-Air Temperature − °C 110 98 −40 Figure 19. Signal-to-Noise Ratio vs Temperature −15 10 35 60 TA − Free-Air Temperature − °C G018 85 110 G019 Figure 20. Channel Separation vs Temperature Copyright © 2008–2015, Texas Instruments Incorporated Product Folder Links: PCM1681 PCM1681-Q1 Submit Documentation Feedback 13 PCM1681, PCM1681-Q1 SLES211C – FEBRUARY 2008 – REVISED JULY 2015 www.ti.com 8 Detailed Description 8.1 Overview The PCM1681 and PCM1681-Q1 are CMOS monolithic integrated circuits which feature an eight-channel 24-bit audio digital-to-analog converter (DAC) and support circuitry in small 28-lead TSSOP PowerPAD packages. The DACs utilize a Burr-Brown enhanced multilevel delta-sigma (ΔΣ) architecture to achieve excellent signal-to-noise performance and a high tolerance to clock jitter. The system clock can operate anywhere from 128 fs to 1152 fs and with respect to the system clock rate the DAC can oversample anywhere from ×16 to ×128. The PCM1681 and PCM1681-Q1 accept TDM (time-division multiplexed) format in addition to industry-standard audio data formats with 16- to 24-bit audio data width. This includes right justified, I2S, left justified, and DSP formats along with sampling rates up to 200 kHz. The PCM1681 and PCM1681-Q1 provide a sub-set of user-programmable functions through a parallel control port, in addition to a full set of user-programmable functions through a serial control port, SPI, or I2C. This is controlled through the MSEL pin as explained in Table 7. A 5-V analog supply and a 3.3-V digital supply are required. The PCM1681 supports –40°C to 85°C for consumer grade applications and the PCM1681-Q1 supports –40°C to 105°C for automotive audio grade systems. 8.2 Functional Block Diagram DAC BCK LRCK DATA1 (1, 2) DATA2 (3, 4) DAC Serial Input I/F 8 Oversampling Digital Filter With Function Controller Enhanced Multilevel Delta-Sigma Modulator MD/SDA/MUTE Function Control I/F Output Amp and VOUT2 DAC Output Amp and Low-Pass Filter VOUT3 DAC Output Amp and Low-Pass Filter VCOM DAC Output Amp and Low-Pass Filter DAC Output Amp and Low-Pass Filter DAC Output Amp and Low-Pass Filter DAC Output Amp and Low-Pass Filter MS/ADR/FMT1 MC/SCL/DEMP VOUT1 Low-Pass Filter DATA3 (5, 6) DATA4 (7, 8) Output Amp and Low-Pass Filter MSEL VOUT4 VOUT5 VOUT6 VOUT7 VOUT8 System Clock 14 Submit Documentation Feedback AGND2 VCC2 AGND1 VCC1 Power Supply DGND Zero Detect VDD Manager ZR2 System Clock ZR1/ZR1/FMT0 SCK Copyright © 2008–2015, Texas Instruments Incorporated Product Folder Links: PCM1681 PCM1681-Q1 PCM1681, PCM1681-Q1 www.ti.com SLES211C – FEBRUARY 2008 – REVISED JULY 2015 8.3 Feature Description 8.3.1 System Clock Input The PCM1681 and PCM1681-Q1 require a system clock for operating the digital interpolation filters and multilevel ΔΣ modulators. The system clock is applied at the SCK input (pin 5). Table 1 shows examples of system clock frequencies for common audio sampling rates. Figure 21 shows the timing requirements for the system clock input. For optimal performance, it is important to use a clock source with low phase jitter and noise. A Texas Instruments PLL170x multi-clock generator is an excellent choice for providing the PCM1681 and PCM1681-Q1 system clock source. Table 1. System Clock Frequencies for Common Audio Sampling Frequencies SYSTEM CLOCK FREQUENCY (fSCK), MHz SAMPLING FREQUENCY 128 fS 192 fS 256 fS 384 fS 512 fS 768 fS 8 kHz 1.024 1.536 2.048 3.072 4.096 6.144 9.216 16 kHz 2.048 3.072 4.096 6.144 8.192 12.288 18.432 32 kHz 4.096 6.144 8.192 12.288 16.384 24.576 36.864 44.1 kHz 5.6448 8.4672 11.2896 16.9344 22.5792 33.8688 — (1) 48 kHz 6.144 9.216 12.288 18.432 24.576 36.864 — (1) 88.2 kHz 96 kHz 192 kHz (1) 1152 fS 11.2896 16.9344 12.288 22.5792 18.432 24.576 24.576 36.864 — (1) 33.8688 36.864 — (1) — (1) — (1) — (1) — (1) — (1) — (1) — (1) — (1) — (1) This system clock frequency is not supported for the given sampling frequency. tw(SCKH) H 2V System Clock 0.8 V L tw(SCKL) tc(SCK)(1) T5A08 (1) System clock pulse cycle time; 1/128 fS, 1/192 fS, 1/256 fS, 1/384 fS, 1/512 fS, 1/768 fS, or 1/1152 fS Figure 21. System Clock Timing Diagram Table 2. System Clock Timing PARAMETER MIN MAX UNIT tc(SCK) System clock cycle time 25 ns tw(SCKH) System clock pulse duration, HIGH 10 ns tw(SCKL) System clock pulse duration, LOW 10 System clock duty cycle 40% ns 60% 8.3.2 Power-on-Reset Function The PCM1681 and PCM1681-Q1 include a power-on-reset function. Figure 22 shows the operation of this function. With the system clock active and VDD > 2.2 V (typical, 1.4 V to 2.9 V), the power-on-reset function is enabled. The initialization sequence requires 65,536 system clocks from the time VDD > 2.2 V. VDD must rise up with a ramp-up rate greater than 1V/ms to ensure reliable initialization. After the initialization period, the PCM1681 and PCM1681-Q1 are set to the respective reset default state, as described in the Mode Control Registers section of this data sheet. Copyright © 2008–2015, Texas Instruments Incorporated Product Folder Links: PCM1681 PCM1681-Q1 Submit Documentation Feedback 15 PCM1681, PCM1681-Q1 SLES211C – FEBRUARY 2008 – REVISED JULY 2015 www.ti.com During the reset period (65,536 system clocks), the analog output is forced to the common voltage (VCOM), or VCC/2. After the reset period, the internal register is initialized in the next 1/fS period and if SCK, BCK, and LRCK are provided continuously, the PCM1681 and PCM1681-Q1 provide the proper analog output with group delay corresponding to the input data. VDD 2.9 V 2.2 V 1.4 V Need ramp−up more than 1V/ms 0V Reset Release Reset State Fix Mode Control Selection Internal Reset Don’t Care 65536 System Clocks System Clock Figure 22. Power-On-Reset Timing 8.3.3 Audio Serial Interface The audio serial interface for the PCM1681 and PCM1681-Q1 is comprised of a 6-wire synchronous serial port. It includes LRCK (pin 8), BCK (pin 7), and DATA1 (pin 6), DATA2 (pin 11), DATA3 (pin 12), and DATA4 (pin 13). BCK is the serial audio bit clock, and it is used to clock the serial data present on DATA1, DATA2, DATA3, and DATA4 into the audio interface serial shift register. Serial data are clocked into the PCM1681 and PCM1681-Q1 on the rising edge of BCK. LRCK is the serial audio left/right word clock. It is used to latch serial data into the serial audio interface internal registers. Both LRCK and BCK must be synchronous with the system clock, SCK. Ideally, it is recommended that LRCK and BCK are derived from SCK. LRCK is operated at the sampling frequency, fS. BCK can be operated at 32, 48, or 64 times the sampling frequency for the PCM formats and times at 128 and 256 the sampling frequency for the TDM formats. Internal operation of the PCM1681 and PCM1681-Q1 is synchronized with LRCK. Accordingly, internal operation is suspended when LRCK is changed or when SCK and/or BCK is interrupted for at least 3-bit clock cycles. If SCK, BCK, and LRCK are provided continuously after this held condition, the internal operation is resynchronized automatically within the following 3/fS period. External resetting is not required. 8.3.4 Audio Data Formats and Timing The PCM1681 and PCM1681-Q1 support industry-standard audio data formats, including right-justified, I2S, leftjustified, and DSP. The PCM1681 and PCM1681-Q1 also support a time-division-multiplexed (TDM) format. The TDM format is supported only at system clocks of 128 fS, 256 fS, and 512 fS. The data formats are shown in Figure 23 and Figure 24. Data formats are selected using the format bits, FMT[3:0], located in control register 9 of the PCM1681 and PCM1681-Q1. The default data format is 16- to 24-bit left-justified. All formats require binary 2s complement, MSB-first audio data. Figure 25 shows a detailed timing diagram for the serial audio interface. DATA1, DATA2, DATA3, and DATA4 each carry two audio channels, designated as the left and right channels in the right-justified, I2S, left-justified, and DSP formats. The left-channel data always precedes the right-channel data in the serial data stream for all data formats. Table 3 shows the mapping of the digital input data to the analog output pins. DATA1 carries eight audio channels in 256 fS mode TDM fornat, and DATA1 and DATA2 each carry four audio channels in 128 fS mode TDM format. Table 3. Audio Input Data to Analog Output Mapping DATA INPUT DATA1 16 Submit Documentation Feedback CHANNEL ANALOG OUTPUT Left VOUT1 Right VOUT2 Copyright © 2008–2015, Texas Instruments Incorporated Product Folder Links: PCM1681 PCM1681-Q1 PCM1681, PCM1681-Q1 www.ti.com SLES211C – FEBRUARY 2008 – REVISED JULY 2015 Table 3. Audio Input Data to Analog Output Mapping (continued) DATA INPUT CHANNEL ANALOG OUTPUT Left VOUT3 Right VOUT4 Left VOUT5 Right VOUT6 Left VOUT7 Right VOUT8 DATA2 DATA3 DATA4 (1) Right-Justified Data Format; L-Channel = HIGH, R-Channel = LOW 1/fS L-Channel LRCK R-Channel BCK (= 32 fS, 48 fS, or 64 fS) 16-Bit Right-Justified, BCK = 32 fS DATA 14 15 16 1 2 3 14 15 16 1 LSB MSB 2 3 14 15 16 MSB LSB 16-Bit Right-Justified, BCK = 48 f S or 64 fS DATA 14 15 16 1 2 3 14 15 16 MSB 1 2 3 14 15 16 MSB LSB LSB 24-Bit Right-Justified, BCK = 48 fS or 64 fS DATA 22 23 24 1 2 3 22 23 24 MSB 1 2 LSB 3 22 23 24 MSB LSB (2) I2S Data Format; L-Channel = LOW, R-Channel = HIGH 1/fS LRCK L-Channel R-Channel BCK (= 32 fS, 48 fS or 64 fS) DATA 1 2 3 N–2 N–1 MSB LSB N 1 2 3 N–2 MSB N–1 N 1 2 N 1 2 LSB (3) Left-Justified Data Format; L-Channel = HIGH, R-Channel = LOW (default) 1/fS LRCK L-Channel R-Channel BCK (= 32 fS, 48 fS, or 64 fS) DATA 1 2 3 N–2 N–1 MSB LSB N 1 2 3 MSB N–2 N–1 LSB Figure 23. Audio Data Input Formats Copyright © 2008–2015, Texas Instruments Incorporated Product Folder Links: PCM1681 PCM1681-Q1 Submit Documentation Feedback 17 PCM1681, PCM1681-Q1 SLES211C – FEBRUARY 2008 – REVISED JULY 2015 www.ti.com (4) 24-Bit DSP Format 1/fs (64 BCKs) LRCK BCK (= 64fS) LJ mode DATA 1 2 3 1 2 22 23 24 1 2 3 1 2 22 23 24 1 2 3 1 2 2 I S mode DATA 22 23 24 3 3 22 23 24 (5) 24-Bit TDM Format 1/fs (256 BCKs or 128 BCKs) LRCK tLRW BCK (= 128 fS or 256 fS) tLRW tLRW LJ mode DATA1 *1 2 I S mode DATA1 *1 LJ mode DATA1/2 *2 1 2 1 2 CH1 32 BCKs 1 2 24 1 2 24 1 2 CH2 32 BCKs 1 2 23 24 1 2 23 24 24 1 2 CH3 32 BCKs 24 1 2 1 2 CH1/CH5 32 BCKs 2 I S mode DATA1/2 *2 24 24 24 1 2 CH4 32 BCKs 1 2 23 24 24 23 24 1 2 CH5 32 BCKs 1 2 1 2 24 24 1 2 CH6 32 BCKs 1 2 23 24 24 1 2 23 24 24 1 2 CH7 32 BCKs 1 2 1 2 CH3/CH7 32 BCKs CH2/CH6 32 BCKs 1 2 24 24 24 1 2 CH8 32 BCKs 1 2 23 24 24 1 2 1 2 CH4/CH8 32 BCKs 1 2 23 24 1 2 *1: BCK = 256 fS mode *2: BCK = 128 fS mode Figure 24. Audio Data Input Formats 18 Submit Documentation Feedback Copyright © 2008–2015, Texas Instruments Incorporated Product Folder Links: PCM1681 PCM1681-Q1 PCM1681, PCM1681-Q1 www.ti.com SLES211C – FEBRUARY 2008 – REVISED JULY 2015 t(LRW) 1.4 V LRCK t(BCL) t(BCH) t(LH) t(LS) 1.4 V BCK t(BCY) t(DS) t(DH) DATA1, DATA2, DATA3, DATA4 1.4 V Figure 25. Audio Interface Timing Diagram Table 4. Audio Interface Timing PARAMETER t(BCY) BCK cycle time t(BCH) BCK pulse duration HIGH t(BCL) BCK pulse duration LOW t(LRW) MIN MAX UNIT 75 (1) ns 35 ns 35 ns LRCK pulse duration HIGH, right-justified, I2S, left-justified 1/2 fS LRCK pulse duration HIGH, DSP format t(BCY) t(BCY) LRCK pulse duration HIGH, TDM format t(BCY) 1/fS – t(BCY) 1/2 fS t(LS) LRCK setup time to BCK rising edge 10 ns t(LH) LRCK hold time to BCK rising edge 10 ns t(DS) DATA1, DATA2, DATA3, DATA4 setup time to BCK rising edge 10 ns t(DH) DATA1, DATA2, DATA3, DATA4 hold time to BCK rising edge 10 ns (1) 2 For right-justified, I S, left-justified, and DSP formats, there is no fS (sampling frequency) limitation for all of 1/32 fS, 1/48 fS, or 1/64 fS. However, for TDM format, allowable fS is limited to fS ≤ 50 kHz for BCK = 256 fS mode and fS ≤ 100 kHz for BCK = 128 fS mode. 8.3.5 De-Emphasis Filter The PCM1681 and PCM1681-Q1 include a digital de-emphasis filter for 32 kHz, 44.1 kHz, and 48 kHz sampling frequencies. 8.3.6 Oversampling Rate Control The PCM1681 and PCM1681-Q1 automatically control the oversampling rate of the ΔΣ DACs according to system clock frequency and oversampling mode. Oversampling mode, narrow or wide, can be selected by the MSEL pin in H/W control mode and the OVER bit of control register 12 in S/W control mode. The oversampling rate is set to 64× oversampling with a 1152 fS, 768 fS, 512 fS system clock, 32× oversampling with a 384 fS, 256 fS system clock, and 16× oversampling with a 192 fS, 128 fS system clock in default, narrow mode, and 128× oversampling with a 1152 fS, 768 fS, 512 fS system clock, 64× oversampling with a 384 fS, 256 fS system clock, and 32× oversampling with a 192 fS, 128 fS system clock in wide mode. Wide mode is recommended for fS ≤ 96 kHz at SCK = 128 fS or 192 fS, fS ≤ 48 kHz at SCK = 256 fS or 384 fS, and fS ≤ 24 kHz at SCK = 512 fS, 768 fS, or 1152 fS. Copyright © 2008–2015, Texas Instruments Incorporated Product Folder Links: PCM1681 PCM1681-Q1 Submit Documentation Feedback 19 PCM1681, PCM1681-Q1 SLES211C – FEBRUARY 2008 – REVISED JULY 2015 www.ti.com Table 5. Oversampling Rate Control OVERSAMPLING RATE OVERSAMPLING MODE SCK = 128 fS or 192 fS SCK = 256 fS or 384 fS SCK = 512 fS, 768 fS, or 1152 fS Narrow mode 16× 32× 64× Wide mode 32× 64× 128× 8.3.7 Zero Flag The PCM1681 and PCM1681-Q1 have two zero-flag pins, ZR1 (pin 1) and ZR2 (pin 28), which are assigned to the combinations A through D as shown in Table 6. Zero-flag combinations are selected using the zero-flag combination bits, AZRO[1:0], located in control register 13 of the PCM1681 and PCM1681-Q1. If the input data of the L-channel and/or R-channel of all assigned channels remains at a logic-0 level for 1024 sampling periods (LRCK clock periods), ZR1 and ZR2 are set to logic-1 states, or high level. If the input data of any of the assigned channels contains a logic-1 level, ZR1 and ZR2 are set to logic-0 states or low level immediately. The active polarity of a zero-flag output can be inverted by setting the ZREV bit of control register 10 to 1. The reset default is ZREV = 0, active-high for zero detection. In parallel hardware control mode, ZR1 is not applicable due to the reassignment of ZR1 as the FMT0 control pin, and the zero-flag output combination is fixed as all 8 channel (DATA1-DATA4) data zero on the ZR2 pin. Table 6. Zero-Flag Output Combinations ZERO-FLAG COMBINATION ZR1/ZR1/FMT0 (PIN 1) ZR2 (PIN 28) A DATA1 L-ch DATA1 R-ch B DATA1-4 DATA1-4 C DATA4 DATA1-3 D DATA1 DATA2-4 8.3.8 Mode Control The PCM1681 and PCM1681-Q1 support three types of interface mode control with three types of oversampling configuration, according to the input state of MSEL (pin 14) as listed in Table 7. The required values of the pullup and pull-down resistors are 220 kΩ ± 5%. Table 7. Interface Mode Control MSEL INTERFACE MODE CONTROL Tied with DGND 2-Wire (I2C) serial control, selectable oversampling configuration Pull-down resistor to DGND 4-Wire parallel H/W control, narrow mode oversampling configuration Pull-up resistor to VDD 4-Wire parallel H/W control, wide mode oversampling configuration Tied with VDD 3-Wire (SPI) serial control, selectable oversampling configuration The input state of the MSEL pin is sampled at power-on with the system clock input; therefore, an input change after a reset is ignored until the next power-on. The assignments of the four pins are controlled by the interface mode control setting as listed in Table 8. Table 8. Interface Mode Control Pin Assignments PIN 20 DEFINITION (Assignment) I2C SPI 4 SDA (input/output) MD (input) MUTE (input) 3 SCL (input) MC (input) DEMP (input) PARALLEL H/W 2 ADR (input) MS (input) FMT1 (input) 1 ZR1 (output) ZR1 (output) FMT0 (input) Submit Documentation Feedback Copyright © 2008–2015, Texas Instruments Incorporated Product Folder Links: PCM1681 PCM1681-Q1 PCM1681, PCM1681-Q1 www.ti.com SLES211C – FEBRUARY 2008 – REVISED JULY 2015 In serial control mode, actual mode control is performed by a register write (and read) through the I2C or SPI compatible serial control port. In parallel H/W control mode, the specific four functions are controlled directly through high-level/low-level control of five specific pins (see Parallel Hardware Control section), and the zero-flag function of ZR1 is not applicable. 8.3.8.1 Parallel Hardware Control Four functions are controlled by five pins, MSEL, FMT0, FMT1, DEMP, and MUTE in parallel hardware control mode. (1) MSEL TERMINATION (1) DESCRIPTION Pull-down resistor to DGND Narrow oversampling mode Pull-up resistor to VDD Wide oversampling mode The MSEL termination controls the oversampling mode for all eight channels. FMT1 (1) (1) (1) (1) FMT0 (1) DESCRIPTION LOW LOW 24-bits right-justified format LOW HIGH 16 to 24-bits I2S format HIGH LOW 16 to 24-bits left-justified format HIGH HIGH 24-bits I2S mode TDM format The FMT0 and FMT1 pins control the audio interface format for all eight channels. DEMP (1) DESCRIPTION LOW De-emphasis off HIGH 44.1-kHz De-emphasis on The DEMP pin controls the 44.1-kHz digital de-emphasis function of all eight channels. MUTE (1) DESCRIPTION LOW Mute off (mute disable) HIGH Mute on (mute enable) The MUTE pin controls all 8 channel outputs at the same time. 8.3.8.2 SPI Control Interface The SPI control interface of the PCM1681 and PCM1681-Q1 is a 3-wire synchronous serial port that operates asynchronously to the serial audio interface. The SPI control interface is used to program the on-chip mode registers. The control interface includes MD (pin 4), MC (pin 3), and MS (pin 2). MD is the serial data input, used to program the mode registers. MC is the control port for the serial bit clock, used to shift in the serial data, and MS is the control port for mode control select, which is used to enable the mode control. The SPI control interface is available when MSEL (pin 14) is tied with VDD and after power-on reset completion. 8.3.8.3 Analog Outputs The PCM1681 and PCM1681-Q1 include eight independent output channels, VOUT1 through VOUT8. These are unbalanced outputs, each capable of driving 3.75 VPP typical into a 5-kΩ ac load with VCC = 5 V. The internal output amplifiers for VOUT1 through VOUT8 are biased to the dc common voltage, equal to 0.486 VCC. The output amplifiers include an RC continuous-time filter, which helps to reduce the out-of-band noise energy present at the DAC outputs due to the noise-shaping characteristics of the PCM1681 and PCM1681-Q1 ΔΣ DACs. The frequency response of this filter is shown in Figure 12. By itself, this filter is not enough to attenuate the out-of-band noise to an acceptable level for most applications. An external low-pass filter is required to provide sufficient out-of-band noise rejection. Further discussion of DAC post-filter circuits is provided in the Application and Implementation section of this data sheet. Copyright © 2008–2015, Texas Instruments Incorporated Product Folder Links: PCM1681 PCM1681-Q1 Submit Documentation Feedback 21 PCM1681, PCM1681-Q1 SLES211C – FEBRUARY 2008 – REVISED JULY 2015 www.ti.com 8.3.8.3.1 VCOM Output One unbuffered common voltage output pin, VCOM (pin 25), is brought out for decoupling purposes. This pin is nominally biased to the dc common voltage, equal to VCC/2. If this pin is to be used to bias external circuitry, a voltage follower is required for buffering purposes. Figure 26 shows an example of a 5-V single-supply filter circuit using the VCOM pin for external biasing applications. AV = - R2 R1 PCM1681 PCM1681-Q1 C1 R3 5V 2 VOUTX 3 C2 - 1 1/2 of OPA2353 R4 C4 10 mF + R2 R1 47 W + R5 10 kW 5V VCOM + + To Additional Low-Pass Filter Circuits OPA337 C3 10 mF - Example: R1: 6.2 kΩ R2: 6.8 kΩ R3: 430 Ω C1: 470 pF C2: 4700 pF AV: –1.10 (1.45 Vrms Output) fC: 70 kHz Figure 26. Single-Supply Filter Circuit Using VCOM for External Biasing Applications 8.3.8.4 Register Write Operation All write operations for the serial control port use 16-bit data words. Figure 27 shows the control data word format. The most significant bit is a fixed 0 for the write operation. Seven bits, labeled IDX[6:0], set the register index (or address) for the write operation. The least significant eight bits, D[7:0], contain the data to be written to the register specified by IDX[6:0]. Figure 28 shows the functional timing diagram for writing to the serial control port. MS is held at a logic-1 state until a register needs to be written. To start the register write cycle, MS is set to logic-0. 16 clock cycles are then provided on MC, corresponding to the 16 bits of the control data word on MD. After completion of the 16th clock cycle, MS is set to logic-1 to latch the data into the indexed mode control register. LSB MSB 0 IDX6 IDX5 IDX4 IDX3 IDX2 IDX1 Register Index (or Address) IDX0 D7 D6 D5 D4 D3 D2 D1 D0 Register Data R0001-01 Figure 27. Control Data Word Format for MD 22 Submit Documentation Feedback Copyright © 2008–2015, Texas Instruments Incorporated Product Folder Links: PCM1681 PCM1681-Q1 PCM1681, PCM1681-Q1 www.ti.com SLES211C – FEBRUARY 2008 – REVISED JULY 2015 MS MC MD 0 X IDX6 IDX5 IDX4 IDX3 IDX2 IDX1 IDX0 D7 D6 D5 D4 D3 D2 D1 D0 X X 0 IDX6 T0048-01 Figure 28. Write Operation Timing 8.3.8.5 Interface Timing Requirements Figure 29 shows a detailed timing diagram for the serial control interface. Special attention to the setup and hold times is required. Also, t(MSS) and t(MSH), which define the minimum delays between the edges of the MS and MC clocks, require special attention. These timing parameters are critical for proper control port operation. t(MHH) MS t(MSS) t(MCL) t(MCH) t(MSH) MC t(MCY) LSB MD t(MDS) t(MDH) T0013-03 Figure 29. Interface Timing Diagram Table 9. Interface Timing MIN UNIT t(MCY) MC cycle time PARAMETER 100 ns t(MCL) MC pulse duration, LOW 50 ns t(MCH) MC pulse duration, HIGH 50 t(MHH) MS pulse duration, HIGH t(MSS) MS falling edge to MC rising edge 20 ns t(MSH) MS hold time, MC rising edge for LSB to MS rising edge 20 ns t(MDH) MD hold time 15 ns t(MDS) MD setup time 20 ns (1) ns ns (1) 3/(256 fS) s (minimum), fS: sampling rate Copyright © 2008–2015, Texas Instruments Incorporated Product Folder Links: PCM1681 PCM1681-Q1 Submit Documentation Feedback 23 PCM1681, PCM1681-Q1 SLES211C – FEBRUARY 2008 – REVISED JULY 2015 www.ti.com 8.4 Device Functional Modes 8.4.1 Control Modes • 3-wire SPI • I2C • Hardware Control 8.4.2 Audio Modes • Right or left justified • I2S • TDM • DSP 8.5 Programming 8.5.1 I2C Interface The PCM1681 and PCM1681-Q1 support the I2C serial bus and the data transmission protocol for standard mode as a slave device. This protocol is explained in the I2C specification 2.0. The PCM1681 and PCM1681-Q1 do not support a board-to-board interface. The I2C control interface is available when MSEL (pin 14) is tied with DGND and after power-on reset completion. 8.5.1.1 Slave Address MSB 1 LSB 0 0 1 1 0 ADR R/W The PCM1681 and PCM1681-Q1 have seven bits for the respective slave address. The first six bits (MSBs) of the slave address are factory preset to 1001 10. The next bit of the address byte is the device select bit, which can be user-defined using the ADR terminal. A maximum of two PCM1681s or PCM1681-Q1s can be connected on the same bus at one time. Each PCM1681 or PCM1681-Q1 responds when it receives its own slave address. 8.5.1.2 Packet Protocol A master device must control packet protocol, which consists of a start condition, slave address, read/write bit, data if writing or acknowledge if reading, and stop condition. The PCM1681 and PCM1681-Q1 support only slave receivers and slave transmitters. The details about DATA for write and read operation are described in the following sections. 24 Submit Documentation Feedback Copyright © 2008–2015, Texas Instruments Incorporated Product Folder Links: PCM1681 PCM1681-Q1 PCM1681, PCM1681-Q1 www.ti.com SLES211C – FEBRUARY 2008 – REVISED JULY 2015 SDA SCL St 1−7 8 9 1−8 9 1−8 9 9 Slave Address R/W ACK DATA ACK DATA ACK ACK R/W: Read Operation if 1; Otherwise, Write Operation ACK: Acknowledgement of a Byte if 0 DATA: 8 Bits (Byte), the details are described in write and read operation NACK: Not Acknowledgement if 1 Start Condition Write Operation Sp Stop Condition Transmitter M M M S M S M S S M Data Type St Slave Address W ACK DATA ACK DATA ACK ACK Sp Read Operation Transmitter M M M S S M S M M M Data Type St Slave Address R ACK DATA ACK DATA ACK NACK Sp M: Master Device S: Slave Device St: Start Condition Sp: Stop Condition W: Write R: Read T0049-01 Figure 30. Basic I2C Framework 8.5.1.3 Write Operation A master can write to any PCM1681 and PCM1681-Q1 registers using a single access. The master sends a PCM1681 or PCM1681-Q1 slave address with a write bit, a register address, and the data. When undefined registers are accessed, the PCM1681 or PCM1681-Q1 sends an acknowledgment, but the write operation does not occur. Figure 31 is a diagram of the write operation. Transmitter M M M S M S M S M Data Type St Slave Address W ACK Reg Address ACK Write Data ACK Sp M: Master Device S: Slave Device St: Start Condition W: Write ACK: Acknowledge Sp: Stop Condition R0002-01 Figure 31. Write Operation 8.5.1.4 Read Operation A master can read any PCM1681 or PCM1681-Q1 register using a single access. The master sends a PCM1681 or PCM1681-Q1 slave address with a read bit after transferring the register address. Then the PCM1681 or PCM1681-Q1 transfers the data in the register specified. Figure 32 is a diagram of the read operation. Copyright © 2008–2015, Texas Instruments Incorporated Product Folder Links: PCM1681 PCM1681-Q1 Submit Documentation Feedback 25 PCM1681, PCM1681-Q1 SLES211C – FEBRUARY 2008 – REVISED JULY 2015 www.ti.com Transmitter M M M S M S M M M S Data Type St Slave Address W ACK Reg Address ACK Sr Slave Address R ACK S M M Read Data NACK Sp M: Master Device S: Slave Device St: Start Condition Sr: Repeated Start Condition ACK: Acknowledge Sp: Stop Condition NACK: Not Acknowledge W: Write R: Read R0002-02 NOTE: The slave address after the repeated start condition must be the same as the previous slave address. Figure 32. Read Operation 8.5.2 Mode Control Registers 8.5.2.1 User-Programmable Mode Controls The PCM1681 and PCM1681-Q1 include a number of user-programmable functions which are accessed via control registers. The registers are programmed using the serial control interface which is discussed in the Mode Control section of this data sheet. Table 10 lists the available mode control functions, along with the respective reset default conditions and associated register index. 8.6 Register Maps The mode control register map is shown in Table 11. The MSB of all registers is fixed to 0. Each register also includes an index (or address) indicated by the IDX[6:0] bits. 8.6.1 Reserved Registers Registers 0 and 15 are reserved for factory use. To ensure proper operation, the user should not write to these registers. Table 10. User-Programmable Mode Control Functions FUNCTION RESET DEFAULT REGISTER BIT 1–6, 16, 17 AT1[7:0], AT2[7:0], AT3[7:0], AT4[7:0], AT5[7:0], AT6[7:0], AT7[7:0], AT8[7:0] Mute disabled 7, 18 MUT[8:1], MUT[8:7] DAC1–DAC8 enabled 8, 19 DAC[8:1], DAC[8:7] 9 FMT[3:0] Digital attenuation control, 0 dB to –63 dB in 0.5-dB steps 0 dB, no attenuation Soft mute control DAC1–DAC8 operation control Audio data format control 16- to 24-bit, left-justified Digital filter roll-off control Sharp roll-off 9 FLT De-emphasis all-channel function control De-emphasis of all channels disabled 10 DMC De-emphasis all-channel sample rate selection 44.1 kHz 10 DMF[1:0] Output phase select Normal phase 10 DREV Zero-flag polarity select High 10 ZREV Software reset control Reset disabled 10 SRST Output phase select per channel Reverse phase 11 REV[8:1] Oversampling rate control Narrow (×64, ×32, ×16) mode 12 OVER Digital filter roll-off control per DATA group Slow roll-off 12 FLT[4:1] Zero-flag combination select ZR1: DATA1 Lch ZR2: DATA1 Rch 13 AZRO[1:0] Digital attenuation mode select 0 to –63 dB, 0.5-dB step 13 DAMS Zero-detect status (read-only, I2C interface only) N/A 14 ZERO[8:1] 26 Submit Documentation Feedback Copyright © 2008–2015, Texas Instruments Incorporated Product Folder Links: PCM1681 PCM1681-Q1 PCM1681, PCM1681-Q1 www.ti.com SLES211C – FEBRUARY 2008 – REVISED JULY 2015 Table 11. Mode Control Register Map IDX (B8–B14) REGISTER B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 00h 0 0 IDX6 IDX5 IDX4 IDX3 IDX2 IDX1 IDX0 N/A (1) N/A (1) N/A (1) N/A (1) N/A (1) N/A (1) N/A (1) N/A (1) 01h 1 0 IDX6 IDX5 IDX4 IDX3 IDX2 IDX1 IDX0 AT17 AT16 AT15 AT14 AT13 AT12 AT11 AT10 02h 2 0 IDX6 IDX5 IDX4 IDX3 IDX2 IDX1 IDX0 AT27 AT26 AT25 AT24 AT23 AT22 AT21 AT20 03h 3 0 IDX6 IDX5 IDX4 IDX3 IDX2 IDX1 IDX0 AT37 AT36 AT35 AT34 AT33 AT32 AT31 AT30 04h 4 0 IDX6 IDX5 IDX4 IDX3 IDX2 IDX1 IDX0 AT47 AT46 AT45 AT44 AT43 AT42 AT41 AT40 05h 5 0 IDX6 IDX5 IDX4 IDX3 IDX2 IDX1 IDX0 AT57 AT56 AT55 AT54 AT53 AT52 AT51 AT50 06h 6 0 IDX6 IDX5 IDX4 IDX3 IDX2 IDX1 IDX0 AT67 AT66 AT65 AT64 AT63 AT62 AT61 AT60 07h 7 0 IDX6 IDX5 IDX4 IDX3 IDX2 IDX1 IDX0 MUT8 MUT7 MUT6 MUT5 MUT4 MUT3 MUT2 MUT1 08h 8 0 IDX6 IDX5 IDX4 IDX3 IDX2 IDX1 IDX0 DAC8 DAC7 DAC6 DAC5 DAC4 DAC3 DAC2 DAC1 09h 9 0 IDX6 IDX5 IDX4 IDX3 IDX2 IDX1 IDX0 RSV (2) RSV (2) FLT RSV (2) FMT3 FMT2 FMT1 FMT0 0Ah 10 0 IDX6 IDX5 IDX4 IDX3 IDX2 IDX1 IDX0 SRST ZREV DREV DMF1 DMF0 RSV (2) RSV (2) DMC 0Bh 11 0 IDX6 IDX5 IDX4 IDX3 IDX2 IDX1 IDX0 REV8 REV7 REV6 REV5 REV4 REV3 REV2 REV1 0Ch 12 0 IDX6 IDX5 IDX4 IDX3 IDX2 IDX1 IDX0 OVER RSV (2) RSV (2) RSV (2) FLT4 FLT3 FLT2 FLT1 0Dh 13 0 IDX6 IDX5 IDX4 IDX3 IDX2 IDX1 IDX0 DAMS AZRO1 AZRO0 RSV (2) RSV (2) RSV (2) RSV (2) RSV (2) 0Eh 14 0 IDX6 IDX5 IDX4 IDX3 IDX2 IDX1 IDX0 ZERO8 ZERO7 ZERO6 ZERO5 ZERO4 ZERO3 ZERO2 ZERO1 10h 16 0 IDX6 IDX5 IDX4 IDX3 IDX2 IDX1 IDX0 AT77 AT76 AT75 AT74 AT73 AT72 AT71 AT70 11h 17 0 IDX6 IDX5 IDX4 IDX3 IDX2 IDX1 IDX0 AT87 AT86 AT85 AT84 AT83 AT82 AT81 AT80 12h 18 0 IDX6 IDX5 IDX4 IDX3 IDX2 IDX1 IDX0 RSV (2) RSV (2) RSV (2) RSV (2) RSV (2) RSV (2) MUT8 MUT7 13h 19 0 IDX6 IDX5 IDX4 IDX3 IDX2 IDX1 IDX0 RSV (2) RSV (2) RSV (2) RSV (2) RSV (2) RSV (2) DAC8 DAC7 (1) (2) Not assigned. No operation even if setting any data Reserved for test operation. It should be set to 0 during normal operation. 8.6.2 Register Definitions REGISTER REGISTER REGISTER REGISTER REGISTER REGISTER REGISTER REGISTER B15 0 0 0 0 0 0 0 0 1 2 3 4 5 6 16 17 B14 IDX6 IDX6 IDX6 IDX6 IDX6 IDX6 IDX6 IDX6 B13 IDX5 IDX5 IDX5 IDX5 IDX5 IDX5 IDX5 IDX5 B12 IDX4 IDX4 IDX4 IDX4 IDX4 IDX4 IDX4 IDX4 B11 IDX3 IDX3 IDX3 IDX3 IDX3 IDX3 IDX3 IDX3 B10 IDX2 IDX2 IDX2 IDX2 IDX2 IDX2 IDX2 IDX2 B9 IDX1 IDX1 IDX1 IDX1 IDX1 IDX1 IDX1 IDX1 B8 IDX0 IDX0 IDX0 IDX0 IDX0 IDX0 IDX0 IDX0 B7 AT17 AT27 AT37 AT47 AT57 AT67 AT77 AT87 B6 AT16 AT26 AT36 AT46 AT56 AT66 AT76 AT86 B5 AT15 AT25 AT35 AT45 AT55 AT65 AT75 AT85 B4 AT14 AT24 AT34 AT44 AT54 AT64 AT74 AT84 B3 AT13 AT23 AT33 AT43 AT53 AT63 AT73 AT83 B2 AT12 AT22 AT32 AT42 AT52 AT62 AT72 AT82 B1 AT11 AT21 AT31 AT41 AT51 AT61 AT71 AT81 B0 AT10 AT20 AT30 AT40 AT50 AT60 AT70 AT80 8.6.2.1 ATx[7:0]: Digital Attenuation Level Setting where x = 1–8, corresponding to the DAC output VOUTx. Default value: 1111 1111b ATx[7:0] DECIMAL VALUE 1111 1111b 1111 1110b 1111 1101b ATTENUATION LEVEL SETTING DAMS = 0 DAMS = 1 255 0 dB, no attenuation (default) 0 dB, no attenuation (default) 254 –0.5 dB –1 dB 253 –1 dB –2 dB : : : : 1001 1100b 156 –49.5 dB –99 dB 1001 1011b 155 –50 dB –100 dB 1001 1010b 154 –50.5 dB Mute : : : : 1000 0010b 130 –62.5 dB Mute 1000 0001b 129 –63 dB Mute 1000 0000b 128 Mute Mute : : : : 0000 0000b 0 Mute Mute Copyright © 2008–2015, Texas Instruments Incorporated Product Folder Links: PCM1681 PCM1681-Q1 Submit Documentation Feedback 27 PCM1681, PCM1681-Q1 SLES211C – FEBRUARY 2008 – REVISED JULY 2015 www.ti.com Each DAC output, VOUT1 through VOUT8, has a digital attenuation function. The attenuation level can be set from 0 dB to R dB, in S-dB steps. Changes in attenuation levels are made by incrementing or decrementing by one step (S-dB) for every 8/fS time interval until the programmed attenuation setting is reached. Alternatively, the attenuation level can be set to infinite attenuation (or mute). Range (R) and step (S) are –63 and 0.5, respectively, for DAMS = 0 and –100 and 1, respectively, for DAMS = 1. The DAMS bit is defined in register 13. The attenuation data for each channel can be set individually. The attenuation level can be calculated using the following formula: Attenuation level (dB) = S • (ATx[7:0]DEC – 255) where ATx[7:0]DEC = 0 through 255. For ATx[7:0]DEC = 0 through 128 with DAMS = 0 or for ATx[7:0]DEC = 0 through 154 with DAMS = 1, the attenuation is set to infinite attenuation (mute). REGISTER 7 REGISTER 18 B15 0 0 B14 B13 B12 B11 B10 B9 B8 B7 IDX6 IDX5 IDX4 IDX3 IDX2 IDX1 IDX0 MUT8 IDX6 IDX5 IDX4 IDX3 IDX2 IDX1 IDX0 RSV B6 MUT7 RSV B5 MUT6 RSV B4 MUT5 RSV B3 MUT4 RSV B2 MUT3 RSV B1 MUT2 MUT8 B0 MUT1 MUT7 8.6.2.2 MUTx: Soft Mute Control where x = 1–8, corresponding to the DAC output VOUTx. Default value: 0 MUTx 0 1 SOFT MUTE CONTROL Mute disabled (default) Mute enabled The mute bits, MUT1 through MUT8, are used to enable or disable the soft mute function for the corresponding DAC outputs, VOUT1 through VOUT8. MUT7 and MUT8 of register 7 and register 18 work as an OR function, either one or both can be used according to the requirements of the application. The soft mute function is incorporated into the digital attenuators. When mute is disabled (MUTx = 0), the attenuator and DAC operate normally. When mute is enabled by setting MUTx = 1, the digital attenuator for the corresponding output is decreased from the current setting to the infinite-attenuation setting one attenuator step (S-dB) at a time. This provides a quiet, pop-free muting of the DAC output. On returning from soft mute, by setting MUTx = 0, the attenuator is increased one step at a time to the previously programmed attenuator level. The step size, S, is 0.5 dB for DAMS = 0 and 1 dB for DAMS = 1. REGISTER 8 REGISTER 19 B15 0 0 B14 B13 B12 B11 B10 B9 B8 IDX6 IDX5 IDX4 IDX3 IDX2 IDX1 IDX0 IDX6 IDX5 IDX4 IDX3 IDX2 IDX1 IDX0 B7 DAC8 RSV B6 DAC7 RSV B5 DAC6 RSV B4 DAC5 RSV B3 DAC4 RSV B2 DAC3 RSV B1 DAC2 DAC8 B0 DAC1 DAC7 8.6.2.3 DACx: DAC Operation Control where x = 1–8, corresponding to the DAC output VOUTx. Default value: 0 DACx 0 1 DAC OPERATION CONTROL DAC operation enabled (default) DAC operation disabled The DAC operation controls are used to enable and disable the DAC outputs, VOUT1 through VOUT8. When DACx = 0, the output amplifier input is connected to the DAC output. When DACx = 1, the output amplifier input is switched to the dc common voltage (VCOM), equal to VCC/2. DAC7 and DAC8 of register 8 and register 19 work as an OR function, either one or both can be used according to the requirements of the application. REGISTER 9 28 B15 0 B14 B13 B12 B11 IDX6 IDX5 IDX4 IDX3 Submit Documentation Feedback B10 IDX2 B9 B8 IDX1 IDX0 B7 RSV B6 RSV B5 FLT B4 RSV B3 FMT3 B2 FMT2 B1 FMT1 B0 FMT0 Copyright © 2008–2015, Texas Instruments Incorporated Product Folder Links: PCM1681 PCM1681-Q1 PCM1681, PCM1681-Q1 www.ti.com SLES211C – FEBRUARY 2008 – REVISED JULY 2015 8.6.2.4 FLT: Digital Filter Roll-Off Control Default value: 0 FLT 0 1 DIGITAL FILTER ROLL-OFF CONTROL Sharp roll-off (default) Slow roll-off The FLT bit allows users to select the digital filter roll-off that is best suited to their application. Two filter roll-off selections are available: sharp or slow. The filter responses for these selections are shown in the Typical Characteristics section of this data sheet. 8.6.2.5 FMT[3:0]: Audio Interface Data Format Default value: 0101b FMT[3:0] 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 AUDIO DATA FORMAT SELECTION Right-justified format, 24-bit Reserved Reserved Right-justified format, 16-bit I2S format, 16- to 24-bit Left-justified format, 16- to 24-bit (default) I2S format, TDM format, 24-bit Left-justified format, TDM format, 24-bit I2S format, DSP format, 24-bit Left-justified format, DSP format, 24-bit The FMT[3:0] bits are used to select the data format for the serial audio interface. The format details and restrictions related with the system clock are described in the section Audio Data Formats and Timing. REGISTER 10 B15 0 B14 B13 B12 B11 B10 B9 B8 IDX6 IDX5 IDX4 IDX3 IDX2 IDX1 IDX0 B7 SRST B6 ZREV B5 DREV B4 DMF1 B3 DMF0 B2 RSV B1 RSV B0 DMC 8.6.2.6 SRST: Reset Default value: 0 SRST 0 1 RESET Reset disabled (default) Reset enabled The SRST bit is used to enable or disable the soft reset function. The operation is the same as the power-onreset function with the exception of the reset period, which is 1024 system clocks for the SRST function. All registers are initialized. 8.6.2.7 ZREV: Zero-Flag Polarity Select Default value: 0 ZREV 0 1 ZERO-FLAG POLARITY SELECT Zero-flag pins high at a zero detect (default) Zero-flag pins low at a zero detect The ZREV bit allows the user to select the polarity of the zero-flag pins. Copyright © 2008–2015, Texas Instruments Incorporated Product Folder Links: PCM1681 PCM1681-Q1 Submit Documentation Feedback 29 PCM1681, PCM1681-Q1 SLES211C – FEBRUARY 2008 – REVISED JULY 2015 www.ti.com 8.6.2.8 DREV: Output Phase Select Default value: 0 DREV 0 1 OUTPUT PHASE SELECT Normal output (default) Inverted output The DREV bit allows the user to select the phase of the analog output signal. 8.6.2.9 DMF[1:0]: Sampling Frequency Selection for the De-Emphasis Function Default value: 00b DMF[1:0] 00 01 10 11 DE-EMPHASIS SAMPLING RATE SELECTION 44.1 kHz (default) 48 kHz 32 kHz Reserved The DMF[1:0] bits select the sampling frequency used for the digital de-emphasis function when it is enabled. The de-emphasis curves are shown in the Typical Characteristics section of this data sheet. The preceding table shows the available sampling frequencies. 8.6.2.10 DMC: Digital De-Emphasis All-Channel Function Control Default value: 0 DMC 0 1 DIGITAL DE-EMPHASIS ALL-CHANNEL FUNCTION CONTROL De-emphasis disabled for all channels (default) De-emphasis enabled for all channels The DMC bit is used to enable or disable the de-emphasis function for all channels. REGISTER 11 B15 0 B14 B13 B12 B11 B10 B9 B8 IDX6 IDX5 IDX4 IDX3 IDX2 IDX1 IDX0 B7 REV8 B6 REV7 B5 REV6 B4 REV5 B3 REV4 B2 REV3 B1 REV2 B0 REV1 8.6.2.11 REV[8:1]: Output Phase Select per Channel Where x = 1 – 8, corresponding to the DAC output VOUTx. Default value: 1 REVx 0 1 OUTPUT PHASE SELECT PER CHANNEL Normal output Inverted output (default) The REVx bit allows the user to select the phase of the analog output signal per channel when DREV = 1 is set on Register 10. REGISTER 12 B15 0 B14 IDX6 B13 IDX5 B12 IDX4 B11 IDX3 B10 IDX2 B9 IDX1 B8 IDX0 B7 OVER B6 RSV B5 RSV B4 RSV B3 B2 B1 B0 FLT4 FLT3 FLT2 FLT1 8.6.2.12 OVER: Oversampling Rate Control Default value: 0 OVER 0 1 30 512 fS, 768 fS, 1152 fS ×64 oversampling, narrow mode (default) ×128 oversampling, wide mode Submit Documentation Feedback 256 fS, 384 fS 128 fS, 192 fS ×32 oversampling, narrow ×16 oversampling, narrow mode (default) mode (default) ×64 oversampling, wide mode ×32 oversampling, wide mode Copyright © 2008–2015, Texas Instruments Incorporated Product Folder Links: PCM1681 PCM1681-Q1 PCM1681, PCM1681-Q1 www.ti.com SLES211C – FEBRUARY 2008 – REVISED JULY 2015 8.6.2.13 FLTx: Digital Filter Roll-Off Control per DATA Group Where x = 1 – 4, corresponding to the DATAx. Default value: 1 FLTx 0 1 DIGITAL FILTER ROLL-OFF CONTROL PER DATA GROUP Sharp roll-off Slow roll-off (default) The FLTx bit allows the user to select the digital filter roll-off characteristic per 2 channels when FLT = 1 is set, so that it is best suited to the application. Two filter roll-off sections are available: sharp or slow. The filter responses for these selections are shown in the Typical Characteristics section. REGISTER 13 B15 B14 B13 B12 B11 B10 B9 0 IDX IDX IDX IDX IDX IDX 6 5 4 3 2 1 B8 IDX 0 B7 DAMS B6 B5 AZRO1 AZRO0 B4 RSV B3 RSV B2 RSV B1 RSV B0 RSV 8.6.2.14 DAMS: Digital Attenuation Mode Select Default value: 0 DAMS 0 1 DIGITAL ATTENUATION MODE SELECT Fine step, 0.5 dB/step for 0 to –63 dB range (default) Wide range, 1 dB/step for 0 to –100 dB range The DAMS bit is used to select the digital attenuation mode. 8.6.2.15 AZRO[1:0]: Zero-Flag Channel-Combination Select Default value: 00b AZRO[1:0] 00 01 10 11 Combination Combination Combination Combination ZERO-FLAG CHANNEL-COMBINATION SELECT A (ZR1: DATA1 L-ch, ZR2: DATA1 R-ch) (default) B (ZR1: DATA1–DATA4, ZR2: DATA1–DATA4) C (ZR1: DATA4, ZR2: DATA1–DATA3) D (ZR1: DATA1, ZR2: DATA2–DATA4) The AZRO[1:0] bits are used to select the zero-flag channel combinations for ZR1 and ZR2. REGISTER 14 B15 B14 B13 B12 B11 B10 B9 0 IDX IDX IDX IDX IDX IDX 6 5 4 3 2 1 B8 B7 B6 B5 B4 B3 B2 B1 B0 IDX ZERO8 ZERO7 ZERO6 ZERO5 ZERO4 ZERO3 ZERO2 ZERO1 0 8.6.2.16 ZERO[8:1]: Zero-Detect Status (Read-Only, I2C Interface Only) Default value: N/A The ZERO[8:1] bits show the status of zero detect for each channel. The status is set to 1 by detecting a zero state without regard to the ZREV bit setting. Copyright © 2008–2015, Texas Instruments Incorporated Product Folder Links: PCM1681 PCM1681-Q1 Submit Documentation Feedback 31 PCM1681, PCM1681-Q1 SLES211C – FEBRUARY 2008 – REVISED JULY 2015 www.ti.com 9 Application and Implementation NOTE Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality. 9.1 Application Information 9.1.1 D/A Output Filter Circuits ΔΣ DACs use noise shaping techniques to improve in-band signal-to-noise ratio (SNR) performance at the expense of generating increased out-of-band noise above the Nyquist frequency, or fS/2. The out-of-band noise must be low-pass filtered in order to provide optimal converter performance. This is accomplished by a combination of on-chip and external low-pass filtering. Figure 26 and Figure 33 show the recommended external low-pass active filter circuits for dual- and singlesupply applications. These circuits are second-order Butterworth filters using a multiple-feedback (MFB) circuit arrangement, which reduces sensitivity to passive component variations over frequency and temperature. For more information regarding MFB active filter design, see Dynamic Performance Testing of Digital Audio D/A Converters (SBAA055). Because the overall system performance is defined by the quality of the D/A converters and their associated analog output circuitry, high-quality audio operational amplifiers are recommended for the active filters. Texas Instruments’ OPA2353 and OPA2134 dual operational amplifiers are shown in Figure 26 and Figure 33, and are recommended for use with the PCM1681 and PCM1681-Q1. R2 R1 + R3 VIN C3 10 mF AV = - C1 C2 2 3 – OPA2134 + 1 R4 VOUT 47 W R2 R1 Example: R1: 5.1 kW R2: 8.2 kW R3: 560 W C1: 470 pF C2: 4700 pF AV: −1.61 fc: 57 kHz Figure 33. Dual-Supply Filter Circuit 9.2 Typical Application A basic connection diagram is shown in Figure 34, with the necessary power supply bypassing and decoupling components. Texas Instruments’ PLL170x is used to generate the system clock input at SCK, as well as generating the clock for the audio signal processor. The use of series resistors (22 Ω to 100 Ω) is recommended for SCK, LRCK, BCK, DATA1, DATA2, DATA3, and DATA4. The series resistor combines with the stray PCB capacitance and device input capacitance to form a low-pass filter that removes high-frequency noise from the digital signal, thus reducing high-frequency emission. 32 Submit Documentation Feedback Copyright © 2008–2015, Texas Instruments Incorporated Product Folder Links: PCM1681 PCM1681-Q1 PCM1681, PCM1681-Q1 www.ti.com SLES211C – FEBRUARY 2008 – REVISED JULY 2015 Typical Application (continued) 1 ZR1/ZR1/FMT0 2 MS/ADR/FMT1 VOUT1 27 3 MC/SCL/DEMP VOUT2 26 4 MD/SDA/MUTE VCOM 25 5 SCK AGND2 24 mC or mP R1 PLL170x 6 7 R3 8 R2 Audio DSP or Decoder R5 R6 R7 Termination 3.3 V Digital 5 V Analog C9 9 VCC2 DATA1 VOUT3 BCK LRCK VOUT4 VOUT5 VDD + C1 + C2 + C12 L R 23 22 21 20 10 DGND VOUT6 19 11 DATA2 AGND1 18 12 DATA3 VCC1 17 13 DATA4 VOUT7 16 14 MSEL VOUT8 15 C13 + 28 C11 R4 27-MHz Master Clock ZR2 + C3 + C4 + C5 + C6 Output Low-Pass Filter LF RF LS RS CTR SUB C10 + C7 + C8 PCM1681 PCM1681-Q1 C14 + 0V C1-C8: 4.7-mF to 10-mF Electrolytic Typical C9-C11: 1-mF Ceramic Typical C12: 2.2-mF to 10-mF Electrolytic Typical C13, C14: 10-mF Electrolytic Typical R1-R7: 22 W to 100 W Typical The termination for mode/configuration control: Either one of the following circuits has to be applied according to necessary mode/configuration. Resistor value has to be 220 kW ±5% tolerant. 3.3 V 3.3 V 14 14 (2) (1) 14 14 0V 0V (3) (4) Figure 34. Basic Connection Diagram 9.2.1 Design Requirements • Control: Hardware, I2C, or SPI • Audio Input: PCM Serial data, TDM, or DSP • Audio Output: 3.75-Vpp analog audio • Master Clock: PLL170X IC Copyright © 2008–2015, Texas Instruments Incorporated Product Folder Links: PCM1681 PCM1681-Q1 Submit Documentation Feedback 33 PCM1681, PCM1681-Q1 SLES211C – FEBRUARY 2008 – REVISED JULY 2015 www.ti.com Typical Application (continued) 9.2.2 Detailed Design Procedure 9.2.2.1 Hardware Control Method There are 3 ways to control the PCM1681, hardware control, SPI, or I2C. Hardware control will provide a limited access to control features available in the PCM1681 but can be implemented with pull up and pull downs, or with GPIO of a microcontroller. Control via SPI or I2C will provide access to all control registers and features but will require a digital device that can implement SPI or I2C. 9.2.2.2 Audio Input For audio input there are 3 options, PCM serial data, TDM, or DSP. All three will support the same quality of audio data, but having these 3 options to match the audio sources available outputs allows for greater flexibility. This selection is made by configuring the MSEL pin which is detailed in Table 7 and shown in Figure 34. 9.2.2.3 Audio Output The output of the PCM1681 will produce a 3.75-Vpp signal at full scale into a 5-kΩ load, that should be filtered before being sent to an amplifier. 9.2.2.4 Master Clock The master clock can come from wither a dedicated IC such as the PLL170X series, a crystal or the audio source IC. What is important is that the audio source and the PCM1681 are driven from the same source so that the audio clocks will be synchronous. 9.2.3 Application Curve 0 Amplitude – dB −20 −40 −60 −80 −100 −120 0 1 2 Frequency [× fS] 3 4 G001 Figure 35. Frequency Response (Sharp Roll-off) 10 Power Supply Recommendations The PCM1681 and PCM1681-Q1 require 5 V for the analog supply and 3.3 V for the digital supply. The 5-V supply is used to power the DAC analog and output filter circuitry, and the 3.3 V supply is used to power the digital filter and serial interface circuitry. For best performance, a 5-V supply and a 3.3-V supply with linear regulators are recommended. Five capacitors are required for supply bypassing, as shown in Figure 34. These capacitors should be located as close as possible to the PCM1681 and PCM1681-Q1 package. The 10-μF capacitor should be tantalum or aluminum electrolytic, while the three 1-μF capacitors are ceramic. 34 Submit Documentation Feedback Copyright © 2008–2015, Texas Instruments Incorporated Product Folder Links: PCM1681 PCM1681-Q1 PCM1681, PCM1681-Q1 www.ti.com SLES211C – FEBRUARY 2008 – REVISED JULY 2015 11 Layout 11.1 Layout Guidelines A typical printed circuit board (PCB) floor plan for the PCM1681 and PCM1681-Q1 is shown in Figure 36. A ground plane is recommended, with the analog and digital sections being isolated from one another using a split or cut in the circuit board. The PCM1681 and PCM1681-Q1 should be oriented with the digital I/O pins facing the ground plane split/cut to allow for short, direct connections to the digital audio interface and control signals originating from the digital section of the board. Separate power supplies are recommended for the digital and analog sections of the board. This prevents the switching noise present on the digital supply from contaminating the analog power supply and degrading the dynamic performance of the PCM1681 and PCM1681-Q1. The PowerPAD can be left open without being soldered to the ground plane of the PCB for the PCM1681. However, it must be soldered to the ground plane which has low thermal resistance for the PCM1681-Q1. 11.2 Layout Example Analog Power Digital Power +3.3VD AGND DGND +5VA +VS ±VS VDD VCC Digital Logic and Audio Processor DGND PCM1681 PCM1681-Q1 Output Circuits Digital Ground AGND Digital Section Analog Section Analog Ground Return Path for 3.3 VD and Digital Signals Figure 36. Recommended PCB Layout Copyright © 2008–2015, Texas Instruments Incorporated Product Folder Links: PCM1681 PCM1681-Q1 Submit Documentation Feedback 35 PCM1681, PCM1681-Q1 SLES211C – FEBRUARY 2008 – REVISED JULY 2015 www.ti.com 12 Device and Documentation Support 12.1 Device Support 12.1.1 Third-Party Products Disclaimer TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE. 12.2 Documentation Support 12.2.1 Related Documentation For related documentation see the following: Dynamic Performance Testing of Digital Audio D/A Converters (SBAA055) 12.3 Related Links The table below lists quick access links. Categories include technical documents, support and community resources, tools and software, and quick access to sample or buy. Table 12. Related Links PARTS PRODUCT FOLDER SAMPLE & BUY TECHNICAL DOCUMENTS TOOLS & SOFTWARE SUPPORT & COMMUNITY PCM1681 Click here Click here Click here Click here Click here PCM1681-Q1 Click here Click here Click here Click here Click here 12.4 Trademarks PowerPAD is a trademark of Texas Instruments. System Two, Audio Precision are trademarks of Audio Precision, Inc. SPI is a trademark of Motorola. I2C, I2S are trademarks of NXP Semiconductors. All other trademarks are the property of their respective owners. 12.5 Electrostatic Discharge Caution These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. 12.6 Glossary SLYZ022 — TI Glossary. This glossary lists and explains terms, acronyms, and definitions. 13 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. 36 Submit Documentation Feedback Copyright © 2008–2015, Texas Instruments Incorporated Product Folder Links: PCM1681 PCM1681-Q1 PACKAGE OPTION ADDENDUM www.ti.com 14-Oct-2022 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) Samples (4/5) (6) PCM1681PWP ACTIVE HTSSOP PWP 28 50 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 85 PCM1681 Samples PCM1681PWPR ACTIVE HTSSOP PWP 28 2000 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 85 PCM1681 Samples PCM1681TPWPQ1 ACTIVE HTSSOP PWP 28 50 RoHS & Green NIPDAU Level-4-260C-72 HR -40 to 105 PCM1681TQ1 Samples PCM1681TPWPRQ1 ACTIVE HTSSOP PWP 28 2000 RoHS & Green NIPDAU Level-4-260C-72 HR -40 to 105 PCM1681TQ1 Samples (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of