49%
FPO
®
PCM1710U
Stereo Audio
DIGITAL-TO-ANALOG CONVERTER
FEATURES
DESCRIPTION
● COMPLETE STEREO DAC:
8X Oversampling Digital Filter
Multi-Level Delta-Sigma DAC
Analog Low Pass Filter
Output Amplifier
● HIGH PERFORMANCE:
–92dB THD+N
98dB Dynamic Range
110dB SNR
The PCM1710 is a complete stereo audio digital-toanalog converter, including digital interpolation filter,
delta-sigma DAC, and analog voltage output. PCM1710
can accept either 16-bit normal or 20-Bit normal input
data (MSB first, right justified), or 16-bit IIS data
(32-bits per word, continuous clock).
The digital filter performs an 8X interpolation function, as well as special functions such as soft mute,
digital attenuation, de-emphasis and double-speed
dubbing. Performance of the digital feature is excellent, featuring –62dB stop band attenuation and
±0.008dB ripple in the pass band.
●
●
●
●
ACCEPTS 16 OR 20 BITS INPUT DATA
SYSTEM CLOCK: 256fs or 384fs
SINGLE +5V POWER SUPPLY
ON-CHIP DIGITAL FILTER:
Soft Mute and Attenuator
Digital De-emphasis
Double-Speed Dubbing Mode
● SMALL 28-PIN SOIC PACKAGE
Digital In
Input Interface
and
Attentuator
Oversampling
Digital Filter
PCM1710 is suitable for a wide variety of consumer
applications where good performance is required.
Its low cost, small size and single +5V power supply
make it ideal for automotive CD players, bookshelf
CD players, BS tuners, keyboards, MPEG audio,
MIDI applications, set-top boxes, CD-ROM drives,
CD-Interactive and CD-Karaoke systems.
4th-Order
Multi-Level
Delta
Sigma
Lch OUT
DAC
Low-Pass
Filter
Output
Op Amp
Rch OUT
Mode Control
System Clock
International Airport Industrial Park • Mailing Address: PO Box 11400
Tel: (520) 746-1111 • Twx: 910-952-1111 • Cable: BBRCORP •
© 1994 Burr-Brown Corporation
SBAS030
• Tucson, AZ 85734 • Street Address: 6730 S. Tucson Blvd. • Tucson, AZ 85706
Telex: 066-6491 • FAX: (520) 889-1510 • Immediate Product Info: (800) 548-6132
PDS-1217B
Printed in U.S.A. June, 1995
SPECIFICATIONS
All specifications at +25°C, +VCC = +VDD = +5V, fS = 44.1kHz, fSYS = 384/256fs, and 16-bit data, unless otherwise noted.
PCM1710U
PARAMETER
CONDITIONS
RESOLUTION
MIN
TYP
16
DIGITAL INPUT
Logic Family
Input Logic Level (except XTI)
VIH
VIL
Input Logic Current (except XTI)
Input Logic Level (XTI)
VIH
VIL
Input Logic Current (XTI)
Output Logic Level (CLKO):
VOH
VOL
Output Logic Current (CLKO)
Data Format
Sampling Frequency
System Clock Frequency
System Clock Frequency
DC ACCURACY
Gain Error
Gain Mis-Match Channel-To-Channel
Bipolar Zero Error
Gain Drift
Bipolar Gain Drift
DYNAMIC PERFORMANCE(1)
THD+N at F/S (0dB)(2)
THD+N at –60fdB(2)
Dynamic Range
S/N Ratio
Channel Separation
DIGITAL FILTER PERFORMANCE
Pass Band Ripple
Pass Band Ripple
Stop Band Attenuation
Stop Band Attenuation
Pass Band
Pass Band
Stop Band
Stop Band
De-emphasis Error
MAX
UNITS
20
Bits
0.8
–200
VDC
VDC
µA
1.4
±50
VDC
VDC
µA
2.0
3.2
4.5
0.5
VDC
VDC
mA
44.1
16.934
11.2894
48
18.432
12.288
kHz
MHz
MHz
±1.0
±1.0
±20.0
±50
±20
±5.0
±5.0
% of FSR
% of FSR
mV
ppm of FSR/°C
ppm of FSR/°C
–92
–36
98
110
94
–88
–32
dB
dB
dB
dB
dB
±0.008
±0.018
dB
dB
dB
dB
fs
fs
fs
fs
dB
±10
Normal (16/20-bit)/IIS (16-bit) selectable
32
12.288
8.192
384fS
256fS
VO = 1/2VCC at Bipolar Zero
fIN = 991kHz
fIN = 991kHz
EIAJ A-weighted
EIAJ A-weighted
Normal Mode
Double Speed Mode
Normal Mode
Double Speed Mode
Normal Mode
Double Speed Mode
Normal Mode
Double Speed Mode
(fS 32kHz ~ 48kHz)
ANALOG OUTPUT
Voltage Range
Load Impedance
Center Voltage
104
90
–62
–58
0.4535
0.4535
0.5465
0.5465
+0.03
–0.05
3.2
Vp-p
kΩ
V
5
+1/2VCC
POWER SUPPLY REQUIREMENTS
Voltage Range: +VCC
+VDD
Supply Current (+ICC) + (+IDD)
+4.5
+4.5
TEMPERATURE RANGE
Operation
Storage
–25
–55
+5.0
+5.0
45
+5.5
+5.5
70
VDC
VDC
mA
+85
+100
°C
°C
NOTE: (1) Dynamic performance specs are tested with external 20kHz low pass filter. (2) 30kHz LPF, 400Hz HPF, Average Mode. Shibusoku #725 THD Meter.
The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes
no responsibility for the use of this information, and all use of such information shall be entirely at the user’s own risk. Prices and specifications are subject to change
without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant
any BURR-BROWN product for use in life support devices and/or systems.
®
PCM1710U
2
PIN ASSIGNMENTS
PIN NAME
NUMBER
FUNCTION
Input Interface Pins
LRCIN
1
DIN
2
Sample Rate Clock Input. Controls the update rate (fs).
Serial Data Input. MSB first, right justified format contains a frame of 16-bit or 20-bit data.
BCKIN
3
Bit Clock Input. Clocks in the data present on DIN input.
Mode Controls and Clock Signals
CLKO
4
Buffered Output of Oscillator. Equivalent to fs.
XTI
5
Oscillator Input (External Clock Input). For an internal clock, tie XTI to one side of the crystal oscillator. For an external clock,
tie XTI to the output of the chosen external clock.
XTO
6
Oscillator Output. When using the internal clock, tie to the opposite side (from pin 5) of the crystal oscillator. When using an
external clock, leave XTO open.
CKSL
23
System Clock Select. For 384fs, tie CKSL “High”. For 256fs, tie CKSL “Low”.
MODE
24
Operation Mode Select. For serial mode, tie MODE “High”. For parallel mode, tie MODE “Low”.
MUTE
25
Mute Control. To disable soft mute, tie MUTE “High”. To enable soft mute, tie MUTE “Low”.
MD/DM1
26
Mode Control for Data/De-emphasis. See “Mode Control Functions” on page 11.
MC/DM2
27
Mode Control for BCKIN/De-emphasis. See “Mode Control Functions” on page 11.
ML/DSD
28
Mode Control for WDCK/Double speed dubbing. See “Mode Control Functions” on page 11.
Analog Functions
VOUTR
13
Right Channel Analog Output.
VOUTL
16
Left Channel Analog Output.
Power Supply Connections
DGND
7, 22
Digital Ground.
VDD
8, 21
Digital Power Supply (+5V).
VCC2R
9
Analog Power Supply (+5V), Right Channel DAC.
AGND2R
10
Analog Ground (DAC), Right Channel.
EXT1R
11
Output Amplifier Common, Right Channel. Bypass to ground with a 10µF capacitor.
EXT2R
12
Output Amplifier Bias, Right Channel. Connect to EXT1R.
AGND
14
Analog Ground.
VCC
15
Analog Power Supply (+5V).
EXT2L
17
Output Amplifier Bias, Left Channel. Connect to EXT1L.
EXT1L
18
Output Amplifier Common, Left Channel. Bypass to ground with a 10µF capacitor.
AGND2L
19
Analog Ground (DAC), Left Channel.
VCC2L
20
Analog Power Supply (+5V), Left Channel DAC.
ABSOLUTE MAXIMUM RATINGS
PACKAGE INFORMATION
Power Supply Voltages ................................................................ ±6.5VDC
+VCC to VDD Voltage .......................................................................... ±0.1V
Input Logic Voltage ..................................................... –0.3V to VDD +0.3V
Power Dissipation .......................................................................... 400mW
Operating Temperature Range ......................................... –25°C to +85°C
Storage Temperature Range .......................................... –55°C to +125°C
Lead Temperature (soldering, 5s) ................................................. +260°C
MODEL
PCM1710U
PACKAGE
PACKAGE DRAWING
NUMBER(1)
28-Pin SOIC
217
NOTE: (1) For detailed drawing and dimension table, please see end of data
sheet, or Appendix D of Burr-Brown IC Data Book.
®
3
PCM1710U
PIN CONFIGURATION
LRCIN
1
DIN
2
BCKIN
Input
Interface
Digital
Filter
3
CLKO
4
XTI
5
XTO
6
DGND
7
VDD
8
VCC2R
9
AGND2R
10
EXT1R
11
EXT2R
12
VOUTR
13
AGND1
14
Mode
Control
Timing
Control
Noise
Shaper
5-Level ∆Σ DAC
Right
5-Level ∆Σ DAC
Left
Low-Pass
Filter-Left
Output
Amplifier
Left
28
ML/DSD
27
MC/DM2
26
MD/DM1
25
MUTE
24
MODE
23
CKSL
22
DGND
21
VDD
20
VCC2L
19
AGND2L
18
EXT1L
17
EXT2L
16
VOUTL
15
VCC1
CONNECTION DIAGRAM
1
Serial
Data Input(2)
2
Digital
Filter
3
4
10pF ~ 22pF x 2
28
Input
Interface
Mode
Control
25
24
Noise
Shaper
6
10
10µF
+
5-Level ∆Σ DAC
Left
Low-Pass
Filter Right
Low-Pass
Filter Left
13
Output
Amplifier
Left
14
(1)
19
10µF
18
Output
Amplifier
Right
(1)
21
20
11
12
Post
Low Pass
Filter
22
5-Level ∆Σ DAC
Right
9
(1)
Rch OUT
23
7
8
26
Mode Control(3)
Timing
Control
5
(1)
27
+
17
Post
Low Pass
Filter
16
15
(1)
+
–
Lch OUT
100µF
+5V
Power Supply
NOTES: (1) Bypass Capacitor :1µF ~ 10µF.
(2) Input pins require pull-up resistors. (3) Mode
control pins require pull-up resistors.
®
PCM1710U
4
DATA INPUT TIMING
1 f/s
Left-channel Data
Right-channel Data
MSB
DIN
1
2
14
15
LSB
MSB
16
1
LSB
2
14
15
16
BCKIN
LRCIN
FIGURE 1. Normal Format, 16-Bit (LRCIN H: Lch).
1 f/s
Left-channel Data
Right-channel Data
MSB
DIN
1
2
18
19
LSB
MSB
20
1
LSB
2
18
19
20
BCKIN
LRCIN
FIGURE 2. Normal Format, 20-Bit (LRCIN H: Lch).
1 f/s
Left-channel Data
Right-channel Data
MSB
DIN
16
1
LSB MSB
2
3
13
14
15 16
1
LSB
2
13
14
15 16
BCKIN
LRCIN
FIGURE 3. IIS Format, (16-Bit, 32 BCKIN Clock Cycles Per fs Interval).
®
5
PCM1710U
BCKIN
tBCWH
tBCWL
tBCY
DIN
tDH
tDS
tBL
tLB
LRCIN
FIGURE 4. Data Input Timing.
MC
tMCWH
tMCWL
tMCY
MD
tMH
tMS
tMCS
tMCH
ML
tMLY
tF
tR
2.0V
MC, MD, ML
0.8V
FIGURE 5. Serial Mode Control Timing.
BCK Pulsewidth (H Level)
BCK Pulsewidth (L Level)
BCK Pulse Cycle Time
DIN Setup Time
DIN Hold Time
BCK Rising Edge ➝ LRCI Edge
LRC I Edge ➝ BCK Rising Edge
tBCWH
tBCWL
tBCY
tDS
tDH
tBL
tLB
MC Pulsewidth (H Level)
MC Pulsewidth (L Level)
MC Pulse Cycle Time
MD Setup Time
MD Hold Time
ML Setup Time
ML Hold Time
ML Low-Level Time
MC, MD, ML Rise Time
MC, MD, ML Fall Time
70ns (min)
70ns (min)
140ns (min)
30ns (min)
30ns (min)
30ns (min)
30ns (min)
TABLE I. Data Input Timing Specifications (Refer to
Figure 4).
tMCWH
tMCWL
tMCY
tMS
tMH
tMCS
tMCH
tMLY
tR
tF
50ns (min)
50ns (min)
100ns (min)
30ns (min)
30ns (min)
30ns (min)
30ns (min)
1/sysclk + 20ns (min)
15ns (max)
15ns (max)
TABLE II. Serial Mode Control Timing Specifications
(Refer to Figure 5).
®
PCM1710U
6
TYPICAL PERFORMANCE CURVES
All specifications at +25°C, +VCC = + VDD + 5V, fS = 44.1kHz, fSYS = 384/256fs, and 16-bit data, unless otherwise noted.
DIGITAL FILTER
PASSBAND RIPPLE CHARACTERISTIC
NORMAL MODE (De-emphasis: OFF)
OVERALL FREQUENCY CHARACTERISTIC
NORMAL MODE (De-emphasis: OFF)
0
–0.03
–20
–0.035
–40
dB
dB
–60
–0.04
–80
–100
–0.045
–120
–140
–0.05
0
20k
40k
60k
80k
100k 120k 140k 160k 180k
0
5k
10k
15k
20k
Frequency (Hz)
Frequency (Hz)
OVERALL FREQUENCY CHARACTERISTIC
DOUBLE-SPEED MODE (De-emphasis: OFF)
PASSBAND RIPPLE FREQUENCY CHARACTERISTIC
DOUBLE-SPEED MODE (De-emphasis: OFF)
0
–0.02
–20
–0.03
–40
dB
dB
–60
–0.04
–80
–100
–0.05
–120
–0.06
–140
0
20k
40k
60k
80k
100k 120k 140k 160k 180k
0
5k
10k
Frequency (Hz)
20k
25k
30k
35k
40k
Frequency (Hz)
DE-EMPHASIS CHARACTERISTIC
DOUBLE-SPEED MODE
DE-EMPHASIS CHARACTERISTIC, NORMAL MODE
0
0
–2
–2
–4
–4
dB
dB
15k
–6
–6
–8
–8
–10
–10
–12
–12
0
10k
20k
30k
40k
50k
0
Frequency (Hz)
5k
10k
15k
20k
25k
Frequency (Hz)
®
7
PCM1710U
TYPICAL PERFORMANCE CURVES (CONT)
At TA = +25°C, VS = ±5V, RL = 100Ω, CL = 2pF, and RFB = 402Ω, unless otherwise noted. Based on 200 piece sample from 3 diffusion runs.
DYNAMIC PERFORMANCE
256fs
THD+N vs VCC, VDD
FULL-SCALE INPUT
384fs
THD+N vs VCC, VDD
FULL SCALE INPUT
–88
–89
–89
–90
Maximum
–91
Maximum
THD+N (dB)
THD+N (dB)
–90
–91
–92
Average
–93
–92
–93
Average
–94
Minimum
Minimum
–94
–95
–95
–96
5.0
5.5
4.5
VCC, VDD (V)
256fs
DYNAMIC RANGE vs VCC, VDD
384fs
DYNAMIC RANGE vs VCC, VDD
91
92
92
93
93
Minimum
94
Average
95
Maximum
96
97
94
5.5
Minimum
95
96
Average
97
Maximum
98
98
99
4.5
5.0
5.5
4.5
5.0
VCC, VDD (V)
VCC, VDD (V)
384fs
GAIN ERROR vs VCC, VDD
384fs
BPZ ERROR vs VCC, VDD
2.0
1.8
1.6
Maximum
1.4
1.2
Average
1
Minimum
BPZ Error (mV)
Gain Error (%)
5.0
VCC, VDD (V)
Dynamic Range (dB)
Dynamic Range (dB)
4.5
0.8
0.6
0.4
0.2
0
4.5
5
5.5
Maximum
Average
Minimum
4.5
VCC, VDD (V)
5
VCC, VDD (V)
®
PCM1710U
15
13
11
9
7
5
3
1
–1
–3
–5
–7
–9
–11
–13
–15
8
5.5
5.5
TYPICAL PERFORMANCE CURVES (CONT)
At TA = +25°C, VS = ±5V, RL = 100Ω, CL = 2pF, and RFB = 402Ω, unless otherwise noted. Based on 200 piece sample from 3 diffusion runs.
DYNAMIC PERFORMANCE
INTERMODULATION DISTORTION
vs FREQUENCY (f1 = 11kHz, f2 = 12kHz)
384fs
SNR vs TEMPERATURE and POWER SUPPLY
111
0
110
–20
VCC, VDD = 4.5V
–40
VCC, VDD = 5.5V
IMD (dB)
SNR (dB)
109
108
107
–60
–80
VCC, VDD = 5.0V
106
–100
105
–120
104
–140
–25
0
25
50
20
75
Temperature (°C)
100
1k
Frequency (Hz)
10k
20k
INTERMODULATION DISTORTION
vs FREQUENCY (f1 = 60Hz, f2 = 7kHz)
0
–20
IMD (dB)
–40
–60
–80
–100
–120
–140
20
100
1k
Frequency (Hz)
10k
20k
CAUTION: Minimum and maximum values on typical performance curves are not meant to imply a guarantee. Curves should
be used for reference only. Refer to specification for guaranteed performances.
®
9
PCM1710U
FUNCTIONAL DESCRIPTION
PARALLEL-MODE: DE-EMPHASIS CONTROL
(PIN 24 [MODE] = L)
PCM1710 has several built-in functions including digital
attenuation, digital de-emphasis and soft mute. These functions are software controlled. PCM1710 can be operated in
two different modes, Serial or Parallel. Serial Mode is a
three-wire interface using pin 26 (MD), pin 27 (MC), and pin
28 (ML). Data on these pins are used to control de-emphasis
mode, mute, double-speed dubbing, input resolution and
input format. PCM1710 can also be operated in parallel
mode, where static control signals are used on pin 26 (DM1),
pin 27 (DM2), and pin 28 (DSD). Operation of both of these
modes are covered in detail in the next sections.
DM1 (Pin 26)
DM2 (Pin 27)
De-emphasis
L
H
L
H
L
L
H
H
OFF
32kHz
48kHz
44.1kHz
TABLE V. De-emphasis (Pins 26 and 27).
In the parallel mode, de-emphasis conditions are controlled
by the logic levels on pin 26 (DM1) and pin 27 (DM2). For
PCM1710, de-emphasis can operate at 32kHz, 44.1kHz,
48kHz, or disabled.
CAUTION: Mode control signals operate on level triggered
logic. The minimum timing conditions detailed in Figures 5
and 6 MUST be observed.
PARALLEL-MODE: DOUBLE-SPEED DUBBING
CONTROL (PIN 24 [MODE] = L)
MODE CONTROL: SERIAL/PARALLEL SELECTION
MODE = H
Serial Mode
MODE = L
Parallel Mode
PARALLEL MODE
(MODE = L)
0
0
0
0
0
0
0
X(Normal Mode Fixed)
X(16-bit Fixed)
X
0
0
X
0
Input Data Format Selection
Input Data Bit Selection
Input LRCI Polarity Selection
De-emphasis Control
Mute
Attenuation
Double Speed Dubbing
In the parallel mode, double-speed dubbing can be enabled
by holding pin 28 (DSD) at a logic “low”.
CAUTION: Double-speed dubbing cannot operate if the
system clock is set at 256fs.
SERIAL MODE CONTROL
In order to use all of PCM1710’s functionality, the serial
mode control should be used. PCM1710 must be addressed
three separate times to set all of the various registers and
flags that control these functions.
Table VII together with Figure 6 details the control of the
PCM1710 in the serial mode. Internal latches are used to
hold this serial data until the PCM1710 is enabled to use the
data. The serial mode is used by applying clocked data to the
following pins:
NOTE: 0: Selectable, X: Not Selectable.
TABLE IV. Selectable Functions in Serial Mode and
Parallel Mode.
Table IV indicates which functions are selectable within the
user’s chosen mode. All of the functions shown are selectable within the serial mode, but only de-emphasis control,
mute and double-speed dubbing may be selected when using
PCM1710 in the parallel mode.
®
PCM1710U
Double-Speed Dubbing Mode
TABLE VI. DSD (Pin 28).
MODE CONTROL: SELECTABLE FUNCTIONS
SERIAL MODE
(MODE = H)
Normal Mode
DSD = L
NOTE: When the Double-Speed Dubbing Mode is selected, the System
Clock must be 384fs (CKSL: Pin 23 = H).
TABLE III. Serial and Parallel Mode are Selectable by
MODE Pin (Pin 24).
FUNCTION
DSD = H
10
NAME
PIN
FUNCTION
MC
27
Clock for Strobing in Data
ML
28
Latches Data into the Registers
MD
26
8-bit Data Word Defining Operation
B0
B1
B2
FUNCTION MODE SELECTION
BIT NO.
MODE
FLAG
MODE
B3
B4
DEEM2
DEEM1
Sampling Frequency
BIT VALUE
H
L
L
DEEM1
De-emphasis
0
De-emphasis OFF
1
De-emphasis ON
B6
MUTE
Mute
0
Mute OFF
1
Mute ON
0
Double-speed OFF
1
Double-speed ON
0
Infinite Zero Detection OFF
1
Infinite Zero Detection ON
DSD
Double-Speed
B3
L
H
OFF
OFF
OFF
Not Assigned
B4
H
32kHz
1
48kHz
44.1kHz
IIR
1
Mode
0
1
B5
B7
MODE BY
DEFAULT
DEEM2
0
for De-emphasis
Mode
SELECTED FUNCTION
TST
B5
Test Mode
IW
Input Resolution
2
B6
LRPL
B7
Polarity for LRCI
IIS
Input Format
0
16-Bit
1
20-Bit
ON
16-Bit
0
Lch:high/Rch:low
Lch:high
1
Lch:low/Rch:high
Rch:low
0
Normal
1
IIS
Normal
TABLE VII. Serial-Mode Control Input Format (Pin 24 [MODE] = H)—Refer to Figure 6 for Timing Diagram.
MC
ML
ATT_DATA
MD
Attenuation
Mode
L
D6
D5
D4
D3
D2
D1
D0
Mode 1
H
L
L
DEEM2
DEEM1
IIR
MUTE
DSD
Mode 2
H
L
H
TST
IW
LRPL
IIS
Bit#
B0
B1
B2
B4
B5
B6
B7
B3
NOTE: Cycle Time for Model Control—Cycle time for mode control must be set over 128 times of minimum system clock.
FIGURE 6. Mode Control Input Format, Serial Mode.
MODE 1 CONTROLS
DIGITAL ATTENUATION
One of the functions which can be implemented through use
of the serial mode control is attenuation. This function
allows the user to control the level of the output, independent of the of the input level set by the actual input data
supplied to the DAC.
Referring to Figure 6, when the first data bit (B0) on MD
(pin 26) is low, the attenuation function is enabled. The next
seven bits (B1 - B6) define a binary value, ATT_DATA, that
indicates the desired level of attenuation. The attenuation
level is given by:
This mode can be enabled with the sequence of 1, 0, 0 as the
first three bits on MD (pin 26). This mode allows for the
following functions:
De-emphasis
De-emphasis Frequency
Soft Mute
Double-Speed Dubbing
On/Off
32kHz, 44.1kHz, 48kHz
On/Off
On/Off
DIGITAL DE-EMPHASIS
PCM1710 allows three different sampling rates for digital
de-emphasis. B3 and B4 are used for binary control of the
de-emphasis frequency:
Level = 20log10 (1 - ATT_DATA/127) dB
When all 7 bits of the ATT_DATA word are high
(ATT_DATA = 127), attenuation is infinite and the output
of PCM1710 will be zero.
B3
B4
Frequency
0
0
1
1
0
1
0
1
OFF
48kHz
32kHz
44.1kHz
®
11
PCM1710U
SAMPLE RATE CLOCK POLARITY
B6 controls the polarity of the sample rate clock (LRCIN)
polarity. When B6 is low, data will be accepted on the left
channel when LRCIN is high, and on the right channel when
LRCIN is low. When B6 is high, data will be accepted on the
right channel when LRCIN is high, and on the left channel
when LRCIN is low.
Once the reset has been established on pin 27 (MC), the deemphasis frequency defaults to 44.1kHz. B5 is a master
control for de-emphasis. A high level on B5 enables deemphasis (frequency controlled by B3 and B4), and a low
level on B5 disables de-emphasis.
SOFT MUTE
Soft mute is enabled when B6 is high. The soft mute occurs
gradually, unlike the forced infinite zero detection. When
the mute data bit is high, complete muting will occur in
127/fs seconds. For fS = 44.1kHz, complete mute will occur
in 2.88ms.
INPUT FORMAT
Normal input mode for PCM1710 is MSB first, right justified. PCM1710 may also be operated with IIS (32 continuous clock cycles per word) input format. When B7 is low,
the input format is “normal”. When B7 is high, the input
format is “IIS”. However, PCM1710 can only accept IIS
input format when it is in 16-bit mode. 20-bit data must be
entered in normal mode.
DOUBLE-SPEED DUBBING
Double-speed dubbing is used when the application allows
for the CD to be copied at twice the normal playback rate.
Double-speed dubbing is enabled when B7 is high. This
mode can only operate when the system clock is set at 384fs.
Double-speed dubbing can only occur when the sample rate
is 44.1kHz. Since fS is set at 44.1kHz, the system clock in
double-speed mode is at 192fs.
DEFAULT MODE
At initial power-on, default settings for PCM1710 are 44.1kHz
fS, de-emphasis off, mute off, double-speed off, infinite zero
detect on, 16-bit input LRCIN left channel high, and normal
input mode.
MODE 2 CONTROLS
SYSTEM CLOCK
Mode 2 is enabled when B0 is high, B1 is low, and B2 is
high. This mode controls infinite zero detection, input resolution, LRCI polarity and input format.
SAMPLING FREQUENCY
32kHz
32kHz
44.1kHz
44.1kHz
48kHz
48kHz
INFINITE ZERO DETECTION
B4 is used to enable or disable infinite zero detection.
PCM1710 monitors both data input (DIN) and bit clock
(BCKIN). When the data input is continuously zero or one
for 65,536 cycles of the bit clock, infinite zero detection
occurs, which forces the output of the PCM1710 to one-half
of VCC (typically 2.5V). Once this happens, only the output
amplifier is connected. This is done to avoid having the
noise shaped output spectrum of the DAC appear at the
output of the PCM1710. This function is especially useful
for CD applications when the player is between tracks. An
inherent attribute of all delta-sigma architectures is the
presence of quantization noise when the input is constant (all
1s or 0s). When the zero detect circuit disconnects the DAC
from the output amplifier, a very low level “click” noise may
be audible. The click noise occurs at approximately –76dB,
and in many cases is inaudible.
256fs
384fs
256fs
384fs
256fs
384fs
8.1920MHz
12.2880MHz
11.2896MHz
16.9344MHz
12.2880MHz
18.4320MHz
TABLE VIII. Relationship of fs and System Clock.
NORMAL/DOUBLE-SPEED DUBBING
For most CD playback applications operating at 384fs, the
system clock frequency must be 16.9344MHz, in both the
normal mode and double-speed dubbing mode. Table VIII
illustrates the relationship between fs and output clock
frequency in both modes.
ML/DSD (PIN 28)
PARAMETER
XTI Input Clock Frequency
XTI Frequency
CLKO Output Clock Frequency
INPUT RESOLUTION
H
(Normal)
L
(Double Speed)
384fs
16.9344MHz
(fS = 44.1kHz)
384fs
192fs
16.9344MHz
(fS = 88.2kHz)
192fs
TABLE IX. Relationship Between Normal/Double Speed
and fs.
PCM1710 is capable of accepting either 16-bit or 20-bit
input data. Specifications for PCM1710 are tested and guaranteed using 16-bit data. When 20 bits are used, dynamic
performance is improved by approximately 2dB. Refer to
“Typical Performance Curves” for a comparison of 16-bit
and 20-bit data. A low on B5 places PCM1710 in 16-bit
mode, and a high on B5 sets PCM1710 to 20-bit mode.
®
PCM1710U
SYSTEM CLOCK FREQUENCY
12
EXTERNAL SYSTEM CLOCK
Figure 7 is a diagram showing the internal clock in conjunction with an external crystal oscillator.
Digital
Power Supply
Internal System Clock
Analog
Power Supply
VDD
VCC
DGND
AGND
FIGURE 9. Latch-up Prevention Circuit.
CLKO (XTI)
XTI
XTO
mance at low levels (such as keyboards, synthesizers, etc.)
it may be beneficial to provide additional bypassing on
pin 15 (VCC1) with a low ESR 100µF capacitor. This will
eliminate stray tones which may be above the noise floor.
Crystal
C1
C1, C2: 10pF ~ 20pF
C2
FIGURE 7. External Crystal Oscillator.
THEORY OF OPERATION
Figure 8 is a diagram showing the internal clock with an
external clock source, instead of an oscillator. An external system clock (input to XTI) must meet the following conditions:
PCM1710 is an oversampling delta-sigma D/A converter,
consisting of an input interface/attenuator, a 4th-order multilevel delta-sigma modulator, a low pass filter and an output
amplifier (see Figure 10).
HIGH LEVEL
VIH > 0.64VDD
TH > 10ns
LOW LEVEL
VIH > 0.28VDD
TL > 10ns
NOTE: (1) XTO must be open.
Internal System Clock
CLKO (XTI)
XTI
MODULATOR
The delta-sigma section of the PCM1710 is based on a 5level amplitude quantizer and a 4th-order filter. This converts oversampled 16-or 20-bit input data to 5-level deltasigma format. A block diagram of the 5-level modulator is
shown in Figure 11.
This 5-level delta-sigma modulator has the advantage of
improved stability and jitter sensitivity over the typical one
bit (2-level) delta-sigma modulator.
The combined oversampling rate of the delta-sigma modulator and the internal 8X oversampling digital filter is 48fs at
a system clock of 384fs and 32fs at a system clock of 256fs.
XTO(1)
External System Clock Input
FIGURE 8. External System Clock.
POWER SUPPLY CONNECTIONS
PCM1710 has two power supply connections: digital (VDD)
and analog (VCC). Each connection also has a separate
ground. If the power supplies turn on at different times, there
is a possibility of a latch-up condition. To avoid this condition, it is recommended to have a common connection
between the digital and analog power supplies. If separate
supplies are used without a common connection, the delta
between the two supplies during ramp-up time must be less
than 0.6V.
An application circuit to avoid a latch-up condition is shown
in Figure 9.
A block diagram of the 4th-order filter section Hf (z) in the
delta-sigma modulator is shown in Figure 12.
In general, high order one-bit delta-sigma modulators have
disadvantages due to loop instability (multiple integration
stages). The five level delta-sigma modulator of the PCM1710
uses phase compensation techniques to obtain stable operation. In Figure 12, the coefficients B1 to B4 give the basic
form of the filter, and A2 to A4 are used for phase compensation of the feedback loop.
The theoretical quantization noise performance of five level
delta-sigma modulator is shown in Figure 13 and 14. In the
audio band, the quantization noise floor level of the PCM1710
is less than 130dB (at a system clock of 384fs).
BYPASSING POWER SUPPLIES
The power supplies should be bypassed as close as possible
to the unit. Refer to Figure 19 for optimal values of bypass
capacitors. For applications which require very high perfor-
®
13
PCM1710U
1fs (NM: Normal Mode)
2fs (DS: Double-Speed Dubbing Mode)
Digital
Input
FIR-1
x2 85TAP
Attenuator
4fs (NM)
8fs (DS)
FIR-2
x2 15TAP
De-emphasis
Normal
8fs
FIR-3
x2 TTAP
Interpolator
x6
Double Speed
48fs (384fs System Clock)
4th-Order Multi-Level ∆Σ
Analog
Output
Vp-p = 3.2V
CMOS
Amp
2nd-Order
LP Filter
DAC
FIGURE 10. PCM1710 Block Diagram.
5-level Quantizer
4
In
+
Out
3
2
8fs
16/20-bits
1
+
Hf(Z)
32fs/48fs
5-level
0
FIGURE 11. Block Diagram of Multi-level ∆Σ Modulator.
In
B4
B3
+
B2
+
+
B1
+
+
+
+
Out
+
–A1
–A2
FIGURE 12. Block Diagram of 4th-order Filter Section (Hf (z)).
PCM1710 NOISE SHAPING AT 384fs
PCM1710 NOISE SHAPING AT 256fs
0
0
–20
–20
–40
–40
Gain (dB)
Gain (dB)
–60
–80
–100
–120
–60
–80
–100
–120
–140
–140
–160
–160
–180
0
10
20
30
40
50
0
Frequency (kHz)
20
30
40
50
Frequency (kHz)
FIGURE 14. Theoretical Modulator Performance at 256fs.
FIGURE 13. Theoretical Modulator Performance at 384fs.
®
PCM1710U
10
14
APPLICATION
CONSIDERATIONS
changed during operation, output data is invalid during the
delay period (TD) and for two subsequent cycles of LRCIN.
After two cycles of LRCIN, the output is a valid representation of the input data.
16-BIT vs 20-BIT OPERATION
In the serial mode, PCM1710 can be configured to accept
either 16-bit or 20-bit data. The specifications listed in this
data sheet are the 16-bit data. Some improvements in
dynamic performance can be realized by using 20-bit data.
Internally, the PCM1710’s digital filter uses only 20-bit
data. If the input data is 16-bit, the filter adds four zeros
to complete the 20-bit input word. Typical performance
differences between 16-bit and 20-bit data are shown in
Tables X and XI.
DATA
256fs
384fs
16-bit
20-bit
–91dB
–94dB
–93dB
–96dB
OUTPUT FILTERING
For testing purposes all dynamic tests are done on the
PCM1710 using a 20kHz low pass filter. This filter limits
the measured bandwidth for THD+N, etc. to 20kHz. Failure
to use such a filter will result in higher THD+N and lower
SNR and Dynamic Range readings than are found in the
specifications. The low pass filter removes out of band
noise. Although it is not audible, it may affect dynamic
specification numbers.
The performance of the internal low pass filter from DC to
24kHz is shown in Figure 15. The higher frequency rolloff
of the filter is shown in Figure 16. If the user’s application
has the PCM1710 driving a wideband amplifier, it is recommended to use an external low pass filter. A simple 3rdorder filter is shown in Figure 17. For some applications, a
passive RC filter or 2nd-order filter may be adequate.
TABLE X. THD+N Performance at Full Scale.
DATA
256fs
384fs
16-bit
20-bit
94dB
96dB
96dB
98dB
SIMULATED ANALOG FILTER
FREQUENCY RESPONSE
(20Hz~24kHz, Expanded Scale)
TABLE XI. Dynamic Range.
1.0
DELAY TIME
There is a finite delay time in delta-sigma converters. In
A/D converters, this is commonly referred to as latency.
For a delta-sigma D/A converter, delay time is determined
by the order number of the FIR filter stage, and the chosen
sampling rate. The following equation expresses the delay
time of PCM1710:
TD = 22.625 x 1/fs
dB
0.5
0
–0.5
For fS = 44.1kHz, TD = 22.625/44.1kHz = 513.04µs
–1.0
20
Applications using data from a disc or tape source, such as
CD audio, CD-Interactive, Video CD, DAT, Minidisc, etc.,
generally are not affected by delay time. For some professional applications such as broadcast audio for studios, it is
important for total delay time to be less than 2ms.
100
1k
Frequency (Hz)
10k
24k
FIGURE 15. Low Pass Filter Frequency Response.
SIMULATED ANALOG FILTER
FREQUENCY RESPONSE
(10Hz~10MHz)
dB
INTERNAL RESET
If the sample rate clock (LRCIN) is stopped during operation, the infinite zero detect circuit will cause the output to
go to VCC /2 after 65,536 cycles of the bit clock (BCKIN).
Once a new system clock has been applied, there will be a
delay until output data is correlated to the input. This is
due to the digital delay of the filter.
When power is first applied to PCM1710, an automatic
reset function occurs after 64 cycles of LRCIN.
CHANGING SAMPLING RATE
10
5
0
–5
–10
–15
–20
–25
–30
–35
–40
–45
–50
–55
–60
10
For normal operation, LRCIN and XTI should be synchronized at either 256fs or 384fs. When the sampling rate is
100
1k
10k
100k
1M
10M
Frequency (Hz)
FIGURE 16. Low Pass Filter Frequency Response.
®
15
PCM1710U
TEST CONDITIONS
Figure 18 illustrates the actual test conditions applied to
PCM1710 in production. The 11th-order filter is necessary
in the production environment for the removal of noise,
resulting from the relatively long physical distance between
the unit and the test analyzer. In most actual applications, the
third-order filter shown in Figure 17 is adequate. Under
normal conditions, THD+N typical performance is –70dB
with a 30kHz low pass filter (shown here on the THD
meter), improving to –92dB when the external 20kHz second-order filter is used.
oscillator. All of the functions can be controlled by on-board
switches. DEM-PCM1710 does not contain a receiver chip
or an external low pass filter. DEM-PCM1710 requires a
single +5V power supply.
DEM-DAI1710
This fixture is more complete than DEM-PCM1710; it
includes a Digital Audio Interface (DAI) receiver chip for
easy use and to provide a low-jitter 256fs system clock to the
PCM1710. Also included are dual second-order low pass
filters using Burr-Brown’s OPA2604 dual FET-input op
amp. The output of the DEM-DAI1710 is 2Vrms, using
standard BNC-type connectors.
All of the functions of PCM1710 can be evaluated by using
the DEM-DAI1710 jumper selections. DEM-DAI1710 requires +5V and ±5V to ±15V power supplies. The schematic
diagram for DEM-DAI1710 is shown in Figure 19. For more
detailed information on the evaluation fixtures, contact your
local Burr-Brown representative.
EVALUATION FIXTURES
Two different evaluation fixtures are available for PCM1710.
DEM-PCM1710
This evaluation fixture is primarily intended for quick evaluation of the PCM1710’s performance. DEM-PCM1710 can
accept either an external clock or a user-installed crystal
1
1500pF
4
5
+
10kΩ
2
3
10kΩ
10kΩ
100pF
680pF
VSIN
–
GAIN vs FREQUENCY
90
6
0
–34
–90
–180
–54
Phase (°)
Gain (dB)
Gain
–14
Phase
–270
–74
–360
–94
100
1k
10k
Frequency (Hz)
100k
1M
FIGURE 17. 3rd-Order LPF.
Shibasoku #725
Test Disk
Through
Lch
CD
Player
Digital
DEMDAI1710
11th-order
20kHz
LPF
Rch
PGA
THD
Meter
0dB/60dB
30KHz LPF on
For test of S/N ratio and Dynamic Range, A-filter ON.
FIGURE 18. Test Block Diagram.
®
PCM1710U
16
GND
+VCC
–VS
GND
+VS
CN
C27
100µF
+
C26
100µF
+
C25
100µF
+
R15
10kΩ
R14
10kΩ
R13
10kΩ
U1
CS8412CP
2
4
CC/FO
SDATA
5
6
7
+
C1
0.047µF
Digital In
C5
0.1µF
C4
10µF
8
C2
9
0.047µF
10
11
R1
75Ω
12
13
M1
+VD
+VA
DGND
RXP
AGND
RXN
FRT
FSYNC
MCK
SCK
M3
CS12/FCK
+VS
+5V VCC
U2
PCM1710U
1
3
–VS
+5V VCC
+5V VCC
28
1
27
2
26
3
25
4
24
5
23
6
22
7
+
C6
0.1µF
21
C7
10µF
C12
+ 10µF
C13
0.1µF
20
9
19
10
C10
10µF
+
18
17
R2
1KΩ
16
11
12
13
15
14
8
14
LRCIN
ML/DSD
DIN
MC/DM2
BCKIN
MD/DM1
CLCKO
XTI
XTO
DGND
VDD
VCC2R
AGND2R
MUTE
MODE
CKSL
DGND
VDD
VCC2L
AGND2L
EXT1R
EXT1L
EXT2R
EXT2L
VOUTR
VOUTL
AGND1
VCC1
C3
0.047µF
28
27
J1
26
J2
R3
10KΩ
25
+
24
J3
J4
23
Q1
C1815 or
equivalent
22
C14
0.1µF
21
C15
+ 10µF
20
19
18
C11
10µF
17
+
16
15
+
C8
10µF
C9
0.1µF
+VS
C18
4.7µF
R6
5.6kΩ
R4
10KΩ
C16
10µF
C23
0.1µF
C17
4.7µF
R8
10kΩ
R10
3.9kΩ
C22
330pF
R12
100Ω
R5
5.6kΩ
R7
10kΩ
R9
3.9kΩ
C21
330pF
R11
100Ω
Rch Out
C20
2700pF
Lch Out
1/2 U3
OPA2604
C19
2700pF
1/2 U3
OPA2604
C24
0.1µF
–VS
FIGURE 19. DEM-DAI1710 Schematic Circuit Diagram.
®
17
PCM1710U
PACKAGE OPTION ADDENDUM
www.ti.com
19-Jan-2010
PACKAGING INFORMATION
Orderable Device
Status (1)
Package
Type
Package
Drawing
Pins Package Eco Plan (2)
Qty
PCM1710U
NRND
SOIC
DW
28
PCM1710U/1K
NRND
SOIC
DW
PCM1710U/1KG4
NRND
SOIC
PCM1710UG4
NRND
SOIC
28
Lead/Ball Finish
MSL Peak Temp (3)
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
28
1000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
DW
28
1000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
DW
28
CU NIPDAU
Level-2-260C-1 YEAR
28
Green (RoHS &
no Sb/Br)
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
25-Sep-2008
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
PCM1710U/1K
Package Package Pins
Type Drawing
SOIC
DW
28
SPQ
Reel
Reel
Diameter Width
(mm) W1 (mm)
1000
330.0
25.4
Pack Materials-Page 1
A0 (mm)
B0 (mm)
K0 (mm)
P1
(mm)
W
Pin1
(mm) Quadrant
10.9
18.2
2.9
16.0
24.0
Q1
PACKAGE MATERIALS INFORMATION
www.ti.com
25-Sep-2008
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
PCM1710U/1K
SOIC
DW
28
1000
333.2
345.9
31.8
Pack Materials-Page 2
IMPORTANT NOTICE
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements,
and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should
obtain the latest relevant information before placing orders and should verify that such information is current and complete. All products are
sold subject to TI’s terms and conditions of sale supplied at the time of order acknowledgment.
TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI’s standard
warranty. Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty. Except where
mandated by government requirements, testing of all parameters of each product is not necessarily performed.
TI assumes no liability for applications assistance or customer product design. Customers are responsible for their products and
applications using TI components. To minimize the risks associated with customer products and applications, customers should provide
adequate design and operating safeguards.
TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right, copyright, mask work right,
or other TI intellectual property right relating to any combination, machine, or process in which TI products or services are used. Information
published by TI regarding third-party products or services does not constitute a license from TI to use such products or services or a
warranty or endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual
property of the third party, or a license from TI under the patents or other intellectual property of TI.
Reproduction of TI information in TI data books or data sheets is permissible only if reproduction is without alteration and is accompanied
by all associated warranties, conditions, limitations, and notices. Reproduction of this information with alteration is an unfair and deceptive
business practice. TI is not responsible or liable for such altered documentation. Information of third parties may be subject to additional
restrictions.
Resale of TI products or services with statements different from or beyond the parameters stated by TI for that product or service voids all
express and any implied warranties for the associated TI product or service and is an unfair and deceptive business practice. TI is not
responsible or liable for any such statements.
TI products are not authorized for use in safety-critical applications (such as life support) where a failure of the TI product would reasonably
be expected to cause severe personal injury or death, unless officers of the parties have executed an agreement specifically governing
such use. Buyers represent that they have all necessary expertise in the safety and regulatory ramifications of their applications, and
acknowledge and agree that they are solely responsible for all legal, regulatory and safety-related requirements concerning their products
and any use of TI products in such safety-critical applications, notwithstanding any applications-related information or support that may be
provided by TI. Further, Buyers must fully indemnify TI and its representatives against any damages arising out of the use of TI products in
such safety-critical applications.
TI products are neither designed nor intended for use in military/aerospace applications or environments unless the TI products are
specifically designated by TI as military-grade or "enhanced plastic." Only products designated by TI as military-grade meet military
specifications. Buyers acknowledge and agree that any such use of TI products which TI has not designated as military-grade is solely at
the Buyer's risk, and that they are solely responsible for compliance with all legal and regulatory requirements in connection with such use.
TI products are neither designed nor intended for use in automotive applications or environments unless the specific TI products are
designated by TI as compliant with ISO/TS 16949 requirements. Buyers acknowledge and agree that, if they use any non-designated
products in automotive applications, TI will not be responsible for any failure to meet such requirements.
Following are URLs where you can obtain information on other Texas Instruments products and application solutions:
Products
Applications
Amplifiers
amplifier.ti.com
Audio
www.ti.com/audio
Data Converters
dataconverter.ti.com
Automotive
www.ti.com/automotive
DLP® Products
www.dlp.com
Communications and
Telecom
www.ti.com/communications
DSP
dsp.ti.com
Computers and
Peripherals
www.ti.com/computers
Clocks and Timers
www.ti.com/clocks
Consumer Electronics
www.ti.com/consumer-apps
Interface
interface.ti.com
Energy
www.ti.com/energy
Logic
logic.ti.com
Industrial
www.ti.com/industrial
Power Mgmt
power.ti.com
Medical
www.ti.com/medical
Microcontrollers
microcontroller.ti.com
Security
www.ti.com/security
RFID
www.ti-rfid.com
Space, Avionics &
Defense
www.ti.com/space-avionics-defense
RF/IF and ZigBee® Solutions www.ti.com/lprf
Video and Imaging
www.ti.com/video
Wireless
www.ti.com/wireless-apps
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2010, Texas Instruments Incorporated
工商网监
湘ICP备2023018690号
